40th week of 2010 patent applcation highlights part 20 |
Patent application number | Title | Published |
20100253356 | FUEL CELL MEASUREMENT APPARATUS - A fuel cell measurement apparatus capable of measuring electric characteristics of a solid oxide fuel cell is provided. The fuel cell measurement apparatus comprises a first current collecting unit, a second current collecting unit, a top holding set, a bottom holding set and an adjustable elastic load set. The solid oxide fuel cell is clipped by the first current collecting unit fixed by the top holding set and the second collection unit fixed by the bottom holding set. The adjustable elastic load set is capable of adjusting the tension between the top holding set and the bottom holding set. The first (second) current collecting unit comprises a first (second) conductive mesh and a first (second) porous plate having a first (second) through hole and a first (second) gas channel communicating with each other, wherein the first (second) conductive mesh is sintered on the first (second) porous plate. | 2010-10-07 |
20100253357 | Battery System, Electric Vehicle, And Battery Control Apparatus - A battery system has: a voltage detection apparatus including a voltage detection portion which includes an AD converter which converts an analog voltage signal having a measurement target analog voltage into a digital voltage signal to output the digital voltage signal, a voltage level discrimination portion which is connected to a voltage detection line across which the analog voltage signal is delivered, and which discriminates the voltage level of the measurement target analog voltage to output a discrimination result, and a fault detection portion which detects, based on the output of the AD converter and the output of the voltage level discrimination portion, a fault in the voltage detection portion in a state in which the voltage value of the digital voltage signal is within a predetermined voltage range; a battery as a voltage source of the measurement target analog voltage; and a control portion which, when the fault detection portion detects the fault, limits the discharging of the battery, or limits the charging of the battery, or limits the discharging and charging of the battery. | 2010-10-07 |
20100253358 | CONTACTLESS SYSTEM AND METHOD FOR ELECTROSTATIC SENSING WITH A HIGH SPATIAL RESOLUTION - In the illustrated embodiment of the invention a scanning system is provided for scanning a chargeable surface for latent image detection. The chargeable surface is charged to a first potential, and a scanner probe is charged to a second potential within a predetermined potential difference from the first potential. The scanner probe is oscillated at a selected frequency and reads or measures the oscillation current that is induced from the oscillation and detects any latent images or other electrostatic distributions on the chargeable surface. A processor processes the probe measurements for determining the potential of a latent image on the chargeable surface based on the scanner probe readings. | 2010-10-07 |
20100253359 | ELECTRODE FOR AN IONIZATION CHAMBER AND METHOD PRODUCING THE SAME - An electrode for an ionization chamber and an ionization chamber including an electrode are provided wherein the electrode comprises a substrate comprising a first material, and a plurality of nanowires extending from the substrate and manufactured by processing the first material of the substrate. | 2010-10-07 |
20100253360 | CORONA EFFLUENT SENSING DEVICE - The presently disclosed embodiments are directed to the detection and monitoring of corona effluent. The present embodiments pertain to a corona sensing device that employs a film of organic charge transporting material, as the active component in a corona effluent sensing device, that is disposed onto a patterned electrode bearing support member. | 2010-10-07 |
20100253361 | SENSOR, SENSOR SYSTEM, PORTABLE SENSOR SYSTEM, METHOD OF ANALYZING METAL IONS, MOUNTING SUBSTRATE, METHOD OF ANALYZING PLATING PREVENTING CHEMICAL SPECIES, METHOD OF ANALYZING PRODUCED COMPOUND, AND METHOD OF ANALYZING MONOVALENT COPPER CHEMICAL SPECIES - This invention provides a sensor having such a structure that the area in which a sensor electrode comes into contact with a liquid, a mist or a gas containing an analyte has been previously specified. The sensor comprises at least an electroconductive first electrode, an electroconductive second electrode, electroconductive first and second wirings connected to the first and second electrodes, and an insulating part for insulating the first and second wirings from each other and from a liquid, a mist or a gas containing the analyte. The insulating part is formed of an organic material. In the first and second electrodes, at least the surface, which comes into contact with a liquid, a mist or a gas containing the analyte, is formed of a material which is insoluble in a liquid or a mist containing the analyte, or is not attacked by a gas containing the analyte. | 2010-10-07 |
20100253362 | PCB DELIVERY APPARATUS PCB TESTING SYSTEM EMPLOYING THE SAME - A printed circuit board (PCB) testing system includes two gear groups, a pair of transmission belts and a driver. The pair of transmission belts geared onto and driven by the two gear groups is parallel and respectively perpendicular to the PCB transmission guideway so as to define a PCB accommodation space therebetween. Each transmission belt includes a plurality of projections. The two gear groups are rotated synchronously and inversely. During operation, the projections on the pair of transmission belts, facing the PCB accommodation space, move down, the projections move away from each other and to the bottom of the corresponding transmission belts, and a PCB supported by the pair of projections drops onto the PCB transmission guideway. | 2010-10-07 |
20100253363 | Method and system for cable detection - There are provided systems and methods for cable detection, such as a video cable. There is provided a device including an output stage, a comparator, a reference selector, a peak detector, and logic gates, which may be arranged to optimize power consumption of the output stage while the cable is unplugged. A method is also provided for such a device, the method comprising detecting whether the cable is unplugged using a cable detector after a first duration of time, turning off the output stage for a second duration of time in response to the cable detector detecting the cable is unplugged, turning on the output stage after the second duration of time, and proceeding to transmit data if the cable detector detects the cable is plugged in for a third period of time, or otherwise repeating the detection, turning off, and turning on steps. | 2010-10-07 |
20100253364 | METHOD AND SYSTEM FOR PASSIVELY DETECTING AND LOCATING WIRE HARNESS DEFECTS - A method and system for detecting defects in a wire or wire harness includes a pair of sensors wrapped around the wire or harness, a data acquisition device for monitoring pulses in the signal produced by the sensors around the wires, and a diagnostics engine. The diagnostics engine includes an analysis module to determine features of the signals captured by the data acquisition device and a decision module for determining whether the pulse represents a defect in the wire, and the location of the defect. The system operates passively and can be used to monitor the wires while they are in use for carrying signals or current and does not require disconnecting the wires to be monitored. | 2010-10-07 |
20100253365 | FAULT DETECTION CIRCUIT - A fault detection circuit connects to and determines the occurrence of failure in an inverter circuit. The inverter circuit comprises three outputs to connect three groups of lamps respectively, and the fault detection circuit comprises a magnetic unit and a signal detection unit. The magnetic unit comprises first, second and third flux generating windings electrically connected to the three outputs of the inverter circuit, and a flux detection winding. If no fault occurs on the outputs of the inverter circuit, total flux generated by the flux generating windings is cancelled out. As long as any fault occurs on the outputs of the inverter circuit, flux generated by the flux generating windings cannot be canceled out, and the flux detection winding is electromagnetically coupled accordingly and driven by the generated flux to output a coupling signal, based on which the signal detection unit generates an alert signal accordingly. | 2010-10-07 |
20100253366 | Broadband high impedance pickoff circuit - A measuring system minimizes the parasitic affects of lumped circuit elements. The system includes two or more in-situ interfaces configured to conductively link a source to an internal load and an external load. The in-situ interfaces are linked to a shunt conductor. Two or more linear and dynamic elements conductively link the in-situ interfaces in series. The dynamic elements are configured to overwhelm the parasitic self-capacitance of an input circuit coupled to at least one of the in-situ interfaces. A shield enclosing at least one of the linear and dynamic elements has a conductive surface to fields and electromagnetic interference. The shield has attenuation ratios that substantially dampen the parasitic capacitance between the linear and dynamic elements that bridge some of the in-situ interfaces. | 2010-10-07 |
20100253367 | ELECTROMAGNETIC WAVE GENERATION SOURCE SEARCHING METHOD AND CURRENT PROBE USED THEREFOR - A junction-current probe is provided which can measure a current flowing in a junction port adapted to connect a circuit board or an electronic apparatus to a chassis under the condition that the circuit board or electronic apparatus is packaged to the chassis. Structurally, the current probe has a circular or rectangular insulator having a hole in the center, a coiled conductor wire for converting linkage flux into voltage, an insulating member for preventing the insulator from making electrical contact with surroundings, an extraction lead for connecting opposite ends of the conductor wire to a cable and the cable for connection to a measurement unit. The current probe is reduced in thickness within in a range in which the condition of packaging to the chassis can remain unchanged. | 2010-10-07 |
20100253368 | CAPACITOR INTERFACE CIRCUIT - A capacitor interface circuit is provided. A capacitor under test (CUT) is divided into a variable portion and an invariable portion, and the capacitance of an offset capacitor is designed to equal to or close to the fixed capacitance of the CUT. The offset capacitor is used to store the charges opposite to the invariable portion of the CUT for neutralizing the effect of the invariable portion of the CUT. Thereupon, the charge converter composed by the fully-differential amplifier and the feedback capacitors only responses for the variable portion of the CUT so as to increase the accuracy of the follow-up data processing. | 2010-10-07 |
20100253369 | SOIL HUMIDITY EVALUATION WITH CONTACT FREE COUPLING - Systems and methods that evaluate moisture content of the soil through change of capacitance and alternative current. A contact free inductive coupling can be provided between a sensor arrangement associated with the soil, and a reader arrangement (e.g., combination of inductor(s) and capacitor(s)) to determine frequency changes of resulting sinusoidal oscillator. Such frequency change can be correlated with moisture content of the soil. | 2010-10-07 |
20100253370 | Systems and Methods for Integrated Electrochemical and Electrical Detection - An integrated sensing device is capable of detecting analytes using electrochemical (EC) and electrical (E) signals. The device introduces synergetic new capabilities and enhances the sensitivity and selectivity for real-time detection of an analyte in complex matrices, including the presence of high concentration of interferences in liquids and in gas phases. | 2010-10-07 |
20100253371 | Method and Device for Determining a Fuel Portion in a Motor Oil of a Motor Vehicle - A method and device for determining a fuel portion in a motor oil of a motor vehicle. The motor oil is brought between at least two electrodes forming a capacitor. The capacitance of the capacitor is determined while the motor oil is located between the electrodes, and the fuel portion in the motor oil is determined from the capacitance of the capacitor. | 2010-10-07 |
20100253372 | SEMICONDUCTOR DEVICE AND WAFER WITH A TEST STRUCTURE AND METHOD FOR ASSESSING ADHESION OF UNDER-BUMP METALLIZATION - Semiconductor device with a patterned pad metal layer and a patterned under-bump metallization layer being mutually electrically connected in a common contact area | 2010-10-07 |
20100253373 | DETECTION APPARATUS AND METHOD FOR SUPERCONDUCTING COIL QUENCH - The quench of the superconducting coil is desired to be detected early while suppressing the influences of the noise generated in charge and discharge of the superconducting coil. A superconducting coil quench detection apparatus detects the balance voltage of a bridge circuit formed by the superconducting coil and a resistor to output it as a quench detection signal for detecting the quench thereof. A signal indicating the hold period where the energy accumulated in the superconducting coil is held is generated. A signal included in the hold period is extracted from the quench detection signal. The quench of the superconducting coil is detected based on the extracted signal. | 2010-10-07 |
20100253374 | Method and apparatus for Terminating A Test Signal Applied To Multiple Semiconductor Loads Under Test - Apparatus for terminating a test signal applied to multiple semiconductor loads under test is described—for example apparatus for interfacing a test signal between a tester and a semiconductor device under test (DUT). In some examples, a probe card assembly may include at least one probe substrate each having test probes configured to contact test features of a DUT; a wiring substrate, coupled to the at least one probe substrate, having a connector configured for coupling with a source termination of a tester; a signal path formed on and/or in the wiring substrate and the at least one probe substrate, the signal path having a trace and trace stubs fanning out from the trace, an input of the trace being coupled to the connector and outputs of the trace stubs being coupled to the test probes; and a resistive termination coupled between the trace and at least one potential. | 2010-10-07 |
20100253375 | ANCHORING CARBON NANOTUBE COLUMNS - A technique for anchoring carbon nanotube columns to a substrate can include use of a filler material placed onto the surface of the substrate into area between the columns and surrounding a base portion of each of the columns. | 2010-10-07 |
20100253376 | LEAK DETECTOR COMPRISING A POSITION DETERMINING SYSTEM FOR THE HAND-OPERATED PROBE - The leak detector comprises a basic unit that is connected to a probe by a hose. The probe tip is placed against test zones of the test object. In case that test gas escapes from the test object, this is detected by a test gas detector in the base unit. According to the disclosure, a position determining system is provided which comprises a transmitter, a receiver that is disposed inside the probe, and a supply and evaluation unit. Thereby, the presence of the probe tip in the individual test zones is monitored and confirmed. | 2010-10-07 |
20100253377 | ACTIVE WAFER PROBE - A probe suitable for probing a semiconductor wafer that includes an active circuit. The probe may include a flexible interconnection between the active circuit and a support structure. The probe may impose a relatively low capacitance on the device under test. | 2010-10-07 |
20100253378 | PROBE FOR HIGH FREQUENCY SIGNAL TRANSMISSION - A probe for high frequency signal transmission includes a metal pin, and a metal line spacedly arranged on and electrically insulated from the metal pin and electrically connected to grounding potential so as to maintain the characteristic impedance of the probe upon transmitting high frequency signal. The maximum diameter of the probe is substantially equal to or smaller than two times of the diameter of the metal pin. Under this circumstance, a big amount of probes can be installed in a probe card for probing a big amount of electronic devices, so that a wafer-level electronic test can be achieved efficiently and rapidly. | 2010-10-07 |
20100253379 | Method and Apparatus for Probing a Wafer - A semiconductor wafer resting on a contact element has a spatially distributed force applied to its frontside and an equal and opposing force applied to its backside. The contact element comprises a solid immersion lens (SIL), and has an area less than the area of the wafer, but no less than the larger of the area of an optical collection area and an electrical probe assembly. The equal and opposing forces cause the wafer to conform to the shape of the contact element. Measurements, including electrical testing, optical probing and wafer characterization are performed on the wafer. | 2010-10-07 |
20100253380 | DIELECTRIC FILM AND LAYER TESTING - A system for testing and a method for making a semiconductor device is disclosed. A preferred embodiment includes a conductor overlying a dielectric layer. The conductor is coupled to a first test pad via a first conducting line and to a second test pad via a second conducting line. | 2010-10-07 |
20100253381 | On-Chip Logic To Support In-Field Or Post-Tape-Out X-Masking In BIST Designs - Techniques for masking unknown and irrelevant response values that may be produced by a BIST process. Masking circuitry is provided for selectively masking the response values obtained from a BIST process. The operation of the selective masking circuitry is controlled by a programmable mask circuitry controller that can be programmed after the integrated circuit has been manufactured. A user can analyze an integrated circuit after it has been manufactured to identify irrelevant and unknown data values in a BIST process. After the irrelevant and unknown data values have been identified, the user can program the programmable mask controller to have the selective masking circuitry mask the identified irrelevant and unknown data values. | 2010-10-07 |
20100253382 | System and Method for Observing Threshold Voltage Variations - A system and method for observing threshold voltage variations are provided. A ring oscillator circuit comprises a plurality of inverters arranged in a sequential loop, a plurality of test circuits having devices under test, each coupled between a respective one of the inverters and a power supply. Each test circuit has a bypass field effect transistor (FET) having a first channel coupled between the power supply and a respective one of the inverters responsive to an individual enable signal, and a FET device under test having a second channel arranged in parallel to the first channel. A method is described for determining the threshold voltage of the device under test by disabling, for one of the inverters in the ring oscillator, the first FET device such that the device under test is coupled between the power supply and the respective inverter and affects the operating frequency of the ring oscillator. | 2010-10-07 |
20100253383 | CIRCUIT TOPOLOGY FOR MULTIPLE LOADS - A circuit topology for multiple loads includes a driving terminal for transmitting a driving signal, a number of transmitting lines, and a number of loads operable to receive the driving signal from the driving terminal. The number of loads are connected to the driving terminal one by one via the number of transmitting lines. Two transmitting lines of the number of transmitting lines, which are nearest and farthest respectively from the driving terminal, are both greater than widths of the other transmitting lines. | 2010-10-07 |
20100253384 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, sequentially activates the data and a first pull-up delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-up delayed signals having different delay times in the second mode of operation. A pull-up driving unit sequentially pulls a data output terminal up in response to the data and the first to third pull-up delayed signals. A pull-down slew rate controller, upon a second transition of the data, sequentially activates the data and the first pull-down delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-down delayed signals having different delay times in the second mode of operation. A pull-down driving unit sequentially pulls the data output terminal down in response to the data and the first to third pull-down delayed signals. | 2010-10-07 |
20100253385 | EDGE DETECT RECEIVER CIRCUIT - A digital signal detector detects digital signals by only sensing the rising and falling edges of a received digital signal and latches the logic state between the detected edges. Such edges contain very high frequencies that are much higher than the fundamental frequency of the digital signal train. A small high pass filter filters out at least the DC component and the fundamental frequency of the received digital signal. A filtered edge appears as a spike that goes either positive or negative depending on whether the edge is a rising or falling edge. A memory element, such as comprising an RS flip flop, is triggered by the positive and negative spikes. A positive spike triggers the flip flop to output a logical one, and a negative spike triggers the latch to output a logical zero. In this way, the digital signal is recreated without the original digital signal itself being required to pass through the high pass filter. | 2010-10-07 |
20100253386 | DATA TRANSMITTER AND RELATED SEMICONDUCTOR DEVICE - A semiconductor device transmitting a plurality of data using a multilevel signal includes a parity bit control unit generating a parity bit that varies with a number of data in which a most significant bit (MSB) and least significant bit (LSB) are different. A data conversion unit either inversely outputs the MSB or the LSB, or outputs the data without a change in response to the parity bit. Transmission units transmit data provided by the data conversion unit using the multilevel signal. | 2010-10-07 |
20100253387 | SYSTEM AND METHOD FOR AUTO-POWER GATING SYNTHESIS FOR ACTIVE LEAKAGE REDUCTION - A method includes parsing a design of the integrated circuit to define cells in automatic power gating power domains, automatically creating an automatic power gating power domain netlist from the parsed design of the integrated circuit, and placing and routing the automatic power gating power domain netlist to produce a layout for the integrated circuit. The parsing partitions a high-level power domain of the integrated circuit into one or more automatic power gating power domains. The automatic power gating power domains have substantially zero-cycle power up times, thereby enabling transparent operation. Furthermore, the automatic power gating power domains may be automatically inserted into designs of integrated circuits, thereby relieving integrated circuit designers of the task of inserting power domains and associated hardware and software. | 2010-10-07 |
20100253388 | INTERFACE CIRCUIT - An interface circuit comprising: a first output circuit configured to allow an access signal to be input thereto and output the access signal to a storage circuit, the access signal capable of being changed to one logic level or the other logic level for accessing the storage circuit; a second output circuit configured to output the access signal outputted from the first output circuit; and a comparison circuit configured to compare the number of times a logic level of the access signal inputted to the first output circuit is changed and the number of times a logic level of the access signal outputted from the second output circuit is changed, and output a comparison signal indicating whether predetermined access has been performed based on the access signal inputted to the first output circuit, after at least a part of the access signal is inputted to the first output circuit. | 2010-10-07 |
20100253389 | Low-noise PECL output driver - An integrated circuit output driver is provided that exhibits improved performance and signal integrity. In one embodiment, circuitry for producing an oscillatory output signal having a peak voltage of V volts uses MOS transistor circuitry transistors of which are designed for a maximum port-to-port voltage of substantially less than V volts. A first inverter chain is coupled to an input signal to produce a predriver output signal. A second inverter chain of multiple of inverters including a first inverter produces a driver output signal. Circuitry is provided for AC-coupling the predriver output signal to the second inverter chain, it being configured to translate the predriver output signal to a higher voltage range to produce a translated predriver output signal. A driver transistor is controlled using the driver output signal to produce the oscillatory output signal, and circuitry coupled to the driver output transistor ensures that no port-to-port voltage of the driver output transistor exceeds the maximum port-to-port voltage. | 2010-10-07 |
20100253390 | SEMICONDUCTOR PACKAGE, STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME, AND A METHOD FOR SELECTING ONE SEMICONDUCTOR CHIP IN A STACKED SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip having a circuit section. A first chip selection electrode passes through a first position of the semiconductor chip, and the first chip selection electrode has a first resistance and outputs a first signal. A second chip selection electrode passes through a second position of the semiconductor chip, and the second chip selection electrode has a second resistance greater than the first resistance and outputs a second signal. A signal comparison part is formed in the semiconductor chip and is electrically connected to the first and second chip selection electrodes. The signal comparison part compares the first signal applied from the first chip selection electrode to the second signal applied from the second chip selection electrode and outputs a chip selection signal to the circuit section depending upon the result of the comparison. | 2010-10-07 |
20100253391 | APPARATUS AND METHOD FOR CONTROLLING DELAY STAGE OF OFF-CHIP DRIVER - A multiple-finger off-chip driver (OCD) uses delay between branches of the output stage. The delay between branches is controlled using bias circuitry which compensates for process, temperature, and voltage (PVT) variations, resulting in less variation of slew rate at the output of the OCD. The OCD includes a time domain delay stage; a pre-driver stage; a final driver stage; and a bias circuit, for providing bias voltages to the time domain stage that compensate for process, temperature and voltage (PVT) variations on the time domain stage. | 2010-10-07 |
20100253392 | I/O BUFFER WITH TWICE THE SUPPLY VOLTAGE TOLERANCE USING NORMAL SUPPLY VOLTAGE DEVICES - The invention relates to an I/O buffer with twice the supply voltage tolerance using normal supply voltage devices. The I/O buffer of the invention includes a driver, a first level converter, a gate-controlled circuit and a dynamic source output stage. Signals of the I/O buffer are classified into a first voltage range and a second voltage range. The first voltage range is zero to the normal supply voltage, and the second voltage range is the normal supply voltage to twice the supply voltage. Therefore, the voltage between any two terminals of any of the transistors in the I/O buffer does not exceed the normal supply voltage so that the I/O buffer of the invention can transmit and receive signals with a voltage swing twice as high as the normal power supply voltage using normal supply voltage devices and without gate-oxide reliability problems. | 2010-10-07 |
20100253393 | BUFFER AND DISPLAY DEVICE - A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section | 2010-10-07 |
20100253394 | BUFFER WITH AN OUTPUT SWING CREATED USING AN OVER-SUPPLY VOLTAGE - A pre-drive circuit with an output buffer that may contain a bootstrap circuit is described. The bootstrap circuit may be configured to output a voltage level greater in magnitude than the supply voltage that the bootstrap circuit is coupled with. The pre-drive circuit may contain a timing circuit. The timing circuit may be configured to at least partially determine when the bootstrap circuit outputs a voltage greater in magnitude than the supply voltage. The pre-drive circuit may also contain a pre-drive buffer circuit. This pre-drive buffer circuit may be capable of three outputs: (1) logical zero, or roughly electrical ground; (2) logical one, or roughly the level of the voltage supply, and (3) an outputted voltage greater than the voltage supply. | 2010-10-07 |
20100253395 | TRANSISTOR Gate Driver for Short Circuit Protection - Particular embodiments generally relate to driver structures. In one embodiment, an apparatus includes a first driver that drives a first current for a transistor. The first driver drives the first current during a first portion of a drive time of driving the transistor. The first driver is OFF during a second portion. A second driver drives a second current for the transistor during the second portion. | 2010-10-07 |
20100253396 | APPARATUS AND METHOD FOR CONTROLLING A COMMON-MODE VOLTAGE OF SWITCHING AMPLIFIERS - The present invention relates to an H-bridge controller and method for controlling a common-mode voltage and/or current of an H-bridge circuit. The H-bridge controller comprises a section for receiving a signal indicating at least one of a common-mode voltage and common-mode current of the H-bridge circuit, and a section for generating control signals which determine switching of the H-bridge circuit so as to control at least one of the common-mode voltage and common-mode current of the H-bridge circuit. | 2010-10-07 |
20100253397 | FREQUENCY DIVIDER CIRCUIT - Fractional frequency division is performed by sequentially selecting phase signals for division, where transitioning from a previous phase signal to a next phase signal for division occurs in response to not only the frequency-divided previous phase signal but also a second one of the phase signals. A phase transition that is triggered at least in part in response to a second phase signal having a phase that is greater (with respect to the phase signal sequence) than the phase of the next phase signal can aid minimization of signal glitches. The first frequency-divided signal can be further divided to produce a second frequency-divided signal having a 50-percent duty cycle. | 2010-10-07 |
20100253398 | Fully Differential Single-Stage Frequency Divider Having 50% Duty Cycle - A fully differential frequency divider includes a first fully differential single-stage latch circuit configured to receive an input signal and provide a corresponding output signal upon transition of a clock signal, the output signal corresponding to an in-phase portion of a communication signal, and a second fully differential single-stage latch circuit coupled to the first fully differential single-stage latch circuit, the second fully differential single-stage latch circuit configured to provide a corresponding output signal upon transition of the clock signal. The second fully differential single-stage latch circuit is also configured to receive as an input signal the output signal of the first fully differential single-stage latch circuit, the output signal of the second fully differential single-stage latch circuit corresponding to a quadrature-phase portion of the communication signal, where the output signal of the second fully differential single-stage latch circuit is provided as the input signal to the first fully differential single-stage latch circuit. | 2010-10-07 |
20100253399 | Circuit Arrangement for Operating Voltage Detection - A circuit arrangement for operating voltage detection has a detection block ( | 2010-10-07 |
20100253400 | Phase-Locked Loop (PLL) Having Extended Tracking Range - A method for extending a tracking range of a PLL includes the steps of: establishing an initial tracking window of the PLL, the tracking window having a first width associated therewith; and dynamically adjusting the tracking window of the PLL within an extended tracking range when a frequency of an input signal supplied to the PLL is outside of the tracking window, the extended tracking range having a second width associated therewith which is greater than the first width. | 2010-10-07 |
20100253401 | SIGNAL PROCESSING CIRCUIT AND SIGNAL PROCESSING METHOD - A signal processing circuit includes: a first operation circuit for receiving a phase component of an input signal, and generating an adjusted phase component and at least one weighting factor according to the phase component of the input signal; a second operation circuit, coupled to the first operation circuit, for receiving the adjusted phase component and converting the adjusted phase component into a frequency component corresponding to the adjusted phase component; a third operation circuit, coupled to the first operation circuit, for receiving an amplitude component of the input signal, and adjusting the amplitude component according to the at least one weighting factor to generate an adjusted amplitude component; and a fourth operation circuit, coupled to the second operation circuit and the third operation circuit, for generating an output signal according to the frequency component and the adjusted amplitude component. | 2010-10-07 |
20100253402 | COMMUNICATION SYSTEM, PHASE-LOCKED LOOP, MOVABLE BODY AND COMMUNICATION METHOD - A communication system includes a phase-locked loop that maintains synchronization of a reception signal. The phase-locked loop includes a loop filter that has a circuit configuration m for an m-th order phase-locked loop including a circuit configuration n for an n-th order phase-locked loop (m>n), and a switching section that switches circuit configurations, which are activated in the loop filter, between the circuit configuration n and the circuit configuration m. | 2010-10-07 |
20100253403 | Radiation-Hardened Charge Pump Topology - A radiation-hardened charge pump circuit is provided. The circuit includes a first charge pump having a first charge pump output, a second charge pump having a second charge pump output, a first coincidence detector receiving as inputs the first charge pump output and the second charge pump output and producing as an output a first coincidence signal, and an analog 2:1 multiplexor for selecting either the first charge pump output or the second charge pump output based on the first coincidence signal. In alternative embodiment, the circuit includes at least three charge pumps, at least two coincidence detectors, decision logic, and a correspondingly-sized analog multiplexor. | 2010-10-07 |
20100253404 | CLOCK JITTER COMPENSATED CLOCK CIRCUITS AND METHODS FOR GENERATING JITTER COMPENSATED CLOCK SIGNALS - Clock circuits, memories and methods for generating a clock signal are described. One such clock circuit includes a delay locked loop (DLL) configured to receive a reference clock signal and generate an output clock signal having an adjustable phase relationship relative to the reference clock signal, and further includes a clock jitter feedback circuit coupled to a clock tree and the DLL. The clock jitter feedback circuit is configured to synchronize a clock jitter feedback signal and a DLL feedback signal that is based on the output clock signal. The clock jitter feedback circuit is further configured to provide the clock jitter feedback signal to the DLL for synchronization with a buffered reference clock signal. The clock jitter feedback signal is based on and generated in response to receiving a distributed output clock signal from the clock tree circuit and the buffered reference signal is based on the reference clock signal. | 2010-10-07 |
20100253405 | TECHNIQUES FOR NON-OVERLAPPING CLOCK GENERATION - Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (t | 2010-10-07 |
20100253406 | APPARATUS AND METHOD FOR COMPENSATING FOR PROCESS, VOLTAGE, AND TEMPERATURE VARIATION OF THE TIME DELAY OF A DIGITAL DELAY LINE - A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit. | 2010-10-07 |
20100253407 | APPARATUS AND METHOD OF GENERATING REFERENCE CLOCK FOR DLL CIRCUIT - An apparatus for generating a reference clock for a DLL circuit includes a buffering unit configured to buffer an external clock so as to generate a first reference clock and a second reference clock, and to invert the second reference clock so as to generate a negative second reference clock. A duty cycle compensating unit generates a reference clock from the first reference clock and the negative second reference clock. | 2010-10-07 |
20100253408 | TIMING GENERATING CIRCUIT AND PHASE SHIFT CIRCUIT - There are provided a timing generating circuit which can generate the rising edge or the falling edge of pulses with a resolution higher than the frequency of a repeat signal generating circuit, and a phase shift circuit which can be applied to the timing generating circuit. The phase shift circuit receiving a repeat signal generates a signal of which a phase is shifted by a predetermined quantity on the basis of the repeat signal, the phase shift controller controls what phase of signal the phase shift circuit output among first to M-th signals, and the counter circuit counts the number of output signals of the phase shift circuit and generates a count end signal when the count value reaches a set value, and thereby the counter circuit outputs a synthesized timing signal of the timing of the repeat signal and the timing shifted by the phase shift circuit. | 2010-10-07 |
20100253409 | CLOCK GENERATION SYSTEM AND CLOCK DIVIDING MODULE - A clock gating system includes a clock divider, a first clock gating unit and a second clock gating unit. The clock divider is employed to generate clock signals with different frequencies. The first clock gating unit is configured for generating a gated clock to a first functional block, while the second clock gating unit is configured for generating a gated clock to a second functional block. Logically the first clock gating unit and the second clock gating unit are included in the first functional block and the to second functional block, respectively, and in physical layout the first clock gating unit and the second clock gating unit are disposed close to the clock divider. | 2010-10-07 |
20100253410 | CLAMP PROTECTION CIRCUIT AND A PFC CONTROL CIRCUIT EMPLOYING SUCH CLAMP PROTECTION CIRCUIT - The present invention relates to clamp protection circuit and a PFC control circuit employing such clamp protection circuit. Said clamp protection circuit comprises a high voltage isolation module used for receiving power from a high voltage power supply; a voltage clamp module used for receiving an output low voltage from the high voltage isolation module and realizing a clamp protection; and a low voltage bias module used for providing bias voltage to the high voltage isolation module and the voltage clamp module. By employing the clamp protection circuit, the precision of the clamp voltage is improved, the design is simplified and the silicon area is reduced. Meanwhile, the transient response is enhanced. Moreover, when the clamp protection circuit is applied in a PFC control circuit, the design of the whole PFC control circuit is simplified and the silicon area is reduced, and the precision and transient response of the clamp voltage of the clamp protection circuit inside the PFC control circuit are improved. | 2010-10-07 |
20100253411 | Method and system for generating wavelets | 2010-10-07 |
20100253412 | PASSIVE HARMONIC-REJECTION MIXER - An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals. | 2010-10-07 |
20100253413 | INRUSH CURRENT LIMITING CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - An inrush limiting circuit is connected between an external power source and a plurality of capacitors, and includes a delay trigger signal generator, a plurality of reversing circuits and a plurality of transmission gates. The delay trigger signal generator is connected to the external power source, to receive external power signals and generate a plurality of delay trigger signals. The reversing circuits are connected to the delay trigger signal generator, to reverse the delay trigger signals and output a plurality of the reversed delay trigger signals. The transmission gates are correspondingly connected to the delay trigger signal generator, the reversing circuits and the capacitors, to turn on respectively at different times based on the delay trigger signals and the reversed delay trigger signals, to cause the external power source to charge the capacitors at the different times so as to avoid an inrush current. | 2010-10-07 |
20100253414 | SAMPLING - There is disclosed current-mode time-interleaved sampling circuitry configured to be driven by substantially sinusoidal clock signals. Such circuitry may be incorporated in ADC circuitry, for example as integrated circuitry on an IC chip. The disclosed circuitry is capable of calibrating itself without being taken off-line. | 2010-10-07 |
20100253415 | HIGH POWERED HIGH SPEED SWITCH - An amplified signal switching system comprises a plurality of transducers, and a switch operable for diverting amplified transient signals to selected transducers and preventing the amplified transient signals from being sent to non-selected transducers, wherein the amplified transient signals are AC or acoustic signals, wherein the plurality of transducers comprise a plurality of speakers, and wherein the plurality of transducers are isolated from one another. The switching system further comprises an amplifier operable for sending the amplified transient signals to the switch. The switch selectively turns the amplified transient signals on and off to the selected transducers in order to prevent the non-selected transducers from receiving the amplified transient signals. Moreover, the switch minimizes signal distortion in the selected transducers, and alternatively, the switch eliminates signal output to the non-selected transducers. | 2010-10-07 |
20100253416 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a delay characteristic compensating circuit that is provided in a logic area including an inside and a surface of a chip. The delay characteristic compensating circuit includes a heat generating circuit that heats the semiconductor integrated circuit, a temperature sensor that measures a junction temperature, a voltage monitor that measures a power supply voltage, and a control circuit that actuates the heat generating circuit when the junction temperature does not reach a reference temperature and when the power supply voltage is lower than a reference voltage and stops actuating the heat generating circuit when the junction temperature reaches the reference temperature. | 2010-10-07 |
20100253417 | Conducting Polymer for Electronic, Photonic and Electromechanical Systems - The present invention concerns doped organic semiconductors composites. In certain aspects, organic polymers are doped with large anions, such as DBS | 2010-10-07 |
20100253418 | CHARGE PUMP CIRCUITS, SYSTEMS, AND OPERATIONAL METHODS THEREOF - A charge pump circuit includes at least one stage between an input end and an output end. The at least one stage includes a first CMOS transistor coupled with a first capacitor and a second CMOS transistor coupled with a second capacitor. The at least one stage is capable of receiving a first timing signal and a second timing signal for pumping an input voltage at the input end to an output voltage at the output end. During a transitional period of the first timing signal and the second timing signal, the at least one stage is capable of substantially turning off at least one of the first CMOS transistor and the second CMOS transistor for substantially reducing leakage currents flowing through at least one of the first CMOS transistor and the second CMOS transistor. | 2010-10-07 |
20100253419 | SEMICONDUCTOR DEVICE AND SYSTEM - A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased. | 2010-10-07 |
20100253420 | Power Efficiency of a Line Driver - An apparatus comprising a first line driver, a second line driver, a charge pump, and a control logic circuit coupled to the first line driver and the second line driver and configured to disable the charge pump when both a first control signal associated with the first line driver and a second control signal associated with the second line driver indicate a charge pump disable state. A network component comprising at least one processor configured to implement a method comprising receiving a first control signal and a second control signal, disabling a charge pump when both the first control signal and the second control signal indicate a charge pump disable state, and operating the charge pump to boost a voltage when the first control signal, the second control signal, or both indicate a charge pump active state. | 2010-10-07 |
20100253421 | Electronic Device for Supplying DC Power - An electronic device for delivering DC power includes a load, a power end, an upper gate switch including a first end coupled to the power, a second end, and a third end, for conducting connection between the first and third ends according to the signal level of the second end, a lower gate switch including a first end coupled to the third end of the upper gate switch, a second end, and a third end coupled to ground, for conducting connection between the first and third ends according to the signal level of the second end, an inductor, and a switch control unit, coupled to the second end of the upper gate switch and the second end of the lower gate switch, for switching the upper gate switch between an ON state and an OFF state, and switching the lower gate switch between an ON state and a semi-ON state. | 2010-10-07 |
20100253422 | SEMICONDUCTOR DEVICE AND APPARATUS INCLUDING SEMICONDUCTOR DEVICE - A semiconductor device includes a substrate on which an electronic circuit is provided. Two or more pads may be present which can connect the electronic circuit to an external device outside the substrate. A current meter is electrically in contact with at least a part of the substrate and/or the pad. The meter can measure a parameter forming a measure for an aggregate amount of a current flowing between the substrate and said pads. A control unit is connected to the current meter and the electronic circuit, for controlling the electronic circuit based on the measured parameter. | 2010-10-07 |
20100253423 | DIFFUSED INTEGRATED RESISTOR - Methods and apparatus according to various aspects of the present invention may operate in conjunction with a resistor formed of a lightly-doped P-type region formed in a portion of a lightly-doped N-type semiconductor well extending on a lightly-doped P-type semiconductor substrate, the well being laterally delimited by a P-type wall extending down to the substrate, the portion of the well being delimited, vertically, by a heavily-doped N-type area at the limit between the well and the substrate and, horizontally, by a heavily-doped N-type wall. A diode may be placed between a terminal of the resistor and the heavily-doped N-type wall, the cathode of the diode being connected to said terminal. | 2010-10-07 |
20100253424 | AMPLIFYING DEVICE AND ITS CONTROL METHOD - An amplifying device comprises a first amplifying unit ( | 2010-10-07 |
20100253425 | METHOD AND APPARATUS FOR PERFORMING PREDISTORTION - Embodiments are described herein to provide better predistortion solutions for the linearization of high power amplifiers, especially those with memory effects. Many embodiments involve a method in which a predistorted signal z | 2010-10-07 |
20100253426 | High-Efficiency Power Amplifier - A high-efficiency power amplifier is provided, including a drive amplifier and a final power amplifier, and further including a first digital pre-distortion (DPD) correction module and a second DPD correction module. The first DPD correction module is configured to pre-distort nonlinear characteristics of drive signals output by the drive amplifier, and the second DPD correction module is connected to the first DPD correction module in series, and is configured to pre-distort nonlinear characteristics of amplified signals output by the final power amplifier. Another high-efficiency power amplifier is also provided, including a drive amplifier and a final power amplifier, and further including a second multi-path control module, a fourth DPD correction module, and a second gating module. The overall efficiency of the high-efficiency power amplifier is increased by improving the working efficiency of the drive amplifier. Further, higher overall efficiency is also achieved for a power amplifier with a higher gain. | 2010-10-07 |
20100253427 | CLASS-D AMPLIFIER - The invention discloses a class-D amplifier, which is used for driving a two-terminal load according to a set of analog signals. The D-class amplifier includes a pulse-width modulation (PWM) circuit, a signal processing circuit and a driving amplifier circuit. The PWM circuit receives the set of analog signals and converts them into a set of PWM signals with identical phase. The signal processing circuit generates a set of pulse signals which are attached to the set of PWM signals respectively. The driving amplifier circuit is coupled between the signal processing circuit and the two-terminal load. The driving amplifier circuit receives and amplifies the set of PWM signals. According to the set of PWM signals, the driving amplification circuit drives the two-terminal in a filterless way. | 2010-10-07 |
20100253428 | PWM AMPLIFIER - Amplifier device of the pulse width modulation amplifier type (PWM amplifier), which comprises a switch according to a micro-electromechanical system (MEMS-switch) for a signal to be amplified (V | 2010-10-07 |
20100253429 | METHOD FOR MEASURING THE SATURATION RATE OF AN AUDIO AMPLIFIER - A method and corresponding circuit that adjusts the gain of an audio output stage having a class D amplifier, this method including the steps of setting the gain to a nominal value, analyzing an output signal during successive clock periods, counting the number of clock periods during which the signal is in a state corresponding to a saturation, decreasing the gain if the number reaches, before the end of a first time interval, a value corresponding to a first percentage, maintaining the gain constant if, at the end of a second time interval, different from the first interval, the number corresponds to a second percentage being comprised between the first percentage and a third percentage, and increasing the gain if, at the end of the second time interval, the number corresponds to a fourth percentage, lower than the third percentage. | 2010-10-07 |
20100253430 | CONSTANT GAIN CONTROL FOR MULTISTAGE AMPLIFIERS - This disclosure relates to maintaining constant gain within multi-stage amplifiers. | 2010-10-07 |
20100253431 | NON-INVERTING AMPLIFIER CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND PHASE COMPENSATION METHOD OF NON-INVERTING AMPLIFIER CIRCUIT - A circuit includes a differential amplifier unit that receives an input signal at a non-inverting input thereof, a constant current source, a load circuit, an output transistor that receives an output of the differential amplifier unit as an input and drives a load circuit, a phase compensation circuit including a variable resistor and a capacitor connected in series between the input of the output transistor and a feedback path, an output current monitor circuit that detects an output current flowing through the output transistor, and a bias voltage generation circuit that varies a resistance value of the variable resistor in accordance with a result of the detection of the output current by the output current monitor circuit. A signal obtained by voltage dividing an output of the output transistor by resistors is supplied to an inverting input of the differential amplifier unit. | 2010-10-07 |
20100253432 | SIGNAL PROCESSOR COMPRISING AN AMPLIFIER - An amplifier (A | 2010-10-07 |
20100253433 | LOW PHASE NOISE AMPLIFIER CIRCUIT - The amplifier circuit ( | 2010-10-07 |
20100253434 | DISTRIBUTED AMPLIFICATION APPARATUS AND AMPLIFIER - Provided is a distributed amplification apparatus that outputs an output signal obtained by amplifying an input signal input thereto, comprising an input-side transmission line that transmits the input signal; an output-side transmission line that transmits the output signal; and a plurality of amplifiers that are provided in parallel between the input-side transmission line and the output-side transmission line, the amplifiers each amplifying the input signal transmitted on the input-side transmission line and supplying the amplified signal to the output-side transmission line. Each amplifier includes a transistor; a capacitor provided on a line that transmits the input signal to a gate terminal of the transistor; and a gate-ground resistance that is provided between the gate terminal of the transistor and a ground potential. | 2010-10-07 |
20100253435 | RF POWER AMPLIFIER CIRCUIT UTILIZING BONDWIRES IN IMPEDANCE MATCHING - A radio frequency amplifier module includes a first transmitting RF amplifier configured to produce a first amplified RF signal in response to an input RF signal, a second transmitting RF amplifier configured to produce a second amplified RF signal in response to the first amplified RF signal, and an inter-stage impedance matching circuit that is in part formed by a bond wire. | 2010-10-07 |
20100253436 | AMPLIFIER - An amplifier is realized by a distributed-constant-type amplifier including an input-side transmission line and an output-side transmission line, and a plurality of unit circuits coupled between the input-side transmission line and the output-side transmission line, in which each of the plurality of unit circuits is formed by including an amplification circuit having a gain equal to or greater than one. | 2010-10-07 |
20100253437 | METHOD AND SYSTEM FOR USING A MEMS STRUCTURE AS A TIMING SOURCE - A system and method is disclosed that provides a technique for generating an accurate time base for MEMS sensors and actuators which has a vibrating MEMS structure. The accurate clock is generated from the MEMS oscillations and converted to the usable range by means of a frequency translation circuit. | 2010-10-07 |
20100253438 | Phase Locked Loop Circuit - A PLL circuit comprises a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and two variable voltage sources. The phase detector and the charge pump each comprises low-voltage transistors, and operates with a fixed supply voltage VCC1 (e.g., 5 V) which is a potential difference applied from the variable voltage source of a power-supply voltage VL and the variable voltage source of a power-supply voltage VDC (=VL+VCC1). A tuning control signal VC generated by integrating an output current signal of the charge pump using the loop filter is input to the VCO having an input voltage range of the tuning control signal from 0 V to VCC2 (e.g., 16 V). At this time, the output voltage range of the tuning control signal is from VL to VDC, but the output voltage range is expanded to cover the full input voltage range from 0 V to VCC2 by controlling the output voltages VL, VDC of the variable voltage sources, thereby allowing the VCO to output an output signal with a desired oscillation frequency. | 2010-10-07 |
20100253439 | Electronic Circuitry - Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature. | 2010-10-07 |
20100253440 | Ring-Based Multi-Push Voltage-Controlled Oscillator - A ring-based multi-push voltage-controlled oscillator (VCO) with the control voltage to generate the multi-push output signal is disclosed. The ring-based multi-push VCO includes a plurality of delay cells, a plurality of buffer amplifiers, and a bias unit. The delay cells connect each other in sequence to form a ring structure, and each delay cell connects with the respective buffer amplifier. The bias unit connects with the buffer amplifiers to output the multi-push output signal. The control voltage supplied to the delay cells is utilized to control the frequency of the multi-push output signal, and the ring structure formed by delay cells is to multiply the frequency tuning range. | 2010-10-07 |
20100253441 | VARIABLE INDUCTOR - A variable simulated inductor comprises an integrator connected to receive the voltage across the input to the circuit. The output of the inductor is connected to a control terminal of a transconductor connected across the input of the circuit. The gain of the transconductor is electronically controllable in order to control the inductance of the circuit. An oscillator using a variable simulated inductor and a piezoelectric resonator connected in parallel is also provided. | 2010-10-07 |
20100253442 | Tank Tuning for Band Pass Filter Used in Radio Communications - A tuning method and circuit for an LC tank resonant circuit, including an inductor and a variable capacitor, are described. In a tuning mode, an RF input signal is applied to an input port of the circuit, and the RF output signal is monitored as a variable capacitor control input is varied. A peak output is detected, and the corresponding variable capacitor control input is stored, and applied to the variable capacitor in an operating mode. In one embodiment, the variable capacitor control input is adjusted for delay in the peak detection process. In one embodiment, the variable capacitor comprises a coarse capacitor and a fine capacitor; the tuning procedure is repeated for each capacitor; and both coarse and fine variable capacitor control inputs are stored and applied to the respective capacitors in operating mode. | 2010-10-07 |
20100253443 | UNBALANCED-BALANCED CONVERTER - A first balance electrode unit electrically connected to a pair of balance terminals (a first balance terminal and a second balance terminal) is formed on a main surface of a fourth dielectric layer sandwiched by an upper grounding electrode and a lower grounding electrode in a dielectric substrate. A second balance electrode unit electrically connected to a pair of balance terminals on the main surface of a seventh dielectric layer. An unbalance electrode unit electrically connected to an unbalance terminal is formed on the main surface of a fifth dielectric layer. | 2010-10-07 |
20100253444 | VARIABLE IMPEDANCE ADAPTER FOR TUNING SYSTEM PERFORMANCE - A variable impedance adapter that has a value of characteristic impedance that is responsive to changes in the configuration of the adapter. In one embodiment, the variable impedance adapter includes an elongated section and a telescoping section that surround a center conductor that transmits an electrical signal across the adapter. A pair of tuning elements is disposed on a portion of the center conductor, one or more of the elements being shaped and configured to move along the center conductor amongst a plurality of positions in response to relative movement between the elongated section and the telescoping section. The first position and the second position correspond to different values of characteristic impedance of the variable impedance adapter. | 2010-10-07 |
20100253445 | HIGH FREQUENCY SWITCH - Disclosed is a high frequency switch wherein a first switch circuit is connected in series to a first λ/4 signal transmission path connected between an antenna connecting terminal and a transmission terminal. In the first switch circuit, a first λ/4 transmission path and a first parallel resonant circuit, which includes one first PIN diode, are connected in series. In a first inductor of the first parallel resonant circuit, a constant is set so that a resonance frequency of the first parallel resonant circuit and the center frequency of a first antenna switch are the same when the first PIN diode is turned off. | 2010-10-07 |
20100253446 | METHOD AND DEVICE FOR PSEUDO-DIFFERENTIAL TRANSMISSION - The invention relates to a method and a device for pseudo-differential transmission in interconnections used for sending a plurality of electrical signals. The ends of an interconnection having 4 transmission conductors and a return conductor distinct from the reference conductor are each connected to a termination circuit. Three damping circuits are connected between the return conductor and the reference conductor. The transmitting circuits receive at their inputs the signals from the 4 channels of the two sources, and are connected to the conductors of the interconnection. The receiving circuits are connected to the conductors of the interconnection, each receiving circuit being such that the 4 channels of a source connected to a transmitting circuit in the activated state are sent to the four channels of the destinations without noticeable external crosstalk. | 2010-10-07 |
20100253447 | FILTER BANKS FOR ENHANCING SIGNALS USING OVERSAMPLED SUBBAND TRANSFORMS - For subband decomposition of a d-dimensional input signal (S) into a number K of subband components (F | 2010-10-07 |
20100253448 | Diplexer, and Wireless Communication Module and Wireless Communication Apparatus Using the Same - A diplexer that can demultiplex and multiplex two signals having wide frequency bands, and a wireless communication module and a wireless communication apparatus using the same, are provided. A diplexer has a multilayer body including a first interlayer, a second interlayer and a third interlayer. On the first interlayer, first resonant electrodes are disposed in an interdigital form. On the second interlayer, a plurality of second resonant electrodes are disposed in an interdigital form. On the third interlayer, there are disposed an input coupling electrode that faces the input-stage first resonant electrode and the input-stage second resonant electrode in an interdigital form, a first output coupling electrode that faces the output-stage first resonant electrode in an interdigital form, and a second output coupling electrode that faces the output-stage second resonant electrode. | 2010-10-07 |
20100253449 | METHOD AND SYSTEM FOR GENERATING QUADRATURE SIGNALS UTILIZING AN ON-CHIP TRANSFORMER - Aspects of a method and system for generating quadrature signals utilizing an on-chip transformer are provided. In this regard, a pair of phase-quadrature signals may be generated from a single-phase signal via a transformer, one or more variable capacitors, and one or more variable resistors integrated on-chip. The transformer may comprise a plurality of loops fabricated in a plurality of metal layers in the chip. Each of the one or more variable capacitors may comprise a configurable capacitor bank and each of the one or more variable resistors may comprise a configurable resistor bank. The one or more capacitor banks may be programmatically configured on-chip, based on a frequency of the single-phase signal. The one or more resistor banks may be programmatically configured on-chip, based on a frequency of said single-phase signal. | 2010-10-07 |
20100253450 | APPARATUS FOR TRANSITIONING MILLIMETER WAVE BETWEEN DIELECTRIC WAVEGUIDE AND TRANSMISSION LINE - Provided is an apparatus for transitioning a millimeter wave between dielectric waveguide and transmission line using a millimeter wave transition structure formed by the dielectric waveguide, the transmission line, and a slot to transition a signal with lower losses. The apparatus includes: transmission lines disposed respectively at input and output terminals on an uppermost dielectric substrate in a signal transition direction and adapted to transition a signal; a dielectric waveguide formed by a via array disposed between top and bottom ground surfaces of a lowermost dielectric substrate in the signal transition direction as a signal transition path; and slots disposed at a signal transition path of an upper ground surface of each dielectric substrate to connect the transmission lines to the dielectric waveguide so as to transition a signal from the transmission line of the input terminal to the transmission line of the output terminal through the dielectric waveguide. | 2010-10-07 |
20100253451 | ELECTROLYTIC CORROSION PREVENTION STRUCTURE AND WAVEGUIDE CONNECTION STRUCTURE - An electrolytic corrosion prevention structure at a flange connection part in which the occurrence of an electrolytic corrosion is suppressed without increasing the number of the airtight and/or watertight parts and that can be easily processed is provided.
| 2010-10-07 |
20100253452 | VEHICLE CABIN INTERIOR SURFACE WITH EMBEDDED MAGNETIC HOLDER - A magnetic holding system for a vehicle cabin includes a non-ferrous panel having a front side exposed to the vehicle cabin and a rear side. A magnet is located on the rear side of the non-ferrous panel. The thickness panel, in the region where the magnet is located, and the strength of the magnet are selected to grip a ferrous element when it is placed on the front side of the panel in the region where the magnet is located. The ferrous element may be an object to be held on the non-ferrous surface or it may be attachable to the underside of an object that is to be held. | 2010-10-07 |
20100253453 | COIL FOR ELECTROMAGNET - A coil for an electromagnet used in a clutch for a compressor of a vehicle is disclosed. The coil consists of a plurality of aluminum wires coated with an insulator and wound around a bobbin, in which the plurality of wires are simultaneously wound around the bobbin, and the wound wires are connected in parallel with each other. As compared with a copper wire, although a volume of the aluminum wires is increased, the whole resistance value is low, and thus, the heating value is reduced. Since the heating value of the aluminum wires is equal, the electromagnet has the same performance in a saturation state. | 2010-10-07 |
20100253454 | BALUN FOR MAGNETIC RESONANCE IMAGING - An inductive component in the form of a balun for use in magnetic resonance imaging tomographs comprises a winding of a coaxial line. For adjusting inductance of the winding, a length of the winding of the coaxial line is deformable. For this, a first end of the coaxial line is fastened to a first fastening block, and a second end to a second fastening block. Change of the length is effected by means of an adjusting screw which varies the distance between the two fastening blocks. | 2010-10-07 |
20100253455 | Ignition Coil for Vehicle - A spark plug coil assembly has a primary core bearing primary windings and a secondary winding spool around which secondary windings are wound and in which the primary core is received. A case receives the spool with core. The entire case can be made of composite Iron to function as a magnetic return path for the core, or a composite Iron shield can be overmolded to an otherwise plastic case. | 2010-10-07 |