40th week of 2010 patent applcation highlights part 15 |
Patent application number | Title | Published |
20100252855 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - In semiconductor light-emitting devices in which a light-emitting layer is formed on one surface of a substrate, and an n-side electrode and a p-side electrode are formed over the same surface of the substrate as the light-emitting layer, heat generated by a semiconductor light-emitting element needs to be dissipated to a submount. However, it is extremely complicated to fabricate connection members serving also as heat dissipating members and to control fabrication of the connection members, according to semiconductor light-emitting elements having electrodes of various sizes and shapes. By increasing the density of p-side bumps near the n-side electrode, the heat transfer area from the semiconductor light-emitting element to the submount is increased near the n-side electrode, whereby the heat dissipation effect is enhanced. | 2010-10-07 |
20100252856 | Header structure of opto-electronic element and opto-electronic element using the same - An opto-electronic element includes a header and an opto-electronic chip. The header have a metal stem and an insulating structure, and the opto-electronic chip located on the stem or insulating structure. The opto-electronic chip is grown with an epitaxy layer structure on a thicker and homogeneous electroconductive base, and the electrodes are located on the same side and have the same metal structure. Thus, the chip is located on the insulating structure and isolated from each electrode, and the chip and header are kept in an insulated state. Furthermore, an auxiliary pin for supporting the chip and for forming an open circuit or serving as an electrode of the chip is located in an axial direction of the insulating structure. The combination of the stem and insulating structure may be replaced with a non-metal stem with a corresponding shape, and a periphery of the non-metal stem may further have an extended wall portion combined with a cap to form the opto-electronic element. | 2010-10-07 |
20100252857 | ORGANIC EL DEVICE, EL DISPLAY PANEL, METHOD FOR MANUFACTURING THE ORGANIC EL DEVICE AND METHOD FOR MANUFACTURING THE EL DISPLAY PANEL - Disclosed is a method for manufacturing an organic EL device which comprises a hole injection layer having a flat surface that is not contaminated. Specifically disclosed method for manufacturing an organic EL device, which comprises a step of forming an anode on a substrate; a step of forming a hole injection layer on the anode; a step of forming an inorganic film on the substrate and the hole injection layer; a step of forming a bank on the inorganic film in such a manner that at least a part of the inorganic film formed on the hole injection layer is exposed; a step of etching the exposed inorganic film by using the bank as a mask so that the hole injection layer is exposed therefrom; and a step of forming an organic light-emitting layer by applying an organic light-emitting material onto the exposed hole injection layer. The hole injection layer contains tungsten oxide or molybdenum oxide. | 2010-10-07 |
20100252858 | GLASS, COATING MATERIAL FOR LIGHT-EMITTING DEVICES AND LIGHT-EMITTING DEVICE - To provide glass with which a sealing treatment can be carried out at a temperature of at most 400° C. and which does not deteriorate or change in quality for a long time. | 2010-10-07 |
20100252859 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor light emitting device and a method of fabricating the same. The semiconductor light emitting device comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer. The first conductive type semiconductor layer comprises an insulation layers comprising a predetermined interval and a voids between the insulation layers. The active layer is disposed on the first conductive type semiconductor layer. The second conductive type semiconductor layer is disposed on the active layer. | 2010-10-07 |
20100252860 | LATERAL BIPOLAR JUNCTION TRANSISTOR WITH REDUCED BASE RESISTANCE - A lateral bipolar junction transistor formed in a semiconductor substrate includes an emitter region; a base region surrounding the emitter region; a gate disposed at least over a portion of the base region; a collector region having at least one open side and being disposed about a periphery of the base region; a shallow trench isolation (STI) region disposed about a periphery of the collector region; a base contact region disposed about a periphery of the STI region; and an extension region merging with the base contact region and laterally extending to the gate on the open side of the collector region. | 2010-10-07 |
20100252861 | Devices Formed from a Non-Polar Plane of a Crystalline Material and Method of Making the Same - Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region. | 2010-10-07 |
20100252862 | Source/Drain Engineering of Devices with High-Mobility Channels - An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof. | 2010-10-07 |
20100252863 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device which reduces a source resistance and a manufacturing method for the same are provided. The semiconductor device has a nitride based compound semiconductor layer arranged on a substrate, an active region which has an aluminum gallium nitride layer arranged on the nitride based compound semiconductor layer, and a gate electrode, source electrode and drain electrode arranged on the active region. The semiconductor device has gate terminal electrodes, source terminal electrodes and drain terminal electrode connected to the gate electrode, source electrode and drain electrode respectively. The semiconductor device has end face electrodes which are arranged on a side face of the substrate by a side where the source terminal electrode is arranged, and which are connected to the source terminal electrode. The semiconductor device has a projection arranged on the end face electrode which prevents solder used in die bonding from reaching the source terminal electrodes. | 2010-10-07 |
20100252864 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor device which reduces source resistance and a manufacturing method for the same are provided. A semiconductor device has a nitride based compound semiconductor layer on a substrate and an active region on the nitride based compound semiconductor layer. The semiconductor device has a gate electrode, a source electrode and a drain on the active region, a source terminal electrode connected to the source electrode arranged on the nitride based compound semiconductor layer in a direction which the source electrode extends. Furthermore, the semiconductor device has an end face electrode which is arranged on the end face of the substrate in a source terminal electrode side, is connected to the source terminal electrode, and includes a multilayer metal layer including three or more layers which includes different metals, and prevents solder for die bonding from reaching the source terminal electrode. | 2010-10-07 |
20100252865 | ELECTRONIC DEVICE - The invention relates to an electronic device having a semiconductor die comprising at least one RF-transistor (RFT) occupying a total RF-transistor active area (ARFT) on the die (DS). The total RF-transistor active area (ARFT) includes at least one transistor channel (C) having a channel width (W) and a channel length (L), and at least one bias cell (BC) for biasing the RF-transistor (RFT). The total bias cell active area (ABC) includes at least one transistor channel (C) having a channel width (W) and a channel length (L). The at least one bias cell (BC) occupies a total bias cell active area (ABC) on the die (SD). The total RF-transistor active area (ARFT) is substantially greater than the total bias cell active area (ABC). The total bias cell active area (ABC) has a common centre of area (COABC). The total RF-transistor active area (ARFT) has a common centre of area (COARF). The active areas (ABC, ARFT) are arranged such that both, the common centre of area or sub-areas of the RF-transistor (COARF) and the common centre of area or sub-areas of the bias cell (COABC) are positioned on an axis (AX | 2010-10-07 |
20100252866 | TRANSISTOR HAVING A CHANNEL WITH TENSILE STRAIN AND ORIENTED ALONG A CRYSTALLOGRAPHIC ORIENTATION WITH INCREASED CHARGE CARRIER MOBILITY - By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the <100> direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four. | 2010-10-07 |
20100252867 | MFMS-FET, Ferroelectric Memory Device, And Methods Of Manufacturing The Same - Disclosed herein are a metal-ferroelectric-metal-substrate (MFMS) field-effect transistor (FET), an MFMS-ferroelectric memory device, and method of manufacturing the same. The MFMS-FET and the ferroelectric memory device in accordance with the present invention include: a substrate including source and drain regions, and a channel region formed therebetween; a buffer layer formed on the top of the channel region of the substrate; a ferroelectric layer formed on the buffer layer; and a gate electrode formed on the ferroelectric layer, wherein the buffer layer is formed of a conductive material. | 2010-10-07 |
20100252868 | ENHANCED FIELD EFFECT TRANSISTOR - An enhanced FET capable of controlling current above and below a gate of the FET. The FET is formed on a semiconductor substrate. A source and drain are formed in the substrate (or in a well in the substrate). A first epitaxial layer of similar doping to the source and drain are grown on the source and drain, the first epitaxial layer is thicker than the gate, but not so thick as to cover the top of the gate. A second epitaxial layer of opposite doping is grown on the first epitaxial layer thick enough to cover the top of the gate. The portion of the second epitaxial layer above the gate serves as a body through which the gate controls current flow between portions of the first epitaxial layer over the drain and the source. | 2010-10-07 |
20100252869 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a gate electrode formed on a semiconductor substrate via a gate insulating film; Si:C layers formed on the semiconductor substrate in sides of the gate electrode; p-type source/drain regions formed in sides of the gate electrode in the semiconductor substrate, and a part of the p-type source/drain regions being formed in the Si:C layers; and silicide layers formed on the Si:C layers. | 2010-10-07 |
20100252870 | DUAL SHALLOW TRENCH ISOLATION AND RELATED APPLICATIONS - Embodiments of the invention relate to dual shallow trench isolations (STI). In various embodiments related to CMOS Image Sensor (CIS) technologies, the dual STI refers to one STI structure in the pixel region and another STI structure in the periphery or logic region. The depth of each STI structure depends on the need and/or isolation tolerance of devices in each region. In an embodiment, the pixel region uses NMOS devices and the STI in this region is shallower than that of in the periphery region that includes both NMOS and PMOS device having different P- and N-wells and that desire more protective isolation (i.e., deeper STI). Depending on implementations, different numbers of masks (e.g., two, three) are used to generate the dual STI, and are disclosed in various method embodiments. | 2010-10-07 |
20100252871 | LIGHT SENSORS WITH INFRARED SUPPRESSION - Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors. | 2010-10-07 |
20100252872 | NONVOLATILE FERROELECTRIC MEMORY DEVICE - A nonvolatile ferroelectric memory device includes a plurality of unit cell arrays, wherein each of the plurality of unit cell arrays includes: a bottom word line; a plurality of insulating layers formed on the bottom word line, respectively; a floating channel layer comprising a plurality of channel regions located on the plurality of insulating layers and a plurality of drain and source regions which are alternately electrically connected in series to the plurality of channel regions; a plurality of ferroelectric layers formed respectively on the plurality of channel regions of the floating channel layer; and a plurality of word lines formed on the plurality of ferroelectric layers, respectively. The unit cell array reads and writes a plurality of data by inducing different channel resistance to the plurality of channel regions depending on polarity states of the plurality of ferroelectric layers. | 2010-10-07 |
20100252873 | TRENCH STRUCTURE AND METHOD OF FORMING THE TRENCH STRUCTURE - Disclosed are embodiments of an improved deep trench capacitor structure and memory device that incorporates this deep trench capacitor structure. The deep trench capacitor and memory device embodiments are formed on a semiconductor-on-insulator (SOI) wafer such that the insulator layer remains intact during subsequent deep trench etch processes and, optionally, such that the deep trench of the deep trench capacitor has different shapes and sizes at different depths. By forming the deep trench with different shapes and sizes at different depths the capacitance of the capacitor can be selectively varied and the resistance of the buried conductive strap which connects the capacitor to a transistor in a memory device can be reduced. | 2010-10-07 |
20100252874 | Memory Device - One or more embodiments relate to a floating gate memory device, comprising: a substrate; a floating gate disposed over the substrate; and a control gate substantially laterally surrounding at least a portion of the floating gate. | 2010-10-07 |
20100252875 | STRUCTURE AND FABRICATING PROCESS OF NON-VOLATILE MEMORY - A structure of a non-volatile memory is described, including a substrate, isolation structures disposed in and protrudent over the substrate, floating gates as conductive spacers on the sidewalls of the isolation structures protrudent over the substrate, and a tunneling layer between each floating gate and the substrate. A process for fabricating a non-volatile memory is also described. Isolation structures are formed in a substrate protrudent over the same, a tunneling layer is formed over the substrate, and then floating gates are formed as conductive spacers on the sidewalls of the first isolation structures protrudent over the substrate. | 2010-10-07 |
20100252876 | Structure and method for forming an oscillating MOS transistor and nonvolatile memory - With simply applying the gate voltage, the transistor will start sending out oscillating signals, working like a semiconductor “engine”. A special MOS field effect transistor (FET) includes an extended lightly doped drain and an intrinsic undoped or very lightly doped “gap” between the gate and the heavily doped source. The gap needs to be specially engineered so that the transistor is not always turned on by the MOSFET gate voltage, but will be turned on by the carriers from the forward-biased channel-drain junction diode. Oscillation occurs to the drain current (or voltage) when a suitable gate voltage is applied, due to the repeated back and forth actions of deep depletion in the transistor well and forward bias of the drain-well p-n junction diode. By forming a second spacer gate on one side of the main gate, the device can be used as a non-volatile memory, with the charges stored at the dielectrics / silicon interface, which can significantly impact the oscillating for the READ operation of a memory. This device can also be a frequency amplifier. | 2010-10-07 |
20100252877 | Non-Volatile Semiconductor Memory Devices Having Charge Trap Layers Between Word Lines and Active Regions Thereof - A non-volatile memory device includes: word line disposed on a substrate; an active region crossing over the word line; and a charge trap layer that is between the word line and the active region. | 2010-10-07 |
20100252878 | NON-VOLATILE MEMORY CELL - A super-silicon-rich oxide (SSRO) non-volatile memory cell includes a gate conductive layer on a substrate, a source/drain in the substrate at respective sides of the gate conductive layer, a tunneling dielectric layer between the gate conductive layer and the substrate, a SSRO layer serving as a charge trapping layer between the gate conductive layer and the tunneling dielectric layer, and an upper-dielectric layer between the gate conductive layer and the SSRO layer. | 2010-10-07 |
20100252879 | Semiconductor device and method of forming the same - A semiconductor device includes a semiconductor substrate; a well of a first conductivity type in the semiconductor substrate; a first element; and a first vertical transistor. The first element supplies potential to the well, the first element being in the well. The first element may include, but is not limited to, a first pillar body of the first conductivity type. The first pillar body has an upper portion that includes a first diffusion layer of the first conductivity type. The first diffusion layer is greater in impurity concentration than the well. The first vertical transistor is in the well. The first vertical transistor may include a second pillar body of the first conductivity type. The second pillar body has an upper portion that includes a second diffusion layer of a second conductivity type. | 2010-10-07 |
20100252880 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, AND A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises the steps of, in sequence: depositing a first silicon layer; patterning the first silicon layer to obtain a first silicon region; implanting a first dopant into a first part of the first silicon region, the first part of the first silicon region defined using a first mask; depositing a second silicon layer; patterning the second silicon layer to obtain a second silicon region; and implanting a second dopant into a second part of the first silicon region, the second part of the first silicon region defined by the first mask and the second silicon region. | 2010-10-07 |
20100252881 | CMOS DIODES WITH DUAL GATE CONDUCTORS, AND METHODS FOR FORMING THE SAME - The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor. | 2010-10-07 |
20100252882 | MOS Transistor with Gate Trench Adjacent to Drain Extension Field Insulation - An integrated circuit containing an MOS transistor with a trenched gate abutting an isolation dielectric layer over a drift region. The body well and source diffused region overlap the bottom surface of the gate trench. An integrated circuit containing an MOS transistor with a first trenched gate abutting an isolation dielectric layer over a drift region, and a second trenched gate located over a heavily doped buried layer. The buried layer is the same conductivity type as the drift region. A process of forming an integrated circuit containing an MOS transistor, which includes an isolation dielectric layer over a drift region of a drain of the transistor, and a gate formed in a gate trench which abuts the isolation dielectric layer. The gate trench is formed by removing substrate material adjacent to the isolation dielectric layer. | 2010-10-07 |
20100252883 | Lateral High-Voltage Semiconductor Devices with Majorities of Both Types for Conduction - This invention provides a lateral high-voltage semiconductor device, which is a three-terminal one with two types of carriers for conduction and consists of a highest voltage region and a lowest voltage region referring to the substrate and a surface voltage-sustaining region between the highest voltage region and the lowest voltage region. The highest voltage region and the lowest region have an outer control terminal and an inner control terminal respectively, where one terminal is for controlling the flow of majorities of one conductivity type and another for controlling the flow of majorities of the other conductivity type. The potential of the inner control terminal is regulated by the voltage applied to the outer control terminal. The figure presented schematically shows a device by using an n-MOSFET to control the flow of electrons and a pnp bipolar transistor to control the flow of holes, and the potential of the base region of the pnp transistor is regulated by the voltage applied to the gate electrode of the n-MOSFET. | 2010-10-07 |
20100252884 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an insulating layer; a semiconductor layer formed on the insulating layer; a first partially depleted transistor formed in the semiconductor layer; and a second transistor formed in the semiconductor layer, wherein the first transistor has a first gate electrode formed above the semiconductor layer via an insulating film and a first source or a first drain of a first conductivity type formed in the semiconductor layer below both sides of the first gate electrode, the second transistor has a second gate electrode formed above the semiconductor layer via an insulating film and a second source or a second drain of a second conductivity type formed in the semiconductor layer below both sides of the second gate electrode, and one of the second source and the second drain is electrically connected to the semiconductor layer in a region just below the first gate electrode. | 2010-10-07 |
20100252885 | SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - A semiconductor device ( | 2010-10-07 |
20100252886 | FIN STRUCTURES AND METHODS OF FABRICATING FIN STRUCTURES - There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins. | 2010-10-07 |
20100252887 | Damage Implantation of a Cap Layer - A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer. | 2010-10-07 |
20100252888 | SEMICONDUCTOR DEVICE - A semiconductor device includes a field-effect transistor on a substrate. The field-effect transistor includes a gate insulating film and a gate electrode. The gate electrode has a laminated structure including a first electrode layer made of a first metal, a second electrode layer made of a second metal, and a third electrode layer made of a silicon layer. The second metal is a material having a workfunction for alleviating band discontinuity between the first electrode layer and the third electrode layer, with respect to a majority carrier of the silicon layer. | 2010-10-07 |
20100252889 | Linear Gate Level Cross-Coupled Transistor Device with Contiguous p-type Diffusion Regions and Contiguous n-type Diffusion Regions - A semiconductor device includes a substrate having a plurality of diffusion regions defined therein to form first and second p-type diffusion regions, and first and second n-type diffusion regions, with each of these diffusion regions electrically connected to a common node. The first p-type active area and the second p-type active area are contiguously formed together. The first n-type active area and the second n-type active area are contiguously formed together. Each of a number of conductive features within a gate electrode level region of the semiconductor device is fabricated from a respective originating rectangular-shaped layout feature. A centerline of each originating rectangular-shaped layout feature is aligned in a parallel manner. A first PMOS transistor gate electrode is electrically connected to a second NMOS transistor gate electrode, and a second PMOS transistor gate electrode is electrically connected to a first NMOS transistor gate electrode. | 2010-10-07 |
20100252890 | Linear Gate Level Cross-Coupled Transistor Device with Non-Overlapping PMOS Transistors and Non-Overlapping NMOS Transistors Relative to Direction of Gate Electrodes - A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions. | 2010-10-07 |
20100252891 | Linear Gate Level Cross-Coupled Transistor Device with Equal Width PMOS Transistors and Equal Width NMOS Transistors - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are substantially equal, such that the first and second PMOS transistor devices have substantially equal widths. Widths of the first and second n-type diffusion regions are substantially equal, such that the first and second NMOS transistor devices have substantially equal widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration. | 2010-10-07 |
20100252892 | Channelized Gate Level Cross-Coupled Transistor Device with Different Width PMOS Transistors and Different Width NMOS Transistors - A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are different, such that the first and second PMOS transistor devices have different widths. Widths of the first and second n-type diffusion regions are different, such that the first and second NMOS transistor devices have different widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration. | 2010-10-07 |
20100252893 | Channelized Gate Level Cross-Coupled Transistor Device with Cross-Coupled Transistors Defined on Three Gate Electrode Tracks with Crossing Gate Electrode Connections - A semiconductor device includes conductive features that are each defined within any one gate level channel uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along second and third gate electrode tracks, respectively. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. | 2010-10-07 |
20100252894 | Memory devices having diodes and methods of fabricating the same - A non-volatile memory devices includes: a substrate including a circuit device and a metal line electrically connected with the circuit device; a diode connected with the metal line in a vertical direction with respect to a surface of the substrate, and including a metal layer disposed on a lower part of the diode facing the surface of the substrate; and a resistor electrically connected with the diode in series. | 2010-10-07 |
20100252895 | APPARATUS OF MEMORY ARRAY USING FINFETS - A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element. | 2010-10-07 |
20100252896 | Methods, Structures, and Designs for Self-Aligning Local Interconnects used in Integrated Circuits - Methods, structures and designs for self-aligned local interconnects are provided. The method includes designing diffusion regions to be in a substrate. Some of a plurality of gates are designed to be active gates and some of the plurality of gates are designed to be formed over isolation regions. The method includes designing the plurality of gates in a regular and repeating alignment along a same direction, and each of the plurality of gates are designed to have dielectric spacers. The method also includes designing a local interconnect layer between or adjacent to the plurality of gates. The local interconnect layer is conductive and disposed over the substrate to allow electrical contact and interconnection with or to some of the diffusion regions of the active gates. The local interconnect layer is self-aligned by the dielectric spacers of the plurality of gates. | 2010-10-07 |
20100252897 | PERFORMANCE-ENHANCING TWO-SIDED MEMS ANCHOR DESIGN FOR VERTICALLY INTEGRATED MICROMACHINED DEVICES - An anchoring assembly for anchoring MEMS device is disclosed. The anchoring assembly comprises: a top substrate; a bottom substrate substantially parallel to the top substrate; and a first portion of the anchor between the top substrate and the bottom substrate. The first portion of the anchor is rigidly connected to the top substrate; and the first portion of the anchor is rigidly connected to the bottom substrate. A second portion of the anchor is between the top substrate and the bottom substrate. The second portion of the anchor is rigidly connected to the top substrate; the second portion of the anchor being an anchoring point for the MEMS device. A substantially flexible mechanical element coupling the first portion of the anchor and the second portion of the anchor; the flexible element providing the electrical connection between the first portion of the anchor and the second portion of the anchor. | 2010-10-07 |
20100252898 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, and a sealing member. The first semiconductor substrate has a surface and includes a sensing portion on the surface side. The sensing portion has a movable portion. The first semiconductor substrate and the second semiconductor substrate are bonded together to form a stacked substrate. The stacked substrate defines a hermetically sealed space for accommodating the sensing portion between the first and second semiconductor substrates. The stacked substrate further defines a recess extending between the first semiconductor substrate and the second semiconductor substrate to penetrate an interface between the first semiconductor substrate and the second semiconductor substrate. The sealing member is located in the recess. | 2010-10-07 |
20100252899 | PACKAGE INTERFACE PLATE FOR PACKAGE ISOLATION STRUCTURES - A package assembly comprises a package base, a sensor die, an isolation plate, and a package interface plate. The isolation plate is bonded to the sensor die and has a plurality of flexible beams. Each flexible beam is configured to deflect under stress such that effects on the sensor die of a thermal mismatch between the package base and the sensor die are reduced. The package interface plate is bonded to the isolation plate and the package base. The package interface plate is configured to limit the maximum distance each flexible beam is able to deflect. | 2010-10-07 |
20100252900 | Vertical Hall Sensor and Method of Producing a Vertical Hall Sensor - Through a main surface ( | 2010-10-07 |
20100252901 | FERROELECTRIC THIN FILMS - Ferroelectric structures and methods of making the structures are presented. The ferroelectric structures can include an electrode in contact with a ferroelectric thin film. The contact can be arranged so that a portion of the atoms of the ferroelectric thin film are in contact with at least a portion of the atoms of the electrode. The electrode can be made of metal, a metal alloy, or a semiconducting material. A second electrode can be used and placed in contact with the ferroelectric thin film. Methods of making and using the ferroelectric structures are also presented. | 2010-10-07 |
20100252902 | SEMICONDUCTOR DEVICE AND IMAGING DEVICE USING THE SEMICONDUCTOR DEVICE - A semiconductor device, includes: a semiconductor substrate including a first surface and a second surface which are opposite to one another; a light receiving portion provided at the first surface of the semiconductor substrate; and an optical transparent protective member so as to cover and to be adjacent to the first surface or the second surface of the semiconductor substrate; wherein a plurality of depressed portions are formed at the optical transparent protective member so as to be opposite to the light receiving portion. | 2010-10-07 |
20100252903 | PHOTOELECTRIC TRANSDUCER AND MANUFACTURING METHOD THEREFOR - The surrounding length of a junction separation portion can be shortened to improve an insulating resistance in order to provide a solar cell with highly efficiency. | 2010-10-07 |
20100252904 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling. | 2010-10-07 |
20100252905 | LOCOS NITRIDE CAPPING OF DEEP TRENCH POLYSILICON FILL - A polysilicon-filled isolation trench in a substrate is effective to isolate adjacent semiconductor devices from one another. A silicon nitride cap is provided to protect the polysilicon in the isolation trench from subsequent field oxidation. The cap has lateral boundaries that extend between the side boundaries of the polysilicon and the sidewalls of the trench. Subsequent field oxide regions formed adjacent to the trench establish a gap dimension from the substrate to a top surface of the field oxide regions adjacent to the polysilicon side boundaries that is no less than half of the field oxide thickness. | 2010-10-07 |
20100252906 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device including a thin film device unit including a TFT, and a peripheral device unit provided around the thin film device unit and including a semiconductor element, includes a first step of preparing a substrate, a second step of bonding the peripheral device unit directly to the substrate, and a third step of forming the thin film device unit on the substrate to which the peripheral device unit is bonded. | 2010-10-07 |
20100252907 | Shallow Trench Isolation Dummy Pattern and Layout Method Using the Same - A dummy cell pattern for shallow trench isolation (STI). Active and shallow trench isolation areas are bounded by a circumference. An active area pattern completely overlaps the active area and a first polysilicon pattern in the shallow trench isolation area is outside the active area pattern. Layout methods using the same are also disclosed. | 2010-10-07 |
20100252908 | ELECTRICALLY ALTERABLE CIRCUIT FOR USE IN AN INTEGRATED CIRCUIT DEVICE - An electrically alterable circuit (EAC), suitable for use in an integrated circuit, includes a first interconnect, a link element, and a second interconnect. A first set of interconnect vias provides an electrically conductive connection between the first interconnect and a first end of the link element; A second set of interconnect vias provides an electrically conductive connection between the second interconnect and a second end of the link element. The EAC further includes a third interconnect and a one or more fuse vias that provide an electrical connection between the third interconnect and the link element. A conductance of the one or more fuse vias is less than a conductance of the first set of interconnect vias, a conductance of the second set of interconnect vias, or both. | 2010-10-07 |
20100252909 | Three-Dimensional Memory Devices - An integrated circuit memory device may include a semiconductor substrate and a plurality of word-line layers wherein adjacent word-line layers are separated by respective word-line insulating layers. A plurality of active pillars may extend from a surface of the semiconductor substrate through the plurality of word-line layers and insulating layers. Dielectric information storage layers may be provided between the active pillars and the respective word-line layers. Related methods of operation and fabrication are also discussed. | 2010-10-07 |
20100252910 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a conventional semiconductor device, part of a dielectric film of a capacitive element is removed when photoresist is peeled off, and this causes problems of variation in capacitance value of the capacitive element and deterioration of breakdown voltage characteristics. In a semiconductor device according to the present invention, a silicon nitride film serving as a dielectric film is formed on the top face of a lower electrode of a capacitive element, and an upper electrode is formed on the top face of the silicon nitride film. The upper electrode is formed of a laminated structure having a silicon film and a polysilicon film protecting the silicon nitride film. This structure prevents part of the silicon nitride film from being removed when, for example, photoresist is peeled off, thereby preventing variation in capacitance value of the capacitive element and deterioration of the breakdown voltage characteristics. | 2010-10-07 |
20100252911 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor. | 2010-10-07 |
20100252912 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device, comprising the steps of preparing a structure including a semiconductor substrate, an element formed therein, a through hole formed to penetrate the semiconductor substrate, and an insulating layer formed on both surface sides of the semiconductor substrate and an inner surface of the through hole, and covering the element, forming a penetrating electrode in the through hole, forming a first barrier metal pattern layer covering the penetrating electrode, forming a contact hole reaching a connection portion of the element in the insulating layer, removing a natural oxide film on the connection portion of the element in the contact hole, and forming a wiring layer connected to the first barrier metal pattern layer and connected to the element through the contact hole. | 2010-10-07 |
20100252913 | SEMICONDUCTOR DEVICE - A GaN layer is grown on a sapphire substrate, an SiO | 2010-10-07 |
20100252914 | OPTICAL SEMICONDUCTOR DEVICE WITH A CONCENTRATION OF RESIDUAL SILICON - In a crystal growth reactor, a source material having an etching action and a crystal growth source material are simultaneously supplied to a semiconductor wafer surface, so that residual impurities can be eliminated in an efficient manner by balancing etching rate and crystal growth rate. | 2010-10-07 |
20100252915 | MICROELECTRONIC DEVICE WAFERS AND METHODS OF MANUFACTURING - Methods of forming microelectronic device wafers include fabricating a plurality of semiconductor dies at an active side of a semiconductor wafer, depositing a mask on the semiconductor wafer, removing a central portion of the mask and the semiconductor wafer, and etching. The semiconductor wafer has an outer perimeter edge and a backside that is spaced from the active side by a first thickness. The mask is deposited on the backside of the semiconductor wafer and has a face that is spaced from the backside by a mask thickness. The thinned portion has a thinned surface that is spaced from the active side by a second thickness that is less than the first thickness, and the thinned surface is etched. | 2010-10-07 |
20100252916 | STRUCTURE FOR IMPROVING DIE SAW QUALITY - A semiconductor device is provided that includes a semiconductor substrate, a plurality of dies formed on the semiconductor substrate, the plurality of dies being separated from one another by a first region extending along a first direction and a second region extending along a second direction different from the first direction, a dummy metal structure formed within a third region that includes a region defined by an intersection of the first region and the second region, a plurality of metal interconnection layers formed over the substrate, and a plurality of dielectric layers formed over the substrate. Each of the metal interconnection layers is disposed within each of the dielectric layers and a dielectric constant of at least one of the dielectric layers is less than about 2.6. | 2010-10-07 |
20100252917 | CARBOSILANE POLYMER COMPOSITIONS FOR ANTI-REFLECTIVE COATINGS - A silicon polymer material, which has a silicon polymer backbone with chromophore groups attached directly to at least a part of the silicon atoms, the polymer further exhibiting carbosilane bonds. The film forming composition and resulting coating properties can be tailored to suit the specific exposure wavelength and device fabrication and design requirements. By using two different chromophores the refractive index and the absorption co-efficient can be efficiently tuned. By varying the proportion of carbosilane bonds, and a desired Si-content of the anti-reflective coating composition can be obtained. | 2010-10-07 |
20100252918 | MULTI-DIE PACKAGE WITH IMPROVED HEAT DISSIPATION - The present invention discloses a multi-die package which facilitates heat dissipation for a high power consumption die. In the package, part of the lead frame is bent so as to be exposed at the surface of the package. On the opposite side of the exposed surface, a high power consumption die is attached. The other die with lower power consumption is not at the surface of the multi-die package. | 2010-10-07 |
20100252919 | ELECTRONIC DEVICE AND METHOD OF PACKAGING AN ELECTRONIC DEVICE - An electronic device can include a package device structure including a die encapsulated within a packaging material. The package device structure can have a first side and a second side opposite the first side. The electronic device can include a first layer along the first side of the package device structure. The first layer can be capable of causing a first deformation of the package device structure. The electronic device can also include a second layer along the second side of the package device structure. The second layer can be capable of causing a second deformation of the package device structure, the second deformation opposite the first deformation. | 2010-10-07 |
20100252920 | Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates - In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at least one non-system functional pin located in the at least one functional pin depopulation zone. Other embodiments are described and claimed. | 2010-10-07 |
20100252921 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device includes: a semiconductor element that has a first surface on which an electrode terminal is formed and a second surface opposite to the first surface; a resin mold portion in which the semiconductor element is embedded and that has a third surface exposing the first surface and a fourth surface opposite to the third surface; and a wiring layer formed on the third surface and the first surface, wherein a plurality of conducting portions are provided in the resin mold portion, which penetrate the resin mold portion along a thickness direction thereof to be electrically connected to the wiring layer. | 2010-10-07 |
20100252922 | Power Semiconductor Module, Power Semiconductor Module Assembly and Method for Fabricating a Power Semiconductor Module Assembly - The invention relates to a power semiconductor module including a power semiconductor chip arranged on a substrate and comprising a bottom side facing the substrate, a top side facing away from the substrate, and an electrical contact face arranged on the top side. A bond wire is bonded to the contact face. At least when the power semiconductor module is fastened to a heatsink, a contact pressure element creates a contact pressure force (F) acting on a sub-portion | 2010-10-07 |
20100252923 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device of the present invention includes a semiconductor chip formed with an electrode pad on a front side thereof, a wiring board having a wiring pattern, the wiring board having a front side opposing the back side of the semiconductor chip, a wire for electrically connecting the electrode pad of the semiconductor chip with the wiring pattern of the wiring board, an external terminal arranged on the back side of the wiring board for electrical connection with the electrode pad through the wire and the wiring pattern, and a sealant for fixing the semiconductor chip on the front side of the wiring board so as to form a hollow which is continuous to a portion straddling the entirety of the back side of the semiconductor chip and the front side of the wiring board, and continuous to a portion adjacent to at least one outer peripheral surface of the semiconductor chip except for the back side of the same. The wiring board includes a throughhole in communication with the hollow. | 2010-10-07 |
20100252924 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another. | 2010-10-07 |
20100252925 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor chip having a rectangular surface on which a plurality of electrodes are formed; a plurality of resin protrusions formed on the surface of the semiconductor chip; and a plurality of interconnects each of which is electrically connected to one of the electrodes and includes an electrical connection section disposed on one of the resin protrusions. At least part of the resin protrusions are disposed in a region near a short side of the surface and extend in a direction which intersects the short side. | 2010-10-07 |
20100252926 | Semiconductor Element, Method for Manufacturing the Same, and Mounting Structure Having the Semiconductor Element Mounted Thereon - A semiconductor element that is excellent in both mechanical reliability and electrical reliability and a mounting structure for the semiconductor element are provided. | 2010-10-07 |
20100252927 | Pattern-Print Thin-Film Transistors with Top Gate Geometry - A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode. | 2010-10-07 |
20100252928 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first conductor formed over a semiconductor device; an insulation film formed over the semiconductor substrate and the first conductor and having an opening arriving at the first conductor; a first film formed in the opening and formed of a compound containing Zr; a second film formed over the first film in the opening and formed of an oxide containing Mn; and a second conductor buried in the opening and containing Cu. | 2010-10-07 |
20100252929 | GROUP II ELEMENT ALLOYS FOR PROTECTING METAL INTERCONNECTS - A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and methods to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect. | 2010-10-07 |
20100252930 | Method for Improving Performance of Etch Stop Layer - A method of forming an interconnect structure includes providing a dielectric layer; forming a metal line in the dielectric layer; and forming a composite etch stop layer (ESL), which includes forming a lower ESL over the metal line and the dielectric layer; and forming an upper ESL over the lower ESL. The upper ESL and the lower ESL have different compositions. The step of forming the lower ESL and the step of forming the upper ESL are in-situ performed. | 2010-10-07 |
20100252931 | FLASH MEMORY STORAGE APPARATUS - A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host. | 2010-10-07 |
20100252932 | SENSOR DEVICE AND METHOD OF MANUFACTURING THE SENSOR DEVICE - A sensor device includes a substrate which includes an element forming region, a plurality of sensor elements formed in the element forming region, a plurality of connection pads formed on a region of the substrate other than the element forming region, a plurality of first wiring formed on the substrate and electrically connected with the plurality of sensor elements, a plurality of second wiring formed on the substrate and electrically connected with the plurality of connection pads, a plurality of third wiring formed on a different layer to the plurality of first wiring and the plurality of second wiring and formed to intersect with the plurality of first wiring and the plurality of second wiring, and an insulation layer formed between the plurality of first wiring, the plurality of second wiring and the plurality of third wiring. | 2010-10-07 |
20100252933 | SEMICONDUCTOR DEVICE - As etch-stop films or Cu-diffusion barrier films used in insulation films constituting conductor layers of a stacked structure, films having smaller dielectric constant than silicon nitride films are used, and an insulation film at a lower-layer part of the stacked structure is made to have smaller dielectric constant than that at an upper-layer part thereof, and further this insulation film is a silicon oxide (SiO) film and has, in the interior thereof, nano-pores of from 0.05 nm or more to 4 nm or less in diameter as chief construction. This makes it possible to dramatically reduce effective dielectric constant while keeping the mechanical strength of the conductor layers themselves, and can materialize a highly reliable and high-performance semiconductor device having mitigated the wiring delay of signals which pass through wirings. | 2010-10-07 |
20100252934 | Three-Dimensional Semiconductor Architecture - A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate. | 2010-10-07 |
20100252935 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a method for fabricating the same according to an embodiment. In the method, a portion of a substrate comprising a pad is removed to form a via hole. An insulating layer is formed on the substrate. A portion of the insulating layer is removed to form an opening part comprising a plurality of openings exposing portions of the pad. A through electrode is formed to fill the via hole and to be electrically connected to the pad through one of the plurality of openings. A portion of the pad is exposed by another opening among the plurality of openings. | 2010-10-07 |
20100252936 | SEMICONDUCTOR MODULE AND PORTABLE DEVICES - A semiconductor module includes: a substrate having a wiring layer; a first rectangular-shaped semiconductor device mounted on one surface of the substrate; a second rectangular-shaped semiconductor device mounted on the other surface of the substrate. The first semiconductor device is arranged such that each side thereof is not parallel to that of the second semiconductor device, and that the first semiconductor device is superimposed on the second semiconductor device, when seen from the direction perpendicular to the surface of the substrate. | 2010-10-07 |
20100252937 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING SAME - An electronic device includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first electronic component, a first sealing resin, and a first multilayer interconnection structure including a first interconnection pattern directly connected to a first electrode pad of the first electronic component. The second semiconductor device includes a second electronic component, a second sealing resin, and a second multilayer interconnection structure including a second interconnection pattern directly connected to a second electrode pad of the second electronic component. The first semiconductor device is stacked on and bonded to the second semiconductor device through an adhesive layer with the first multilayer interconnection structure of the first semiconductor device facing toward the second sealing resin of the second semiconductor device. The first interconnection pattern and the second interconnection pattern are connected through a through electrode provided through the adhesive layer and the second sealing resin. | 2010-10-07 |
20100252938 | SEMICONDUCTOR PACKAGE - A semiconductor package includes: a semiconductor element mounted on a one-sided plane of a wiring board; an underfill agent dropped so as to be filled between the semiconductor element and the wiring board; and a pad group constituted by a plurality of pads which are formed in the vicinity of a circumference of the wiring board and along the circumference, the pad group being formed on a bottom plane of a groove portion formed in a solder resist which covers the one-sided plane of the wiring board, wherein a corner edge of the groove portion located in the vicinity of a dropping starting portion to which dropping of the underfill agent is started is formed at an obtuse angle or in an arc shape in order to avoid the dropped underfill agent from entering into an inner portion of the groove portion. | 2010-10-07 |
20100252939 | CHIP MODULE AND METHOD FOR PRODUCING A CHIP MODULE - A chip module having a substrate and at least one chip connected to the substrate is provided, the substrate featuring a first main plane of extension and the chip featuring a second main plane of extension, and an acute angle being provided between the first main plane of extension and the second main plane of extension, and the substrate also comprising a mold housing. | 2010-10-07 |
20100252940 | POLYIMIDE SHIELD AND INTEGRATED CIRCUIT STRUCTURE HAVING THE SAME - A polyimide shield includes a base film layer that is made from polyimide, and a colored film layer that overlies the base film layer and that contains a coloring agent dispersed in a polymer. A method of making the polyimide shield includes forming the base film layer from polyimide and applying a liquid composition onto the base film layer. The liquid composition contains a polymer and the coloring agent that is dispersed in the polymer. An integrated circuit structure includes a circuitry substrate and the polyimide shield that covers the circuitry substrate. | 2010-10-07 |
20100252941 | OPTICAL ELEMENT MANUFACTURING METHOD - A method of manufacturing an optical element used at a second air pressure different from a first air pressure comprises: a measuring step of measuring a surface shape of the optical member at the first air pressure; a calculating step of calculating a deformation amount of the optical member that occurs owing to an air pressure difference between the first air pressure and the second air pressure; and a processing step of processing the optical member at the first air pressure so as to make the surface shape of the optical member match a target shape at the second air pressure, based on the surface shape measured in the measuring step and the deformation amount calculated in the calculating step. | 2010-10-07 |
20100252942 | DIFFRACTIVE OPTICAL ELEMENT AND OPTICAL SYSTEM USING THE SAME - A diffractive optical element includes stacked first and second diffraction gratings made of different materials. The materials of the first and second diffraction gratings are glass. The first and second diffraction gratings have grating surfaces contacted to each other. The materials satisfy a predetermined condition when Tg | 2010-10-07 |
20100252943 | Method for producing granular composition - A method for producing a granular composition including the steps of: stirring and granulating a mixture containing not less than 3 parts by weight and not more than 80 parts by weight of a phenol compound represented by the formula (1): | 2010-10-07 |
20100252944 | METHOD AND DEVICE FOR MONITORING, DOCUMENTING, AND/OR CONTROLLING AN INJECTION MOLDING MACHINE - A method for monitoring, documenting, and/or controlling an injection molding machine (P) having an injection molding tool ( | 2010-10-07 |
20100252945 | MOULD CARRIER UNIT WITH CONTROLLED NOZZLE - The mould carrier unit for manufacturing containers by a stretch blow-moulding operation of preforms ( | 2010-10-07 |
20100252946 | METHOD FOR THE PRODUCTION OF CELLULAR CONCRETE AND FOAMED CONCRETE, AND SYSTEM FOR CARRYING OUT THE METHOD - Process for the production of aerated-concrete or foamed-concrete moldings with envelope densities ≦450, where a cement- and sulfate-carrier-free lime formulation is produced, made of a CaO component made of a lime or lime hydrate and of an SiO | 2010-10-07 |
20100252947 | HIGH PROCESSING TEMPERATURE FOAMING POLYMER COMPOSITION - A foaming composition comprising a melt processible fluoropolymer, and a chemical foaming agent, where the chemical foaming agent is ammonium polyphosphate. | 2010-10-07 |
20100252948 | Method of compacting material - A method of compacting material such as but not limited to cathode material for electrochemical cells. A mixture is inserted into a die cavity and the mixture is compacted into a disk shape by the action of a first plunger pressing down on the material and a second plunger pressing upwardly on the material. Flashing of material during ejection of the disk from the die is prevented by fitting a polymeric sleeve around the outer surface of the first plunger. The sleeve flexes to bulge outwardly and does not enter the die cavity during compaction of material and returns to its original position during ejection of the compacted disk from the die. Contact between the disk and sleeve prevents flashing during ejection. Alternatively, a polymeric seal ring is placed around the outer surface of the first plunger. The disk presses against the seal ring preventing flashing of material during ejection. | 2010-10-07 |
20100252949 | Process for Preparing Pramipexole Dihydrochloride Tablets - The present invention relates to a process for preparing tablets of pramipexole dihydrochloride. In particular, the present invention relates to a process for preparing tablets of pramipexole dihydrochloride wherein the tablets exhibit enhanced storage stability properties. | 2010-10-07 |
20100252950 | METHOD OF PRODUCING POLYCRYSTALLINE TRANSPARENT CERAMIC SUBSTRATE AND METHOD OF PRODUCING SPINEL SUBSTRATE - There is provided a method of producing a polycrystalline transparent ceramic substrate used in a transparent substrate or the like for a liquid crystal projector. The method of producing a polycrystalline transparent ceramic substrate is characterized in comprising a step for sintering a ceramic body molded into a predetermined shape and producing a polycrystalline transparent ceramic sintered body, a step for cutting the polycrystalline transparent ceramic sintered body and producing a plurality of polycrystalline transparent ceramic cut bodies, a step for polishing the cut surfaces of the polycrystalline transparent ceramic cut bodies and producing polycrystalline transparent ceramic polished bodies, and a step for applying an antireflection coating to the polycrystalline transparent ceramic polished bodies and producing coated polycrystalline transparent ceramic bodies. | 2010-10-07 |
20100252951 | PROCESS FOR PRODUCING RECLAIMED CASTING SAND - The present invention relates to a process for producing reclaimed casting sand, which has step (I) of grinding recovered sand in the presence of an additive (A) containing a liquid having a surface tension of not higher than 35 mN/m at 25° C. and a boiling point of not lower than 150° C. at 1 atmospheric pressure. | 2010-10-07 |
20100252952 | KIT AND METHOD FOR CONVERTING A REFURBISHING MACHINE INTO A REFORMING APPARATUS, AND RESULTING APPARATUS - A kit and method for converting a refurbishing machine into a reforming apparatus. The apparatus reforms a portion of a plastic container using induction heating. The kit includes a reform heating assembly that achieves a temperature of above about 500° F., heats the container via radiant and convection heating without contacting the container, and has a power and thermocouple connection to a first controller. The kit also includes a reform cooling assembly that has a forming die which contacts and reforms the container portion, a support housing a Peltier thermoelectric cooler, a heat sink facilitating heat transfer away from the forming die, and a power and thermocouple connection to a second controller. The method includes the steps of replacing heating assemblies of the refurbishing machine with the reform heating assembly and the reform cooling assembly, respectively, using the existing equipment utilities of the refurbishing machine. | 2010-10-07 |
20100252953 | COATED MINING BOLT - A mine support includes an elongate metal member and a coating comprising post-consumer recycled thermoplastic disposed on the member. The thermoplastic may include post-consumer recycled poly(ethylene terephthalate), and the coating may be an injection molded coating. A first layer of the coating may be provided with a thickness at least about 0.1 mm and a crystallinity between about 16% and about 30%, and a second layer of the coating may be provided with a thickness at least about 0.1 mm and a crystallinity between about 6% and about 14%. Either the first layer or second layer may contact the elongate metal member. | 2010-10-07 |
20100252954 | APPARATUS AND METHOD FOR FORMING PANEL - Disclosed herein is an apparatus and method for forming a panel. The apparatus includes a first mold unit may include a right-angled upper mold provided on the front portion of an upper mold to reciprocate vertically, and a right-angled lower mold provided on the front portion of a lower mold, thus compressing base materials to impart a pattern of a right triangular waveform. A second mold unit may include an obtuse upper mold provided on the central portion of the upper mold to reciprocate in a direction inclined relative to a progressing direction of the base materials, and an obtuse lower mold provided on the central portion of the lower mold, thus compressing the base materials to impart a pattern of an obtuse triangular waveform. A third mold unit may be provided behind the second mold unit and linearly presses the base materials in a direction from front to rear. | 2010-10-07 |