40th week of 2011 patent applcation highlights part 18 |
Patent application number | Title | Published |
20110241046 | Light Emitting Device Having Peripheral Emissive Region - Light emitting devices are provided that include one or more OLEDs disposed only on a peripheral region of the substrate. An OLED may be disposed only on a peripheral region of a substantially transparent substrate and configured to emit light into the substrate. Another surface of the substrate may be roughened or include other features to outcouple light from the substrate. The edges of the substrate may be beveled and/or reflective. The area of the OLED(s) may be relatively small compared to the substrate surface area through which light is emitted from the device. One or more OLEDs also or alternatively may be disposed on an edge of the substrate about perpendicular to the surface of the substrate through which light is emitted, such that they emit light into the substrate. A mode expanding region may be included between each such OLED and the substrate. | 2011-10-06 |
20110241047 | PHOTO-EMISSION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A photo-emission semiconductor device superior in reliability is provided. The photo-emission semiconductor device includes a semiconductor layer, a light reflection layer provided on the semiconductor layer, and a protective layer formed by electroless plating to cover the light reflection layer. Therefore, even if the whole structure is reduced in size, the protective layer reliably covers the light reflection layer without gap. | 2011-10-06 |
20110241048 | RESIN COMPOSITION, REFLECTOR FOR LIGHT-EMITTING SEMICONDUCTOR DEVICE, AND LIGHT-EMITTING SEMICONDUCTOR UNIT - Disclosed herein is a resin composition including 100 parts by weight of an organic resin and 50 to 1,000 parts by weight of an inorganic filler, wherein 10 to 100% of the inorganic filler is composed of an oxide of a rare earth element. | 2011-10-06 |
20110241049 | SUBSTRATE FOR MOUNTING LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DEVICE EMPLOYING THE SUBSTRATE - To provide a substrate for mounting a light-emitting element, which is provided with a reflection layer having a high optical reflectance and being less susceptible to deterioration of the reflectance due to corrosion and which has an improved light extraction efficiency and heat dissipation property, and a light-emitting device employing such a substance. | 2011-10-06 |
20110241050 | HIGH EFFICIENCY LIGHT EMITTING DIODE AND METHOD FOR FABRICATING THE SAME - A high-efficiency light emitting diode including: a semiconductor stack positioned on a support substrate, including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; an insulating layer disposed in an opening that divides the p-type compound semiconductor layer and active layer; a transparent electrode layer disposed on the insulating layer and the p-type compound semiconductor layer; a reflective insulating layer covering the transparent electrode layer, to reflect light from the active layer away from the support substrate; a p-electrode covering the reflective insulating layer; and an n-electrode is formed on top of the n-type compound semiconductor layer. The p-electrode is electrically connected to the transparent electrode layer through the insulating layer. | 2011-10-06 |
20110241051 | Organic Electroluminescent Device - An organic electroluminescent device comprising: a substrate; a first electrode disposed over the substrate for injecting charge of a first polarity; a second electrode disposed over the first electrode for injecting charge of a second polarity opposite to said first polarity; an organic light emitting layer disposed between the first and the second electrode, the second electrode being transparent to light emitted by the light emitting layer; and a transparent encapsulant disposed over the second electrode, wherein the transparent encapsulant comprises a microlens array formed by a top surface of the transparent encapsulant and a diffraction grating formed by a bottom surface of the transparent encapsulant. | 2011-10-06 |
20110241052 | LIGHTING SYSTEM - The present invention relates to a light emitting device ( | 2011-10-06 |
20110241053 | LIGHT EMITTING DEVICE - Disclosed is a light emitting device. The light emitting device includes a light emitting structure comprising an active layer to generate first light, a first conductive semiconductor layer on the active layer, and a second conductive semiconductor layer on the active layer so that the active layer is disposed between the first and second conductive semiconductor layers, wherein a portion of the light emitting structure is implanted with at least one element which generates second light from the first light. | 2011-10-06 |
20110241054 | LED PACKAGE HAVING AN ARRAY OF LIGHT EMITTING CELLS COUPLED IN SERIES - Disclosed is a light emitting diode (LED) package having an array of light emitting cells coupled in series. The LED package comprises a package body and an LED chip mounted on the package body. The LED chip has an array of light emitting cells coupled in series. Since the LED chip having the array of light emitting cells coupled in series is mounted on the LED package, it can be driven directly using an AC power source. | 2011-10-06 |
20110241055 | OPTICAL SEMICONDUCTOR ELEMENT MOUNTING PACKAGE, AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME - An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes. | 2011-10-06 |
20110241056 | SEMICONDUCTOR LIGHT EMITTING DEVICE WITH LIGHT EXTRACTION STRUCTURES - Structures are incorporated into a semiconductor light emitting device which may increase the extraction of light emitted at glancing incidence angles. In some embodiments, the device includes a low index material that directs light away from the metal contacts by total internal reflection. In some embodiments, the device includes extraction features such as cavities in the semiconductor structure which may extract glancing angle light directly, or direct the glancing angle light into smaller incidence angles which are more easily extracted from the device. | 2011-10-06 |
20110241057 | HIGH-EFFICIENCY LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting device includes a substrate; a first semiconductor layer formed on the substrate; an active layer formed on the first semiconductor layer; a second semiconductor layer formed on the active layer; and a first pad formed on the second semiconductor layer, wherein the second semiconductor layer includes a plurality of voids between the active layer and the first pad. | 2011-10-06 |
20110241058 | LED HEAT DISSIPATING MODULE - A light emitting diode (LED) heat dissipating module includes an aluminum base plate, at least one connecting hole formed on aluminum base plate, and a copper pillar installed in the connecting hole, such that the bottom of the aluminum heat dissipating base plate of the LED is coupled to a distal surface of the copper pillar, and the heat produced by the aluminum heat dissipating base plate can be conducted to the aluminum base plate by a copper body to achieve a quick heat dissipating effect. | 2011-10-06 |
20110241059 | LED DIE STRUCTURE AND METHOD FOR MANUFACTURING THE BOTTOM TERMINAL THEREOF - An LED die structure and a method for manufacturing the bottom terminal of the LED die structure, wherein the LED die includes a substrate, a light-emitting layer positioned at the top of the substrate, at least one bottom terminal positioned at the bottom of the substrate, at least one top terminal positioned at the top of the light-emitting layer, and at least one side terminal positioned at the side of the bottom of the substrate, and wherein the method comprises the following steps: a) recessing the bottom side of the wafer to a predetermined height when the LED is formed in a wafer type; b) coating the metal material to the bottom of the wafer and to the inside of the recesses; and c) dividing the wafer along the recesses into dies. In this way, the bottom terminal and the side terminal are formed at the bottom of the substrate of the die. Moreover, the LED die structure enhances the quality of the electric connection between the die-bonding paste and the LED die. | 2011-10-06 |
20110241060 | Glass sealing package and manufacturing method thereof - Disclosed herein are a glass sealing package and a manufacturing method thereof. The glass sealing package includes a first glass substrate, a second glass substrate and a frit. The coefficient of thermal expansion of the frit lies between that of the two glass substrates. A light emitting element on the first glass substrate is situated in a sealed room formed among the two substrates and the frit. The method includes the steps of proving a first and a second glass substrate, dispensing a frit on the second glass substrate, pre-sintering the frit, assembling the two substrates, and sealing the frit to join the two substrates. | 2011-10-06 |
20110241061 | HEAT DISSIPATION BY THROUGH SILICON PLUGS - The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip. | 2011-10-06 |
20110241062 | LED lamps - A high power LED lamp has a GaN chip placed over an AlGaInP chip. A reflector is placed between the two chips. Each of the chips has trenches diverting light for output. The chip pair can be arranged to produce white light having a spectral distribution in the red to blue region that is close to that of daylight. Also, the chip pair can be used to provide an RGB lamp or a red-amber-green traffic lamp. The active regions of both chips can be less than 50 microns away from a heat sink. | 2011-10-06 |
20110241063 | MULTILAYER DEVICES ON FLEXIBLE SUPPORTS - A flexible element has a flexible support comprising two or more layers with different modulus of elasticities in bound contact with each other, and at least one thin film wherein the total thickness of the thin film(s) is less than the total thickness of the flexible support at any point of contact between the support and the thin film(s); and at least one thin film is deposited on the outer surface of the layer of the flexible support having the higher elastic modulus. | 2011-10-06 |
20110241064 | LIGHT EMITTING DIODE - A LED chip including a substrate, a semiconductor device layer, a current blocking layer, a current spread layer, a first electrode and a second electrode is provided. The semiconductor device layer is disposed on the substrate. The current blocking layer is disposed on a part of the semiconductor device layer and includes a current blocking segment and a current distribution adjusting segment. The current spread layer is disposed on a part of the semiconductor device layer and covers the current blocking layer. The first electrode is disposed on the current spread layer, wherein a part of the current blocking segment is overlapped with the first electrode. Contours of the current blocking segment and the first electrode are similar figures. Contour of the first electrode and is within contour of the current blocking segment. The current distribution adjusting segment is not overlapped with the first electrode. | 2011-10-06 |
20110241065 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a light emitting structure including a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; an electrode layer on the plurality of compound semiconductor layers; and a channel layer including protrusion and formed along a peripheral portion of an upper surface of the plurality of compound semiconductor layers. | 2011-10-06 |
20110241066 | SEMICONDUCTOR LIGHT EMITTING DEVICE, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE USING THE SAME - There is provided a semiconductor light emitting device, a method of manufacturing the same, and a semiconductor light emitting device package using the same. A semiconductor light emitting device having a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, a second electrode layer, and insulating layer, a first electrode layer, and a conductive substrate sequentially laminated, wherein the second electrode layer has an exposed area at the interface between the second electrode layer and the second conductivity type semiconductor layer, and the first electrode layer comprises at least one contact hole electrically connected to the first conductivity type semiconductor layer, electrically insulated from the second conductivity type semiconductor layer and the active layer, and extending from one surface of the first electrode layer to at least part of the first conductivity type semiconductor layer. | 2011-10-06 |
20110241067 | Gate Controlled Atomic Switch - The invention relates to a method for producing a switch element. The invention is characterized in that the switch element comprises three electrodes that are located in an electrolyte, two of which (source electrode and drain electrode) are interconnected by a bridge consisting of one or more atoms that can be reversibly opened and closed. The opening and closing of said contact between the source and drain electrodes can be controlled by the potential that is applied to the third electrode (gate electrode). The switch element is produced by the repeated application of potential cycles between the gate electrode and the source or drain electrode. The potential is increased and reduced during the potential cycles until the conductance between the source and drain electrode can be switched back and forth between two conductances, as a result of said change in potential in the gate electrode, as a reproducible function of the voltage of the gate electrode. | 2011-10-06 |
20110241068 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device which can make the generation of gate parasitic oscillations more difficult than a semiconductor device of the related art is provided. The semiconductor device includes: a drift layer which is constituted of a reference concentration layer and a low concentration layer; a gate electrode structure; a pair of source regions, a pair of base regions, and depletion-layer extension regions which are formed in the reference concentration layer below the base regions, wherein the depletion-layer extension regions are formed such that a lower surface of the depletion-layer extension region is deeper than a boundary between the low concentration layer and the reference concentration layer and projects into the low concentration layers, and a dVDS/dt-decreasing diffusion layer which contains an n-type impurity at a concentration higher than the concentration of the impurity which the reference concentration layer contains and decreases dVDS/dt when the semiconductor device is turned off is formed on a surface of the reference concentration layer. | 2011-10-06 |
20110241069 | Low side zener reference voltage extended drain SCR clamps - In an ultra high voltage lateral DMOS-type device (UHV LDMOS device), a central pad that defines the drain region is surrounded by a racetrack-shaped source region with striations of alternating n-type and p-type material radiating outwardly from the pad to the source to provide for an adjustable snapback voltage. | 2011-10-06 |
20110241070 | AVALANCHE PHOTODIODE AND METHOD FOR MANUFACTURING THE AVALANCHE PHOTODIODE - An avalanche photodiode including a first electrode; and a substrate including a first semiconductor layer of a first conduction type electrically connected to the first electrode, in which at least an avalanche multiplication layer, a light absorption layer, and a second semiconductor layer of a second conduction type with a larger band gap than the light absorption layer are deposited on the substrate. The second semiconductor layer is separated into inner and outer regions by a groove formed therein, the inner region electrically connected to a second. With the configuration, the avalanche photodiode has a low dark current and high long-term reliability. In addition, the outer region includes an outer trench, and at least the light absorption layer is removed by the outer trench to form a side face of the light absorption layer. With the configuration, the dark current can be further reduced. | 2011-10-06 |
20110241071 | Semiconductor Devices Having Field Effect Transistors With Epitaxial Patterns in Recessed Regions - A semiconductor device includes a device isolation pattern, a gate line, and an epitaxial pattern. The device isolation pattern is disposed in a semiconductor substrate to define an active area. The gate line intersects the active area. The epitaxial pattern fills a recess region in the active area at one side of the gate line and includes a different constituent semiconductor element than the semiconductor substrate. The recess region includes a first inner sidewall that is adjacent to the device isolation pattern and extends in the lengthwise direction of the gate, and a second inner sidewall that extends in the direction perpendicular to the lengthwise direction of the gate line. The active area forms the first inner sidewall of the recess, while the device isolation layer forms at least a portion of the second inner sidewall of the recess. The epitaxial pattern contacts the first inner sidewall and the second inner sidewall of the recess region. | 2011-10-06 |
20110241072 | SEMICONDUCTOR STRUCTURE HAVING AN ELOG ON A THERMALLY AND ELECTRICALLY CONDUCTIVE MASK - A semiconductor structure includes a substrate, a thermally and electrically conductive mask positioned upon the substrate, and an epitaxial lateral over growth (ELOG) material positioned upon the thermally and electrically conductive mask. | 2011-10-06 |
20110241073 | STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN - A method for fabricating an upside-down p-FET includes: fully etching source and drain regions in a donor substrate by etching a silicon-on-insulator layer through buried oxide and partially etching the silicon substrate; refilling a bottom and sidewall surfaces of the etched source and drain regions with epitaxial silicide/germanide to form e-SiGe source and drain regions; capping the source and drain regions with self-aligning silicide/germanide; providing a silicide layer formed over the gate conductor line; providing a first stress liner over the gate and the e-SiGe source and drain regions; depositing a planarized dielectric over the self-aligning silicide/germanide; inverting the donor substrate; bonding the donor substrate to a host wafer; and selectively exposing the buried oxide and the e-SiGe source and drain regions by removing the donor wafer. | 2011-10-06 |
20110241074 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A GaN layer and an n-type AlGaN layer are formed over an insulating substrate, and thereafter, a gate electrode, a source electrode and a drain electrode are formed on them. Next, an opening reaching at least a surface of the insulating substrate is formed in the source electrode, the GaN layer and the n-type AlGaN layer. Then, a nickel (Ni) layer is formed in the opening. Thereafter, by conducting dry etching from the back side while making the nickel (Ni) layer serve as an etching stopper, a via hole reaching the nickel (Ni) layer is formed in the insulating substrate. Then, a via wiring is formed extending from an inside the via hole to the back surface of the insulating substrate. | 2011-10-06 |
20110241075 | BIPOLAR TRANSISTOR - A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [ | 2011-10-06 |
20110241076 | P-type Field-Effect Transistor and Method of Production - An n-layer is arranged above a substrate, which can be GaAs, and a p-layer ( | 2011-10-06 |
20110241077 | INTEGRATED CIRCUIT 3D MEMORY ARRAY AND MANUFACTURING METHOD - A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable element and a rectifier. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection. | 2011-10-06 |
20110241078 | Stacked Bit Line Dual Word Line Nonvolatile Memory - An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics. | 2011-10-06 |
20110241079 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - Disclosed herein is a solid-state imaging device including a photoelectric conversion element operable to generate electric charge according to the amount of incident light and to accumulate the electric charge in the inside thereof, an electric-charge holding region in which the electric charge generated through photoelectric conversion by the photoelectric conversion element is held until read out, and a transfer gate having a complete transfer path through which the electric charge accumulated in the photoelectric conversion element is completely transferred into the electric-charge holding region, and an intermediate transfer path through which the electric charge generated by the photoelectric conversion element during an exposure period and being in excess of a predetermined charge amount is transferred into the electric-charge holding region. The complete transfer path and the intermediate transfer path are formed in different regions. | 2011-10-06 |
20110241080 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - Disclosed herein is a solid-state imaging device, including a plurality of unit pixels, wherein the plurality of unit pixels include: a photoelectric conversion element; a first transfer gate; a charge retaining region; a second transfer gate; and a floating diffusion region; a boundary part between the photoelectric conversion element and the charge retaining region having a structure of an overflow path formed at a potential determining a predetermined amount of charge, the overflow path transferring a charge by which the predetermined amount of charge is exceeded as a signal charge from the photoelectric conversion element to the charge retaining region, and the first transfer gate having two electrodes with different work functions as gate electrodes arranged above the overflow path and above the charge retaining region, respectively. | 2011-10-06 |
20110241081 | METHODS AND APPARATUS FOR MEASURING ANALYTES USING LARGE SCALE FET ARRAYS - Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis. | 2011-10-06 |
20110241082 | DOUBLE-SIDED INTEGRATED CIRCUIT CHIPS - A semiconductor structure and method of fabricating the structure. The method includes removing the backside silicon from two silicon-on-insulator wafers having devices fabricated therein and bonding them back to back utilizing the buried oxide layers. Contacts are then formed in the upper wafer to devices in the lower wafer and wiring levels are formed on the upper wafer. The lower wafer may include wiring levels. The lower wafer may include landing pads for the contacts. Contacts to the silicon layer of the lower wafer may be silicided. | 2011-10-06 |
20110241083 | SEMICONDUCTOR DEVICE AND METHOD - Transistors ( | 2011-10-06 |
20110241084 | Semiconductor Device with a Buried Stressor - A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs. | 2011-10-06 |
20110241085 | DUAL SIDEWALL SPACER FOR SEAM PROTECTION OF A PATTERNED STRUCTURE - A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer. | 2011-10-06 |
20110241086 | ALUMINUM FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATE ELECTRODE STRUCTURES - In sophisticated semiconductor devices, electronic fuses may be provided on the basis of a replacement gate approach by using the aluminum material as an efficient metal for inducing electromigration in the electronic fuses. The electronic fuse may be formed on an isolation structure, thereby providing an efficient thermal decoupling of the electronic fuse from the semiconductor material and the substrate material, thereby enabling the provision of efficient electronic fuses in a bulk configuration, while avoiding incorporation of fuses into the metallization system. | 2011-10-06 |
20110241087 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A gate insulating film is formed on a substrate. Next, a gate electrode film is formed on the gate insulating film. A mask film is formed on a portion of the gate electrode film. The gate electrode film is selectively removed by etching using the mask film as a mask. A gate sidewall film is formed so as to be in contact with the lateral surfaces of the mask film and the gate electrode film. The mask film is formed of a laminated film in which at least a first film, a second film and a third film are laminated in this order. The second film has a higher etching selectivity ratio than that of the third film with respect to the gate sidewall film. The third film has a higher etching selectivity ratio than that of the second film with respect to the gate electrode film. | 2011-10-06 |
20110241088 | FIELD EFFECT TRANSISTOR, METHOD OF MANUFACTURING FIELD EFFECT TRANSISTOR, AND METHOD OF FORMING GROOVE - A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×10 | 2011-10-06 |
20110241089 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - Disclosed herein is a solid-state imaging device including: a semiconductor region of a second conductivity type which is formed on a face side of a semiconductor substrate; a photoelectric conversion element which has an impurity region of a first conductivity type and which is operable to generate electric charge according to the amount of incident light and to accumulate the electric charge in the inside thereof; an electric-charge holding region which has an impurity region of the first conductivity type and in which the electric charge generated through photoelectric conversion by the photoelectric conversion element is held until read out; an intermediate transfer path through which only the electric charge generated by the photoelectric conversion element during an exposure period and being in excess of a predetermined electric charge amount is transferred into the electric-charge holding region; and an impurity layer. | 2011-10-06 |
20110241090 | HIGH FULL-WELL CAPACITY PIXEL WITH GRADED PHOTODETECTOR IMPLANT - Embodiments of a process for forming a photodetector region in a CMOS pixel by dopant implantation, the process comprising masking a photodetector area of a surface of a substrate for formation of the photodetector region, positioning the substrate at a plurality of twist angles, and at each of the plurality of twist angles, directing dopants at the photodetector area at a selected tilt angle. Embodiments of a CMOS pixel comprising a photodetector region formed in a substrate, the photodetector region comprising overlapping first and second dopant implants, wherein the overlap region has a different dopant concentration than the non-overlapping parts of the first and second implants, a floating diffusion formed in the substrate, and a transfer gate formed on the substrate between the photodetector and the transfer gate. Other embodiments are disclosed and claimed. | 2011-10-06 |
20110241091 | CONTROLLING FERROELECTRICITY IN DIELECTRIC FILMS BY PROCESS INDUCED UNIAXIAL STRAIN - A method of controlling ferroelectric characteristics of integrated circuit device components includes forming a ferroelectrically controllable dielectric layer over a substrate; and forming a stress exerting structure proximate the ferroelectrically controllable dielectric layer such that a substantially uniaxial strain is induced in the ferroelectrically controllable dielectric layer by the stress exerting structure; wherein the ferroelectrically controllable dielectric layer comprises one or more of: a ferroelectric oxide layer and a normally non-ferroelectric material layer that does not exhibit ferroelectric properties in the absence of an applied stress. | 2011-10-06 |
20110241092 | ELECTRONIC DEVICE WITH CAPCITIVELY COUPLED FLOATING BURIED LAYER - Transistors ( | 2011-10-06 |
20110241093 | SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME - A dual channel transistor includes a semiconductor island isolated by a first shallow trench isolation (STI) extending along a first direction and a second STI extending along a second direction, wherein the first direction intersect the second direction. The dual channel transistor further includes a gate trench recessed into the semiconductor island and extending along the second direction. A gate is located in the gate trench. A first U-shaped channel region is formed in the semiconductor island. A second U-shaped channel region is formed in the semiconductor island, wherein the second U-shaped channel region is segregate from the first U-shaped channel region by the gate. During operation, the gate controls two U-shaped channel regions simultaneously. | 2011-10-06 |
20110241094 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - According to one embodiment, a semiconductor memory device includes each of memory cells including a floating electrode above a semiconductor substrate via the gate insulator, a control gate electrode above the floating gate electrode via a first inter-gate insulator, first diffusion layers as source or drain, a contact electrode portion including a bottom electrode with an opening and a top electrode on the bottom electrode, the bottom electrode being arranged on the first gate insulator having the opening, the top electrode being electrically connected to the semiconductor substrate via the first opening, and a connection diffusion layer formed in the semiconductor substrate below the first opening. | 2011-10-06 |
20110241095 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In one embodiment, a semiconductor memory device, including a memory cell having a floating gate electrode above a semiconductor substrate via a first gate insulator and a control gate electrode above the floating gate electrode via a first inter-gate insulator, a contact electrode having a bottom electrode contacted to an upper surface of the semiconductor substrate, top electrodes via a second inter-gate insulators on both edge portions of the bottom electrode and a plug electrode between the top electrodes, the plug electrode contacted to an upper surface of the bottom electrode. | 2011-10-06 |
20110241096 | ISOLATION REGIONS - Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material. | 2011-10-06 |
20110241097 | Semiconductor device and manufacturing method thereof - Device isolation regions for isolating a device forming region are formed over a substrate. Subsequently, a gate insulation film is formed over the device forming region. Then, a lower gate electrode film comprised of a metal nitride film is formed over the gate insulation film. Further, a heat treatment is performed to the lower gate electrode film and then an upper gate electrode film is formed over the lower gate electrode film. | 2011-10-06 |
20110241098 | 3D STACKED ARRAY HAVING CUT-OFF GATE LINE AND FABRICATION METHOD THEREOF - A three-dimensional stacked flash memory array having cut-off gate line and a fabricating method of the same are provided. The flash memory array enables to operate two memory cells by each word line, to produce a high integrity without limitation by vertical stacks of word lines, to increase operating speed and uniformity of electrical property between cells by using a single crystal substrate as a channel region, and to reduce a fabricating cost to a great amount by a fabricating method which is including steps of forming a plurality of trenches in a semiconductor substrate and stacking repeatedly a conductive material interlaid with an insulating layer from bottom of each trench to form a cut-off gate line and a plurality of word lines. | 2011-10-06 |
20110241099 | SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND FUSE CIRCUIT AND SEMICONDUCTOR MODULE INCLUDING THE SAME - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate, a first node impurity region, a second node impurity region, a third node impurity region, and an insulating layer. The first through third node impurity regions are disposed in the semiconductor substrate. Each of the first through third node impurity regions has a longitudinal length, a transverse length and a thickness respectively corresponding to first through third directions, which are perpendicular with respect to each other. The first node impurity region is parallel to the second and third node impurity regions, which are disposed in the substantially same line. The insulating layer is located between the first through third node impurity regions in the semiconductor substrate. | 2011-10-06 |
20110241100 | STACKED NON-VOLATILE MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME - A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation. | 2011-10-06 |
20110241101 | SEMICONDUCTOR MEMORY ELEMENT AND SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory element includes a semiconductor layer, a tunnel insulator provided on the semiconductor layer, a charge accumulation film provided on the tunnel insulator having a film thickness of 0.9 nm or more and 2.8 nm or less and the charge accumulation film containing cubic HfO | 2011-10-06 |
20110241102 | SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND BURIED CHANNEL ARRAY TRANSISTOR, METHODS OF FABRICATING THE SAME, AND SEMICONDUCTOR MODULES, ELECTRONIC CIRCUIT BOARDS AND ELECTRONIC SYSTEMS INCLUDING THE SAME - A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode. | 2011-10-06 |
20110241103 | METHOD OF MANUFACTURING A TUNNEL TRANSISTOR AND IC COMPRISING THE SAME - A method of manufacturing a tunnel field effect transistor is disclosed. The method comprises forming a two-step profile in a silicon substrate ( | 2011-10-06 |
20110241104 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR ITS PRODUCTION - An integrated circuit device includes a semiconductor body fitted with a first electrode and a second electrode on opposite surfaces. A control electrode on an insulating layer controls channel regions of body zones for a current flow between the two electrodes. A drift section adjoining the channel regions comprises drift zones and charge compensation zones. A part of the charge compensation zones includes conductively connected charge compensation zones electrically connected to the first electrode. Another part includes nearly-floating charge compensation zones, so that an increased control electrode surface has a monolithically integrated additional capacitance C | 2011-10-06 |
20110241105 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device positioned on an SOI substrate. A semiconductor memory device includes two transistors with three terminals which serve as a source, a reading drain and a writing drain, respectively. The writing drain is heavily-doped for high writing efficiency. A floating body region for storing charges is also heavily-doped to reach long data retention time. | 2011-10-06 |
20110241106 | SEMICONDUCTOR DEVICE WITH BURIED GATES AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a supplementary layer and a silicon layer stacked over a substrate, a trench penetrating the supplementary layer and the silicon layer and formed over the substrate, a gate insulation layer formed along a surface of the trench, and a buried gate formed over the gate insulation layer and filling a portion of the trench. | 2011-10-06 |
20110241107 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed are a semiconductor device with a metal gate and a method of manufacturing the same. The method of the present invention includes: preparing a semiconductor substrate having a isolation layer to define an active region; forming a gate insulation layer on the semiconductor substrate; sequentially forming a polysilicon layer, a first metal silicide layer, a metal nitride layer and a metal layer on the gate insulation layer including the isolation layer; etching the metal layer and the metal nitride layer so that the metal layer and the metal nitride layer have a narrower width than that of a desired gate; forming a second metal silicide layer on the first metal silicide layer including the etched metal nitride layer and the metal layer; forming a hard mask on the second metal silicide layer so that the hard mask has a desired gate width; and etching the second metal silicide layer, the first metal silicide layer, the polysilicon layer and the gate insulation layer by using the hard mask as an etching barrier, so as to form a metal gate with a structure in. which the metal nitride and the metal layer are enclosed with the first and second metal silicide layers. | 2011-10-06 |
20110241108 | LDMOS With No Reverse Recovery - A transistor includes a source region including a first impurity region implanted into a substrate, a drain region including a second impurity region implanted into the substrate, and a gate including an oxide layer formed over the substrate and a conductive material formed over the oxide layer, the oxide layer comprising a first side and a second side, the first side formed over a portion of the first impurity region and the second side formed over a portion of the second impurity region, the first side having a thickness of less than about 100 Å, and the second side having a thickness equal to or greater than 125 Å. | 2011-10-06 |
20110241109 | Power NLDMOS array with enhanced self-protection - In a self protected NLDMOS array, a deep implant is included on the drain side of each NLDMOS device to balance ESD current. | 2011-10-06 |
20110241110 | TERMINAL STRUCTURE FOR SUPERJUNCTION DEVICE AND METHOD OF MANUFACTURING THE SAME - A terminal structure for superjunction device is disclosed. The terminal structure comprises from inside out at least one P type implantation ring and several P type trench rings formed in an N type epitaxial layer to form alternating P type and N type regions. A channel cut-off ring is formed at the border of the device. The P type implantation ring is formed adjacent to the active area of the device and covers at least one trench ring. A terminal dielectric layer is formed to cover the P type implantation ring and the trench rings. A plurality of field plates are formed above the terminal dielectric layer. Methods of manufacturing terminal structure are also disclosed. | 2011-10-06 |
20110241111 | SEMICONDUCTOR DEVICE - Investigation of problems of the device structure of a power MOSFET and mass production of it in relation to high breakdown voltage and low ON resistance when an epitaxy trench filling system is employed has revealed that it has the following problem, that is, a high breakdown voltage as expected cannot be achieved because a P-column region does not have an ideal rectangular parallelepipedal shape but has an inverted trapezoidal shape narrower at the bottom thereof and at the same time, has a concentration distribution lower at the bottom. In order to overcome the problem, the present invention provides a semiconductor device including a power MOSFET portion equipped, in an active cell region thereof, a super junction structure formed by a trench filling system, wherein a base epitaxial layer has a multistage structure with the upper portion having a higher impurity concentration. | 2011-10-06 |
20110241112 | LDMOS Device with P-Body for Reduced Capacitance - A transistor includes an n-well implanted in a substrate, a source region including a p-body region, a n+ region and a p+ region in the p-body region, a drain region comprising a n+ region, and a gate between the source region and the drain region. The p-body region includes a first implant region having a first depth, a first lateral spread and a first concentration of a p-type impurity, and a second implant region having a second depth, a second lateral spread and a second concentration of the p-type impurity. The second depth is less than the first depth, the second lateral spread is greater than the first lateral spread and the second concentration is greater than the first concentration. The p+ region and n+ region abut the second implant region. | 2011-10-06 |
20110241113 | Dual Gate LDMOS Device with Reduced Capacitance - A transistor includes an n-well implanted in a substrate, a source region including a p-body region in the n-well, and a n+ region and a p+ region in the p-body region, a drain region including a n+ region, and a dual gate between the source region and the drain region. The dual gate includes a first gate on a side closer to the source region and a second gate on a side closer to the drain region, the first gate separated from the second gate by a pre-determined distance sufficient that a capacitance between the gate and the drain is at least 15% lower than a capacitance of a transistor of the same unit cell size and configuration excepting that the first gate and second gate abut. | 2011-10-06 |
20110241114 | HIGH VOLTAGE MOS TRANSISTOR - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well. | 2011-10-06 |
20110241115 | Schottky Junction Source/Drain FET Fabrication Using Sulfur or Flourine Co-Implantation - A Schottky field effect transistor (FET) includes a gate stack located on a silicon on insulator (SOI) layer, the gate stack comprising a gate silicide region; and source/drain silicide regions located in the SOI layer, the source/drain silicide regions comprising and at least one of sulfur and fluorine, wherein an interface comprising arsenic is located between each of the source/drain silicide regions and the SOI layer. A method of forming a contact, the contact comprising a silicide region adjacent to a silicon region, includes co-implanting the silicide region with arsenic and at least one of sulfur and fluorine; and drive-in annealing the co-implanted silicide region to diffuse the arsenic to an interface between the silicide region and the silicon region. | 2011-10-06 |
20110241116 | FET with FUSI Gate and Reduced Source/Drain Contact Resistance - A method for forming a field effect transistor (FET) includes forming a gate stack on a silicon layer, the gate stack comprising a gate polysilicon on top of a gate oxide layer; forming a fully silicided gate from the gate polysilicon and forming source/drain silicide regions in the silicon layer; implanting the gate silicide and the source/drain silicide with dopants; and performing rapid thermal annealing to form a gate interfacial layer in between the gate silicide and the gate oxide layer, and source/drain interfacial layers between the source/drain silicide regions and the silicon layer. | 2011-10-06 |
20110241117 | Semiconductor Device Comprising Metal Gate Structures Formed by a Replacement Gate Approach and eFuses Including a Silicide - In a replacement gate approach for forming high-k metal gate electrode structures, electronic fuses may be provided on the basis of a semiconductor material in combination with a metal silicide by using a recessed surface topography and/or a superior selectivity of the metal silicide material during the replacement gate process. For example, in some illustrative embodiments, electronic fuses may be provided in a recessed portion of an isolation region, thereby avoiding the removal of the semiconductor material when replacing the semiconductor material of the gate electrode structures with a metal-containing electrode material. Consequently, the concept of well-established semiconductor-based electronic fuses may be applied together with sophisticated replacement gate structures of transistors. | 2011-10-06 |
20110241118 | METAL GATE FILL BY OPTIMIZING ETCH IN SACRIFICIAL GATE PROFILE - A high-k metal gate electrode is formed with reduced gate voids. An embodiment includes forming a replaceable gate electrode, for example of amorphous silicon, having a top surface and a bottom surface, the top surface being larger than the bottom surface, removing the replaceable gate electrode, forming a cavity having a top opening larger than a bottom opening, and filling the cavity with metal. The larger top surface may be formed by etching the bottom portion of the amorphous silicon at greater temperature than the top portion, or by doping the top and bottom portions of the amorphous silicon differently such that the bottom has a greater lateral etch rate than the top. | 2011-10-06 |
20110241119 | SYSTEM AND METHOD FOR PROVIDING ALIGNMENT MARK FOR HIGH-K METAL GATE PROCESS - The alignment mark and method for making the same are described. In one embodiment, a semiconductor structure includes a substrate having a device region and an alignment region; a first shallow trench isolation (STI) feature in the alignment region and having a first depth D | 2011-10-06 |
20110241120 | Field Effect Transistor Device and Fabrication - A method for forming a field effect transistor (FET) device includes forming a dielectric layer on a substrate, forming a first metal layer on the dielectric layer, removing a portion of the first metal layer to expose a portion of the dielectric layer, forming a second metal layer on the dielectric layer and the first metal layer, and removing a portion of the first metal layer and the second metal layer to define a boundary region between a first FET device and a second FET device. | 2011-10-06 |
20110241121 | Semiconductor Devices Including SRAM Cell and Methods for Fabricating the Same - An SRAM cell of a semiconductor device includes a load transistor, a driver transistor and an access transistor. First source/drains of the load, driver and access transistors are connected to a node. A power line, a ground line and a bit line are electrically connected to second source/drains of the load transistor, the driver transistor and the access transistor. The power line, the ground line and the bit line are disposed at substantially the same level to extend in a first direction. A word line is electrically connected to a gate of the access transistor to extend in a second direction perpendicular to the first direction. The word line is disposed at a different level from the level of the power line, the ground line and the bit line. | 2011-10-06 |
20110241122 | SEMICONDUCTOR DEVICE - There is provided a high-integrated complementary metal-oxide semiconductor static random-access memory including an inverter. The inverter includes: a first pillar that is formed by integrating a first-conductivity-type semiconductor, a second-conductivity-type semiconductor, and an insulating material disposed between the first-conductivity-type semiconductor and the second-conductivity-type semiconductor, and that vertically extends with respect to a substrate; a first second-conductivity-type high-concentration semiconductor disposed on the first-conductivity-type semiconductor; a second second-conductivity-type high-concentration semiconductor disposed under the first-conductivity-type semiconductor; a first first-conductivity-type high-concentration semiconductor disposed on the second-conductivity-type semiconductor; a second first-conductivity-type high-concentration semiconductor disposed under the second-conductivity-type semiconductor; a gate insulating material formed around the first pillar; and a gate conductive material formed around the gate insulating material. | 2011-10-06 |
20110241123 | Semiconductor Devices and Methods of Manufacture Thereof - Methods of forming transistors and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece, a gate dielectric disposed over the workpiece, and a thin layer of conductive material disposed over the gate dielectric. A layer of semiconductive material is disposed over the thin layer of conductive material. The layer of semiconductive material and the thin layer of conductive material comprise a gate electrode of a transistor. A source region and a drain region are formed in the workpiece proximate the gate dielectric. The thin layer of conductive material comprises a thickness of about 50 Angstroms or less. | 2011-10-06 |
20110241124 | SEMICONDUCTOR DEVICE COMPRISING HIGH-K METAL GATE ELECTRODE STRUCTURES AND eFUSES FORMED IN THE SEMICONDUCTOR MATERIAL - A semiconductor-based electronic fuse may be provided in a sophisticated semiconductor device having a bulk configuration by appropriately embedding the electronic fuse into a semiconductor material of reduced heat conductivity. For example, a silicon/germanium fuse region may be provided in the silicon base material. Consequently, sophisticated gate electrode structures may be formed on the basis of replacement gate approaches on bulk devices substantially without affecting the electronic characteristics of the electronic fuses. | 2011-10-06 |
20110241125 | Power Semiconductor Device with Low Parasitic Metal and Package Resistance - A power semiconductor device includes a semiconductor die with a power transistor on a semiconductor substrate, a plurality of wiring layers vertically spaced apart from one another and the transistor, and a plurality of conductive bumps on each wire of the wiring layer spaced farthest from the substrate. Each wire of the layer closest to the substrate is electrically connected to a terminal of the transistor. The wires of the layer spaced farthest from the substrate extend in generally parallel lines and are electrically connected to a terminal of the transistor through each underlying layer. An additional metal layer having a thickness of at least 50 μm is connected to the die so that contact regions of the additional metal layer are electrically connected to the bumps of the die. | 2011-10-06 |
20110241126 | RF CMOS TRANSISTOR DESIGN - An improved RF CMOS transistor design is described. Local, narrow interconnect lines, which are located substantially above the active area of the transistor, are each connected to either a source terminal or a drain terminal. The source and the drain terminal are arranged orthogonally to the local interconnect lines and each terminal is significantly wider than a local interconnect line. In an example, the local interconnect lines are formed in a first metal layer and the source and drain terminals are formed in one or more subsequent metal layers. | 2011-10-06 |
20110241127 | Well implant through dummy gate oxide in gate-last process - The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate. | 2011-10-06 |
20110241128 | MULTILAYER SIDEWALL SPACER FOR SEAM PROTECTION OF A PATTERNED STRUCTURE - A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure. | 2011-10-06 |
20110241129 | TRANSISTOR, SEMICONDUCTOR DEVICE AND TRANSISTOR FABRICATION PROCESS - The present invention provides a transistor, a semiconductor device and a transistor fabrication process that thoroughly ameliorate electric fields in a transistor element. Namely, the transistor includes a semiconductor substrate, incline portions, a gate electrode, side walls, and a source and a drain. The semiconductor substrate includes a protrusion portion at a surface thereof. The incline portions constitute side surface portions of the protrusion portion and are inclined from the bottom to the top of the protrusion portion. The gate electrode is formed on the top of the protrusion portion, with a gate insulation film interposed therebelow. The side walls are formed on the top of the protrusion portion at two side surfaces of the gate electrode and the gate insulation film. The source and the drain each include a low density region and a high-density region. | 2011-10-06 |
20110241130 | SEMICONDUCTOR DEVICE HAVING A BLOCKING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a blocking structure between a metal layer and at least one underlying layer. The blocking structure has a first layer configured for preventing diffusion of metal from the metal layer into the at least one underlying layer, and a second layer configured for enhancing electrical performance of the semiconductor device. | 2011-10-06 |
20110241131 | SEMICONDUCTOR MEMORY DEVICE WITH BIT LINE OF SMALL RESISTANCE AND MANUFACTURING METHOD THEREOF - A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it. | 2011-10-06 |
20110241132 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The semiconductor device includes a thin film transistor; a first interlayer insulating film over the thin film transistor; a first electrode electrically connected to one of a source region and a drain region, over the first interlayer insulating film; a second electrode electrically connected to the other of the source region and the drain region; a second interlayer insulating film formed over the first interlayer insulating film, the first electrode, and the second electrode; a first wiring electrically connected to one of the first electrode and the second electrode, on the second interlayer insulating film; and a second wiring not electrically connected to the other of the first electrode and the second electrode, on the second interlayer insulating film; in which the second wiring is not electrically connected to the other of the first electrode and the second electrode by a separation region formed in the second interlayer insulating film. | 2011-10-06 |
20110241133 | Semiconductor device and manufacturing method thereof - A semiconductor device has a gate electrode including polysilicon, and a hydrogen occluding layer covering at least a top face of the gate electrode and having a function of occluding hydrogen. | 2011-10-06 |
20110241134 | MICRO-CHANNEL CHIP AND MICRO-ANALYSIS SYSTEM - A micro-channel chip can be coated uniformly with a thin inorganic oxide film and can prevent an ionic hydrophobic substance from adsorbing through a surface of an inorganic oxide film. In the micro-channel chip, surfaces of inner walls of through-holes in an upper plate member and a channel of a lower plate member are entirely coated with a SiO | 2011-10-06 |
20110241135 | MEMS ELEMENT - According to an embodiment of the present invention, a MEMS element includes: a semiconductor substrate; an island insulating layer formed on the substrate, the insulating layer including an air gap layer having an air gap group, the air gap group including a plurality of air gaps disposed in an in-plane direction; and a MEMS capacitor formed above the air gap group on the insulating layer. | 2011-10-06 |
20110241136 | MEMS DEVICE - A MEMS device includes a substrate, an insulating layer section formed above the substrate and having a cavity, a functional element contained in the cavity, and a fuse element contained in the cavity and electrically connected with the functional element. It is preferable that the fuse element is spaced apart from the substrate. | 2011-10-06 |
20110241137 | Integrated Circuit and Fabricating Method thereof - A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials. | 2011-10-06 |
20110241138 | MAGNETORESISTIVE RANDOM ACCESS MEMORY ELEMENT AND FABRICATION METHOD THEREOF - A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer. | 2011-10-06 |
20110241139 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory (MRAM) has a perpendicular magnetization direction. The MRAM includes a first magnetic layer, a second magnetic layer, a first polarization enhancement layer, a second polarization enhancement layer, a barrier layer, a spacer, and a free assisting layer. A pinned layer formed by the first magnetic layer and the first polarization enhancement layer has a first magnetization direction and a first perpendicular magnetic anisotropy. A free layer formed by the second magnetic layer and the second polarization enhancement layer has a second magnetization direction and a second perpendicular magnetic anisotropy. The barrier layer is disposed between the first polarization enhancement layer and the second polarization enhancement layer. The spacer is disposed on the second magnetic layer. The free assisting layer is disposed on the spacer and has an in-plane magnetic anisotropy. The spacer and the barrier layer are on opposite sides of the free layer. | 2011-10-06 |
20110241140 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE ASSEMBLY - A semiconductor device excellent in the magnetic shielding effect of blocking off external magnetic fields is provided. The semiconductor device includes: an interlayer insulating film so formed as to cover a switching element formed over a main surface of a semiconductor substrate; a flat plate-like lead wiring; a coupling wiring coupling the lead wiring and the switching element with each other; and a magnetoresistive element including a magnetization free layer the orientation of magnetization of which is variable and formed over the lead wiring. The semiconductor device has a wiring and another wiring through which the magnetization state of the magnetization free layer can be varied. In a memory cell area where multiple magnetoresistive elements are arranged, a first high permeability film arranged above the magnetoresistive elements is extended from the memory cell area up to a peripheral area that is an area other than the memory cell area. | 2011-10-06 |
20110241141 | Magnetic Element Having Low Saturation Magnetization - A magnetic device including a magnetic element is described. The magnetic element includes a fixed layer having a fixed layer magnetization, a spacer layer that is nonmagnetic, and a free layer having a free layer magnetization. The free layer is changeable due to spin transfer when a write current above a threshold is passed through the first free layer. The free layer is includes low saturation magnetization materials. | 2011-10-06 |
20110241142 | Semiconductor device and manufacturing method of the semiconductor device - An MTJ element is formed in a wiring layer located in a lower tier and yet application of heat to the MTJ element is suppressed. A first insulating layer is formed over a substrate. Subsequently, the MTJ element is formed over the first insulating layer. After that a first wiring is formed over the MTJ element. Thereafter, a second insulating layer is formed over the first wiring. Then a second wiring is formed in the superficial layer of the second insulating layer. The second wiring is heat treated by photoirradiation. A shield conductor is formed at the step of forming the second wiring. | 2011-10-06 |
20110241143 | X-ray pixels including double photoconductors and x-ray detectors including the x-ray pixels - Example embodiments are directed to X-ray detectors including double photoconductors. According to example embodiments, the X-ray detector includes a first photoconductor on which X-rays are incident, and a second photoconductor on which X-rays transmitted through the first photoconductor are incident. The first photoconductor and the second photoconductor include a tandem structure. The first photoconductor is formed of silicon and absorbs X-rays in a low energy band, and the second photoconductor is formed of a material that absorbs X-rays in an energy band higher than the low energy band of the X-rays absorbed by silicon. | 2011-10-06 |
20110241144 | Nuclear Batteries - We introduce a new technology for Manufactureable, High Power Density, High Volume Utilization Nuclear Batteries. Betavoltaic batteries are an excellent choice for battery applications which require long life, high power density, or the ability to operate in harsh environments. In order to optimize the performance of betavoltaic batteries for these applications or any other application, it is desirable to maximize the efficiency of beta particle energy conversion into power, while at the same time increasing the power density of an overall device. The small (submicron) thickness of the active volume of both the isotope layer and the semiconductor device is due to the short absorption length of beta electrons. The absorption length determines the self absorption of the beta particles in the radioisotope layer as well as the range, or travel distance, of the betas in the semiconductor converter which is typically a semiconductor device comprising at least one PN junction. Various devices and methods to solve the current industry problems and limitations are presented here. | 2011-10-06 |
20110241145 | BACKSIDE ILLUMINATION IMAGE SENSORS WITH REFLECTIVE LIGHT GUIDES - Image sensors with backside illumination image pixel arrays are provided. An image pixel array may have image pixels that are formed on a silicon substrate having front and back surfaces. The pixel array may have photodiodes formed in the front surface. A dielectric stack may be formed on the front surface. The dielectric stack may include interconnect structures and reflective light guides. A color filter array may be formed on the back surface of the substrate. Microlenses may be formed on the color filter array from the side facing the back surface. The pixel array may receive incoming light through the microlenses. The incoming light may enter the substrate through the back surface. The incoming light may penetrate the substrate and may be reflected by a light reflector in the reflective light guide back towards the photodiode. The image pixel array may exhibit improved quantum efficiency, sensitivity, and image contrast. | 2011-10-06 |