40th week of 2009 patent applcation highlights part 25 |
Patent application number | Title | Published |
20090243637 | MEASURING APPARATUS HAVING NANOTUBE PROBE - An object of the present invention is to provide a measuring apparatus such as a conduction characteristics evaluation apparatus, a probe microscope, etc. having a nanotube probe, wherein the measuring apparatus is succeeded in reducing the electrical resistance of the carbon nanotube as well as the electrical resistance between the carbon nanotube and a metal substrate to improve electrical conduction characteristics of the nanotube probe and attain a uniform diameter, thus improving the measurement accuracy. | 2009-10-01 |
20090243638 | Receiver for recovering and retiming electromagnetically coupled data - In one embodiment, the present invention includes a system having an electromagnetic coupler probe to electromagnetically sample signals from a device under test or a link under test and a receiver, e.g., configured as an integrated circuit that is to receive the sampled electromagnetic signals from the probe and output digital signals corresponding thereto. Other embodiments are described and claimed. | 2009-10-01 |
20090243639 | Circuit for Multi-Pads Test - The present invention relates to a circuit for multi-pads test, which is used for testing a plurality of pads. The circuit comprises one or more testing circuits, a plurality of testing switches, and a plurality of pad switches. The plurality of testing switches is coupled between the testing circuits and the plurality of pads, respectively; the plurality of pad switches is coupled between the pads, respectively. Thereby, by coordination of the plurality of pad switches and the plurality of testing switches, the number of testing probes of the testing apparatus for testing the pads can be reduced, the design difficulty of the testing apparatus can be reduced, and thus the costs can be reduced. | 2009-10-01 |
20090243640 | CONDUCTIVE CONTACT PIN AND SEMICONDUCTOR TESTING EQUIPMENT - In a conductive contact pin brought into contact with the external electrode of a semiconductor device to conduct a test on the electrical characteristics of the semiconductor device, an upper plunger | 2009-10-01 |
20090243641 | DISPLAY DEVICE - An array substrate is provided with thereon a display area in which plural pixels are arranged in a matrix shape. Output-side mounting terminals for a source driving circuit chip, which is COG-mounted on a frame area on the outside of the display area, have a plural-row zigzag arrangement. Inspection terminals individually provided in correspondence to the output-side mounting terminals have a zigzag arrangement opposite to the zigzag arrangement of the output-side mounting terminals in a terminal-row direction. Additionally, the output-side mounting terminals and the inspection terminals are disposed below the source driving circuit chip. | 2009-10-01 |
20090243642 | Electronic Device Testing System and Method - The invention provides a testing system and method suitable for determining whether the pins of the socket are properly connected to a printed circuit board. The testing system includes a testing signal source, a socket, a signal sensing unit, a fixing element, and an analysis unit. The signal sensing unit comprises a sensor board, a probe, and an operation amplifier. The sensor board is electrically coupled to the socket, and the sensor board has a probing point. The probe is selectively contacted with the probing point of the sensor board for receiving and outputting a sensing signal. The operation amplifier is electrically connected to the probe for receiving, amplifying and outputting the sensing signal. The fixing element is used for fixing the sensor board between the socket and the fixing element. | 2009-10-01 |
20090243643 | TESTING SYSTEM MODULE - A testing system module for testing printed circuit board (PCB) includes at least one robot having a pogo pin for moving to a testing point of the PCB; a pressure detecting unit for detecting a current pressure value on the printed circuit board; and a control system for keeping the pogo pin to contact with the PCB with constant pressure. | 2009-10-01 |
20090243644 | SOCKET, TEST DEVICE AND TEST METHOD FOR TESTING ELECTRONIC ELEMENT PACKAGES WITH LEADS - The present invention relates to a socket, test device and test method for testing electronic element packages with leads, and particularly relates to a socket, test device and test method for testing image sensors with leads. The test device comprises a socket, a plurality of test probes and a test circuit board. The socket comprises a base having a plurality of first holes, a guiding structure having a plurality of second holes and at least one floating member used to connect the base and the guiding structure. In the socket, test device and test method of the present invention, each test probe is received into one first hole and one second hole to maintain the top surface of guiding structure to be even for preventing the deflective placing of the electronic element packages, and for preventing the damage to the test probes. The test probes are controlled by compressing the floating member for protruding form the top surface of the guiding structure and for providing a shorter delivering path of the electronic signals between the test circuit board and the electronic element packages. This shorter delivering path of the electronic signals can improve the accuracy and reliability of the test process for the electronic element packages with leads. | 2009-10-01 |
20090243645 | MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE, A SEMICONDUCTOR WAFER, AND A TEST METHOD - The present invention aims to increase the number of test elements of a TEG without increasing the area of each of slice areas. Test electrode pads are disposed in alignment in one row in each of areas separated from semiconductor chips provided over a semiconductor wafer. Test elements are formed corresponding to these test electrode pads and in areas lying directly therebelow. Electrode terminals of the test elements are electrically coupled to the test electrode pads adjacent to the corresponding electrode pads and the test electrode pads further adjacent thereto with being spaced one test electrode pad apart. Upon testing, probe pins are brought into contact with the odd-numbered test electrode pads to conduct testing. Next, the probe pins are brought into contact with the even-numbered test electrode pads while being shifted by one electrode pad pitch thereby to conduct testing. | 2009-10-01 |
20090243646 | DETECTING CIRCUIT - A detecting circuit for detecting a battery having a first and second electrode, includes a contacting portion electrically connecting to the first electrode of the battery, a seesaw electrically connected to the second electrode of the battery, and an actuator electrically connecting to the second electrode of the battery. One end of the seesaw electrically contacts with the contacting portion when the battery have a protection circuit. The actuator is configured for providing power onto another end of the seesaw to separate the contacting portion with the seesaw when the battery has no a protection circuit. The detecting circuit can truly and handily judges whether the detected battery has the protection circuit according to the action of the seesaw | 2009-10-01 |
20090243647 | Non-Invasive monitoring and diagnosis of electric machines by measuring external flux density - System and methods for monitoring electric machines are provided. A magnetic field associated with the electric machine is measured at one or more points external to the electric machine, wherein a respective magnetic field value is associated with each of the one or more points. The one or more measured magnetic field values are compared to one or more corresponding expected values, and a determination of whether a fault is present in the electric machine is made based at least in part on the comparison. | 2009-10-01 |
20090243648 | OPTIMAL LOCAL SUPPLY VOLTAGE DETERMINATION CIRCUIT - A test circuit that compares test results between two tests with different local supply voltages is provided. The output of each stage of the logic circuits is stored in a first register of each test circuit. Each test is performed with a critical test vector and a local supply voltage that decreases from test to test. The outputs of successive tests are compared in each test circuit. The tests are performed iteratively with successive reduction in the value of the local supply voltage until at least one stage of the logic circuits produces non-matching results between the first and second register. The voltage immediately before producing such non-matching results is the minimum operational voltage for the local voltage island. | 2009-10-01 |
20090243649 | MEMORY MODULE AND METHOD HAVING IMPROVED SIGNAL ROUTING TOPOLOGY - A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends to either another transmission line or one of the memory devices. The branches are arranged in several layers of hierarchy, with the transmission lines in branches having the same hierarchy having the same length. Each transmission line preferably has a characteristic impedance that is half the characteristic impedance of any pair of downstream transmission lines to which it is coupled to provide impedance matching. A dedicated transmission line is used to couple an additional memory device, which may or may not be an error checking memory device, to the register. | 2009-10-01 |
20090243650 | PROGRAMMABLE LOGIC DEVICES COMPRISING TIME MULTIPLEXED PROGRAMMABLE INTERCONNECT - A time multiplexed programmable switch of a semiconductor device comprising: a first node; and a plurality of second nodes, each of the second nodes having a path to couple to the first node, the path comprising: a first configurable device configured to select or deselect the path; and a second configurable device in series with the first configurable device configured to select or deselect the path by a digital signal; wherein, the plurality of digital signals are time multiplexed to have no more than one second device in the select state within a time interval. | 2009-10-01 |
20090243651 | Method and Apparatus for Decomposing Functions in a Configurable IC - Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function. | 2009-10-01 |
20090243652 | INCREMENTER BASED ON CARRY CHAIN COMPRESSION - A computational unit is disclosed to increment or decrement n-bits of data. The unit has n/3 logic blocks to process the n-bits of data, each logic block including: first and second multiplexers to propagate a carry chain; and first, second and third exclusive—OR (XOR) circuits coupled to the carry chain of the multiplexers to generate a 3-bit incremented output. | 2009-10-01 |
20090243653 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes an n-channel spin FET including one of a magnetic tunnel junction and a magneto-semiconductor junction, the n-channel spin FET including a gate terminal to receive an input signal, a source terminal to receive a first power supply potential, and a drain terminal connected to an output terminal, a p-channel FET including a gate terminal to receive a clock signal, a source terminal to receive a second power supply potential, and a drain terminal connected to the output terminal, a subsequent circuit connected to the output terminal, and a control circuit which turns on the p-channel FET to start charging the output terminal, then turns off the p-channel FET to end the charging, and supplies the input signal to the gate terminal of the n-channel spin FET. | 2009-10-01 |
20090243654 | LEVEL CONVERTER - A level converter includes a cross-coupled section for holding data and a first switching section connected in series with the cross-coupled section and supplied with a differential input signal. The level converter has a second switching section, a current mirror connection section, a third switching section, and an input/output matching evaluation section. The second switching section is connected in parallel with the cross-coupled section, and the current mirror connection section is connected in a current-mirror configuration with a transistor in the second switching section. The third switching section is connected in series with the current mirror connection section, and the input/output matching evaluation section is used to control a transistor in the third switching section by receiving the input signal and an output node signal. | 2009-10-01 |
20090243655 | CURRENT DRIVER SUITABLE FOR USE IN A SHARED BUS ENVIRONMENT - A transceiver suitable for interfacing a logic device to a shared bus includes a transmit node that receives an input signal from the logic device and an I/O node, that is coupled to the shared bus. The transceiver may be designed for use with a shared-bus, single master, multiple slave architecture, e.g., a Local Interconnect Network (LIN). In a LIN compliant implementation, the transceiver may be suitable for use in at least some types of automobiles and other motorized vehicles. Control logic coupled to the transmit node may assert a current driver enable signal in response to detecting an assertion of the input signal. A current driver of the transceiver is configured to draw a time varying driver current from the shared bus node after detecting an assertion of the current driver enable signal. The driver current may cause a sinusoidal transition of the shared bus voltage. | 2009-10-01 |
20090243656 | OUTPUT BUFFER FOR AN ELECTRONIC DEVICE - In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function. | 2009-10-01 |
20090243657 | METHODS AND APPARATUS FOR FAST UNBALANCED PIPELINE ARCHITECTURE - Methods and apparatus are provided for a fast unbalanced pipeline architecture. A disclosed pipeline buffer comprises a plurality of memory registers connected in series, each of the plurality of memory registers, such as flip-flops, having an enable input and a clock input; and a controlling memory register having an output that drives the enable inputs of the plurality of memory registers, whereby a predefined binary value on an input of the controlling memory register shifts values of the plurality of memory registers on a next clock cycle. A plurality of the disclosed pipeline buffets can be configured in a multiple stage configuration. At least one of the plurality of memory registers can comprise a locking memory register that synchronizes the pipeline buffer. The pipeline buffer can optionally include a delay gate to delay a clock signal and an inverter to invert the delayed clock signal. The clock signal can be delayed by the delay gate such that an output of the pipeline buffer is applied to a next stage of a pipeline buffer at a correct time. | 2009-10-01 |
20090243658 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance. At this point in time, a resistance value as desired is attained through combination of decoupling capacitors having threshold voltages Vth differing from each other. | 2009-10-01 |
20090243659 | METHOD AND DEVICE FOR DETECTING THE ABSENCE OF A PERIODIC SIGNAL - A method and device may determine the absence of a periodic signal or the absence of an edge of the periodic signal. The periodic signal may be a transmitted clock signal in a forwarded clock architecture. The periodic signal may be delayed by a fixed phase difference to produce a delayed periodic signal. The phase difference between the periodic signal and the delayed periodic signal may be determined. If the determined phase difference is above or below the fixed phase difference by a predetermined amount or more the periodic signal may be missing an edge. If the absence of the periodic signal or the absence of the edge of the periodic signal is detected, an error signal may be asserted. The error signal may be an in-band reset signal. | 2009-10-01 |
20090243660 | Mutual charge cancelling sample-reset loop filter for phase locked loops - In general, in one aspect, an apparatus includes a phase frequency detector, a charge pump, a voltage controlled oscillator, an integral capacitor to maintain an integral charge and provide an integral voltage, and a mutual-charge canceling sample reset (MCSR) capacitor to maintain a proportional charge and provide a proportional voltage each reference clock cycle. The MCSR includes a first proportional capacitor, a second proportional capacitor in parallel to, and having substantially identical capacitance value as, the first proportional capacitor, a first set of switches to provide direct coupling of the first and second proportional capacitors, and a second set of switches to provide cross coupling of the first and second proportional capacitors. The first and second set of switches alternatively turn on and off every reference clock cycle so that set of switches coupling the first and second proportional capacitors alternates every reference clock cycle. | 2009-10-01 |
20090243661 | SYSTEM AND METHOD TO DETECT ORDER AND LINEARITY OF SIGNALS - A method comprises applying a first delay to a first signal that is ahead of a second signal in a series of signals and determining a first number of delay units that provides the first delay to change an order between the delayed first signal and the second signal that has a phase difference with the first signal. The method further comprises determining a similar number for any other pair of signals in the series of signals that have the phase difference. The method further comprises determining a maximum and a minimum from the obtained numbers and determining linearity of the seriels of signals based on a difference between the maximum and the minimum. | 2009-10-01 |
20090243662 | MOS INTEGRATED CIRCUIT AND ELECTRONIC EQUIPMENT INCLUDING THE SAME - A MOS integrated circuit includes: a voltage-to-current conversion circuit configured to convert first and second voltages to a first current having a current value corresponding to the first voltage and a second current having a current value corresponding to the second voltage; and a current comparison circuit configured to compare the respective current values of the first and second currents and to output a voltage showing the comparison result. Oxide films of MOS transistors of the current comparison circuit are thinner than oxide films of MOS transistors of the voltage-to-current conversion circuit. | 2009-10-01 |
20090243663 | ANALOG COMPARATOR COMPRISING A DIGITAL OFFSET COMPENSATION - A digital compensation of an input stage of a comparator may be achieved by providing switched load elements, which may be appropriately connected to the differential input pair of the comparator in order to match transistor characteristics of the input pair and also match the load value of the input stage. Thus, enhanced offset behavior may be accomplished without providing an external signal and/or without requiring complex reference voltages/currents. | 2009-10-01 |
20090243664 | Data transfer method, data transfer circuit, output circuit, input circuit, semiconductor device, and electronic apparatus - A data transfer circuit comprises a voltage/current converter circuit for converting a first binary voltage data of n bits (n is an integer equal to or larger than two) to multi-value current data of 2 | 2009-10-01 |
20090243665 | Cascode Driver with Gate Oxide Protection - An apparatus including a bias voltage generator and one or more cascode drivers. Each of the one or more cascode drivers may include a plurality of cascode transistors. The bias voltage generator may control the cascode bias voltages provided to the cascode transistors based on a plurality of programmable control bits received by the bias voltage generator. The received plurality of programmable control bits may include a first set of programmable control bits, which may be used to control the magnitude of the cascode bias voltages, and a second set of programmable control bits, which may be used to control the stability of the cascode bias voltages. | 2009-10-01 |
20090243666 | A DRIVING CIRCUIT TO DRIVE AN OUTPUT STAGE - A driving circuit to drive an output stage comprising a high side NMOS and a low side NMOS is provided. The driving circuit comprises: a diode comprising an anode and a cathode, wherein the anode is electrically connected to a first voltage source and the sources of a first and a second PMOS; a third and a fourth PMOS both comprising a drain, a source and a gate, wherein the sources are respectively connected to the gates of the second and first PMOS, the drains are respectively connected to the drains of the first and second PMOS. A first and a second NMOS both comprise a drain, a source and a gate, wherein the drains are respectively connected to the drain of the fourth and third PMOS, the sources are coupled to a second voltage source, the gates are respectively connected to a first input and a second input. | 2009-10-01 |
20090243667 | OUTPUT DRIVING DEVICE - An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit. | 2009-10-01 |
20090243668 | FREQUENCY DIVIDER SPEED BOOSTER - Embodiments of the present invention synthesize a core frequency divider by adding a switching feedback shell and using multiple clock edges to trigger the frequency divider. Feedback logic is used to determine which edge will be used. Embodiments allow multiple recursive use, which boosts the overall speed resulting frequency divider circuit 2 | 2009-10-01 |
20090243669 | POWER-ON RESET CIRCUIT - A power-on reset circuit includes a voltage-dividing circuit, a first switch and a second switch. The voltage-dividing circuit includes a first resistor and a second resistor connected in series. A first terminal of the voltage-dividing circuit is configured for connect to a power source, a second terminal of the voltage-dividing circuit is grounded. A first switch includes an input terminal, a control terminal, and an output terminal. The input terminal of the first switch is connected to the first terminal of the voltage-dividing circuit via the first resistor, and the output terminal of the first switch is grounded. A second switch includes an input terminal connected to the first terminal of the voltage-dividing circuit, a control terminal connected to the control terminal of the first switch, and an output terminal connected to a reset terminal of an electronic device. | 2009-10-01 |
20090243670 | SELF-REGULATED CHARGE PUMP WITH LOOP FILTER - One embodiment described is a charge pump arrangement that includes at least one input node and two output nodes. A regulator is included to regulate at least one of the two output nodes, the regulator is decoupled from one of the two output nodes, and the regulator has at least one input coupled directly to virtual ground. | 2009-10-01 |
20090243671 | DISTURBANCE SUPPRESSION CAPABLE CHARGE PUMP - One embodiment described is charge pump arrangement that includes a regulator to regulate signals associated with two output nodes. A switching mechanism may be coupled to the regulator. The switching mechanism is to interrupt the regulator. | 2009-10-01 |
20090243672 | MULTI-POLE DELAY ELEMENT DELAY LOCKED LOOP (DLL) - In general, in one aspect, the disclosure describes a delay line including a cascade of delay stages where each stage delays the phase a defined amount. Each delay stage includes an active voltage control delay element and one or more passive delay elements (e.g., resistive-capacitive (RC) networks). The aggregate amplitude gain roll-off of an active/passive multi pole delay stage delaying the phase a defined amount is less than the amplitude gain roll-off of a single pole delay stage delaying the phase the defined amount. Accordingly jitter amplification of the active/passive multi pole delay stage is less than that of a single pole delay stage. The power consumption of an active/passive multi pole delay stage is less than an all active multi pole delay stage. | 2009-10-01 |
20090243673 | PHASE LOCKED LOOP SYSTEM AND PHASE-LOCKING METHOD FOR PHASE LOCKED LOOP - A PLL (phase locked loop) system includes a PLL and a lock detector. The PLL is for outputting a phase-locking clock signal. The lock detector is coupled to the PLL for detecting whether or not the frequency of the phase-locking clock signal falls within a predetermined frequency range and detecting whether or not the phase-locking clock signal is stable. If the frequency of the phase-locking clock signal has fallen within the predetermined frequency range and the phase-locking clock signal is stable by detection, the lock detector outputs a lock signal. | 2009-10-01 |
20090243674 | Fractional-N Phased-Lock-Loop (PLL) System - In one general embodiment, a fractional-N phased-lock-loop (PLL) structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. Additional systems and structures are also presented. | 2009-10-01 |
20090243675 | Optimization Method For Fractional-N Phased-Lock-Loop (PLL) System - In one general embodiment, a method is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Furthermore, the first phase noise is compared with the second phase noise. Also, the second circuit is conditionally modified to optimize the performance of the integrated circuit, based on a result of the comparison. Additional methods are also presented. | 2009-10-01 |
20090243676 | Design Structure For Fractional-N Phased-Lock-Loop (PLL) System - In one general embodiment, a hardware description language (HDL) design structure is encoded on a machine-readable data storage medium, said HDL design structure comprising elements that when processed in a computer-aided design system generates a machine-executable representation of a fractional-N phased-lock-loop (PLL) structure. The fractional-N PLL structure comprises a first circuit located on an integrated circuit, where the first circuit includes a voltage controlled oscillator for generating a periodic output signal, a phase detector for controlling the voltage controlled oscillator, a charge pump for modifying an input to the voltage controlled oscillator, a frequency divider in a feedback path for modifying a frequency of the output signal, a first multiplexer, and a first random number generator. The fractional-N phased-lock-loop (PLL) structure further comprises a second circuit including a second multiplexer and a second random number generator, wherein the second circuit is a programmable circuit located off the integrated circuit and coupled to the first circuit. A method in a computer-aided design system for generating a functional design model of a fractional-N phased-lock-loop (PLL) structure is provided in one embodiment. A design structure embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit is presented in another embodiment. | 2009-10-01 |
20090243677 | Clock generator and methods using closed loop duty cycle correction - Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal. By detecting the duty cycle error in the output signal, the clock generator may achieve improved performance that can correct accumulated duty cycle error and correct for duty cycle error introduced by the duty cycle corrector itself in some embodiments. | 2009-10-01 |
20090243678 | Delay locked-loop circuit and display apparatus - A delay locked-loop circuit includes: a phase comparator detecting a phase difference between an external clock and an internal clock; an up/down counter controlling a delay time in accordance with an output signal from the phase comparator; and a delay line including plural unit delay circuits corresponding to plural bits of a signal output from the up/down counter in order to control the delay of the external clock to conform the external clock to the internal clock, and in which the unit delay circuits controlled by the output from a same bit in the output from the up/down counter are not connected adjacently to each other in the connection of the plural unit delay circuits in series. | 2009-10-01 |
20090243679 | Semi-Digital Delay Locked Loop Circuit and Method - A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal. | 2009-10-01 |
20090243680 | DATA SIGNAL GENERATING APPARATUS - It is an object of the present invention to provide a data signal generating apparatus which is small in size, and can output the serial data in a desired sequence without assuming an indefinite state as well as being capable of dealing with the jitter measurement. In the data signal generating apparatus according to the present invention, synchronization means | 2009-10-01 |
20090243681 | Embedded Source-Synchronous Clock Signals - A synchronous communication system includes two transmitters that transmit respective first and second data signals that are phase offset from one another by about 90 degrees. On the receive side, a pair of extraction circuits extract a first clock signal from the first data signal and a second clock signal from the second data signal. The clock signals are offset from one another by about 90 degrees due to the phase offset of the corresponding data signals. Edges of the first clock signal are thus centered within the symbols of the second data signal, and edges of the second clock signal are centered within the symbols of the first data signal. A pair of receivers employs the first clock signal to sample the second data symbol and the second clock signal to sample the first data signal. | 2009-10-01 |
20090243682 | METHOD, SYSTEM AND DEVICE FOR ELIMINATING INTRA-PAIR SKEW - A method, system and device for eliminating intra-pair skew are disclosed. The method includes: measuring a phase difference between the received differential signals as a transmission delay difference; and compensating delays of the differential signals using the transmission delay difference, to eliminate intra-pair skew of the differential signals. A phase difference measuring apparatus is used to measure a phase difference between the differential signals as the transmission delay difference, so that the transmission delay difference may be adjusted according to the phase difference. Therefore, the procedure for eliminating intra-pair skew is effectively simplified, and the effect of adjusting the transmission delay difference is improved. | 2009-10-01 |
20090243683 | PULSE TRANSFORMER DRIVER - Methods, systems, and devices are described for providing a communication system for handling pulse information. Embodiments of the invention provide a pulse shaping unit operable to avoid saturation of the pulse transformer, while being easily incorporated into IC processes. Some embodiments of the pulse shaping unit provide a two-to-three level driver unit for converting a two-level input voltage signal to a three-level driver signal for driving a pulse transformer. Other embodiments of the pulse shaping unit provide components configured to differentially drive a pulse transformer, effectively converting a two-level input voltage signal to a three-level driver signal. | 2009-10-01 |
20090243684 | METHOD AND DEVICE FOR GENERATING A DIGITAL DATA SIGNAL AND USE THEREOF - In an embodiment, the present invention relates to an integrated circuit comprising at least one data signal input (data | 2009-10-01 |
20090243685 | SIGNAL PROCESSING DEVICE - A signal processing device includes a correction circuit configured to correct the distortion of the duty cycle in a data signal having different occurrence probabilities of 0 and 1. | 2009-10-01 |
20090243686 | LATCH CIRCUIT AND ELECTRONIC DEVICE - A latch circuit includes: four or more gates; three input terminals and one or two output terminals which are connected to at least one of the four or more gates; a feedback circuit in which respective input terminals of the four or more gates are connected to output terminals of at least another two of the four gates; and a data inverting gate which, when all data input into the three input terminals is the same, outputs inverted data of the data from the output terminals, and when all the data input into the three input terminals is not the same, retains previous data. | 2009-10-01 |
20090243687 | ROBUST TIME BORROWING PULSE LATCHES - Configurable time-borrowing flip-flops may be based on configurable pulse generation circuitry and pulse latches. The circuitry may use a self-timed architecture that controls the width of clock pulses that are generated so that the pulse latches that are controlled by the clock pulses exhibit a reduced risk of race through conditions. Latch circuitry may be provided that is based on a pulse latch and an additional latch connected in series with the pulse latch. In situations in which there is a potential for race through conditions on an integrated circuit, the additional latch may be switched into use to convert the latch circuitry into an edge-triggered flip flop. Clock trees may be provide with configurable shorting structures that help to reduce clock skew. Low-contention clock drivers may drive signals onto the clock tree paths. | 2009-10-01 |
20090243688 | SYSTEM AND METHOD OF CHANGING A PWM POWER SPECTRUM - In a particular embodiment, a circuit device includes a pulse edge control circuit to receive at least one pulse-width modulated (PWM) signal from a PWM source. The pulse edge control circuit is adapted to selectively apply a phase shift operation to the at least one PWM signal at integer submultiples of a frame repetition rate to produce at least one modulated PWM signal having a changed power spectrum. The pulse edge control circuit provides the at least one modulated PWM signal to at least one output of the pulse edge control circuit. | 2009-10-01 |
20090243689 | DELAY LINE CIRCUIT - Delay circuitry is described that includes clock mixing circuitry to provide a selectable propagation time. Output signals from the mixing circuitry are selectively coupled through a variable delay line to synchronize two clock signals. | 2009-10-01 |
20090243690 | SINGLE-CLOCK-BASED MULTIPLE-CLOCK FREQUENCY GENERATOR - In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a clock signal quadrature output frequency and a clock signal in-phase output frequency. The clock generator circuit generates a single clock frequency that is a fraction of the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output that is phase and frequency synchronized to the single clock frequency. | 2009-10-01 |
20090243691 | Signal output circuit - Disclosed is a signal output circuit comprising: a first transistor of an emitter follower configuration, which receives an input signal; a second transistor of an emitter follower configuration, which receives the input signal, and has an output connected to an external load ( | 2009-10-01 |
20090243692 | Two Voltage Input Level Shifter with Switches for Core Power Off Application - A voltage level shifter includes a first switch module having a first transistor and a second transistor, each transistor having a drain, a gate, and a source, wherein the drains of the first and the second transistors are coupled to a first voltage terminal. The voltage level shifter further includes a second switch module coupled between the first switch module and a second voltage terminal, the second switch module including at least six transistors coupled each other, wherein each transistor of the second switch module having a gate for receiving a GATE signal, a GATEb signal, a CORE_INPUT signal, a CORE_INPUTb signal, an IO_INPUT signal, or an IO_INPUTb signal, respectively, wherein the second switch module is designed to produce an output signal at an output node in response to the IO_INPUTb signal and the IO_INPUT signal respectively, irrespective of the CORE_INPUTb signal and the CORE_INPUT signal when the GATE signal is logic low, thereby reducing a leakage current flowing from the first voltage terminal to the second voltage terminal. | 2009-10-01 |
20090243693 | CIRCUIT FOR PROVIDING DETERMINISTIC LOGIC LEVEL IN OUTPUT CIRCUIT WHEN A POWER SUPPLY IS GROUNDED - A high voltage analog interface circuit capable of producing a determinate zero or other low voltage when the high voltage power supply is turned off or grounded. | 2009-10-01 |
20090243694 | VOLTAGE CONVERTING DRIVER APPARATUS - A voltage converting apparatus is provided that includes a dynamic driver circuit and a voltage converting circuit. The dynamic driver circuit may receive a clock signal and input signals and provide a dynamic signal based on the clock signal and the input signals. The voltage converting circuit may receive the dynamic signal from the dynamic driver circuit and provide an output signal based on the received dynamic signal. The dynamic driver circuit may be powered by a first voltage source and the voltage converting circuit may be powered by a second voltage source. | 2009-10-01 |
20090243695 | BI-DIRECTIONAL LEVEL SHIFTED INTERRUPT CONTROL - The present example provides a circuit offering interoperability between circuits that may be powered from differing voltages, and that may operate at differing logic levels. Isolation may be provided from the impedance provided by transistor circuits and level shifting may be provided by a divider network. Accordingly, an exemplary slave and a master (or equivalently two circuits which are being coupled together) can operate on different voltages. This may be useful because some circuits such as processors can require higher or lower voltage than other processors that are sought to be coupled together. The circuit also may require one “read only” and another “input/output” pin, therefore, reducing the resources needed to implement the circuit functions. The present example can be useful for microprocessors that can use a software algorithm for the communications protocol, which can be economical to implement as it utilizes one input/output pin and one input only pin. | 2009-10-01 |
20090243696 | HIGH VOLTAGE SEMICONDUCTOR DEVICE HAVING SHIFTERS AND METHOD OF FABRICATING THE SAME - Provided are a high-voltage semiconductor device including a junction termination which electrically isolates a low voltage unit from a high voltage unit, and a method of fabricating the same. The high voltage semiconductor device includes a high voltage unit, a low voltage unit surrounding the high voltage unit, and a junction termination formed between the high voltage unit and the low voltage unit and surrounding the high voltage unit to electrically isolate the high voltage unit from the low voltage unit. The junction termination includes at least one level shifter which level shifts signals from the low voltage unit and supplies the same to the high voltage unit, a first device isolation region surrounding the high voltage unit to electrically isolate the high voltage unit from the level shifter, and a resistor layer electrically connecting neighboring level shifters. | 2009-10-01 |
20090243697 | LEVEL SHIFT CIRCUIT, METHOD FOR DRIVING THE SAME, AND SEMICONDUCTOR CIRCUIT DEVICE HAVING THE SAME - A level shift circuit includes a level shift section for receiving a low potential signal oscillating between a high potential and a ground potential and converting it into a high potential signal oscillating between the high potential and the ground potential, the level shift section being connected to at least a high potential power supply for generating the high potential, a low potential power supply for generating the low potential, and a ground power supply for generating the ground potential, an inverter section for inverting-amplifying the high potential signal from the level shift section, and an N-type MOS transistor for supplying the ground potential to the inverter section, the N-type MOS transistor being connected in series to the inverter section between the high potential power supply and the ground power supply and having its gate electrode connected to the low potential power supply. | 2009-10-01 |
20090243698 | MIXER AND FREQUENCY CONVERTING APPARATUS - A mixer includes: a magnetoresistive effect element including a fixed magnetic layer, a free magnetic layer, and a nonmagnetic spacer layer disposed between the fixed magnetic layer and the free magnetic layer; and a magnetic field applying unit that applies a magnetic field to the free magnetic layer. The mixer is operable, when a first high-frequency signal and a second high-frequency signal as a local signal are inputted, to multiply the first high-frequency signal and the second high-frequency signal using the magnetoresistive effect element and to generate a multiplication signal. A frequency converting apparatus includes the mixer and a filter operable, when a higher frequency and a lower frequency out of frequencies of the first high-frequency signal and the second high-frequency signal are expressed as f | 2009-10-01 |
20090243699 | SYSTEM AND METHOD OF COMPANDING AN INPUT SIGNAL OF AN ENERGY DETECTING RECEIVER - An apparatus configured as a compandor to achieve a defined dynamic range for an output signal in response to an input signal. In particular, the apparatus comprises a first circuit adapted to generate a first signal from the input signal, wherein the first signal includes a first dynamic range (e.g., a first sensitivity and first compression point); and a second circuit adapted to generate a second signal from the input signal, wherein the second signal includes a second dynamic range (e.g., a second sensitivity and second compression point) that is different from the first dynamic range of the first signal. The apparatus may further include a third circuit adapted to generate an output signal related to a sum of the first and second signals. By adjusting the first and second dynamic ranges, an overall dynamic range for the output signal of the companding apparatus may be achieved. | 2009-10-01 |
20090243700 | MIXER CIRCUIT FOR FREQUENCY MIXING OF DIFFERENTIAL SIGNALS - A mixer circuit designed for low voltage operation with rail-to-rail local signals. First and second transistors form a first input section to produce a first signal. Third and fourth transistors form a second input section to produce a second signal. Fifth and sixth transistors form a third input section to produce a third signal. Seventh and eighth transistors form a fourth input section to produce a fourth signal. A differential RF input signal drives the first, third, fifth, and seventh transistors, while a differential local signal drives the second, fourth, sixth, and eighth transistors. Ninth and tenth transistors form a positive output section to produce a non-inverted output signal. Eleventh and twelfth transistors form a negative output section to produce an inverted output signal. The ninth to twelfth transistors are driven by the first to fourth signals, respectively. | 2009-10-01 |
20090243701 | Power Supply with Digital Control Loop - One embodiment of an apparatus for switching a transistor includes a first current mirror providing i | 2009-10-01 |
20090243702 | VARACTOR BANK SWITCHING BASED ON NEGATIVE CONTROL VOLTAGE GENERATION - A method and apparatus for varactor bank switching for a voltage controlled oscillator is disclosed. Varactor bank switching involves generating a negative bias voltage signal as a control signal for a varactor bank switch in an off-state, the varactor bank switch comprising a pass-gate circuit including switching transistors. Generating the negative bias voltage signal includes employing an active rectifier circuit running at the speed of an oscillation signal, the negative bias voltage signal maintaining the gate-source voltage of the pass-gate circuit below a threshold voltage to prevent said switching transistors from becoming conductive in an off-state. | 2009-10-01 |
20090243703 | HIGH-FREQUENCY SWITCHING CIRCUIT MODULE - A high-frequency switching circuit module includes a high-frequency switch that includes an FET switching element and that selectively connects between a common input/output terminal and one of input/output terminals, and a matching circuit that is provided to the common input/output terminal Pc and is not provided to the input/output terminals. Although a non-selected input/output terminal of the high-frequency switch acts as a capacitor and the impedance between the common input/output terminal and a selected input/output terminal is displaced from a normal impedance, the displacement is corrected by the matching circuit connected to the common input/output terminal such that the impedance viewed from the common input/output terminal Pc to the high-frequency switch is made equal to the normal impedance. Accordingly, a high-frequency switching circuit module having a small overall size and achieving impedance matching for each terminal is provided. | 2009-10-01 |
20090243704 | Internal voltage generator - An internal voltage generator includes an internal voltage detecting unit that receives an active signal activated in an active operation mode of a semiconductor memory and a bias voltage varying according to temperature variation, detects a level of an internal voltage by using a reference voltage and outputs an internal voltage pumping signal activated according to the level of the internal voltage. | 2009-10-01 |
20090243705 | High Voltage Tolerative Driver Circuit - A high voltage tolerative inverter circuit is disclosed, which comprises a PMOS transistor with a source and drain being connected to a first high voltage power supply (VDDQ) and an output terminal, respectively, a gate of the PMOS transistor being controlled by a first signal having a voltage swing between the VDDQ and a low voltage power supply (VSS), and a NMOS transistor with a source and drain being connected to the VSS and the output terminal, a gate of the NMOS transistor being controlled by a second signal having a voltage swing between a second high voltage power supply (VDD) and the VSS, wherein the VDD is lower than the VDDQ, and the voltage swings between the VDDQ and the VSS by the first signal and between the VDD and the VSS by the second signal are always in the same direction. | 2009-10-01 |
20090243706 | VOLTAGE REGULATED CHARGE PUMP - A voltage regulated charge pump includes a charge pump circuit for receiving an input voltage to generate an output voltage, in which the charge pump circuit further includes a capacitor, a first switch and a second switch. The first switch is coupled between the input voltage and a first end of the capacitor. The second switch is coupled to the first end of the capacitor. The first and second switch are non-simultaneously turned on, so that the capacitor is charged to generate the output voltage. The voltage regulated charge pump further includes a third switch and a voltage regulating circuit. The third switch is coupled to the charge pump circuit. The voltage regulating circuit has an input receiving the output voltage and an output coupled to the third switch. The voltage regulating circuit modulates the third switch for regulating the output voltage generated by the charge pump circuit. | 2009-10-01 |
20090243707 | SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS AND ELECTRONIC APPARATUS - Semiconductor integrated circuit apparatus and electronic apparatus having a leakage current detection circuit where arbitrarily set leakage current detection ratio does not depend on power supply voltage, temperature, or manufacturing variations, and where leakage current detection is straightforward. Semiconductor integrated circuit apparatus extracts a stable potential from the center of two NchMIS transistors, amplifies drain current of an NchMOS transistor taking this potential as a gate potential to a current value of an arbitrary ratio using current mirror circuit, makes this current value flow through NchMOS transistor with the gate and drain connected, and applies drain potential of this NchMOS transistor to the gate of leakage current detection NchMOS transistor. | 2009-10-01 |
20090243708 | BANDGAP VOLTAGE REFERENCE CIRCUIT - A bandgap voltage reference circuit which provides a bandgap reference voltage without requiring a resistor. The circuit comprises an amplifier having an inverting input, a non-inverting input and an output. First and second bipolar transistors are provided which operate at different current densities each coupled to a corresponding one of the inverting and non-inverting inputs of the amplifier. A load MOS transistor of a first aspect ratio is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance r | 2009-10-01 |
20090243709 | DEVICES, SYSTEMS, AND METHODS FOR GENERATING A REFERENCE VOLTAGE - Methods, devices, and systems are disclosed for a voltage reference generator. A voltage reference generator may comprise a bandgap voltage reference circuit configured to output two complementary-to-absolute-temperature (CTAT) signals. The voltage reference generator may further comprise a differential sensing device configured to sense the two complementary-to-absolute-temperature (CTAT) signals and generate a positive reference signal substantially insensitive to temperature variations over an operating temperature range. | 2009-10-01 |
20090243710 | FIREWALL/ISOLATION CELLS FOR ULTRA LOW POWER PRODUCTS - In an integrated circuit (IC) may have several functional blocks adapted to be inactivated independently from each other. At least one firewall cell may be embedded independently of other firewall cells in the vicinity of one functional block. The firewall cell may be electrically isolated from the functional block and may be powered by a constantly supplied voltage source in the IC. Firewall cells may be embedded in free locations on the IC in the functional block domain according to a design that may be free of constraints such as firewall cells array of firewall cells mini-island. | 2009-10-01 |
20090243711 | BIAS CURRENT GENERATOR - A bias current generator for generating bias current is described. The generator comprises an amplifier having an inverting input, a non-inverting input and an output. A first bipolar transistor is associated with one of the inverting and non-inverting inputs of the amplifier. A load MOS device is associated with the other one of the inverting and non-inverting inputs of the amplifier. The load MOS device is driven by the amplifier to operate in the triode region with a corresponding drain-source resistance r | 2009-10-01 |
20090243712 | Device for reducing power consumption inside integrated circuit - The present invention discloses a device for reducing power consumption inside an integrated circuit (IC), comprising: an IC including an up-gate transistor and a low-gate transistor electrically connected with each other, and a control circuit controlling the up-gate transistor and the low-gate transistor; and a resistor located outside the IC, the resistor having one end electrically connected with a node between the up-gate transistor and the low-gate transistor, or electrically connected with an upper end of the up-gate transistor. | 2009-10-01 |
20090243713 | REFERENCE VOLTAGE CIRCUIT - A reference voltage circuit which is less dependent on semiconductor process variations compared to bandgap based reference voltage circuits. The circuit comprises a first amplifier having an inverting input, a non-inverting input and an output. A current biasing circuit provides first and second PTAT currents, and a CTAT current. The CTAT current is equal in value to the second PTAT at a first predetermined temperature and opposite in polarity. A first load element is coupled to the non-inverting input of the first amplifier and arranged for receiving the first PTAT current such that a PTAT voltage is developed across the first load element. A feedback load element is coupled between the inverting input and the output of the amplifier for receiving the summation of the CTAT current and the second PTAT current. The feedback load element is such that at a second predetermined temperature the voltage at the output of the amplifier is substantially equal to the voltage at the output of the amplifier at the first temperature. | 2009-10-01 |
20090243714 | Power noise immunity circuit - A power noise immunity circuit includes a unidirectional device and a switch both connected between a power input terminal and a power output terminal, and a noise detector to control the switch. The power input terminal is for being connected to an external voltage source, and the power output terminal is for being connected to the circuit of an IC. The switch is normally closed and is opened by the noise detector if the noise detector detects power noise at the power input terminal. The power noise immunity circuit thus prevents the IC from power breakdown and provides a stable voltage thereto. | 2009-10-01 |
20090243715 | Device and Method for Limiting Di/Dt Caused by a Switching FET of an Inductive Switching Circuit - A circuit for limiting di/dt caused by a main switching FET during its turn-off against an inductive switching circuit is proposed. The circuit for limiting di/dt includes:
| 2009-10-01 |
20090243716 | DEMODULATION CIRCUIT - A demodulation circuit, including: an input terminal (IN) inputting a current amplitude modulated signal; a first transistor ( | 2009-10-01 |
20090243717 | Compact high-speed modulator driver method and apparatus - Modulator driver for driving an electro-optical modulator in a high-speed optical communications system. In accordance with aspects of the present invention, a modulator driver is presented comprising an input differential limiting amplifier which is coupled to a distributed differential current-switch configuration, where one set of outputs of the distributed differential current-switch configuration are grounded and the other set of outputs are connected to an artificial transmission line structure generating forward traveling and reverse traveling signals, with the reverse traveling signal termination bias inductively coupled to a separately adjustable positive bias voltage, whereby the circuit architecture reduces the number of components and transitions in the high-speed signal path and is compatible with compact, monolithic fabrication requiring a minimal amount of external components for operation. Other methods and apparatus are presented. | 2009-10-01 |
20090243718 | High-speed modulator driver circuit with enhanced drive capability - Modulator driver for driving an electro-optical modulator in a high-speed optical communications system. In accordance with aspects of the present invention, a modulator driver is presented comprising an input differential limiting amplifier providing differential outputs coupled to a distributed enhanced drive output stage configuration, wherein said distributed enhanced drive output stage configuration comprises a plurality of inductively coupled enhanced drive differential amplifiers, each of said enhanced drive differential amplifiers comprising a plurality of transistors in a cascode configuration whereby the control electrode of the upper transistor in said cascode configuration is biased by a voltage having a modulation component derived from either an input signal to or output signal from said enhanced drive differential amplifier, for the purpose of providing an enhanced output voltage swing capability that exceeds the breakdown voltage of a single transistor. Other methods and apparatus are presented. | 2009-10-01 |
20090243719 | Broadband Amplifying Device - The present invention relates to an amplification device for a satellite in order to amplify a plurality of n transmission channels to an output corresponding to a beam, the device comprising:
| 2009-10-01 |
20090243720 | AMPLIFIERS WITH NEGATIVE CAPACITANCE CIRCUITS - Provided herein are amplifiers including negative capacitance circuits for reducing distortion resulting from a gate-source (or base-emitter) capacitance of output stages of such amplifiers. Such a negative capacitance circuit is connected in parallel with the gate-source (or base-emitter) capacitance of the output stage to shunt the gate-source (or base-emitter) capacitance and thereby reduce distortion. Also provided herein are methods for use with amplifiers including an output stage, including connecting a negative capacitance circuit in parallel with a base-emitter capacitance of the output stage. | 2009-10-01 |
20090243721 | FEEDFORWARD AMPLIFIER CIRCUIT AND METHOD FOR CONTROLLING A FEEDFORWARD AMPLIFIER CIRCUIT - A feedforward amplifier circuit includes a controllable error signal subtraction module (CESSM). The CESSM has a module signal input, an error cancellation input, a module control input and a circuit output. The module signal input of the CESSM is coupled to a power amplifier via a coupler and delay circuit. The error cancellation input is coupled to a feedforward subtraction module via an error signal amplifier. The module control input is coupled to the output of a controller. In operation, the CESSM subtracts an error cancellation signal from the module signal input. Upon determining a malfunction of the power amplifier, the controller sends a signal to the module control input resulting in the CESSM isolating the module signal input from the circuit output and directly coupling the error cancellation to the circuit output. | 2009-10-01 |
20090243722 | Reduction of power consumption and EMI of a switching amplifier - A switching amplifier has a network including current sources and resistors connected to the two output terminals of the H-bridge of the switching amplifier, to provide a small current to the load connected between the two output terminals at zero input, whereby the common mode voltage bouncing is reduced and the switching amplifier has less power consumption and reduced electro-magnetic interference. | 2009-10-01 |
20090243723 | DIFFERENTIAL AND SYMMETRICAL CURRENT SOURCE - A controlled, symmetrical, stable current source that can power floating resistive loads, eliminates the need to connect the load directly to either a power supply or ground and protects the load against overpower should either or both sides of the load be shorted to ground. The current source includes two operational amplifiers for providing a current through the load that is proportional to an input voltage applied across the respective non-inverting inputs of the two operational amplifiers; two current sensing resistors for providing voltage drops that are proportional to the current through the load; and four summing resistors connected to the sensing resistors for providing to the inverting inputs of the operational amplifiers voltages that offset the sum of the voltage drops provided by the sensing resistors so that the current through the load is controlled by only the input voltage. | 2009-10-01 |
20090243724 | Third Order Derivative Distortion Cancellation for Ultra Low Power Applications - An apparatus and method for the cancellation of third order derivative distortion for ultra low power (ULP) applications are disclosed involving a first amplifier connected in parallel with a second amplifier for amplifying a received signal. The first amplifier includes at least one transistor operating in the sub-threshold region such that the first amplifier possesses a positive third derivative of a transfer function of the first amplifier, which generates a first amplified signal having in phase third order distortions. The second amplifier includes at least one differential pair of transistors operating in the sub-threshold region such that the second amplifier possesses a negative third derivative of a transfer function of the second amplifier, which generates a second amplified signal having in opposite phase third order distortions. The first and second amplified output signals are combined resulting in cancellation of third order distortions in the combined amplified signal. | 2009-10-01 |
20090243725 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first transistor unit including first field effect transistors with first gate electrodes electrically connected together, first sources electrically connected together, and first drains electrically connected together, the first gate electrodes being electrically connected to the first drains, a second transistor unit including second field effect transistors with second gate electrodes electrically connected together, second sources electrically connected together, and second drains electrically connected together, the second gate electrodes being electrically connected to the first gate electrodes, and dummy gate electrodes electrically isolated from the first gate electrodes and the second gate electrodes. The first gate electrodes, the second gate electrodes, and the dummy gate electrodes are arranged parallel to one another, and at least one dummy gate electrode is located between any one of the first gate electrodes and any one of the second gate electrodes. | 2009-10-01 |
20090243726 | VARIABLE RESISTOR ARRAY AND AMPLIFIER CIRCUIT - A variable resistor array adapted to make a resistance value between a first terminal and a second terminal variable, includes a plurality of resistors connected in series, first through nth MOS transistors selectively connected to the resistors, and first through nth switches having one input terminal connected to the source of the ith MOS transistor, another input terminal connected to a predetermined voltage, and an output terminal connected to a back gate of the ith MOS transistor, and connecting either one of the one input terminal and the other input terminal to the output terminal under control of the ith control signal. The ith switch connects the other input terminal to the output terminal, and the ith switch also connects the one input terminal to the output terminal. | 2009-10-01 |
20090243727 | Compensating for non-linear capacitance effects in a power amplifier - In one implementation, a power amplifier may include a gain device to receive an input signal and to output an amplified signal, and a compensation device coupled to the gain device to compensate for a change in a capacitance of the gain device occurring due to a change in the input signal. The power amplifier may be formed using a complementary metal oxide semiconductor (CMOS) process. | 2009-10-01 |
20090243728 | Splitter circuit - A splitter circuit improves isolation between output ports. The splitter circuit comprises input port | 2009-10-01 |
20090243729 | CONTROLLING OVERLOAD OF A TRANSIMPEDANCE AMPLIFIER IN AN OPTICAL TRANSCEIVER - Briefly, in accordance with one or more embodiments, a transimpedance amplifier of an optical transceiver or the like has a feedback element in a feedback arrangement and is capable of receiving an electrical current from an optical-to-electrical converter to generate an output voltage in response to the electrical current. A control circuit coupled to the feedback element is capable of providing a control signal to control a bias current of the transimpedance amplifier to maintain DC current flowing through the feedback element at or near zero by changing the bias current in response to the control circuit detecting a non-zero DC current flowing through the feedback element. | 2009-10-01 |
20090243730 | CONVERTING CIRCUIT FOR CONVERTING DIFFERENTIAL SIGNAL TO SINGLE-ENDED SIGNAL - A converting circuit for converting differential signals to a single-ended signal. The converting circuit comprises a cascode amplifier comprising a first transistor and a second transistor, wherein the first transistor comprises a control terminal, a first terminal, and a second terminal, the control terminal to which one of the differential signals is input, the control terminal being electrically-grounded; and, the second transistor comprises a first terminal and a second terminal, the first terminal of the second transistor being connected to the first terminal, the second terminal of the second transistor from which output signal is outputted, a capacitor for adjusting the phase, the capacitor being connected to the second terminal; and a current source being connected to the second terminal. | 2009-10-01 |
20090243731 | Apparatus With Clock Generation Function, Method For Setting Reference Frequency, And Method For Adjusting Reference Frequency - An apparatus includes an oscillator, a memory for storing data of a first frequency and of a first voltage, a first controller for causing the oscillator to generate a clock having a required frequency by applying a voltage on the basis of the data of the first frequency and of the first voltage, a second controller for causing the oscillator to generate a clock having a second frequency by applying a second voltage at predetermined timing, an output section for outputting data of the clock of the second frequency to a frequency counter, a writing section for updating the data of the first voltage to data of the second voltage and the data of the first frequency to data of the second frequency when a difference between the second frequency and a third frequency is within a predetermine range. | 2009-10-01 |
20090243732 | SDOC with FPHA & FPXC: System Design On Chip with Field Programmable Hybrid Array of FPAA, FPGA, FPLA, FPMA, FPRA, FPTA and Frequency Programmable Xtaless ClockChip with Trimless/Trimfree Self-Adaptive Bandgap Reference Xtaless ClockChip - The Field Programmable Hybrid Array (FPHA) and Frequency Programmable Xtaless Clock (FPXC) are for high-speed and high frequency System-Design-On-Chip(SDOC). The FPXC adopts the Self-Adaptive Process & Temperature Compensation Bandgap Reference Generator, the Gain-Boost Amplitude Control LC VCO and inverter type flash memory. The FPHA adopts the two-way flash switch and inverter type flash memory Look-Up-Table(LUT). The FPXC adopts the inverter type flash memory as the Non-Volatile Memory(NVM) to keep the setup data in the field frequency programming. The flash technology of FPHA and FPXC are compatible that the FPHA has the FPXC capability. The PLLess CDR(PLL free Clock Data Recovery) is based on the FPXC capability for the SerDes high frequency application. The PLLess CDR and pipeline ADC are for the analog front high frequency application. With the SDOC on FPHA, the Automobile Infotainment Center(MIC) is reduced to be Mobile Infotainment Center(MIC). The ( | 2009-10-01 |
20090243733 | DESIGN STRUCTURE FOR TRANSFORMING AN INPUT VOLTAGE TO OBTAIN LINEARITY BETWEEN INPUT AND OUTPUT FUNCTIONS AND SYSTEM AND METHOD THEREOF - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a first structure for determining a non-linear characteristic of the input voltage to the output frequency response, the first design structure providing a tunneling-based current relationship with the input voltage. Also disclosed is a system and a method of implementing such structure. | 2009-10-01 |
20090243734 | METHOD AND DEVICE FOR DETERMINING A DUTY CYCLE OFFSET - Embodiments of the present invention relate to a method and device operable to determine a duty cycle offset of a periodic signal and correct the periodic signal to a desired duty cycle. Embodiment of the present invention may include a ring oscillator circuit. The ring oscillator includes an odd number of ordered inverting elements. One or more of the inverting elements may be an inverting memory element. Each inverting element's output port (except the last inverting element) may be operably connected to the subsequent inverting element's input port. The last inverting element's output port may be operably connected to the first inverting element's input port, thereby forming a chain or ring. A counter may be incremented by oscillations of an output port of an inverting element during a high portion of a periodic signal and may be decremented by oscillations of the output port of the inverting element during a low portion of the periodic signal. The end result in the counter may be proportional to the duty cycle offset of the periodic signal. The end value may then be used to correct the duty cycle of the periodic signal to a desired duty cycle offset. | 2009-10-01 |
20090243735 | FREQUENCY DIVERSE DISCRETE-TIME PHASE-LOCK DEVICE AND APPARATUS - A discrete-time phase lock loop (DTPLL) includes an analog section comprising a digital-to-analog converter (DAC) and an oscillator, operative to provide a clock signal based on an input from the DAC. The DTPLL also includes a digital signal processor (DSP). The DSP includes a loop controller state machine; a phase detector; a counter, operative to receive clock signals from the oscillator and to provide a count value to the phase detector; a divider, operative to receive a reference signal and to provide a reference pulse output to the phase detector; and a loop filter operative to provide a control effort value based on an output from the phase detector. Based on the phase error value, an output of the oscillator is changed to reduce the phase error to a steady state value. | 2009-10-01 |
20090243736 | Phase locked loop circuit and integrated circuit for the same - The present invention provides a phase locked loop circuit including: a voltage controlled oscillator; a variable frequency-dividing circuit; a phase comparing circuit for comparing a phase of the frequency-dividing signal a charge pump circuit; a loop filter; a voltage supplying circuit; a frequency measuring circuit; and a voltage measuring circuit. | 2009-10-01 |