| 40th week of 2009 patent applcation highlights part 19 |
| Patent application number | Title | Published |
|---|
| 20090243034 | SEMICONDUCTOR DEVICE - A semiconductor device including a doped substrate of a first doping polarity and a doped semiconductor material of a second doping polarity. The semiconductor material is on, or in, the substrate, and the second doping polarity is opposite the first doping polarity such that the semiconductor material and the substrate form a diode. The semiconductor device further includes an inductor on or above the semiconductor material, and a pattern in the semiconductor material for reducing eddy currents. The pattern includes a doped semiconductor material of the first doping polarity and a least one trench within the doped semiconductor material of the first doping polarity, wherein, at least at a depth at which the trench is closest to the inductor, the doped semiconductor material of the first doping polarity fully surrounds the trench so that, at least at the depth, the trench does not touch the doped semiconductor material of the second doping polarity. | 2009-10-01 |
| 20090243035 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE MOUNTING STRUCTURE - In a semiconductor device that is formed by joining two semiconductor elements together to oppose device layers to each other, inductor patterns for transmitting and receiving a signal and feeding a power and bumps for connecting electrically the semiconductor elements and for supporting the inductor patterns and the semiconductor elements being arranged opposedly in an electrically isolated state are provided on a surface of the device layer of at least one of semiconductor elements and an electrically insulating material is filled in a space between opposing surfaces of the semiconductor elements. | 2009-10-01 |
| 20090243036 | Semiconductor Devices and Methods of Manufacture Thereof - Capacitor plates, capacitors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes at least one via and at least one conductive member coupled to the at least one via. The at least one conductive member comprises an enlarged region proximate the at least one via. | 2009-10-01 |
| 20090243037 | SEMICONDUCTOR DEVICE HAVING CAPACITORS FIXED TO SUPPORT PATTERNS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device containing a cylindrical shaped capacitor and a method for manufacturing the same is presented. The semiconductor device includes a plurality of storage nodes and a support pattern. The plurality of storage nodes is formed over a semiconductor substrate. The support pattern is fixed to adjacent storage nodes in which the support pattern has a flowable insulation layer buried within the support pattern. The buried flowable insulation layer direct contacts adjacent storage nodes. | 2009-10-01 |
| 20090243038 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming a capacitor having electrodes and a ferroelectric film provided therebetween above a substrate, forming a pad electrode electrically connected to one of the electrodes of the capacitor above the substrate, forming a protective film covering the pad electrode over the substrate, forming an opening in the protective film exposing at least a part of the pad electrode, bringing a measurement terminal into contact with the exposed surface of the pad electrode, etching the surface of the pad electrode after the measurement terminal is brought into contact therewith, and forming a hydrogen absorbing film on the protective film and the pad electrode exposed through the opening. | 2009-10-01 |
| 20090243039 | MIM Capacitor And Method For Manufacturing the Same - Disclosed are an MIM (Metal-Insulator-Metal) capacitor and a method of manufacturing the same. The MIM capacitor includes: a lower metal layer and a lower metal interconnection on a substrate; a barrier metal layer on the lower metal layer; an insulating layer on the barrier metal layer; an upper metal layer on the insulating layer; an interlayer dielectric layer having a via hole on the lower metal interconnection; and a plug in the via hole. | 2009-10-01 |
| 20090243040 | Micro-heater arrays and pn-junction devices having micro-heater arrays, and methods for fabricating the same - Example embodiments include micro-heater arrays including first and second micro-heaters disposed perpendicular to or parallel with each other on a substrate and methods of fabricating pn junctions between first and second heating portions using the heat generated from the first and second heating portions, respectively, when applying a voltage to the micro-heater array. Accordingly, when forming pn junctions using micro-heaters, a high-quality pn junction may be fabricated on a glass substrate over a large area. | 2009-10-01 |
| 20090243041 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece. | 2009-10-01 |
| 20090243042 | LATERAL SEMICONDUCTOR DEVICE - A semiconductor device has a first main electrode and a second main electrode that are provided on a semiconductor layer. The semiconductor layer has: an n type first semiconductor region in contact with the first main electrode; a p type second semiconductor region in contact with the second main electrode; and an n type third semiconductor region provided between the first and second semiconductor regions. The third semiconductor region has a first layer and a second layer. The impurity concentration in the first layer is uniform. The second layer has a higher impurity concentration than the first layer that increases in a gradient from the first semiconductor region to the second semiconductor region. | 2009-10-01 |
| 20090243043 | GROWTH METHOD USING NANOSTRUCTURE COMPLIANT LAYERS AND HVPE FOR PRODUCING HIGH QUALITY COMPOUND SEMICONDUCTOR MATERIALS - A method utilizes HVPE to grow high quality flat and thick compound semiconductors ( | 2009-10-01 |
| 20090243044 | Semiconductor wafer, semiconductor device, and method of manufacturing semiconductor device - Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or may be exposed to a side surface of a semiconductor chip obtained by dicing the semiconductor wafer along the scribe line region, among the conductive patterns, so that the island-shaped passivation film is opposed to the conductive pattern. | 2009-10-01 |
| 20090243045 | Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection - A semiconductor package includes a semiconductor die having a contact pad formed over a top surface of the semiconductor die. The semiconductor die may include an optical device. In one embodiment, a second semiconductor die is deposited over the semiconductor die. The package includes an insulating material deposited around a portion of the semiconductor die. In one embodiment, the insulating material includes an organic material. A first through hole via (THV) is formed in the insulating material using a conductive material. The first THV may form a protrusion extending beyond a bottom surface of the semiconductor die opposite the top surface and be connected to a first semiconductor device. A redistribution layer (RDL) may be deposited over the semiconductor die. The RDL forms an electrical connection between the contact pad of the semiconductor die and the first THV. | 2009-10-01 |
| 20090243046 | Pulse-Laser Bonding Method for Through-Silicon-Via Based Stacking of Electronic Components - There is described a method of forming a through-silicon-via to form an interconnect between two stacked semiconductor components using pulsed laser energy. A hole is formed in each component, and each hole is filled with a plug formed of a first metal. One component is then stacked on another component such that the holes are in alignment, and a pulse of laser energy is applied to form a bond between the metal plugs. | 2009-10-01 |
| 20090243047 | Semiconductor Device With an Interconnect Element and Method for Manufacture - A semiconductor device is provided configured to be electrically connected to another device by through silicon interconnect technology. The semiconductor device includes a semiconductor substrate with at least one through hole. A through silicon conductor extends inside the through hole from the upper side to the bottom side of the semiconductor substrate. The through silicon conductor is electrical isolated from the semiconductor substrate and includes a conductor bump at one of its ends. Between the inner surface of the through hole and the through silicon conductor a gap is formed. The gap surrounds the through silicon conductor on one side of the semiconductor substrate having the conductor bump, and extends from this side of the substrate into the substrate. The gap is filled with a flexible dielectric material. | 2009-10-01 |
| 20090243048 | METALLIC NANOCRYSTAL ENCAPSULATION - A method of forming a device includes forming protective shells about metallic nanocrystals supported by a substrate. The metallic nanocrystals having protective shells are encapsulated with a layer formed with process parameters that are not compatible with the integrity of unprotected metallic nanocrystals. | 2009-10-01 |
| 20090243049 | DOUBLE DEPOSITION OF A STRESS-INDUCING LAYER IN AN INTERLAYER DIELECTRIC WITH INTERMEDIATE STRESS RELAXATION IN A SEMICONDUCTOR DEVICE - Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process. | 2009-10-01 |
| 20090243050 | Isolation Structure in Memory Device and Method for Fabricating the Same - A method for fabricating an isolation structure in a memory device includes forming a first trench in a cell region of a semiconductor substrate and a second trench in a peripheral region of the semiconductor substrate. The method also includes oxidating the surface of the first and second trenches to form a sidewall oxide layer; depositing a tetraethylorthosilicate(TEOS) layer on the sidewall oxide layer; forming a silicon nitride layer and a silicon oxide layer on the TEOS layer; selectively removing portions of the silicon nitride and silicon oxide layers on the second trench to expose a portion of the underlying TEOS layer; coating a flowable insulation layer that fills the first and second trenches; and curing the flowable insulation layer. | 2009-10-01 |
| 20090243051 | INTEGRATED CONDUCTIVE SHIELD FOR MICROELECTRONIC DEVICE ASSEMBLIES AND ASSOCIATED METHODS - Microelectronic device assemblies having integrated conductive shields are disclosed herein. The microelectronic device assemblies include a semiconductor substrate having a bond site and a solder ball electrically connected to the bond site, a dielectric sidewall at least partially encapsulating the semiconductor substrate, and a conductive shield in direct contact with the sidewall and in electrical communication with the solder ball and the bond site. | 2009-10-01 |
| 20090243052 | Electronic device with shielding structure and method of manufacturing the same - An electronic device includes a substrate, an active circuit, and a shielding structure. The active circuit is formed on the substrate. The shielding structure is disposed surrounding the active circuit, and includes a first heavy ion-doped region, first metal stack, second heavy ion-doped region, second metal stack and top metal. The first heavy ion-doped is formed in the substrate and located at a first side of the active circuit. The first metal stack is formed on the first heavy ion-doped region of the substrate, wherein the first metal stack is connected to a ground voltage. The second heavy ion-doped region is formed in the substrate and located at a second side of the active circuit. The second metal stack is formed on the second heavy ion-doped region of the substrate. The top metal is formed on the first metal stack and second metal stack and passing over the active circuit. | 2009-10-01 |
| 20090243053 | STRUCTURE FOR REDUCTION OF SOFT ERROR RATES IN INTEGRATED CIRCUITS - A structure for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate. | 2009-10-01 |
| 20090243054 | I/O CONNECTION SCHEME FOR QFN LEADFRAME AND PACKAGE STRUCTURES - Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost. | 2009-10-01 |
| 20090243055 | Leadframe, semiconductor packaging structure and manufacturing method thereof - A semiconductor packaging structure includes a plurality of first inner leads, a plurality of second inner leads, a plurality of first outer leads, a plurality of stacked chips, an encapsulating body, and a plurality of wires. Wherein, a first protrusion portion is protruded from each of the first inner leads and is formed a plurality of contact faces with height differences, a second protrusion portion is protruded from each of the second inner leads. Therefore, the wires connected to the stacked chips, the first protrusion portion of the first inner leads, and the second protrusion portion of the second inner leads can be shorten. And, the wire sweep and short-circuit can be prevented during molding process. In addition, the present invention also discloses a leadframe and manufacturing method for the leadframe and its semiconductor packaging structure. | 2009-10-01 |
| 20090243056 | CHIP PACKAGE HAVING ASYMMETRIC MOLDING - A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal. | 2009-10-01 |
| 20090243057 | Semiconductor Chip Package Assembly Method and Apparatus for Countering Leadfinger Deformation - The invention provides semiconductor chip packages, tools, and methods for preventing and for correcting leadfinger deformation caused during wirebonding in semiconductor chip package manufacturing. Disclosed are improved heat blocks and methods for their use in ensuring adequate clearance between leadfingers and adjacent heat spreaders, as well as semiconductor chip package assemblies wherein a selected clearance between leadfingers and parallel surfaces may be assured. Methods of the invention include steps for supporting the proximal ends of the leadfingers using the wirebonding cavity of a heat block. Thus supported, a plurality of bondwires are attached to couple bond pads of the semiconductor chip to the proximal ends of leadfingers. Thereafter, the clearance between the wirebonded proximal ends of the leadfingers and the adjacent parallel surface of the heat spreader is adjusted using a spacing cavity of the heat block. In preferred embodiments of the invention, a plurality of bondwires couple a plurality of bond pads of the semiconductor chip to the proximal end of a single leadfinger, with assured clearance between the proximal end of the leadfinger and an underlying surface. | 2009-10-01 |
| 20090243058 | Lead frame and package of semiconductor device - A lead frame including a shield plate, a main frame, interconnection arms, support arms, and terminals is sealed with a resin mold including a base portion for embedding the shield plate and a peripheral wall for embedding the interconnection arms and support arms, thus forming a package base. The interconnection arms and support arms are subjected to bending so as to depress the shield plate in position compared with the main frame. At least one semiconductor chip (e.g. a microphone chip) is mounted on the base portion just above the shield plate. A cover having conductivity is attached onto the main frame exposed on the upper end of the peripheral wall, thus completely producing a semiconductor device encapsulated in a package. A sound hole is formed in the cover or the package base so as to allow the internal space of the package to communicate with the external space. | 2009-10-01 |
| 20090243059 | Semiconductor package structure - A semiconductor package structure includes a carrier having a plurality of leads, wherein each of the leads is composed of an inner lead and an outer lead; a chip arranged on the bottom surface of the inner leads; an electrical connecting structure and a molding component. The invention discloses that the inner leads are bent outwardly from the horizontal at top surface of the chip to form a ladder-like difference and the outer leads are extended outwardly horizontally, thus a height difference formed between the chip and the outer lead prevents the particles from contacting the chip and the outer lead at the same time to enhance the electrical reliability of the chip. | 2009-10-01 |
| 20090243060 | Lead frame and package of semiconductor device - A lead frame including a stage and a plurality of terminals is embedded in a mold resin including a base portion for mounting a semiconductor chip (e.g. a microphone chip), a peripheral wall disposed in the periphery of the base portion, and an extension portion extended outside of the peripheral wall, thus forming a package base. A plurality of holes is formed in the peripheral wall so as to expose the internal connection surface of the stage and the internal connection surfaces of the terminals. An extension portion of the stage is exposed on the extension portion of the mold resin in which the surfaces of the terminals are embedded. An extension portion (e.g. a brim) of a cover composed of a conductive material is attached to the extension portion of the mold resin of the package base, thus completely producing a semiconductor device. | 2009-10-01 |
| 20090243061 | Complex Semiconductor Packages and Methods of Fabricating the Same - Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first packaging substrate; and a first sealing member covering the first semiconductor chips on the first packaging substrate; and at least one second package separated from the first packaging substrate, disposed in the first sealing member, and including second semiconductor chips. | 2009-10-01 |
| 20090243062 | IC TAG AND MANUFACTURING METHOD OF THE SAME - An IC tag comprises a substrate on which a wiring pattern is formed, an IC chip which is bonded and mounted to the substrate by bringing a bump into press-contact with the wiring pattern, a repulsive member that is arranged on the surface opposite to the surface of the substrate on which surface the IC chip is mounted, and that is made of a material having higher rigidity than the substrate, and an exterior package member which is configured to cover the substrate, the IC chip, and the repulsive member. | 2009-10-01 |
| 20090243063 | PACKAGING METHOD OF MICRO ELECTRO MECHANICAL SYSTEM DEVICE AND PACKAGE THEREOF - Disclosed are a micro electro mechanical system (MEMS) device and a package thereof. The packaging method of a MEMS device comprises: sequentially forming a sacrificial layer, a support layer, and a block copolymer layer on a substrate on which the MEMS device is formed; self-assembling the block copolymer layer formed on the support layer; selectively etching a part of the self-assembled block copolymer layer to form a plurality of nano-pores; forming a plurality of etching holes in the support layer corresponding to the plurality of nano-pores using the block copolymer layer in which the plurality of nano-pores are formed as a mask; removing the sacrificial layer using the etching holes formed in the support layer; and forming a shielding layer on the support layer. | 2009-10-01 |
| 20090243064 | Method and Apparatus For a Package Having Multiple Stacked Die - A method of manufacturing a semiconductor package involves providing a substrate having a window. The substrate may include a leadframe having half-etched leads. First and second semiconductor devices are mounted to a top surface of the substrate on either side of the window using an adhesive. A third semiconductor device is mounted to the first and second semiconductor devices using an adhesive. The third semiconductor device is disposed over the window of the substrate. A wirebond or other electrical interconnect is formed between the third semiconductor device and a contact pad formed over a bottom surface of the substrate opposite the top surface of the substrate. The wirebond or other electrical interconnect passes through the window of the substrate. An encapsulant is deposited over the first, second, and third semiconductor devices. | 2009-10-01 |
| 20090243065 | Semiconductor Device and Method for Manufacturing Semiconductor Device - A semiconductor device ( | 2009-10-01 |
| 20090243066 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH EXPOSED EXTERNAL INTERCONNECTS - The present invention provides a mountable integrated circuit package system comprising: providing an inner integrated circuit package including a first external interconnect having a shoulder; connecting an intraconnect between a second external interconnect and the shoulder; and forming an outer encapsulation over the inner integrated circuit package, the intraconnect, and partially exposing the first external interconnect on a top encapsulation side of the outer encapsulation and the second external interconnect on a bottom encapsulation side of the outer encapsulation. | 2009-10-01 |
| 20090243067 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUBSTRATE - A mountable integrated circuit package system includes: providing a substrate having an opening provided therein; providing an encapsulated integrated circuit package having an external leadfinger; mounting the encapsulated integrated circuit package by the external leadfinger proximate to the opening in the substrate; and connecting the external leadfinger and the substrate. | 2009-10-01 |
| 20090243068 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH NON-SYMMETRICAL SUPPORT STRUCTURES - An integrated circuit package system including: providing a substrate with a wire-bonded die mounted thereover; mounting a first support structure and a second support structure of different size above the substrate; mounting a structure above the first support structure and the second support structure; and encapsulating the wire-bonded die, the first support structure and the second support structure with an encapsulation. | 2009-10-01 |
| 20090243069 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION - An integrated circuit package system comprising: forming a base package having a molded top; providing a surface contact on the base package; and patterning a redistribution layer on the molded top for coupling the surface contact. | 2009-10-01 |
| 20090243070 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH SUPPORT STRUCTURE UNDER WIRE-IN-FILM ADHESIVE - An integrated circuit package in package system including: providing a substrate; mounting a wire bonded die with an active side over the substrate; connecting the active side to the substrate with bond wires; mounting a structure over the wire bonded die having a wire-in-film adhesive between the structure and the wire bonded die and overhangs at ends of the structure between the wire-in-film adhesive and the substrate; mounting support structures at the overhangs between the wire-in-film adhesive and the substrate; and encapsulating the wire bonded die and the structure with an encapsulation. | 2009-10-01 |
| 20090243071 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STACKING MODULE - An integrated circuit package system comprising: providing a module lead array; attaching a module integrated circuit adjacent the module lead array; attaching a module substrate over the module integrated circuit; and applying a module encapsulant over the module integrated circuit wherein the module lead array and the module substrate are partially exposed. | 2009-10-01 |
| 20090243072 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package system includes: providing a base integrated circuit package, and mounting a top integrated circuit package having a top interposer and a top encapsulation with a cavity therein or the cavity as a space between top intra-stack interconnects and the top interposer, with the top interposer exposed by the cavity, over the base integrated circuit package. | 2009-10-01 |
| 20090243073 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package system includes: providing a base integrated circuit package having a base encapsulation with a cavity therein and a base interposer exposed by the cavity; mounting an intermediate integrated circuit package over the base interposer, and mounting a top integrated circuit package over the intermediate integrated circuit package. | 2009-10-01 |
| 20090243074 | SEMICONDUCTOR THROUGH SILICON VIAS OF VARIABLE SIZE AND METHOD OF FORMATION - A through-silicon via structure is formed by providing a substrate having a first conductive catch pad and a second conductive catch pad formed thereon. The substrate is secured to a wafer carrier. A first etch of a first type is performed on the substrate underlying each of the first and second conductive catch pads to form a first partial through-substrate via of a first diameter underlying the first conductive catch pad and a second partial through-substrate via underlying the second conductive catch pad of a second diameter that differs from the first diameter. A second etch of a second type that differs from the first type is performed to continue etching the first partial through-substrate to form equal depth first and second through-substrate vias respectively to the first and second conductive catch pads. | 2009-10-01 |
| 20090243075 | MOUNTING STRUCTURE OF SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS USING SAME - A mounting structure comprises: at least one semiconductor device having solder bumps as outer terminals and a flexible wiring board with wiring formed thereon. The semiconductor device is structured to be wrapped by the flexible wiring board, the mounting structure is provided with outer electrodes on both sides of the flexible wiring board, one side being a side where outer terminals of the semiconductor device are formed, and the other side being an opposite side thereof. At least one wiring layer is formed on the flexible wiring board. A supporting member is provided covering side faces and a surface of the semiconductor device opposite to the side where the outer terminals are formed and protruding from the side faces of the semiconductor device and extending toward the surface on which the outer terminals are formed. | 2009-10-01 |
| 20090243076 | ELECTRONIC SYSTEM MODULES AND METHOD OF FABRICATION - This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths of 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is used to fabricate the interconnection circuits. A polymer base layer is formed on a glass carrier with an intermediate release layer. Alternate layers of metal and dielectric are formed on the base layer, and patterned to create an array of multi-layer interconnection circuits on the glass panel. A thick layer of polymer is deposited on the interconnection circuit, and openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings to form wells filled with solder. After dicing the glass carrier to form separated interconnection circuits, IC chips are stud bumped and assembled using flip chip bonding, wherein the stud bumps on the components are inserted into corresponding wells on the interconnection circuits. The IC chips are tested and reworked to form tested circuit assemblies. Methods for connecting to testers and to other modules and electronic systems are described. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server embodiment is also described. | 2009-10-01 |
| 20090243077 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RIGID LOCKING LEAD - An integrated circuit package system includes: providing a protective layer having an opening; forming a conductive layer over the protective layer and filling the opening; patterning a rigid locking lead, having both a lead locking portion and a lead exposed portion, from the conductive layer; connecting an integrated circuit and the rigid locking lead; and forming an encapsulation over the integrated circuit with the lead locking portion in the encapsulation and the lead exposed portion exposed from the encapsulation. | 2009-10-01 |
| 20090243078 | Power Device Packages Having Thermal Electric Modules Using Peltier Effect and Methods of Fabricating the Same - Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module. | 2009-10-01 |
| 20090243079 | Semiconductor device package - Provided is a semiconductor device package including a substrate formed of a silicon (Si)-based material. The semiconductor device package includes a first substrate which comprises first and second principal planes which are opposite each other, and a substrate body layer disposed between the first and second principal planes, the substrate body layer being formed of a silicon (Si)-based material; and at least one first semiconductor device which is mounted on the first principal plane. | 2009-10-01 |
| 20090243080 | Flip Chip Interconnection Structure with Bump on Partial Pad and Method Thereof - A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped. | 2009-10-01 |
| 20090243081 | SYSTEM AND METHOD OF FORMING A WAFER SCALE PACKAGE - A system and method for forming a wafer level package (WLP) (i.e., wafer level chip size package) is disclosed. The WLP includes a silicon integrated circuit (IC) substrate having a plurality of die pads formed on a top surface thereof and a plurality of polymer laminates positioned thereon. Each of the polymer laminates is comprised of a separate pre-formed laminate sheet and has a plurality of vias formed therein that correspond to a respective die pad. A plurality of metal interconnects are formed on each of the plurality of polymer laminates so as to cover a portion of a top surface of a polymer laminate and extend down through the via and into contact with a metal interconnect on a neighboring polymer laminate positioned below. An input/output (I/O) system interconnect is positioned on a top surface of the wafer level package and is attached to the plurality of metal interconnects. | 2009-10-01 |
| 20090243082 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH PLANAR INTERCONNECT - An integrated circuit package system includes: mounting an integrated circuit die adjacent to a lead; forming a first encapsulation around and exposing the integrated circuit die and the lead; and forming a planar interconnect between the integrated circuit die and the lead with the planar interconnect on the first encapsulation. | 2009-10-01 |
| 20090243083 | Wafer Integrated with Permanent Carrier and Method Therefor - A semiconductor device has a wafer for supporting the device and a conductive layer formed over a top surface of the wafer. A carrier wafer is permanently bonded over the conductive layer. Within the wafer and the carrier wafer, an interconnect structure is formed. The interconnect structure includes a first via formed in the wafer exposing the conductive layer, a second via formed in the carrier wafer exposing the conductive layer, a first metal layer deposited over the first via, the first metal layer in electrical contact with the conductive layer, and a second metal layer deposited over the second via, the second metal layer in electrical contact with the conductive layer. First and second passivation layers are deposited over the first and second metal layers. The first or second passivation layer has an etched portion to expose a portion of the first metal layer or second metal layer. | 2009-10-01 |
| 20090243084 | SUSPENSION MICROSTRUCTURE AND A FABRICATION METHOD FOR THE SAME - A suspension microstructure and its fabrication method, in which the method comprises the steps of: forming at least one insulation layer with inner micro-electro-mechanical structures on an upper surface of a silicon substrate, the micro-electro-mechanical structure includes at least one microstructure and a plurality of metal circuits that are independent from each other, the micro-electro-mechanical structures have an exposed portion on the surface of the insulation layer, and the exposed portion is provided with through holes or stacked metal-via layers correspondingly to the predetermined etching spaces of the micro-electro-mechanical structures, the above predetermined etching spaces and the stacked metal-via layers only penetrate the insulation layer; forming a photoresist with an opening on the upper surface of the exposed portion, and the opening of the photoresist is located outside all the through holes or the stacked metal-via layers; subsequently, conducting etching to realize the suspension of the microstructures. | 2009-10-01 |
| 20090243085 | APPARATUS AND METHOD FOR ATTACHING A HEAT DISSIPATING DEVICE - A microelectronic package is provided. The microelectronic package includes a heat dissipating device having a top side and a bottom side and a thermal interface material disposed adjacent to the bottom side of the heat dissipating device. The microelectronic package also includes a patterned metal layer comprising at least two metals disposed on the bottom side of the heat dissipating device, wherein the patterned metal layer is to adhere the heat dissipating device to the thermal interface material. | 2009-10-01 |
| 20090243086 | Enhanced Thermal Dissipation Ball Grid Array Package - In a semiconductor chip, a thermal adhesive is used to bond an internal heat spreader to an active functional die. In an alternative embodiment a dummy die is place directly on top of the active functional die and a thermal adhesive is used to bond an internal heat spreader to the dummy die. This provides a direct and relatively low thermal conductivity path from the heat source, i.e., the functional device to the top of the package, that is, the internal metal heat spreader which is also exposed to the air. | 2009-10-01 |
| 20090243087 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - In a DC-DC converter, a multilayer wiring layer is provided on a silicon substrate, and a control circuit configured to control an input circuit and an output circuit is formed in the silicon substrate and the multilayer wiring layer. Moreover, a sealing resin layer covering the multilayer wiring layer and a connecting member connected to an uppermost wiring of the multilayer wiring layer, penetrating the sealing resin layer and having an upper end portion protruding from an upper surface of the sealing resin layer are provided. The upper end portion of the connecting member is formed from a protruding electrode. Horizontal cross-sectional area of the connecting member connected to terminals of the output circuit is larger than horizontal cross-sectional area of the connecting member connected to terminals of the control circuit. | 2009-10-01 |
| 20090243088 | Multiple Layer Metal Integrated Circuits and Method for Fabricating Same - A method of fabricating a plurality of layers of metal on a substrate depositing a first layer of metal on the substrate; depositing a first layer of planarization material over the substrate and first layer of metal to a depth above the top of the first layer of metal; polishing the first layer of planarization material down to at least the top of the first layer of metal; and depositing a second layer of metal on the first layer of metal and the first layer of planarization material. | 2009-10-01 |
| 20090243089 | MODULE INCLUDING A ROUGH SOLDER JOINT - A module includes a metallized substrate including a metal layer, a base plate, and a joint joining the metal layer to the base plate. The joint includes solder contacting the base plate and an inter-metallic zone contacting the metal layer and the solder. The inter-metallic zone has spikes up to 100 μm and a roughness (R | 2009-10-01 |
| 20090243090 | MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS - A mock bump system includes providing a flip chip integrated circuit having an edge and forming a mock bump near the edge. | 2009-10-01 |
| 20090243091 | MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS - A mock bump system includes: providing a first structure having an edge; and forming a mock bump near the edge. | 2009-10-01 |
| 20090243092 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element; a plate member disposed opposite to an electronic-circuit forming portion of the semiconductor element; and an elastic body arranged in a compressed state between the semiconductor element and the plate member, wherein the elastic body includes at least one first protruding portion at one end in an extension direction of the elastic body, the first protruding portion being formed opposite to the electronic-circuit forming portion of the semiconductor element, and the semiconductor element and the plate member are fastened by an adhesive agent. | 2009-10-01 |
| 20090243093 | CONTACT STRUCTURE AND CONNECTING STRUCTURE - A contact structure disposed on a substrate is provided. The contact structure includes at least one pad, at least one polymer bump and at least one conductive layer. The pad is disposed on the substrate and the polymer bump is disposed on the substrate. The polymer bump has a curved surface having a plurality of concave-convex structures. The polymer bump is covered by the conductive layer and the conductive layer is electrically connected with the pad. | 2009-10-01 |
| 20090243094 | Semiconductor device and manufacturing method thereof - The semiconductor device comprises a first area and a second area positioned adjacent to the outside of the first area, the semiconductor substrate having a main surface and side surfaces and disposed in such a manner that the main surface is positioned in the first area and each of the side surfaces is positioned at a boundary between the first area and the second area, a plurality of pads formed over the main surface of the semiconductor substrate and a plurality of external connecting terminals formed thereon, which are respectively electrically connected to the pads, a first resin portion which is formed over the main surface of the semiconductor substrate so as to cover the pads and has a main surface and side surfaces, and which is formed in such a manner that the external connecting terminals are exposed from the main surface and each of the side surfaces is positioned at the boundary, and a second resin portion which is positioned in the second area and formed so as to cover the side surfaces of the semiconductor substrate and the side surfaces of the first resin portion and which is different in composition from the first resin portion. | 2009-10-01 |
| 20090243095 | SUBSTRATE, MANUFACTURING METHOD THEREOF, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A substrate on which an IC element is fixed includes: a plurality of metal posts arranged in a plurality of columns in a lengthwise direction and in a plurality of rows in a crosswise direction when viewed in a plan view, the plurality of metal posts having first faces and second faces that face an opposite side to a side that the first faces face; first marks each of the first marks being disposed on extending lines of the plurality of columns; and second marks, each of the second marks being disposed on extending lines of the plurality of rows. | 2009-10-01 |
| 20090243096 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a method of manufacturing the same are disclosed. The method is carried out by forming solder pads on a substrate by wet etching, flipping a semiconductor chip having a plurality of connection bumps formed on an active surface of the semiconductor chip for the connection bumps to be mounted by compression on the solder pads of the substrate correspondingly, at a temperature of the compression between the connection bumps and the solder pads lower than the melting points of the solder pads and the connection bumps, so as to allow the semiconductor chip to be engaged with and electrically connected to the substrate through the connection bumps and the solder pads, thereby enhancing the bonding strength of the solder pads and the connection bumps and increasing the fabrication reliability. | 2009-10-01 |
| 20090243097 | SEMICONDUCTOR DEVICE HAVING LOW DIELECTRIC CONSTANT FILM AND MANUFACTURING METHOD THEREOF - A low dielectric constant film/wiring line stack structure made up of a stack of low dielectric constant films and wiring lines is provided in a region on the upper surface of the semiconductor substrate except for the peripheral part of this surface. The peripheral side surface of the low dielectric constant film/wiring line stack structure is covered with a sealing film. This provides a structure in which the low dielectric constant films do not easily come off. In this case, a lower protective film is provided on the lower surface of a silicon substrate to protect this lower surface against cracks. | 2009-10-01 |
| 20090243098 | UNDERBUMP METALLURGY FOR ENHANCED ELECTROMIGRATION RESISTANCE - A first metallic diffusion barrier layer is formed on a last level metal plate exposed in an opening of a passivation layer. Optionally, a metallic adhesion promotion layer is formed on the first metallic diffusion barrier layer. An elemental metal conductive layer is formed on the metallic adhesion promotion layer, which provides a highly conductive structure that distributes current uniformly due to the higher electrical conductivity of the material than the layers above or below. A stack of the second metallic diffusion barrier layer and a wetting promotion layer is formed, on which a C4 ball is bonded. The elemental metal conductive layer distributes the current uniformly within the underbump metallurgy structure, which induces a more uniform current distribution in the C4 ball and enhanced electromigration resistance of the C4 ball. | 2009-10-01 |
| 20090243099 | WINDOW TYPE BGA SEMICONDUCTOR PACKAGE AND ITS SUBSTRATE - A window-type BGA semiconductor package is revealed, primarily comprising a substrate with a wire-bonding slot, a chip disposed on a top surface of the substrate, and a plurality of bonding wires passing through the wire-bonding slot. A plurality of plating line stubs are formed on a bottom surface of the substrate, connect the bonding fingers on the substrate and extend to the wire-bonding slot. The bonding wires electrically connect the bonding pads of the chip to the corresponding bonding fingers of the substrate. The plating line stubs are compliant to the wire-bonding paths of the bonding wires correspondingly connected at the bonding fingers, such as parallel to the overlapped arrangement, to avoid electrical short between the plating line stubs and the bonding wires with no corresponding relationship of electrical connections. | 2009-10-01 |
| 20090243100 | Methods to Form a Three-Dimensionally Curved Pad in a Substrate and Integrated Circuits Incorporating such a Substrate - Methods to form a three-dimensionally curved pad in a substrate and integrated circuits incorporating such a substrate are disclosed. An example method to form a three-dimensionally curved pad comprises isotropically etching a portion of a surface of a substrate to form a recess having a radial shape, forming a conductive layer in the recess to form the bonding pad, and placing a conductive element in the pad. | 2009-10-01 |
| 20090243101 | METHOD FOR FORMING INTERCONNECTION LEVELS OF AN INTEGRATED CIRCUIT - A method for forming interconnection levels of an integrated circuit, including the steps of: (a) forming an interconnection level comprising conductive tracks and vias separated by a porous dielectric material; (b) forming, on the interconnection level, a layer of a non-porous insulating material, said layer comprising openings above portions of porous dielectric material; (c) repeating steps (a) and (b) to obtain the adequate number of interconnection levels; and (d) annealing the structure. | 2009-10-01 |
| 20090243102 | METHOD OF ALIGNING DEPOSITED NANOTUBES ONTO AN ETCHED FEATURE USING A SPACER - A method of forming an aligned connection between a nanotube layer and a raised feature is disclosed. A substrate having a raised feature has spacers formed next to the side of the raised feature. The spacers are etched until the sidewalls of the raised feature are exposed forming a notched feature at the top of the spacers. A patterned nanotube layer is formed such that the nanotube layer overlies the top of the spacer and contacts a side portion of the raised feature in the notched feature. The nanotube layer is then covered with an insulating layer. Then a top portion of the insulating layer is removed to expose a top portion of the etched feature. | 2009-10-01 |
| 20090243103 | SYNTHESIS OF ZEOLITE CRYSTALS AND FORMATION OF CARBON NANOSTRUCTURES IN PATTERNED STRUCTURES - A method is provided for incorporating zeolite crystals in patterned structures, the zeolite crystals having pores (channels) with an orientation which is defined by the topology of the zeolite crystal type and the geometry of the patterned structure, resulting in pores parallel with the length axis of the patterned structures. The patterned structures may be vias (vertical contacts) and trenches (horizontal lines) in a semiconductor substrate. These zeolite crystals can advantageously be used for dense and aligned nanocarbon growth or in other words growth of carbon nanostructures such as carbon nanotubes (CNT) within the pores of the zeolite structure. The growth of CNT is achieved within the porous structure of the zeolite crystals whereby the pores can be defined as confined spaces (channels) in nanometer dimensions acting as a micro-reactor for CNT growth. A method for growing carbon nanostructures within zeolite crystals is also provided, by adding, after creation of the zeolite crystals, a novel compound within the porous structure of the zeolite crystals whereby said novel compound is acting as a carbon source to create the carbon nanostructures. The improved growth method gives a significantly higher carbon density (yield) compared to state of the art techniques. | 2009-10-01 |
| 20090243104 | FORMING THICK METAL INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS - Embodiments of an apparatus and methods for forming thick metal interconnect structures for integrated structures are generally described herein. Other embodiments may be described and claimed. | 2009-10-01 |
| 20090243105 | WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEMICONDUCTOR DEVICE BY PROVIDING A PROTECTIVE LAYER - In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface. | 2009-10-01 |
| 20090243106 | STRUCTURES AND METHODS TO ENHANCE COPPER METALLIZATION - Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid. | 2009-10-01 |
| 20090243107 | NOVEL APPROACH TO HIGH TEMPERATURE WAFER PROCESSING - At temperatures near, and above, 385° C., gold can diffuse into silicon and into some contact materials. Gold, however, is an excellent material because it is corrosion resistant, electrically conductive, and highly reliable. Using an adhesion layer and removing gold from the contact area above and around a contact allows a Micro-Electro-Mechanical Systems device or semiconductor to be subjected to temperatures above 385° C. without risking gold diffusion. Removing the risk of gold diffusion allows further elevated temperature processing. Bonding a device substrate to a carrier substrate can be an elevated temperature process. | 2009-10-01 |
| 20090243108 | CONTROL OF LOCALIZED AIR GAP FORMATION IN AN INTERCONNECT STACK - The present invention relates to a method for fabricating an interconnect stack of an integrated-circuit device. Air gaps are fabricated in the interconnect stack on one or more interconnect levels. The method comprises forming local etch vias ( | 2009-10-01 |
| 20090243109 | METAL CAP LAYER OF INCREASED ELECTRODE POTENTIAL FOR COPPER-BASED METAL REGIONS IN SEMICONDUCTOR DEVICES - A conductive cap material for a copper region may be provided with enhanced etch resistivity by taking into consideration the standard electrode potential of one or more of the species contained therein. For example, instead of a conventionally used CoWP alloy, a modified alloy may be used, by substituting the cobalt species by a metallic species having a less negative standard electrode potential, such as nickel. Consequently, device performance may be enhanced, while at the same time the overall process complexity may be reduced. | 2009-10-01 |
| 20090243110 | Voltage controlled oscillator - A semiconductor device includes a semiconductor substrate having an element region on a surface thereof, an active element being formed in the element region. An insulating layer is formed on the semiconductor substrate and covers the active element. An inductor is formed on the insulating layer and overlaps with the active element. | 2009-10-01 |
| 20090243111 | SEMICONDUCTOR SUBSTRATE, ELECTRODE FORMING METHOD, AND SOLAR CELL FABRICATING METHOD - The present invention is directed to a semiconductor substrate having an electrode formed thereon, the electrode including at least silver and glass frit, the electrode including: a multi-layered structure constituted of a first electrode layer joined directly to the semiconductor substrate, and an upper electrode layer formed of at least one layer and disposed on the first electrode layer; wherein the upper electrode layer is formed by firing a conductive paste having a total silver content of 75 wt % or more and 95 wt % or less, the content of silver particles having an average particle diameter of 4 μm or greater and 8 μm or smaller with respect to the total silver content in the upper electrode layer being higher than that in the first electrode layer. As a consequence, it is possible to form the electrode, which has the high aspect ratio and hardly suffers an inconvenience such as a break, on the semiconductor substrate by a simple method. | 2009-10-01 |
| 20090243112 | Copper interconnection structure, semiconductor device, and method for forming copper interconnection structure - A copper interconnection structure includes an insulating layer, an interconnection and a barrier layer. The insulating layer includes silicon (element symbol: Si), carbon (element symbol: C), hydrogen (element symbol: H) and oxygen (element symbol: O). The interconnection is located on the insulating layer, and the interconnection includes copper (element symbol: Cu). The barrier layer is located between the insulating layer and the interconnection. The barrier layer includes an additional element, carbon (element symbol: C) and hydrogen (element symbol: H). The barrier layer has atomic concentrations of carbon (element symbol: C) and hydrogen (element symbol: H) maximized in a region of a thickness of the barrier layer where the atomic concentration of the additional element is maximized. | 2009-10-01 |
| 20090243113 | Semiconductor structure - A fusible link between metallization layers of a semiconductor device comprises a tungsten plug deposited in a via interconnecting two aluminum metallization layers. | 2009-10-01 |
| 20090243114 | Densely packed metal segments patterned in a semiconductor die - A method of patterning a metal layer in a semiconductor die comprises forming a mask on the metal layer to define an open region and a dense region. The method further comprises etching the metal layer at a first etch rate to form a number of metal segments in the open region and etching the metal layer at a second etch rate to form a number of metal segments in the dense region, where the first etch rate is approximately equal to the second etch rate. The method further comprises performing a number of strip/passivate cycles to remove a polymer formed on sidewalls of the metal segments in the dense region. The sidewalls of the metal segments in the dense region undergo substantially no undercutting and residue is removed from the sidewalls of the metal segments in the dense region. | 2009-10-01 |
| 20090243115 | Semiconductor device and method of manufacturing the same - Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a memory array on a first substrate; and a peripheral circuit on a second substrate, wherein the first substrate and the second substrate may be attached to each other so that the memory array and the peripheral circuit are electrically connected to each other. | 2009-10-01 |
| 20090243116 | REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS - By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence. | 2009-10-01 |
| 20090243117 | CONTACT STRUCTURE, A SEMICONDUCTOR DEVICE EMPLOYING THE SAME, AND METHODS OF MANUFACTURING THE SAME - A contact structure that includes a first pattern formed on a substrate, wherein the first pattern has a recessed region in an upper surface thereof, a planarized buffer pattern formed on the first pattern, and a conductive pattern formed on the planarized buffer pattern. | 2009-10-01 |
| 20090243118 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. | 2009-10-01 |
| 20090243119 | Semiconductor integrated circuit - Power wiring comprises a first-layer power wiring cluster in which VDD wiring trace and VSS wiring trace of different potentials at single trace width are arranged alternatingly; a second-layer power wiring cluster, disposed in a layer overlying the first-layer power wiring cluster, in which a VDD wiring trace and a VSS wiring trace of different potentials at single trace width are arranged alternatingly; and vias, placed in areas where the first-layer power wiring cluster and second-layer power wiring clusters intersect three-dimensionally, for electrically connecting wiring traces of the same potential in the first-layer power wiring cluster and wiring traces of the same potential in the second-layer power wiring cluster. A signal-wiring formation area is provided between mutually adjacent first-layer power wiring clusters and between mutually adjacent second-layer power wiring clusters. Design rule violation regarding via density is avoided without decline in integration or an increase in chip area. | 2009-10-01 |
| 20090243120 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR ELEMENT FABRICATION METHOD - A semiconductor element is provided that includes a semiconductor substrate, a circuit element disposed on the substrate, and a through-hole formed in the substrate having a stripe-like concavo-convex structure on its sidewall with stripes formed in the direction of the thickness of the semiconductor substrate. | 2009-10-01 |
| 20090243121 | SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD FOR THE SAME - A semi conductor integrated circuit includes a first via-contact configured to connect a first interconnection pattern provided for a first interconnection layer and a second interconnection pattern provided for a second interconnection layer, and a second via-contact configured to connect a third interconnection pattern provided for the first interconnection layer and the second interconnection pattern. A redundant interconnection pattern is formed in the first interconnection layer and configured to connect the first interconnection pattern and the third interconnection pattern to overlap above the second interconnection pattern. | 2009-10-01 |
| 20090243122 | ALIGNMENT MARK FOR OPAQUE LAYER - An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process. | 2009-10-01 |
| 20090243123 | Increasing Exposure Tool Alignment Signal Strength for a Ferroelectric Capacitor Layer - An improved alignment structure for photolithographic pattern alignment is disclosed. A topographical alignment mark in an IC under a low reflectivity layer may be difficult to register. A reflective layer is formed on top of the low reflectivity layer so that the topography of the alignment mark is replicated in the reflective layer, enabling registration of the alignment mark using common photolithographic scanners and steppers. The reflective layer may be one or more layers, and may be metallic, dielectric or both. The reflective layer may be global over the entire IC or may be local to the alignment mark area. The reflective layer may be removed during subsequent processing, possibly with assist from an added etch stop layer, or may remain in the completed IC. The disclosed alignment mark structure is applicable to an IC with a stack of ferroelectric capacitor materials. | 2009-10-01 |
| 20090243124 | Composite Shaft Aspirator Assembly - A composite hollow aspirator shaft is formed of fiberglass-reinforced phenolic resin that resists abrasion and reduces the amount of vibration that is transferred to the motor rotating the shaft, and the motor's bearings to extend motor and bearing life. An aspirator tip is adhesively attached to the composite aspirator shaft and includes an access hole for cleaning inside the hollow aspirator shaft. The hole is in axial alignment with the hollow aspirator shaft and a selectively-removable plug is used to seal the hole during aspirator use. When the aspirator tip is rotated in a liquid, fluidic forces are transferred to the shaft where they are attenuated. A splined hub is used to attach a foam restrictor near the other end of the shaft. The composite shaft material has a flexural modulus, or ratio, within the elastic limit of any applied stress. | 2009-10-01 |
| 20090243125 | METHODS AND APPARATUS FOR INK JET PROVIDED ENERGY RECEPTOR - This invention discloses methods and apparatus for providing a biomedical device, such as an ophthalmic lens with an energy receptor capable of powering a processing device. The energy receptor can include a conductive material deposited onto a media and placed within a mold used to form the biomedical device. In some embodiments, the conductive material is ink jetted onto the media. | 2009-10-01 |
| 20090243126 | METHOD AND APPARATUS FOR IMPRINTING MICROSTRUCTURE AND STAMPER THEREFOR - A method of imprinting a microstructure comprising: contacting a stamper comprising a pattern layer with the microstructure of the order of from micrometers to nanometers in one face of the pattern layer and a substrate supporting the pattern layer with an imprinting member having a deformable layer to which the microstructure is imprinted, wherein the pattern layer is supported on a round surface having a prescribed radius of curvature of the substrate, the center of the round surface protruding towards the rear face of the pattern layer; causing the deformable layer on the imprinting member; and separating the stamper from the cured deformable layer. | 2009-10-01 |
| 20090243127 | Device for Producing Nuclear Fuel Pellets and Production Method Applying Such a Device - Production device including a press, a conveyor ( | 2009-10-01 |
| 20090243128 | COLLECTION OF PROCESS DATA USING IN-SITU SENSORS - A system is provided for collecting data during vacuum molding of a composite part using a mold including an air tight, flexible membrane sealed to a tool. The system comprises a plurality of MEMS sensors coupled with the interior of the mold at different locations over the part. Each of the sensors produces signals related to a process parameter, such as pressure within the bag, that is sensed at the location of the sensor. | 2009-10-01 |
| 20090243129 | DETECTING APPARATUS - A detecting apparatus and method for detecting deformation of a fixed mold plate of an injection molding machine. The apparatus includes a mounting member and an elastic member that is received in the through hole of the mounting member and generally positioned at the center thereof. The apparatus also has a contacting member that is received in the through hole and positioned near or at the first end surface, and a sliding member that is slidably received in the through hole near or at the second end surface. A blocking member is attached to the second end surface of the mounting member. A pressure sensor is fixed between the blocking member and the contacting member. | 2009-10-01 |
| 20090243130 | Method for Achieving a Fragrance Release with Sealing Parts - The invention relates to a method for achieving a fragrance release with release with parts which form a seal that, with correspondingly designed sealing parts, can be repeatedly opened and closed, wherein the respective sealing fan is produced from a meltable plastic material by means of an extrusion apparatus ( | 2009-10-01 |
| 20090243131 | Injection Molding Machine and Control Method of the Injection Molding Machine - An injection molding machine includes a pressure detector | 2009-10-01 |
| 20090243132 | APPARATUS AND METHOD FOR THE MEASUREMENT OF THE VERTICAL POSITION OF UPPER AND LOWER PUNCHES OF A ROTARY TABLET PRESS - The present invention is related to an apparatus and a method for the measurement of the vertical position of upper and lower punches, pairwisely associated to a rotatably driven rotor of a rotary tablet press and rotating synchronously with the rotor, which perform a vertical movement in certain regions along the circumference of their rotational movement during a rotation of the rotor. The apparatus features at least one scale arranged on at least one of the upper and/or lower punches, running in parallel to the vertical movement direction of the respective upper and/or lower punch, and at least one reading device associated to the scale, also rotating synchronously with the rotor, by means of which a vertical position of the respective upper and/or lower punch can be measured by reading out the scale. The inventions is furthermore related to a corresponding rotary tablet press and a corresponding method. | 2009-10-01 |
| 20090243133 | FILM CALIPER CONTROL - A film handling apparatus including an orienter for deforming a polymeric film, a cross-web heat distribution system configured to provide a selectable distribution of heat to the film in the orienter, a measurement device configured to measure at least a portion of a cross-web caliper of the film, and an automated controller that controls the cross-web heat distribution system to adjust heat distribution in response to the measured cross-web caliper of the film. The film handling apparatus can provide for at least partial automatic control of the caliper of a film while the film is being manufactured. | 2009-10-01 |
