39th week of 2010 patent applcation highlights part 21 |
Patent application number | Title | Published |
20100244148 | Structure and fabrication of field-effect transistor having nitrided gate dielectric layer with tailored vertical nitrogen concentration profile - A gate dielectric layer ( | 2010-09-30 |
20100244149 | Structure and fabrication of like-polarity field-effect transistors having different configurations of source/drain extensions, halo pockets, and gate dielectric thicknesses - A group of high-performance like-polarity insulated-gate field-effect transistors ( | 2010-09-30 |
20100244150 | Configuration and fabrication of semiconductor structure in which source and drain extensions of field-effect transistor are defined with different dopants - An insulated-gate field-effect transistor ( | 2010-09-30 |
20100244151 | Structure and fabrication of field-effect transistor having source/drain extension defined by multiple local concentration maxima - An insulated-gate field-effect transistor ( | 2010-09-30 |
20100244152 | Configuration and fabrication of semiconductor structure having extended-drain field-effect transistor - An extended-drain insulated-gate field-effect transistor (104 or 106) contains first and second source/drain zones 324 and 184B or 364 and 186B) laterally separated by a channel (322 or 362) zone constituted by part of a first well region (184A or 186A). A gate dielectric layer (344 or 384) overlies the channel zone. A gate electrode (346 or 386) overlies the gate dielectric layer above the channel zone. The first source/drain zone is normally the source. The second S/D zone, normally the drain, is constituted with a second well region (184B or 186B). A well-separating portion 186A or 186B/212U) of the semiconductor body extends between the well regions and is more lightly doped than each well region. The configuration of the well regions cause the maximum electric field in the IGFET's portion of the semiconductor body to occur well below the upper semiconductor surface, typically at or close to where the well regions are closest to each other. The IGFET's operating characteristics are stable with operational time. | 2010-09-30 |
20100244153 | METHOD OF FABRICATING SPACERS IN A STRAINED SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack. | 2010-09-30 |
20100244154 | SEMICONDUCTOR DEVICE INCLUDING MISFET - A semiconductor device includes a semiconductor substrate, a gate insulating film, a gate electrode, a source/drain layer, and a germanide layer. The gate insulating film is formed on the semiconductor substrate. The gate electrode is formed on the gate insulating film. The source/drain layer is formed on both sides of the gate electrode, contains silicon germanium, and has a germanium layer in a surface layer portion. The germanide layer is formed on the germanium layer of the source/drain layer. | 2010-09-30 |
20100244155 | MAINTAINING INTEGRITY OF A HIGH-K GATE STACK BY AN OFFSET SPACER USED TO DETERMINE AN OFFSET OF A STRAIN-INDUCING SEMICONDUCTOR ALLOY - In sophisticated transistor elements including a high-k gate metal stack, the integrity of the sensitive gate materials may be ensured by a spacer element that may be concurrently used as an offset spacer for defining a lateral offset of a strain-inducing semiconductor alloy. The cap material of the sophisticated gate stack may be removed without compromising integrity of the offset spacer by providing a sacrificial spacer element. Consequently, an efficient strain-inducing mechanism may be obtained in combination with the provision of a sophisticated gate stack with the required material integrity, while reducing overall process complexity compared to conventional strategies. | 2010-09-30 |
20100244156 | METHODS FOR PROTECTING GATE STACKS DURING FABRICATION OF SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES FABRICATED FROM SUCH METHODS - Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. In an embodiment, a method for fabricating a semiconductor device comprises forming a gate stack comprising a first gate stack-forming layer overlying a semiconductor substrate and forming first sidewall spacers about sidewalls of the gate stack. After the step of forming the first sidewall spacers, a portion of the first gate stack-forming layer is exposed. The exposed portion is anisotropically etched using the gate stack and the first sidewall spacers as an etch mask. Second sidewall spacers are formed adjacent the first sidewall spacers after the step of anisotropically etching. | 2010-09-30 |
20100244157 | SEMICONDUCTOR DEVICE - A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×10 | 2010-09-30 |
20100244158 | SEMICONDUCTOR STRUCTURES RESULTING FROM SELECTIVE OXIDATION - Methods for selectively oxidizing a semiconductor structure include generating a gas cluster ion beam comprising an oxidizing source gas, directing the gas cluster ion beam to a region of a substrate adjacent a conductive line and exposing the region to the gas cluster ion beam including an oxidizing matter. Utilizing the gas cluster ion beam enables selective oxidation of a targeted region at temperatures substantially lower than those of typical oxidation processes thus, reducing or eliminating oxidation of the conductive line. Semiconductor devices including transistors formed using such methods are also disclosed. | 2010-09-30 |
20100244159 | EUTECTIC FLOW CONTAINMENT IN A SEMICONDUCTOR FABRICATION PROCESS - Eutectic Flow Containment in a Semiconductor Fabrication Process A disclosed semiconductor fabrication process includes forming a first bonding structure on a first surface of a cap wafer, forming a second bonding structure on a first surface of a device wafer, and forming a device structure on the device wafer. One or more eutectic flow containment structures are formed on the cap wafer, the device wafer, or both. The flow containment structures may include flow containment micro-cavities (FCMCs) and flow containment micro-levee (FCMLs). The FCMLs may be elongated ridges overlying the first surface of the device wafer and extending substantially parallel to the bonding structure. The FCMLs may include interior FCMLs lying within a perimeter of the bonding structure, exterior FCMLs lying outside of the bonding structure perimeter, or both. When the two wafers are bonded, the FCMLs and FCMCs confine flow of the eutectic material to the region of the bonding structure. | 2010-09-30 |
20100244160 | MEMS SENSOR, MEMS SENSOR MANUFACTURING METHOD, AND ELECTRONIC DEVICE - A MEMS sensor formed by processing a multi-layer wiring structure, includes: a movable weight portion coupled to a fixed frame portion with an elastic deformable portion and having a hollow portion formed at the periphery; a capacitance electrode portion including a fixed electrode portion fixed to the fixed frame portion and a movable electrode portion connected to the movable weight portion and arranged to face the fixed electrode portion; and an adjusting layer for adjusting at least one of amass of the movable weight portion, a damping coefficient of the movable electrode portion, and spring characteristics in the elastic deformable portion, wherein the adjusting layer includes at least one insulating layer that is a constituent element of the multi-layer wiring structure. | 2010-09-30 |
20100244161 | WAFER LEVEL PACKAGING USING FLIP CHIP MOUNTING - A semiconductor packaged device, and method of packaging that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device. | 2010-09-30 |
20100244162 | MEMS DEVICE WITH REDUCED STRESS IN THE MEMBRANE AND MANUFACTURING METHOD - A MEMS device comprises a membrane layer and a back-plate layer formed over the membrane layer. The membrane layer comprises an outer portion and an inner portion raised relative to the outer portion and a sidewall for connecting the inner portion and the outer portion. The sidewall is non-orthogonal to the outer portion. | 2010-09-30 |
20100244163 | MAGNETORESISTIVE ELEMENT AND MAGNETIC MEMORY - A magnetoresistive element includes a stabilization layer, a nonmagnetic layer, a spin-polarization layer provided between the stabilization layer and the nonmagnetic layer, the spin-polarization layer having magnetic anisotropy in a perpendicular direction, and a magnetic layer provided on a side of the nonmagnetic layer opposite to a side on which the spin-polarization layer is provided. The stabilization layer has a lattice constant smaller than that of the spin-polarization layer in an in-plane direction. The spin-polarization layer contains at least one element selected from a group consisting of cobalt (Co) and iron (Fe), has a body-centered tetragonal (BCT) structure, and has a lattice constant ratio c/a of 1.10 (inclusive) to 1.35 (inclusive) when a perpendicular direction is a c-axis and an in-plane direction is an a-axis. | 2010-09-30 |
20100244164 | USING POLE PIECES TO GUIDE MAGNETIC FLUX THROUGH A MEMS DEVICE AND METHOD OF MAKING - Two opposing substrate layers each having one or more recesses filled with magnetic material guide the flow of flux through a coil in a MEMS device layer to provide for closed-loop operation. Flux flows from one pole piece through the coil to a second pole piece. A method of making using lithographic etching techniques is also provided. | 2010-09-30 |
20100244165 | METHOD AND APPARATUS PROVIDING COMBINED SPACER AND OPTICAL LENS ELEMENT - A method and apparatus used for forming a lens and spacer combination, and imager module employing the spacer and lens combination. The apparatus includes a mold having a base, spacer section, and mold feature. The method includes using the mold with a blank to create a spacer that includes an integral lens. The spacer and lens combination and imager modules can be formed on a wafer level. | 2010-09-30 |
20100244166 | Multilayer wiring substrate, stack structure sensor package, and method of manufacturing stack structure sensor package - A multilayer wiring substrate has a through hole that passes from a first surface through to a second surface. The multilayer wiring substrate includes an electrical connection terminal formed in at least one of an inner edge portion which is a periphery of the through hole, an outer edge portion which is an outer periphery of the substrate, and a non-edge portion, on at least one of the first surface and the second surface. The electrical connection terminal has a castellation structure that does not pass through to a surface opposite to a formation surface. | 2010-09-30 |
20100244167 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING SAME - A solid-state imaging device includes: a substrate including a plurality of light receiving sections; an optical waveguide provided above each of the plurality of light receiving sections and surrounded by a cladding layer; a color filter provided above each of the optical waveguides; and a lens provided above the color filter, the optical waveguide including a first layer having a first refractive index and a second layer being in contact with the first layer and having a second refractive index higher than the first refractive index. | 2010-09-30 |
20100244168 | SOLID-STATE IMAGING DEVICE - A solid-state imaging device includes: a substrate including a plurality of light receiving sections; and a color filter including a guided-mode resonant grating provided immediately above each of the plurality of light receiving sections, at least one of an upper surface and a lower surface of the guided-mode resonant grating being covered with a layer having a lower refractive index than the guided-mode resonant grating. | 2010-09-30 |
20100244169 | SOLID-STATE IMAGING DEVICE, FABRICATION METHOD THEREOF, IMAGING APPARATUS, AND FABRICATION METHOD OF ANTI-REFLECTION STRUCTURE - A fabrication method of an anti-reflection structure includes the steps of: forming a resin film having micro-particles dispersed therein on a surface of a substrate; forming a protrusion dummy pattern on the resin film by etching the resin film using the micro-particles in the resin film as a mask while gradually etching the micro-particles; and forming a protrusion pattern on the surface of the substrate by etching back the surface of the substrate together with the resin film having the protrusion dummy pattern formed thereon, and transferring a surface shape of the protrusion dummy pattern formed on a surface of the resin film to the surface of the substrate. | 2010-09-30 |
20100244170 | PHOTO DETECTOR AND OPTICALLY INTERCONNECTED LSI - A photo detector having an electrically conductive thin film and a light-receiving unit. A coupling periodic structure is provided on a surface of the film and converts incidence light to surface plasmon. The coupling periodic structure has an opening that penetrates the obverse and reverse surfaces of the thin film. The light-receiving unit is provided at one end of the opening in the surface that is opposite to the surface on which the coupling periodic structure is provided. The opening is shaped like a slit and is broader than half (½) the wavelength of the surface plasmon in a direction that intersects at right angles with a polarization direction of the incidence light and is narrower than half (½) the wavelength of the surface plasmon in a direction parallel to the polarization direction. | 2010-09-30 |
20100244171 | SEMICONDUCTOR MODULE AND CAMERA MODULE MOUNTING SAID SEMICONDUCTOR MODULE - A semiconductor module includes a lower wiring substrate having a semiconductor device mounted and an upper wiring substrate having an opening in a position corresponding to the semiconductor device and having a packaging-component mountable region around the opening. The lower wiring substrate and the upper wiring substrate are electrically connected to each other via a plurality of solder balls provided around the semiconductor device. The solder balls are covered with light blocking under-fills. | 2010-09-30 |
20100244172 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING PATTERNED RADIATION BLOCKING ON A SEMICONDUCTOR DEVICE - Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer. | 2010-09-30 |
20100244173 | IMAGE SENSOR AND METHOD OF FABRICATING SAME - Provided is a method of fabricating an image sensor device. The method includes providing a device substrate having a front side and a back side. The method includes forming first and second radiation-sensing regions in the device substrate, the first and second radiation-sensing regions being separated by an isolation structure. The method also includes forming a transparent layer over the back side of the device substrate. The method further includes forming an opening in the transparent layer, the opening being aligned with the isolation structure. The method also includes filling the opening with an opaque material. | 2010-09-30 |
20100244174 | HIGHLY-DEPLETED LASER DOPED SEMICONDUCTOR VOLUME - A device with increased photo-sensitivity using laser treated semiconductor as detection material is disclosed. In some embodiments, the laser treated semiconductor may be placed between and an n-type and a p-type contact or two Schottky metals. The field within the p-n junction or the Schottky metal junction may aid in depleting the laser treated semiconductor section and may be capable of separating electron hole pairs. Multiple device configurations are presented, including lateral and vertical configurations. | 2010-09-30 |
20100244175 | Image sensor and method of fabricating the same - The image sensor includes a substrate; a wiring structure formed on a front side of the substrate and including a plurality of wiring layers and a plurality of insulating films; a first well formed within the substrate and having a first conductivity type; and a first metal wiring layer directly contacting a backside of the substrate and configured to apply a first well bias to the first well. | 2010-09-30 |
20100244176 | Integrated circuit having wiring structure, solid image pickup element having the wiring structure, and imaging device having the solid image pickup element - (Problems) To provide an integrated circuit having the wiring structure including pads with a small wiring area and capable of highly integrating elements, a solid image pickup element having the wiring structure, and an imaging device having the solid image pickup element. | 2010-09-30 |
20100244177 | PHOTODIODE CELL STRUCTURE OF PHOTODIODE INTEGRATED CIRCUIT FOR OPTICAL PICKUP AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a photodiode cell, including: a first-type substrate; a second-type epitaxial layer disposed on the first-type substrate; heavily-doped second-type layers, each having a small depth, formed on the second-type epitaxial layer; and heavily-doped first-type layers, each having a narrow and shallow section, disposed on the second-type epitaxial layer and formed between the heavily-doped second-type layers, wherein the first-type and second-type have opposite doped states. | 2010-09-30 |
20100244178 | FIELD EFFECT TRANSISTOR GATE PROCESS AND STRUCTURE - A Schottky gate ( | 2010-09-30 |
20100244179 | STRUCTURE AND METHOD FOR LATCHUP IMPROVEMENT USING THROUGH WAFER VIA LATCHUP GUARD RING - A method and structure for preventing latchup. The structure includes a latchup sensitive structure and a through wafer via structure bounding the latch-up sensitive structure to prevent parasitic carriers from being injected into the latch-up sensitive structure. | 2010-09-30 |
20100244180 | METHOD FOR FABRICATING DEVICE ISOLATION STRUCTURE - A method of a fabricating a semiconductor device includes providing a substrate having a first region and a second region. A pad layer is formed overlying the substrate in both the first region and the second region. A mask layer is then formed overlying the pad layer. Thereafter, the mask layer, the pad layer and the substrate are patterned to form a plurality of first trenches in the first region and a plurality of second trenches in the second region. A trimming process is then performed on the mask layer to remove a portion of the mask layer. An insulation layer is formed over the substrate and fills the plurality of the first trenches and the plurality of the second trenches. Ultimately, a planarization process is performed on the insulation layer. | 2010-09-30 |
20100244181 | Filling Gaps in Integrated Circuit Fabrication - A gap may be filled using deposition and sputtering by forming a liner and a gap fill material in the same deposition chamber in some embodiments. The liner may be made harder than the gap fill so that the liner protects the underlying substrate when sputtering is used during the gap fill. | 2010-09-30 |
20100244182 | METHOD OF MANUFACTURING LAMINATED WAFER BY HIGH TEMPERATURE LAMINATING METHOD - To provide a method of manufacturing a laminated wafer by which a strong coupling is achieved between wafers made of different materials having a large difference in thermal expansion coefficient without lowering a maximum heat treatment temperature as well as in which cracks or chips of the wafer does not occur. A method of manufacturing a laminated wafer | 2010-09-30 |
20100244183 | INTEGRATED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An integrated semiconductor device and method of manufacturing the same includes leaving one part of a semiconductor layer so that an inclined surface is formed on a trench when forming the trench on a SOI wafer. A thick silicon oxide film (second insulation film) is formed along this incline surface. This thick silicon oxide film prevents oxygen entering a boundary surface between an insulation layer and the semiconductor layer of the SOI wafer within the trench. | 2010-09-30 |
20100244184 | Method of Forming an Electrical Contact Between a Support Wafer and the Surface of a Top Silicon Layer of a Silicon-on-Insulator Wafer and an Electrical Device Including Such an Electrical Contact - Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method. | 2010-09-30 |
20100244185 | SEMICONDUCTOR DEVICE, SINGLE-CRYSTAL SEMICONDUCTOR THIN FILM-INCLUDING SUBSTRATE, AND PRODUCTION METHODS THEREOF - The present invention provides a semiconductor device, a single-crystal semiconductor thin film-including substrate, and production methods thereof, each allowing single-crystal semiconductor thin film-including single-crystal semiconductor elements produced by being transferred onto a low heat resistant insulating substrate to have enhanced transistor characteristics. | 2010-09-30 |
20100244186 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of stacked component units stacked in a first direction, each of the stacked component units including a first conducting film made of a semiconductor of a first conductivity type provided perpendicular to the first direction and a first insulating film stacked in the first direction with the first conducting film; a semiconductor pillar piercing the stacked structural unit in the first direction and including a conducting region of a second conductivity type, the semiconductor pillar including a first region opposing each of the first conducting films, and a second region provided between the first regions with respect to the first direction, the second region having a resistance different from a resistance of the first region; and a second insulating film provided between the semiconductor pillar and the first conducting film. | 2010-09-30 |
20100244187 | ESD NETWORK CIRCUIT WITH A THROUGH WAFER VIA STRUCTURE AND A METHOD OF MANUFACTURE - The present invention generally relates to a circuit structure and a method of manufacturing a circuit, and more specifically to an electrostatic discharge (ESD) circuit with a through wafer via structure and a method of manufacture. An ESD structure includes an ESD active device and at least one through wafer via structure providing a low series resistance path for the ESD active device to a substrate. An apparatus includes an input, at least one power rail and an ESD circuit electrically connected between the input and the at least one power rail, wherein the ESD circuit comprises at least one through wafer via structure providing a low series resistance path to a substrate. A method, includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate. | 2010-09-30 |
20100244188 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device comprising: a semiconductor substrate in which an integrated circuit is formed; a first resin film provided over the semiconductor substrate; a second resin film provided over an upper surface of the first resin film except at least a peripheral portion of the first resin film; and a thin film inductor provided over the second resin film. | 2010-09-30 |
20100244189 | INTEGRATION SUBSTRATE WITH A ULTRA-HIGH-DENSITY CAPACITOR AND A THROUGH-SUBSTRATE VIA - An integration substrate for a system in package comprises a through-substrate via and a trench capacitor wherein with a trench filling that includes at least four electrically conductive capacitor-electrode layers in an alternating arrangement with dielectric layers. —The capacitor-electrode layers are alternatingly connected to a respective one of two capacitor terminals provided on the first or second substrate side. The trench capacitor and the through-substrate via are formed in respective trench openings and via openings in the semiconductor substrate, which have an equal lateral extension exceeding 10 micrometer. This structure allows, among other advantages, a particularly cost-effective fabrication of the integration substrate because the via openings and the trench openings in the substrate can be fabricated simultaneously. | 2010-09-30 |
20100244190 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device, include a capacitor of a MIM (Metal-Insulator-Metal) structure; and at least one pair of shield parts which sandwich said MIM structure capacitor sandwiched by an insulating film. | 2010-09-30 |
20100244191 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulation interlayer and an etch stop layer sequentially stacked on a substrate wherein a lower structure including a first contact pad is formed. A second contact pad penetrates the insulation interlayer and the etch stop layer and is connected to the first contact pad. The second contact pad protrudes from the etch stop layer. A pad spacer is provided between the second contact pad and the insulation interlayer. A lower electrode is provided on the etch stop layer and is connected to the second contact pad. A dielectric layer and an upper electrode are sequentially provided on the lower electrode. | 2010-09-30 |
20100244192 | DIELECTRIC FILM AND SEMICONDUCTOR DEVICE USING DIELECTRIC FILM - The present invention provides a dielectric film having a high permittivity and a high heat resistance. An embodiment of the present invention is a dielectric film ( | 2010-09-30 |
20100244193 | System-in-Package Having Integrated Passive Devices and Method Therefor - A semiconductor device has a substrate, first passivation layer formed over the substrate, and integrated passive device formed over the substrate. The integrated passive device can include an inductor, capacitor, and resistor. A second passivation layer is formed over the integrated passive device. System components are mounted to the second passivation layer and electrically connect to the second conductive layer. A mold compound is formed over the integrated passive device. A coefficient of thermal expansion of the mold compound is approximately equal to a coefficient of thermal expansion of the system component. The substrate is removed. An opening is etched into the first passivation layer and solder bumps are deposited over the opening in the first passivation layer to electrically connect to the integrated passive device. A metal layer can be formed over the molding compound or first passivation layer for shielding. | 2010-09-30 |
20100244194 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device comprising: a semiconductor substrate having a first conductive type layer; a first diffusion region which has the first conductive type and is formed in the first conductive type layer; a second diffusion region which has a second conductive type and an area larger than an area of the first diffusion region and overlaps the first diffusion region; and a PN junction formed at an interface between the first and the second diffusion regions. | 2010-09-30 |
20100244195 | HOST SUBSTRATE FOR NITRIDE BASED LIGHT EMITTING DEVICES - A host substrate and method of making a host substrate for nitride based thin-film semiconductor devices are provided. According to one embodiment, the method includes the steps of providing a silicon layer; etching a pattern of holes in the silicon layer; plating the silicon layer with copper to fill the holes etched in the silicon layer; bonding the silicon layer to a gallium nitride (GaN) layer, the GaN layer attached to a sapphire substrate; and removing the sapphire substrate. The host substrate is configured to address the coefficient of thermal expansion (CTE) mismatch problem and reduce the amount of stress resulting from such CTE mismatch. A combination of metal and semiconductor materials provide for the desired thermal and electrical conductivity while providing for subsequent dicing and incorporation of the finished semiconductor devices into other circuits. | 2010-09-30 |
20100244196 | Group III nitride semiconductor composite substrate, group III nitride semiconductor substrate, and group III nitride semiconductor composite substrate manufacturing method - A group III nitride semiconductor composite substrate includes a substrate composed of a conductive material having a melting point of not less than 100° C., a group III nitride layer provided on the substrate, and a group III nitride single crystal film provided on the group III nitride layer. The group III nitride layer includes an undulation including a periodic roughness in a surface of the group III nitride layer contacted with the group III nitride single crystal film. The undulation includes a 1-dimensional power spectral density of less than 500 nm | 2010-09-30 |
20100244197 | EPITAXIAL METHODS AND STRUCTURES FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS - The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material. | 2010-09-30 |
20100244198 | CMOS SIGE CHANNEL PFET AND SI CHANNEL NFET DEVICES WITH MINIMAL STI RECESS - Silicon germanium (SiGe) is epitaxially grown on a silicon channel above nFET and pFET regions of a substrate. SiGe is removed above the nFET regions. A device includes a silicon channel above the nFET regions and a SiGe channel above the pFET regions. | 2010-09-30 |
20100244199 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring. | 2010-09-30 |
20100244200 | Integrated circuit connecting structure having flexible layout - A wafer has a cutting part filled with a connecting medium. After the wafer is cut into chips along the cutting part, two contacts on two surfaces of the chip can be connected through corresponding leading wires and the connecting medium. Thus, the chip can have a flexible layout. | 2010-09-30 |
20100244201 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first semiconductor substrate including a first integrated circuit, a second semiconductor substrate mounted over the first semiconductor substrate, the second semiconductor substrate including a second integrated circuit, a post made of an inorganic substance and formed over the first semiconductor substrate, an adhesive layer made of an organic substance arranged between the first and the second semiconductor substrates, and a substrate-through-via made of an electrical conductor extending through the second semiconductor substrate and the post, the substrate-through-via extending to the first semiconductor substrate. | 2010-09-30 |
20100244202 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and its manufacturing method, the semiconductor device comprising: a semi-insulating substrate | 2010-09-30 |
20100244203 | SEMICONDUCTOR STRUCTURE HAVING A PROTECTIVE LAYER - A semiconductor structure includes a substrate having a first nitride-based semiconductor layer. A pseudomorphic protective layer is formed on the first nitride-based semiconductor layer and a second nitride-based semiconductor layer is formed on the pseudomorphic protective layer. The pseudomorphic protective layer has a thickness that is less than a critical thickness so that it drives the material quality of the second nitride-based semiconductor layer to correspond with that of the first nitride-based semiconductor layer. | 2010-09-30 |
20100244204 | FILM FORMING METHOD, FILM FORMING APPARATUS, STORAGE MEDIUM AND SEMICONDUCTOR DEVICE - Provided is a technology capable of obtaining a fluorine-containing carbon film having a good leakage property, coefficient of thermal expansion and mechanical strength. The fluorine-containing carbon film is formed by using active species obtained by activating a C | 2010-09-30 |
20100244205 | Glass Frits - Glass frits, conductive inks and articles having conductive inks applied thereto are described. According to one or more embodiments, glass frits with no intentionally added lead comprise TeO | 2010-09-30 |
20100244206 | METHOD AND STRUCTURE FOR THRESHOLD VOLTAGE CONTROL AND DRIVE CURRENT IMPROVEMENT FOR HIGH-K METAL GATE TRANSISTORS - A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer. | 2010-09-30 |
20100244207 | MULTIPLE THICKNESS AND/OR COMPOSITION HIGH-K GATE DIELECTRICS AND METHODS OF MAKING THEREOF - Disclosed are methods of making an integrated circuit with multiple thickness and/or multiple composition high-K gate dielectric layers and integrated circuits containing multiple thickness and/or multiple composition high-K gate dielectrics. The methods involve forming a layer of high-K atoms over a conventional gate dielectric and heating the layer of high-K atoms to form a high-K gate dielectric layer. Methods of suppressing gate leakage current while mitigating mobility degradation are also described. | 2010-09-30 |
20100244208 | Semiconductor Device and Method of Forming a Shielding Layer Between Stacked Semiconductor Die - A semiconductor device has a first semiconductor die with a shielding layer formed over its back surface. The first semiconductor die is mounted to a carrier. A first insulating layer is formed over the shielding layer. A second semiconductor die is mounted over the first semiconductor die separated by the shielding layer and first insulating layer. A second insulating layer is deposited over the first and second semiconductor die. A first interconnect structure is formed over the second semiconductor die and second insulating layer. A second interconnect structure is formed over the first semiconductor die and second insulating layer. The shielding layer is electrically connected to a low-impedance ground point through a bond wire, RDL, or TSV. The second semiconductor die may also have a shielding layer formed on its back surface. The semiconductor die are bonded through the metal-to-metal shielding layers. | 2010-09-30 |
20100244209 | CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided are: a circuit device demonstrating an improved connection reliability while being mounted; and a method for manufacturing the same. The circuit device of the present invention includes: an island; leads arranged around the island, each lead having a lower surface and a side surface exposed to the outside; and a semiconductor element mounted on the island and electrically connected to the leads through thin metal wires. Furthermore, the exposed end portion of the lead is formed to spread toward the outside. By forming the lead in this manner, the area where the lead comes into contact with a brazing filler material is increased, thus improving the connection strength therebetween. | 2010-09-30 |
20100244210 | LEAD FRAME AND METHOD FOR MANUFACTURING CIRCUIT DEVICE USING THE SAME - Provided are: a lead frame enabling efficient manufacturing of multiple circuit devices; and a method for manufacturing a circuit device using the same. In the lead frame of the present invention, units are arranged and frame-shaped first and second supporters are provided around the units to mechanically support the units. Moreover, a half groove is provided in the first supporter at a portion on an extended line of a dividing line defined at a boundary between each adjacent two of the units. Furthermore, a penetration groove penetrating a part of the second supporter at a portion on an extended line of another dividing line is provided. | 2010-09-30 |
20100244211 | MULTICHIP DISCRETE PACKAGE - A multichip discrete package with a leadframe having a plurality of leads and a first die attach pad (DAP), the first DAP having side portions that extend above the first DAP, a first discrete die bonded to the first DAP, at least a first wirebond which forms an electrical connections between the first discrete die and a first selected one of the plurality of leads, a metal plate attached to tops of the side portions forming a second DAP, a second discrete die bonded to the second DAP, at least a second wirebond which forms an electrical connections between the second discrete die and a second selected one of the leads; and encapsulating material formed around the first and second die and the first and second DAPs. | 2010-09-30 |
20100244212 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH POST TYPE INTERCONNECTOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a bottom package including a first device over a first substrate and a second substrate over the first device; forming an encapsulation material over the bottom package with an opening over the second substrate; and forming a conductive post within the opening. | 2010-09-30 |
20100244213 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes a lead frame | 2010-09-30 |
20100244214 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To improve the heat dissipation characteristics of a semiconductor device. | 2010-09-30 |
20100244215 | WIRELESS IC DEVICE - A wireless IC device includes a radiating plate, a wireless IC chip, and a feeder circuit board, on which the wireless IC chip is mounted. The feeder circuit board includes a resonant circuit with an inductance element, and the resonant circuit is electromagnetically coupled with the radiating plate. The wireless IC chip is interposed between the radiating plate and the feeder circuit board. | 2010-09-30 |
20100244216 | Semiconductor Device and Method of Forming No-Flow Underfill Material Around Vertical Interconnect Structure - A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump. | 2010-09-30 |
20100244217 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED CONFIGURATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first stack layer including a first device over a first substrate, the first device including a through silicon via; configuring a second stack layer over the first stack layer, the second stack layer including an analog device; configuring a third stack layer over the second stack layer; and encapsulating the integrated circuit packaging system. | 2010-09-30 |
20100244218 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI-STACKED FLIP CHIPS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; depositing a through-conductor on the base substrate; depositing a semiconducting layer on the base substrate and around the through-conductor; forming a metal trace connected to the through-conductor; depositing a dielectric surrounding the metal trace; and removing the base substrate. | 2010-09-30 |
20100244219 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PACKAGE STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an encapsulation surrounding an integrated circuit having an inactive side and an active side exposed; forming a hole through the encapsulation with the hole not exposing the integrated circuit; forming a through conductor in the hole; and mounting a substrate with the integrated circuit surrounded by the encapsulation with the active side facing the substrate. | 2010-09-30 |
20100244220 | LAYOUT STRUCTURE AND METHOD OF DIE - A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally. | 2010-09-30 |
20100244221 | INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING DUAL SIDED CONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a device through via and a device interconnect, over a substrate with the device through via traversing the integrated circuit and the device interconnect attached to the device through via; attaching a conductive support over the substrate with the conductive support adjacent to the integrated circuit; providing a pre-formed interposer, having an interposer through via and a pre-attached interconnect, with the pre-attached interconnect attached to the interposer through via; mounting the pre-formed interposer over the integrated circuit and the conductive support with the pre-attached interconnect over the device through via; and forming an encapsulation over the substrate covering the integrated circuit, the conductive support, and partially covering the pre-formed interposer. | 2010-09-30 |
20100244222 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate-interconnect; mounting an internal-interconnect to the substrate-interconnect; mounting a structure having an integral-interposer-structure over the substrate with the integral-interposer-structure connected to the internal-interconnect; mounting an integrated circuit to the substrate and under the integral-interposer-structure; and encapsulating the internal-interconnect and the integrated circuit with an encapsulation. | 2010-09-30 |
20100244223 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTEGRAL-INTERPOSER-STRUCTURE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a shielding channel through a substrate first side and a substrate second side; mounting a first shielding interconnect to the shielding channel; mounting an integrated circuit over the substrate and adjacent to the first shielding interconnect; attaching a silicon interposer, having an integral-conductive-shield and a via, to the first shielding interconnect with the integral-conductive-shield over the integrated circuit; grounding the shielding channel at the substrate second side; and forming an encapsulation over the substrate covering the integrated circuit and the first shielding interconnect. | 2010-09-30 |
20100244224 | SEMICONDUCTOR CHIP MOUNTING BODY, METHOD OF MANUFACTURING SEMICONDUCTOR CHIP MOUNTING BODY AND ELECTRONIC DEVICE - According to one embodiment, a semiconductor chip mounting body, with an enhanced shock-resistance at portions of the bonding member corresponding to the corners of a semiconductor chip, is provided. The semiconductor chip mounting body includes a circuit board having a circuit pattern formed on a mounting surface thereof, a semiconductor chip mounted on the circuit pattern of the circuit board, and a bonding member arranged at least between the circuit board and the semiconductor chip, and on the sides of the semiconductor chip to fix the semiconductor chip on the circuit board. The bonding member contains thermosetting resin and magnetic powder dispersed in the thermosetting resin. The magnetic powder is locally disposed in portions of the bonding member which is located the corners of the semiconductor chip. | 2010-09-30 |
20100244225 | STACKABLE ELECTRONIC PAGKAGE AND METHOD OF FABRICATING SAME - An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween. | 2010-09-30 |
20100244226 | STACKABLE ELECTRONIC PACKAGE AND METHOD OF FABRICATING SAME - An electronic package includes a first layer having a first surface, the first layer includes a first device having a first electrical node, and a first contact pad in electrical communication with the first electrical node and positioned within the first surface. The package includes a second layer having a second surface and a third surface, the second layer includes a first conductor positioned within the second surface and a second contact pad positioned within the third surface and in electrical communication with the first conductor. A first anisotropic conducting paste (ACP) is positioned between the first contact pad and the first conductor to electrically connect the first contact pad to the first conductor such that an electrical signal may pass therebetween. | 2010-09-30 |
20100244227 | Semiconductor packages and electronic systems including the same - Provided are semiconductor packages and electronic systems including the same. A first memory chip may be stacked on a first portion of a substrate. A controller chip may be stacked on a second portion of the substrate, which is different from the first portion. At least one first bonding wire may directly connect the first memory chip with the controller chip. At least one second bonding wire may directly connect the first memory chip with the substrate, and may be electrically connected with the at least one first bonding wire. | 2010-09-30 |
20100244228 | Semiconductor device and method of manufacturing the same - The extent of a bow of a semiconductor device is suppressed in a case where the fillet width of an underfill resin is asymmetrical. The center position | 2010-09-30 |
20100244229 | SEMICONDUCTOR PACKAGE FABRICATION PROCESS AND SEMICONDUCTOR PACKAGE - A substrate is provided with electrical connection pads on a front face and on a rear face, the front pads and rear pads being selectively connected via a network passing through the substrate. A peripheral edge of the substrate is mounted on a rigid annular frame and the rearm face secured to a suction table. A layer of a dielectric sealant containing electrically conductive particles is deposited on the front face and front pads of the substrate. Integrated-circuit chips are positioned on the front face to flatten the layer of dielectric sealant, the included electrically conductive particles making electrical connection between pads of the integrated-circuit and the front pads of the substrate. The resulting assembly in then encapsulated in a block of encapsulating material positioned on top of the front face of the substrate. The block is then diced in order to obtain a plurality of semiconductor packages. | 2010-09-30 |
20100244230 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a wiring board which includes a first face and a second face and in which a conductor pattern and a through part are provided; an electronic component which includes an electrode pad forming face where an electrode pad is formed and which is housed in the through part so that the electrode pad forming face is provided on the first face side; a seal resin which is provided in the through part and the electrode pad forming face, seals the electronic component and includes a first plane exposing a connection face of the electrode pad; and a wiring pattern which is provided in the first face of the wiring board and the first plane of the seal resin and electrically connects the connection face of the electrode pad with a first connected face of the conductor pattern, and which includes a pad part. | 2010-09-30 |
20100244231 | SEMICONDUCTOR DEVICE - A semiconductor device comprises: a semiconductor element; a support substrate arranged on a surface of the semiconductor element opposite to a surface thereof provided with a pad, the support substrate being wider in area than the semiconductor element; a burying insulating layer on the support substrate for burying the semiconductor element therein; a fan-out interconnection led out from the pad to an area on the burying insulating layer lying more peripherally outwardly than the semiconductor element; and a reinforcement portion arranged in a preset area on top of outer periphery of the semiconductor element for augmenting the mechanical strength of the burying insulating layer and the fan-out interconnection. | 2010-09-30 |
20100244232 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH Z-INTERCONNECTS HAVING TRACES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a carrier; mounting an integrated circuit on the carrier; mounting a z-interconnect on the carrier, the z-interconnect for supporting a trace cantilevered over the integrated circuit; encapsulating the integrated circuit with an encapsulation; removing the carrier; and depositing a substrate below the integrated circuit. | 2010-09-30 |
20100244233 | Chip stack package and method of fabricating the same - Provided is a chip stack package and a method of manufacturing the same. A chip stack package may include a base chip including a base substrate, a base through via electrode penetrating the base substrate, a base chip pad connected to the base through via electrode, and a base encapsulant. The chip stack package may further include at least one stack chip on a surface of the base substrate. The chip stack package may also include an external connection terminal connected to the base through via electrode and the base chip pad and protruding from the base encapsulant, and an external encapsulant surrounding and protecting outer surfaces of the base chip and the at least one stack chip, wherein the chip through via electrode and the chip pad are connected to the base through via electrode and the base chip pad of the base chip. | 2010-09-30 |
20100244234 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present invention provides a semiconductor device which includes a semiconductor chip formed with an electrode pad on one surface thereof, a wiring board having a wiring pattern, with its one surface opposing the other surface of the semiconductor chip, a wire for electrically connecting the electrode pad of the semiconductor chip with the wiring pattern of the wiring board, an external terminal arranged on the other surface of the wiring board for electrical connection with the electrode pad through the wire and wiring pattern, and a sealant for fixing the semiconductor chip on one surface of the wiring board such that a hollow is formed between the other surface of the semiconductor chip and the one surface of the wiring board. The wiring board includes a throughhole communicating with the hollow. | 2010-09-30 |
20100244235 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An integrated circuit package includes a first dielectric layer comprising a dielectric film having a first side and a second side. The package also includes a die having an active surface affixed to a contact location of the first side of the dielectric film absent a layer of adhesive therebetween that is distinct from a material of the dielectric film. A die stud is affixed to the active surface of the die and extends through the dielectric film to an interconnect location of the second side of the dielectric film, and a via is formed through the dielectric film by the die stud. | 2010-09-30 |
20100244236 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SPREADER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a package substrate; mounting an integrated circuit die on the package substrate; and attaching a heat spreader assembly, having a thermal adhesive layer formed therein, to the package substrate and the integrated circuit die. | 2010-09-30 |
20100244237 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device comprising a semiconductor module that has a joint surface, a first fitting portion and a second fitting portion provided on the joint surface, the second fitting portion having a shape different from the first fitting portion; and a radiating fin that has a joint surface, a third fitting portion and a fourth fitting portion provided on the joint surface, the fourth fitting portion having a shape different from the third fitting portion; the semiconductor module is bonded to the radiating fin so that the first fitting portion is fitting into the third fitting portion or the third fitting portion is fitting into the first fitting portion, and the second fitting portion is fitting into the fourth fitting portion or the fourth fitting portion is fitting into the second fitting portion. | 2010-09-30 |
20100244238 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips are disposed in an alternating sequence. | 2010-09-30 |
20100244239 | Semiconductor Device and Method of Forming Enhanced UBM Structure for Improving Solder Joint Reliability - A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the first conductive layer. A second conductive layer is formed over first insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. An under bump metallization layer (UBM) is formed over the third insulating layer and second conductive layer. A UBM build-up structure is formed over the UBM. The UBM build-up structure has a sloped sidewall and is confined within a footprint of the UBM. The UBM build-up structure extends above the UBM to a height of 2-20 micrometers. The UBM build-up structure is formed in sections occupying less than an area of the UBM. A solder bump is formed over the UBM and UBM build-up structure. The sections of the UBM build-up structure provide exits for flux vapor escape. | 2010-09-30 |
20100244240 | STACKABLE ELECTRONIC PACKAGE AND METHOD OF MAKING SAME - An apparatus comprises a first chip layer comprising a first component coupled to a first side of a first flex layer, the first component comprising a plurality of electrical pads. The first chip layer also comprises a first plurality of feed-thru pads coupled to the first side of the first flex layer and a first encapsulant encapsulating the first component, the first encapsulant having a portion thereof removed to form a first plurality of cavities in the first encapsulant and to expose the first plurality of feed-thru pads by way of the first plurality of cavities. | 2010-09-30 |
20100244241 | Semiconductor Device and Method of Forming a Thin Wafer Without a Carrier - A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via. | 2010-09-30 |
20100244242 | SEMICONDUCTOR DEVICE - A semiconductor device including a first substrate having first and second surfaces, multiple first mounting pads formed on the first surface of the first substrate and for mounting a first semiconductor element on the first surface of the first substrate, multiple first connection pads formed on the first surface of the first substrate and positioned on the periphery of the multiple first mounting pads, a second substrate formed on the first substrate and having first and second surfaces, the second substrate having a second penetrating electrode which penetrates through the first and second surfaces of the second substrate, multiple second mounting pads formed on the first surface of the second substrate and for mounting a second semiconductor element, and a conductive member formed on one of the first connection pads and electrically connecting an end portion of the second penetrating electrode and the one of the first connection pads. | 2010-09-30 |
20100244243 | SEMICONDUCTOR DEVICE - A semiconductor device has a flexible substrate which can be folded U-shape, and an outer surface of the flexible substrate being provided concave-convex portions for heat radiation. The semiconductor device also has a semiconductor chip which is mounted on an inner surface of the flexible substrate, and the chip being electronically connected with the flexible substrate. | 2010-09-30 |
20100244244 | Chip Having a Bump and Package Having the Same - The present invention relates to a chip having a bump and a package having the same. The chip includes a chip body, at least one via, a passivation layer, an under ball metal layer and at least one bump. The via penetrates the chip body, and is exposed to a surface of the chip body. The passivation layer is disposed on the surface of the chip body, and the passivation layer has at least one opening. The opening exposes the via. The under ball metal layer is disposed in the opening of the passivation layer, and is connected to the via. The bump is disposed on the under ball metal layer, and includes a first metal layer, a second metal layer and a third metal layer. The first metal layer is disposed on the under ball metal layer. The second metal layer is disposed on the first metal layer. The third metal layer is disposed on the second metal layer. As the bumps can connect two chips, the chip is stackable, and so the density of the product is increased while the size of the product is reduced. | 2010-09-30 |
20100244245 | Filp Chip Interconnection Structure with Bump on Partial Pad and Method Thereof - A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR−2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped. | 2010-09-30 |
20100244246 | ELECTRONIC COMPONENT WITH MECHANICALLY DECOUPLED BALL CONNECTIONS - An electronic component including at least one chip and/or one support, the chip configured to be transferred onto the support and linked, at a level of at least one connection site of the chip, formed by at least one portion of a layer of the chip, to at least one connection site of the support formed by at least one portion of a layer of the support, by at least one ball, the chip and/or the support including a mechanism for mechanical decoupling of the connection site of the chip and/or of the support with respect to the chip and/or to the support, which mechanism includes at least one cavity made in the layer of the chip and/or of the support, under the connection site of the chip and/or of the support, and at least one trench, made in the layer of the chip and/or of the support, communicating with the cavity. | 2010-09-30 |
20100244247 | VIA STRUCTURE AND VIA ETCHING PROCESS OF FORMING THE SAME - A via etching process forms a through-substrate via having a round corner and a tapered sidewall profile. A method includes providing a semiconductor substrate; forming a hard mask layer and a patterned photoresist layer on the semiconductor substrate; forming an opening in the hard mask and exposing a portion of the semiconductor substrate; forming a via passing through at least a part of the of semiconductor substrate using the patterned photoresist layer and hard mask layer as a masking element; performing a trimming process to round the top corner of the via; and removing the photoresist layer. | 2010-09-30 |