| 39th week of 2011 patent applcation highlights part 70 |
| Patent application number | Title | Published |
|---|
| 20110238876 | APPARATUS AND METHOD FOR CONFIGURING A BUS SYSTEM - The present invention relates to an apparatus for configuring a bus system which includes a plurality of participants as well as a bus master and a safety monitor having an input unit by means of which suitable configuration information can be entered and/or selected for the configuration of the bus system and having a configuration unit configured to configure both the bus master and also the safety monitor by means of at least a piece of identical common configuration information input or selected via the input unit. The invention further relates to a method which can be carried out by the apparatus in accordance with the invention. | 2011-09-29 |
| 20110238877 | Arbitration in Multiprocessor Device - An integrated circuit device ( | 2011-09-29 |
| 20110238878 | METHOD AND APPARATUS FOR HANDLING AN INTERRUPT DURING TESTING OF A DATA PROCESSING SYSTEM - A method for handling an interrupt during testing of at least one logic block of a processor includes performing a test on at least one logic block of a processor; during the performing, receiving an interrupt; determining a progress status of the test in response to receiving the interrupt; and determining when the processor responds to an interrupt, wherein the determining when the processor responds to an interrupt is based on the progress of the test. | 2011-09-29 |
| 20110238879 | SORTING MOVABLE MEMORY HIERARCHIES IN A COMPUTER SYSTEM - Method and apparatus for optimally placing memory devices within a computer system. A memory controller may include circuitry configured to retrieve or one or more performance metrics a plurality of memory devices connected thereto. Based on the performance metrics and one or more predefined rules for placing memory devices, the circuitry may determine an optimal placement of the memory devices in the system. | 2011-09-29 |
| 20110238880 | INTERFACE CARD SYSTEM - There is provided an interface card system for SD bus control. The interface card system for SD bus control includes a CPU bus interface | 2011-09-29 |
| 20110238881 | DOCKABLE HANDHELD COMPUTING DEVICE WITH GRAPHICAL USER INTERFACE AND METHODS FOR USE THEREWITH - A physical docking interface facilitates co-processing with an extended processing module of an extended computer unit in a physical docked mode, when the handheld computing unit is coupled to the extended computer unit via the physical docking interface. A quasi docking interface facilitates co-processing with the extended processing module in a quasi docked mode when the handheld computing unit is coupled to the extended computer unit via the quasi docking interface. A graphical user interface presents a selectable quasi docking interface graphic for display to a user and responds to a user selection of the selectable quasi docking interface graphic by generating a quasi docking command. The quasi docking interface couples the handheld computing unit to the extended computing unit in response to the quasi docking command. | 2011-09-29 |
| 20110238882 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 2011-09-29 |
| 20110238883 | INFORMATION PROCESSING DEVICE - An information processing device is provided, in which a bit operation is performed without degradation in performance of a bus. An information processing device includes a CPU which fetches and executes an instruction, and a peripheral module which includes internally a register rewritable by the CPU, and is coupled to the CPU via a bus. The CPU has a function of issuing a bus command for commanding a bitwise write operation to the register comprised in the peripheral module, in order to execute a bit operation command fetched. When the bus command is issued, the peripheral module executes a bitwise write operation for the register. Since the CPU does not need to lock the bus after the bus command is issued, a bit operation can be performed without degradation in performance of the bus. | 2011-09-29 |
| 20110238884 | Memory Controller for Setting Page Length and Memory Cell Density for Semiconductor Memory - A memory controller including a type determining module and a page determining module. The type determining module is configured to determine a type of memory to which the memory controller is connected, wherein the memory includes a memory block comprising a plurality of pages, and each page includes a plurality of memory cells. The page configure module is configured to generate a memory map based on the determined type of the memory. The memory map specifies, for each page, (i) a number of memory cells for storing data, and (ii) a number of memory cells for storing overhead. The number of memory cells for storing data and the number of memory cells for storing overhead in a first page is configurable to be different from the number of memory cells for storing data and the number of memory cells for storing overhead in a second page. | 2011-09-29 |
| 20110238885 | STORAGE SUBSYSTEM - Processing in accordance with the updating of data is carried out distributively by a control unit that controls a cache memory and by a memory controller that controls a nonvolatile semiconductor memory. When updating flash memory data, a main processor creates an XOR write command and transfers the same to a flash memory controller, a microprocessor of the flash memory controller parses the XOR write command, reads out an old parity from a page of a user area in the flash memory, creates a new parity by carrying out an exclusive OR operation using the read-out old parity, “b” data, which is the old data, and “d” data, which is the new data, and stores the created new parity in a page of a renewal area in a flash memory for storing parity. | 2011-09-29 |
| 20110238886 | GARBAGE COLLECTION SCHEMES FOR INDEX BLOCK - Systems and methods are provided for handling uncorrectable errors that may occur during garbage collection of an index page or block in non-volatile memory. | 2011-09-29 |
| 20110238887 | HYBRID-DEVICE STORAGE BASED ON ENVIRONMENTAL STATE - A hybrid storage device that includes a hard-disk drive (HDD) and a flash memory is described. When control logic in the hybrid storage device receives a request from an external device to write a block of data to a logical address in a first portion of an address space that maps to the HDD, the control logic writes the block of data to the HDD. However, if there is a change in environmental state information of the hybrid storage device during the write operation, the control logic writes at least a portion of the block of data to a logical address for the block of data in a second portion of the address space which maps to the flash memory. Note that the address space may be common to the external device and the hybrid storage device. | 2011-09-29 |
| 20110238888 | PROVIDING VERSIONING IN A STORAGE DEVICE - Provided are a computer program product, system and method for managing Input/Output (I/O) requests to a storage device. A write request is received having write data for a logical address in the storage device. A determination is made as to whether preserve mode is enabled. A first entry is located in a volume control table for the logical address indicating a version number of the data in the storage device for the logical address and a first physical location in the storage device having the data for the logical address. The write data is written to a second physical location in the storage device. A second entry is added to the volume control table for the logical address to write in response to determining that the preserve mode is enabled. In response to determining that the preserve mode is enabled, the volume control table is updated to have one of the first and second entry for the logical address point to the second physical location and have the version number indicate a current version and to have the first or second entry not indicating the current version to indicate the first physical location and the version number indicate a previous version. | 2011-09-29 |
| 20110238889 | SEMICONDUCTOR MEMORY DEVICE FROM WHICH DATA CAN BE READ AT LOW POWER - According to one embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array is composed of a plurality of memory cells arranged in a matrix pattern. The control circuit sets a first flag data in a second memory cell in order to write data to a plurality of first memory cells of memory cell array, the second memory cell having been selected at the same time as the first memory cells, determines whether the first flag data is set in the second memory cell before data is read from the first memory cells, and reads no data from the first memory cells and outputs data of first logic level if the first flag data is not set in the second memory cell, and reads data from the first memory cells if the first flag data is set in the second memory cell. | 2011-09-29 |
| 20110238890 | MEMORY CONTROLLER, MEMORY SYSTEM, PERSONAL COMPUTER, AND METHOD OF CONTROLLING MEMORY SYSTEM - According to one embodiment, a memory controller that performs control of a nonvolatile semiconductor memory includes a first management table that stores correspondence between logical block addresses and physical block addresses, a second management table that stores a number of times of data writing for each of the logical block addresses, and a third management table that stores a number of times of data erasing for each of the physical block addresses. The memory controller according to the embodiment includes a writing control unit that selects a spare block not associated with the logical block address and writes data in the spare block. The writing control unit levels, based on the number of times of data writing associated with the logical block addresses and the number of times of data erasing associated with the physical block addresses, numbers of times of data erasing among the blocks. | 2011-09-29 |
| 20110238891 | METHOD FOR SUPPRESSING ERRORS, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF - A method for suppressing errors is provided. The method is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: according to an address of data to be written into or read from the Flash memory, determining whether to utilize an original seed as an input seed of a randomizer/derandomizer, where the randomizer/derandomizer is arranged to generate a random function according to the input seed, with the random function being utilized for adjusting a plurality of bits of the data bit by bit, and with regard to at least each block of the blocks, a value of the original seed remains unvaried; and when it is determined that the original seed should not be utilized as the input seed, generating the random function according to a new seed to adjust the data. | 2011-09-29 |
| 20110238892 | WEAR LEVELING METHOD OF NON-VOLATILE MEMORY - A method of wear leveling applied to a non-volatile memory is provided. The method comprises steps of: categorizing all blocks within the non-volatile memory to a first group with erased blocks having higher history numbers, a second group with erased blocks having lower history numbers, or a third group with blocks not either assigned to the first group or the second group; selecting a first block which contains a clod data from the third group; selecting a second block from the first group; copying the cold data from the first block into the second block and updating the history number of the second block; and erasing the first block. | 2011-09-29 |
| 20110238893 | FLASH BASED MEMORY COMPRISING A FLASH TRANSLATION LAYER AND METHOD FOR STORING A FILE THEREIN - A Flash based memory comprising a Flash translation layer which comprises first translation information associating a first logical address of a logical file system emulating a sectored storage medium, the logical address being a logical sector start address with a first physical address of said flash based memory. The logical file system comprises a number of logical stuffing bits expanding a logical size of data of a file stored in said Flash based memory such that the expanded logical size corresponds to an integer number of logical sectors and the Flash translation layer comprises second translation information associating a second logical address with a second physical address and depending on said number of logical stuffing bits, the file being stored in a contiguous physical address sequence starting at the first physical address and ending at the second physical address. | 2011-09-29 |
| 20110238894 | Non-Volatile Memory Devices and Control and Operation Thereof - An improved non-volatile erase block memory device apparatus and method is described that incorporates an improved addressing scheme to provide for extended addressing allowing redundant erase blocks that are not utilized to repair general use erase blocks of the main memory array to be accessed and utilized as additional storage space by an end user. The additional storage space formed by the unused redundant erase blocks and the specified storage space of the main memory array is presented to the end user as a single contiguous address space. Additionally, the redundant erase blocks can be utilized to repair any damaged erase block in the memory array of the non-volatile erase block memory or Flash memory device regardless of bank placement. | 2011-09-29 |
| 20110238895 | NONVOLATILE MEMORY CONTROLLER AND NONVOLATILE STORAGE DEVICE - A flash memory unit includes a plurality of physical blocks including a plurality of memory cells and serving as erase units of data, each of the memory cells is capable of recording information of 1 bit or more, degradation in the characteristics of the memory cells differs according to the amount of information that is recorded, a controller includes a control unit for controlling the reading, writing and erasure of data to and from the flash memory unit, and a degradation level table for recording a degradation level of the memory cells in physical block units, and the control unit stores, in the degradation level table, the degradation level of the memory cells according to the amount of information stored in the memory cells for each cycle of data erasure from the physical blocks. | 2011-09-29 |
| 20110238896 | DATA-PROCESSING METHOD, PROGRAM, AND SYSTEM - A data-processing method in a flash memory with a plurality of sectors, the method includes arranging first data which is not updated in a first sector at a leading portion of a second sector and adding a first identifier of the first data to the second sector by a memory control circuit when transferring data in the first sector to the second sector, the plurality of sectors including the first sector and the second sector. | 2011-09-29 |
| 20110238897 | MEMORY SYSTEM, PERSONAL COMPUTER, AND METHOD OF CONTROLLING THE MEMORY SYSTEM - According to one embodiment, a memory system includes: a nonvolatile semiconductor memory including a plurality of normal blocks and at least one dummy block, each of the normal blocks being a unit of data erasing; a writing control unit that rewrites the dummy block the number of times equal to or larger than a maximum number of times among the numbers of times of rewriting of the normal blocks; a monitor unit that monitors a data erasing time or a data writing time of the dummy block; and a wear-leveling control unit that averages the numbers of times of rewriting of the normal blocks. The memory system determines, based on a monitor result of the monitor unit, possibility of continuation of the rewriting of the normal blocks. | 2011-09-29 |
| 20110238898 | NONVOLATILE MEMORY CONTROLLER AND NONVOLATILE STORAGE DEVICE - A controller includes a control unit for controlling writing and/or reading of data to and from physical block based on a logical address from a host device, a logical defective cluster table for storing information concerning a logical address of a logical defective cluster which is one or more partial areas within the effective logical address range and an address conversion table for storing corresponding information of a logical address of the effective logical address range and a physical address of the physical block on the data stored in the physical block. Upon receiving a data write command from the host device for writing data to the logical address stored in the logical defective cluster table, the control unit disables the reflection of writing of data for the logical address to the physical block. | 2011-09-29 |
| 20110238899 | MEMORY SYSTEM, METHOD OF CONTROLLING MEMORY SYSTEM, AND INFORMATION PROCESSING APPARATUS - A WC resource usage is compared with an auto flush (AU) threshold Caf that is smaller than an upper limit Clmt, and when the WC resource usage exceeds the AF threshold Caf, the organizing state of a NAND memory | 2011-09-29 |
| 20110238900 | Method of managing a solid state drive, associated systems and implementations - In one embodiment, the method includes storing, by a status checking module, status information for a solid state drive, and determining a status state of the solid state drive based on the status information. The status state is one of a good state, an intermediate state and a bad state, and the intermediate state is a state between the good state and the bad state. | 2011-09-29 |
| 20110238901 | INFORMATION PROCESSING APPARATUS CAPABLE OF ENABLING SELECTION OF USER DATA ERASE METHOD, DATA PROCESSING METHOD, AND STORAGE MEDIUM - A mechanism which makes it possible to automatically and appropriately select an erase method of erasing user data in a shorter time such that the user data can by no means be reproduced, according to the type of a connected nonvolatile storage device. An information processing apparatus determines an erase method of erasing an erase area of the nonvolatile storage device according to a management table generated based on attribute information acquired from the nonvolatile storage device. Then, the image forming apparatus erases information stored in the erase area according to the determined erase method. | 2011-09-29 |
| 20110238902 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD - A nonvolatile semiconductor memory device in which a memory cell life can be prolonged while making it possible to perform writing in units of bits. When command information represents writing, a comparing unit | 2011-09-29 |
| 20110238903 | METHOD AND DEVICE OF MANAGING A REDUCED WEAR MEMORY - A method of encoding and storing data. The method comprises providing digital data designated to be written in at least one memory element having a plurality of memory cells, encoding digital data so as to increase the prevalence of at least one memory cell state in relation to the prevalence of at least one other memory cell state by conditionally inverting the data bits in accordance with the count of a particular state in the data to be written, and programming the plurality of memory cells to store the encoded digital data. | 2011-09-29 |
| 20110238904 | ALIGNMENT OF INSTRUCTIONS AND REPLIES ACROSS MULTIPLE DEVICES IN A CASCADED SYSTEM, USING BUFFERS OF PROGRAMMABLE DEPTHS - Buffers of programmable depths are used in the instruction and reply paths of cascaded devices to account for possible differences in latencies between the devices. The buffers may be enabled or bypassed such that the alignment of instruction and result may be performed at the boundaries between separate groups of devices having different instruction latencies. | 2011-09-29 |
| 20110238905 | PRIMARY STORAGE MEDIA WITH ASSOCIATED SECONDARY STORAGE MEDIA FOR EFFICIENT DATA MANAGEMENT - A system according to one embodiment includes a tape cartridge, the tape cartridge comprising: a housing; a magnetic recording tape in the housing; and a non-tape nonvolatile memory coupled to the housing, the nonvolatile memory being for storing therein an index comprising file system information for a plurality of files stored on the magnetic recording tape. A method for storing data on a tape cartridge according to one embodiment includes writing a plurality of files to a magnetic recording tape of a tape cartridge; and writing an index to a non-tape nonvolatile memory of the tape cartridge, the index including information about locations of data of the plurality of files on the magnetic recording tape. | 2011-09-29 |
| 20110238906 | FILE INDEX, METADATA STORAGE, AND FILE SYSTEM MANAGEMENT FOR MAGNETIC TAPE - In one embodiment, a method includes loading a tape cartridge into at least one tape drive installed in an automated tape library, where a tape of the tape cartridge has at least two partitions; writing plurality of data blocks on a first of the partitions; and writing an index on a second of the partitions, wherein the index includes information about at least one of files and the blocks on the first partition | 2011-09-29 |
| 20110238907 | WAKE-AHEAD BASED ON PATTERNS - A method may include detecting an event, determining whether the event correlates to a hard disk access, requesting a wake-ahead of a hard disk drive if it is determined that the event correlates to a hard disk access, weighing a performance improvement of the hard disk drive if the wake ahead request is granted against a life of the hard disk drive if the wake ahead request is not granted, and waking ahead the hard disk drive if the performance improvement outweighs the life of the hard disk drive. | 2011-09-29 |
| 20110238908 | DISC DEVICE - In a disc device according to the present invention, when a controller | 2011-09-29 |
| 20110238909 | Multicasting Write Requests To Multiple Storage Controllers - In one embodiment, the present invention includes a method for performing multicasting, including receiving a write request including write data and an address from a first server in a first canister, determining if the address is within a multicast region of a first system memory, and if so, sending the write request directly to the multicast region to store the write data and also to a mirror port of a second canister coupled to the first canister to mirror the write data to a second system memory of the second canister. Other embodiments are described and claimed. | 2011-09-29 |
| 20110238910 | DATA STORAGE SYSTEM AND SYNCHRONIZING METHOD FOR CONSISTENCY THEREOF - The invention discloses a data storage system and a synchronizing method for consistency thereof, especially for the data storage system specified in RAID 5 architecture. The data storage system according to the invention includes N storage devices, where N is an integer equal to or larger than 3. The synchronizing method according to the invention performs writing commands for the designated storage device among the N storage devices, and reading commands for the other (N−1) storage devices, to reduce synchronization time of the data storage system. | 2011-09-29 |
| 20110238911 | METHOD OF CONTROLLING OPTICAL DISC DRIVE ARCHIVE SYSTEM - A method of controlling an ODD archive system comprising three or more ODDs is provided comprising storing information on a parity drive in a memory, and setting a parity drive in which parity data is to be recorded based on the information when data recording is requested in a RAID 3 or 4 manner. The information on the parity drive may include a cumulative value of number of times by which each ODD has been set as the parity drive up to now. Or the information on the parity drive may be managed for each of one or more magazine having optical discs the number of which is equal to or less than the number of ODDs included in the archive system. | 2011-09-29 |
| 20110238912 | FLEXIBLE DATA STORAGE SYSTEM - Methods and systems for managing and locating available storage space in a system comprising data files stored in a plurality of storage devices and configured in accordance with various data storage schemes (mirroring, striping and parity-striping). A mapping table associated with each of the plurality of storage devices is used to determine the available locations and amount of available space in the storage devices. The data storage schemes for one or more of the stored data files are changed to a basic storage mode when the size of a new data file configured in accordance with an assigned data storage scheme exceeds the amount of available space. The configured new data file is stored in accordance with the assigned data storage scheme in one or more of the available locations and the locations of the new data file are recorded. | 2011-09-29 |
| 20110238913 | DISK ARRAY CONTROL DEVICE AND STORAGE DEVICE - According to one embodiment, a disk array control device manages a plurality of drives as a single logical drive. The disk array control device includes a first register configured to store a to-be-accessed drive number which is designated by a host, and a control module. The control module is configured to receive a command from the host, determine whether the received command is a predetermined command which is used for maintenance of each of the drives, and execute, in a case where the received command is the predetermined command, a pass-through process of sending the received command to the drive which is designated by the to-be-accessed drive number in the first register. | 2011-09-29 |
| 20110238914 | STORAGE APPARATUS AND DATA PROCESSING METHOD FOR THE SAME - The present invention aims for efficient use of storage capacity in a storage system by reducing the amount of time taken for processing including removing redundancy and data compression executed with respect to transferred data. | 2011-09-29 |
| 20110238915 | STORAGE SYSTEM - A switch device includes interfaces connected to a host, a first storage device, and a second storage device having a cache memory, and a processor executing receiving a copy command indicating to copy target data stored in the first storage device to the second storage device from the host, transmitting a reading out command indicating to read out the target data stored in the first storage device corresponding to the copy command, receiving the target data corresponding to the transmitted reading out command from the first storage device, and transmitting, to the second storage device, a writing command for writing the target data and release information indicating that the target data is releasable from the cache memory. | 2011-09-29 |
| 20110238916 | REPRESENTING A TREE STRUCTURE ON A FLAT STRUCTURE - An apparatus and a method for accessing data at a server node of a data grid system with distributed cache is described. The server receives a request to access a logical tree structure of a cache nodes at a tree structure interface module of the server. The tree structure interface operates on a flat map structure of the cache nodes corresponding to the logical tree structure, transparent to the request. Each cache node is defined and operated on using a two-dimensional coordinate including a fully qualified name and a type. | 2011-09-29 |
| 20110238917 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions, Further, the cache control unit is also configured to examine instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information, to create a plurality of tracks based on the extracted instruction information; and to fill the at least one or more instructions based on one or more tracks from the plurality of instruction tracks, | 2011-09-29 |
| 20110238918 | CACHE WRITE INTEGRITY LOGGING - An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver. In an embodiment, a non-volatile cache may be implemented by creating a device option read only memory (ROM), or modifying the associated computer basic input-output system (BIOS) to trap software interrupts associated with disk and other media access requests. Associated addresses, such as logical block addresses, can be stored in a log for data that is modified. The resulting log can be stored in a non-volatile medium, including the cache itself. If the available log space is not large enough to record all write activity prior to loading operating system drivers, a flag may be set to indicate the overrun condition. | 2011-09-29 |
| 20110238919 | CONTROL OF PROCESSOR CACHE MEMORY OCCUPANCY - Techniques are described for controlling processor cache memory within a processor system. Cache occupancy values for each of a plurality of entities executing the processor system can be calculated. A cache replacement algorithm uses the cache occupancy values when making subsequent cache line replacement decisions. In some variations, entities can have occupancy profiles specifying a maximum cache quota and/or a minimum cache quota which can be adjusted to achieve desired performance criteria. Related methods, systems, and articles are also described. | 2011-09-29 |
| 20110238920 | BOUNDING BOX PREFETCHER WITH REDUCED WARM-UP PENALTY ON MEMORY BLOCK CROSSINGS - A microprocessor includes a cache memory and a data prefetcher. The data prefetcher detects a pattern of memory accesses within a first memory block and prefetch into the cache memory cache lines from the first memory block based on the pattern. The data prefetcher also observes a new memory access request to a second memory block. The data prefetcher also determines that the first memory block is virtually adjacent to the second memory block and that the pattern, when continued from the first memory block to the second memory block, predicts an access to a cache line implicated by the new request within the second memory block. The data prefetcher also responsively prefetches into the cache memory cache lines from the second memory block based on the pattern. | 2011-09-29 |
| 20110238921 | ANTICIPATORY RESPONSE PRE-CACHING - Interaction between a client and a service in which the service responds to requests from the client. In addition to responding to specific client requests, the service also anticipates or speculates about what the client may request in the future. Rather than await the client request (that may or may not ultimately be made), the service provides the unrequested anticipatory data to the client in the same data stream as the response data that actual responds to the specific client requests. The client may then use the anticipatory data to fully or partially respond to future requests from the client, if the client does make the request anticipated by the service. Thus, in some cases, latency may be reduced when responding to requests in which anticipatory data has already been provided. The service may give priority to the actual requested data, and gives secondary priority to the anticipatory data. | 2011-09-29 |
| 20110238922 | BOUNDING BOX PREFETCHER - A data prefetcher in a microprocessor having a cache memory receives memory accesses each to an address within a memory block. The access addresses are non-monotonically increasing or decreasing as a function of time. As the accesses are received, the prefetcher maintains a largest address and a smallest address of the accesses and counts of changes to the largest and smallest addresses and maintains a history of recently accessed cache lines implicated by the access addresses within the memory block. The prefetcher also determines a predominant access direction based on the counts and determines a predominant access pattern based on the history. The prefetcher also prefetches into the cache memory, in the predominant access direction according to the predominant access pattern, cache lines of the memory block which the history indicates have not been recently accessed. | 2011-09-29 |
| 20110238923 | COMBINED L2 CACHE AND L1D CACHE PREFETCHER - A microprocessor includes a first-level cache memory, a second-level cache memory, and a data prefetcher that detects a predominant direction and pattern of recent memory accesses presented to the second-level cache memory and prefetches cache lines into the second-level cache memory based on the predominant direction and pattern. The data prefetcher also receives from the first-level cache memory an address of a memory access received by the first-level cache memory, wherein the address implicates a cache line. The data prefetcher also determines one or more cache lines indicated by the pattern beyond the implicated cache line in the predominant direction. The data prefetcher also causes the one or more cache lines to be prefetched into the first-level cache memory. | 2011-09-29 |
| 20110238924 | WEBPAGE REQUEST HANDLING - A method, computer program product, and system for webpage request handling is described. A method may comprise recording, in a memory, a change time for each of a plurality of elements of a website available from an origin server, each time a change to any one of the plurality of elements occurs. The method may further comprise updating a system-last-modified time of the website to a latest change time. | 2011-09-29 |
| 20110238925 | CACHE CONTROLLER AND METHOD OF OPERATION - In one embodiment, there are described a sectored cache system and method of operation. A cache data block comprises separately updatable cache sectors. A common tag block contains metadata for the cache sectors of the data block and is writable as a whole. A pending allocation table (PAT) contains data representing pending writes to the tag block. When writing changes data to the tag block, the changed data is broadcast to the PAT to update data representing other pending writes to the tag block so that when the other pending writes are written to the tag block changed data from received broadcasts is included. | 2011-09-29 |
| 20110238926 | Method And Apparatus For Supporting Scalable Coherence On Many-Core Products Through Restricted Exposure - In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed. | 2011-09-29 |
| 20110238927 | CONTENTS DISTRIBUTION DEVICE , CONTENTS DISTRIBUTION CONTROL METHOD, CONTENTS DISTRIBUTION CONTROL PROGRAM AND CACHE CONTROL DEVICE - Solved is a problem that use efficiency of a memory cache is low because in contents distribution using a memory cache whose capacity is limited, even when only a part of contents is accessed, the entire contents will be stored in the memory cache. | 2011-09-29 |
| 20110238928 | MEMORY SYSTEM - According to one embodiment, a memory system includes a memory that includes a plurality of parallel operation elements, each of which stores therein write data from a host device and on each of which read/write is individually performed, a control unit that performs the read/write to the parallel operation elements simultaneously, and a required-performance measuring unit that measures a required performance from the host device are included. The control unit changes the number of simultaneous executions of the read/write of the parallel operation elements based on the required performance measured by the required-performance measuring unit. | 2011-09-29 |
| 20110238929 | LIBRARY APPAPRATUS AND METHOD FOR CONTROLLING THE SAME - A library apparatus includes a medium name storage unit that stores medium name conversion information in which a virtual medium name specifying a storage medium in a read/write request from a host is related to a real medium name specifying the storage medium in the library apparatus, a conveying mechanism unit that conveys the storage medium, a drive that reads/writes data from/to the storage medium conveyed by the conveying mechanism unit in response to the received read/write request, a conversion unit that converts the virtual medium name included in the received read/write request to the real medium name on the basis of the medium name conversion information stored in the medium name storage unit, and a conveying mechanism control unit that controls the conveying mechanism unit to convey the storage medium having the real medium name converted by the conversion unit to the drive. | 2011-09-29 |
| 20110238930 | TRANSMISSION APPARATUS AND CONTROL DATA PROCESSING METHOD AND PROGRAM - A transmission apparatus includes a memory and a circuit. The memory store control data included in a frame received from outside the apparatus and state information indicating a state of the control data in the transmission apparatus in association with each other. The circuit records the control data included in the frame to the memory. The circuit changes the state information to information indicating that the recording of the control data is completed. The circuit determines whether or not the control data stored in the memory is to be rewritten. The circuit rewrites the control data stored in the memory, upon determining that the control data is rewritten. The circuit changes the state information to information indicating that the rewriting of the control data is completed. The circuit reads the control data stored in the memory. | 2011-09-29 |
| 20110238931 | MEMORY DEVICE, MEMORY SYSTEM AND MICROCONTROLLER INCLUDING MEMORY DEVICE, AND MEMORY CONTROL DEVICE - A memory device includes: a plurality of word lines and bit lines specifying addresses to be accessed; and a plurality of memory cells of consecutive addresses arranged to correspond to each of the word lines. The plurality of memory cells of the consecutive addresses are accessible in parallel by the plurality of bit lines each corresponding to one of the memory cells. Among the plurality of word lines, a first word line and a second word line that specifies an address next to that of the first word line have an overlapping address range, and a first memory cell connected to the first word line and a second memory cell connected to the second word line are assigned in dual fashion to a same address. | 2011-09-29 |
| 20110238932 | CONTROLLER AND METHOD FOR OPERATING A CONTROLLER, COMPUTER PROGRAM, COMPUTER PROGRAM PRODUCT - In a controller, a method for operating a controller, a computer program, and a computer program product, data are saved in a memory, a setpoint is defined, an actual value is identified, the actual value is compared with the setpoint, and the data is saved as a function of the comparison result. | 2011-09-29 |
| 20110238933 | MEMORY DEVICE AND CONTROLLING METHOD OF THE SAME - A memory device includes a memory which has memory areas, and a controller has a first mode and a second mode. Upon receipt of write data, the controller writes data in the memory areas while managing correspondence between logical addresses of write data and memory areas which store corresponding write data. A plurality of the memory areas constitutes a management unit. The controller in the first mode is able to write pieces of data in respective memory areas and configured to maintain data in memory areas in one management unit which contains data to be updated. The controller in the second mode writes pieces of data in respective memory areas in the ascending order of logical addresses of the pieces of data and invalidates data in memory areas in one management unit which contains updated data. | 2011-09-29 |
| 20110238934 | ASYNCHRONOUSLY SCHEDULING MEMORY ACCESS REQUESTS - A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The scheduler is operated using a clock signal with a frequency different from the frequency of the clock signal used to operate the memory controller. The clock signal used to clock the scheduler can have a lower frequency than the clock used by a memory controller. As a result, the scheduler is able to consider a greater number of pending memory access requests when selecting the next pending memory access request to be submitted to the memory for servicing and thus the resulting sequence of selected memory access requests is more likely to be optimized for memory access throughput. | 2011-09-29 |
| 20110238935 | Systems and/or methods for distributed data archiving - Certain example embodiments of this invention relate to system and/or methods that pair a data extractor with a data accumulator, wherein these components may be located on any one or more computers in a network system. This distributed peer extract-accumulate approach is advantageous in that it reduces (and sometimes completely eliminates) the need for a “funnel” approach to data archiving, wherein all data is moved or backed up through a central computer or central computer system. In certain example embodiments, recall-accumulate, search, verify, and/or other archive-related activities may be performed in a similar peer-based and/or distributed manner. Certain example embodiments may in addition or in the alternative incorporate techniques for verifying the integrity of data in an archive system, and/or techniques for restoring/importing data from a non-consumable form. | 2011-09-29 |
| 20110238936 | METHOD AND SYSTEM FOR EFFICIENT SNAPSHOTTING OF DATA-OBJECTS - One embodiment of the present invention is directed to a multi-node data-storage system, including a number of component-data-storage-system nodes, which stores data objects, each data object stored as a mirrored portion and an additional portion and a snapshot-operation-triggering mechanism that invokes a snapshot operation on a data object in which mirrored data stored in the mirrored portion of the data object is transformed into data stored in non-mirroring redundant data storage associated with a next snapshot level within the additional portion of the data object. An additional embodiment of the present invention is directed to a multi-node data-storage system in which a snapshot-operation-triggering mechanism automatically invokes a snapshot operation on a data object. | 2011-09-29 |
| 20110238937 | STORAGE APPARATUS AND SNAPSHOT CONTROL METHOD OF THE SAME - [Problem] Providing a storage apparatus and a snapshot control method for the same for preventing, even after long-term operation of snapshots as a means for backup, an increase in the amount of pre-update data retained in a differential volume. | 2011-09-29 |
| 20110238938 | EFFICIENT MIRRORING OF DATA ACROSS STORAGE CONTROLLERS - A method includes multicasting an Input/Output (I/O) data associated with a host computing device through a multicast device associated with a storage controller coupled to another storage controller in a redundant configuration, and minoring, through the multicasting, the I/O data across the storage controller and the another storage controller through a bus utilized to couple the storage controller and the another storage controller. The method also includes transmitting an early write status message to the host computing device following the minoring of the I/O data across the storage controller and the another storage controller. The early write status message is associated with a successful completion of the mirroring of the I/O data across the storage controller and the another storage controller prior to the I/O data being written to a storage device associated therewith. | 2011-09-29 |
| 20110238939 | MEMORY DEVICES WITH DATA PROTECTION - A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit. | 2011-09-29 |
| 20110238940 | OPERATION PROCESSING DEVICE AND METHOD OF DETECTING MEMORY LEAK - A memory leak detecting method includes: producing an object which occupies an area on a first area of the memory; checking a presence of a pointer which points at the object separately so as to remove the object and to repeatedly carry out a process for counting up a counter value of the object separately upon the pointer not being present and being present; moving the area occupied by the object from the area on the first area of the memory to an area on the second area of the memory upon the counter value exceeding a first threshold; and moving the area occupied by the object from the area on the second area to the area on the first area and clearing the counter value of the object upon the object occupying the area on the second area being run. | 2011-09-29 |
| 20110238941 | SCHEDULING MEMORY ACCESS REQUESTS USING PREDICTED MEMORY TIMING AND STATE INFORMATION - A data processing system employs an improved arbitration process in selecting pending memory access requests received from the one or more processor cores for servicing by the memory. The arbitration process uses memory timing and state information pertaining both to memory access requests already submitted to the memory for servicing and to the pending memory access requests which have not yet been selected for servicing by the memory. The memory timing and state information may be predicted memory timing and state information; that is, the component of the data processing system that implements the improved scheduling algorithm may not be able to determine the exact point in time at which a memory controller initiates a memory access for a corresponding memory access request and thus the component maintains information that estimates or otherwise predicts the particular state of the memory at any given time. | 2011-09-29 |
| 20110238942 | SYSTEM AND METHOD FOR ROBUST AND EFFICIENT FREE CHAIN MANAGEMENT - Disclosed herein are systems, methods, and non-transitory computer-readable storage media for managing free chains of compute resources. A system configured to practice the method divides a free chain of compute resources into a usable part (UP) which contains resources available for immediate allocation and an unusable part (UUP) which contains resources not available for immediate allocation but which become available after a certain minimum number of allocations. The system sorts resources in the UP by block number, and maintains a last used object (LUO) vector, indexed by block number, which records a last object in the UP for each block. Each time the system frees a resource, the system adds the freed resource to a tail of the UUP and promotes an oldest resource in the UUP to the UP. This approach can manage free chains in a manner that is both flaw tolerant and has relatively high performance. | 2011-09-29 |
| 20110238943 | MODELING MEMORY COMPRESSION - A method, system, and computer usable program product for modeling memory compression are provided in the illustrative embodiments. A subset of candidate pages is received. The subset of candidate pages is a subset of a set of candidate pages used in executing a workload in a data processing system. A candidate page is compressible uncompressed data in a memory associated with the data processing system. The subset of candidate pages is compressed in a scratch space. A compressibility of the workload is computed based on the compression of the subset of candidate pages. Page reference information of the subset of candidate pages is received. A memory reference rate of the workload is determined. A recommendation is presented about a memory compression model for the workload in the data processing system. | 2011-09-29 |
| 20110238944 | DETERMINISTIC MEMORY MANAGEMENT IN A COMPUTING ENVIRONMENT - Systems and methods for memory management in a computing environment are provided. The method comprises monitoring instantiation of objects during a web session established between a client applet and a server over the world wide web, wherein the client applet submits requests to the server and one or more objects are instantiated by a servlet application running on the server to service the submitted requests, wherein server memory space is allocated to said one or more objects instantiated by the servlet; determining execution scope of a first object instantiated by a servlet, in response to the server receiving a request from the client applet, wherein the execution scope of the first object is determined according to a context in which the first object is instantiated. | 2011-09-29 |
| 20110238945 | APPARATUS AND METHOD FOR GENERATING CODE OVERLAY - Provided is an apparatus and method for generating code overlay capable of minimizing the number of memory copies. A static temporal relationship graph (STRG) is generated in which each of functions of a program corresponds to a node of the STRG and a conflict miss value corresponds to an edge of the STRG. The conflict miss value is the maximum number of possible conflict misses between functions. Overlay is generated by selecting at least one function from the STRG, calculating an allocation cost for each region of a memory to be given when the at least one selected function is allocated, and allocating the at least one selected function to a region that has the smallest allocation cost. | 2011-09-29 |
| 20110238946 | Data Reorganization through Hardware-Supported Intermediate Addresses - A virtual address scheme for improving performance and efficiency of memory accesses of sparsely-stored data items in a cached memory system is disclosed. In a preferred embodiment of the present invention, a special address translation unit is used to translate sets of non-contiguous addresses in real memory into contiguous blocks of addresses in an “intermediate address space.” This intermediate address space is a fictitious or “virtual” address space, but is distinguishable from the virtual address space visible to application programs, and in user-level memory operations, effective addresses seen/manipulated by application programs are translated into intermediate addresses by an additional address translation unit for memory caching purposes. This scheme allows non-contiguous data items in memory to be assembled into contiguous cache lines for more efficient caching/access (due to the perceived spatial proximity of the data from the perspective of the processor). | 2011-09-29 |
| 20110238947 | Memory management apparatus, memory management method and non-transitory computer readable storage medium - A memory management apparatus has an ASID conversion table, an actual ASID use table, and a TLB flush control section. The ASID conversion table and the actual ASID use table manage virtual ASID, actual ASID and an overlap flag so that they are related for each VM. The TLB flush control section reads actual ASIDs allocated to VM as a switching target at the time of switching VM as a switching source into the VM as the switching target, determines whether the read actual ASID is allocated to the plurality of VMs in an overlapped manner with reference to the overlap flag, and sets the actual ASID in the read actual ASIDs determined being allocated in the overlapped manner as a target for the TLB flush. | 2011-09-29 |
| 20110238948 | METHOD AND DEVICE FOR COUPLING A DATA PROCESSING UNIT AND A DATA PROCESSING ARRAY - The present invention relates to a method of coupling at least one (conventional) unit processing data in a sequential manner, e.g. a CPU, von-Neumann-Processor and/or microcontroller, the (conventional) unit for data processing comprising an instruction pipeline, and an array for processing data comprising a plurality of data processing cells, e.g. a preferably coarse grain and/or preferably runtime reconfigurable data processor, FPGA, DFP, DSP, XPP or chaemeleon-technology-like data processing fabric, wherein the array is coupled to the instruction pipeline. | 2011-09-29 |
| 20110238949 | Distributed Administration Of A Lock For An Operational Group Of Compute Nodes In A Hierarchical Tree Structured Network - Distributed administration of a lock for an operational group of compute nodes in a hierarchical tree structured network including assigning the root node of the operational group to send acknowledgments for lock requests, the root lock administration module comprising a module of automated computing machinery; receiving a lock request assigned to a particular node from a child node; determining whether another request from another child is directly ahead in an acknowledgement queue; if a request from another child is directly ahead in the acknowledgement queue, putting the lock request for the particular node in the acknowledgement queue until the lock request directly ahead in the acknowledgement queue is satisfied and when the lock request ahead in the queue is satisfied, sending the particular node for whom the lock request is assigned a message acknowledging the particular node has the lock; and if a request from another child is not directly ahead in a queue, sending to the particular node for whom the lock request is assigned a message acknowledging that the particular node has the lock. | 2011-09-29 |
| 20110238950 | Performing A Scatterv Operation On A Hierarchical Tree Network Optimized For Collective Operations - Performing a scattery operation on a hierarchical tree network optimized for collective operations including receiving, by the scattery module installed on the node, from a nearest neighbor parent above the node a chunk of data having at least a portion of data for the node; maintaining, by the scattery module installed on the node, the portion of the data for the node; determining, by the scattery module installed on the node, whether any portions of the data are for a particular nearest neighbor child below the node or one or more other nodes below the particular nearest neighbor child; and sending, by the scattery module installed on the node, those portions of data to the nearest neighbor child if any portions of the data are for a particular nearest neighbor child below the node or one or more other nodes below the particular nearest neighbor child. | 2011-09-29 |
| 20110238951 | IMAGE FORMING APPARATUS, IMAGE FORMING SYSTEM, AND INFORMATION GENERATING METHOD - An image forming apparatus includes:
| 2011-09-29 |
| 20110238952 | INSTRUCTION FETCH APPARATUS, PROCESSOR AND PROGRAM COUNTER ADDITION CONTROL METHOD - An instruction fetch apparatus is disclosed which includes: a program counter configured to manage the address of an instruction targeted to be executed in a program in which instructions belonging to a plurality of instruction sequences are placed sequentially; a change designation register configured to designate a change of an increment value on the program counter; an increment value register configured to hold the changed increment value; and an addition control section configured such that if the change designation register designates the change of the increment value on the program counter, then the addition control section increments the program counter based on the changed increment value held in the increment value register, the addition control section further incrementing the program counter by an instruction word length if the change designation register does not designate any change of the increment value on the program counter. | 2011-09-29 |
| 20110238953 | INSTRUCTION FETCH APPARATUS AND PROCESSOR - An instruction fetch apparatus is disclosed which includes: a detection state setting section configured to set the execution state of a program of which an instruction prefetch timing is to be detected; a program execution state generation section configured to generate the current execution state of the program; an instruction prefetch timing detection section configured to detect the instruction prefetch timing in the case of a match between the current execution state of the program and the set execution state thereof upon comparison therebetween; and an instruction prefetch section configured to prefetch the next instruction upon detection of the instruction prefetch timing. | 2011-09-29 |
| 20110238954 | DATA PROCESSING APPARATUS - Source code to be processed is analyzed and configuration data in implementing in accordance with each of plural implementation systems is created and is stored in a local memory of a DRP incorporating system. When execution of target processing is started, the implementation system determination processing calculates estimated processing time when the configuration of each of the implementation systems is adopted and determines the optimum one of the implementation systems based on a combination of the estimated processing time and the circuit scale of the configuration. | 2011-09-29 |
| 20110238955 | METHODS FOR SCALABLY EXPLOITING PARALLELISM IN A PARALLEL PROCESSING SYSTEM - Parallelism in a parallel processing subsystem is exploited in a scalable manner. A problem to be solved can be hierarchically decomposed into at least two levels of sub-problems. Individual threads of program execution are defined to solve the lowest-level sub-problems. The threads are grouped into one or more thread arrays, each of which solves a higher-level sub-problem. The thread arrays are executable by processing cores, each of which can execute at least one thread array at a time. Thread arrays can be grouped into grids of independent thread arrays, which solve still higher-level sub-problems or an entire problem. Thread arrays within a grid, or entire grids, can be distributed across all of the available processing cores as available in a particular system implementation. | 2011-09-29 |
| 20110238956 | Collective Acceleration Unit Tree Structure - A mechanism is provided in a collective acceleration unit for performing a collective operation to distribute or collect data among a plurality of participant nodes. The mechanism receives an input collective packet for a collective operation from a neighbor node within a collective tree. The input collective packet comprises a tree identifier and an input data field and wherein the collective tree comprises a plurality of sub trees. The mechanism maps the tree identifier to an index within the collective acceleration unit. The index identifies a portion of resources within the collective acceleration unit and is associated with a set of neighbor nodes in a given sub tree within the collective tree. For each neighbor node the collective acceleration unit stores destination information. The collective acceleration unit performs an operation on the input data field using the portion of resources to effect the collective operation. | 2011-09-29 |
| 20110238957 | SOFTWARE CONVERSION PROGRAM PRODUCT AND COMPUTER SYSTEM - According to one embodiment, a software conversion program product having a computer readable medium including programmed instructions, wherein the instructions, when executed by a computer system including a host processor and one or more accelerator processors, causes the computer system to perform: analyzing input software and obtaining a compute intensity calculated by dividing the number of arithmetic processing times in a loop by the size of data accessed in the loop and a data reference area size that is a total size of areas where data is referred to; determining a processor that executes loops on the basis of obtained values and a preliminarily prepared win-loss table in which wins and losses of execution times between the host processor and the accelerator processor are defined; and converting the input software so that the determined processor executes the loops. | 2011-09-29 |
| 20110238958 | DATA PROCESSING DEVICE - A data processing device has an instruction decoder, a control logic unit, and ALU. The instruction decoder decodes instruction codes of an arithmetic instruction. The control logic unit detects the effective data width of operation data to be processed according to the decode result from the instruction decoder and determines the number of cycles for the instruction execution corresponding to the effective, data width. The ALU executes the instruction with the number of cycles of the instruction execution determined by the control logic unit. | 2011-09-29 |
| 20110238959 | DISTRIBUTED CONTROLLER, DISTRIBUTED PROCESSING SYSTEM, AND DISTRIBUTED PROCESSING METHOD - A distributed controller is connected to two or more processing elements and controls the two or more processing elements to execute distributed processing. The distributed controller comprises a plurality of control modules, each of which is connected to at least one other control module. The distributed controller determines a processing path between processing elements using at least two of the plurality of control modules. | 2011-09-29 |
| 20110238960 | DISTRIBUTED PROCESSING SYSTEM, CONTROL UNIT, PROCESSING ELEMENT, DISTRIBUTED PROCESSING METHOD AND COMPUTER PROGRAM - A distributed processing system has a control unit and a plurality of processing elements and includes a control line through which control information is sent and received between the control unit and the processing elements, and a data line through which data to be processed is transmitted from at least one selected from the control unit and the processing elements to the processing element connected thereto. The data line is independent from the control line. The processing element has a processing content changing section that changes the content of processing in the processing element using processing content changing information received through the control line when a monitored processing context of the processing element meets a processing content changing condition received through the control line. | 2011-09-29 |
| 20110238961 | SYSTEM AND METHOD OF INSTRUCTION MODIFICATION - A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine language instruction is modified. Information can be substituted into the segment based on specifics outlined in the trigger pattern. Alternatively, information can be combined with the segment via logical and/or arithmetic operations. Modification of the segment produces a second machine language instruction that is executed by units of the processor. In one embodiment, information may be taken from a queue and used to replace data from the segment. How information is taken from the queue and how the information so taken is used to replace fields of the segment are defined by the trigger pattern. | 2011-09-29 |
| 20110238962 | Register Checkpointing for Speculative Modes of Execution in Out-of-Order Processors - A mechanism is provided for generating a checkpoint for a speculatively executed portion of code. The mechanisms identify, during a speculative execution of a portion of code, a register renaming operation occurring to an entry in a register renaming table of the processor. In response to the register renaming operation occurring to the register renaming table, a determination is made as to whether an update to an entry in a hardware-implemented recovery renaming table is to be performed. If so, the entry in the hardware-implemented recovery renaming table is updated. The entry in the recovery renaming table is part of the checkpoint for the speculative execution of the portion of code. | 2011-09-29 |
| 20110238963 | RECONFIGURABLE ARRAY AND METHOD OF CONTROLLING THE RECONFIGURABLE ARRAY - A reconfigurable array is provided. The reconfigurable array includes a Very Long Instruction Word (VLIW) mode and a Coarse-Grained Array (CGA) mode. When the VLIW mode is converted to the CGA mode, instead of sharing a central register file between the VLIW mode and the CGA mode, live data to be used in the CGA mode is copied from the central register file to local register files. | 2011-09-29 |
| 20110238964 | DATA PROCESSOR - The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register. | 2011-09-29 |
| 20110238965 | BRANCH PREDICTION METHOD AND BRANCH PREDICTION CIRCUIT PERFORMING THE METHOD - A branch prediction circuit includes: a memory for storing information representing a branch instruction and a branch prediction; a control circuit for controlling rewriting information in the memory in accordance with a result of determining whether or not a predicted branch has been taken, and determining an attribute of the predicted branch from a branch condition set by the branch instruction and the predicted branch that has been taken, if the predicted branch has been taken; and a rewriting circuit rewriting the information in the memory under the control of the control circuit. | 2011-09-29 |
| 20110238966 | BRANCH PREDICTION METHOD AND BRANCH PREDICTION CIRCUIT FOR EXECUTING THE SAME - A branch prediction method executed in a branch prediction circuit executes the branch instruction, the branch prediction method includes: a branch information storing process for storing the information in the first storage unit or the second storage unit; a process for determining on the basis of a branch condition set by the branch instruction and a realized branch whether the branch prediction is realized; a rewriting process for performing a rewrite of the information in one of the first storage unit and the second storage unit in accordance with the determination and the degree of likelihood that a branch indicated by the branch prediction occurs; and a process for performing branch prediction in response to the branch information when the branch instruction is executed in the processor. | 2011-09-29 |
| 20110238967 | METHOD AND APPARATUS FOR SHARING AN INTEGRITY SECURITY MODULE IN A DUAL-ENVIRONMENT COMPUTING DEVICE - A method and apparatus are disclosed for sharing an integrity security module in a dual-environment computing device. The apparatus include an integrity security module, one or more processors, a detection module and a regeneration module. The one or more processors may have access to the integrity security module and may operate in two distinct operating environments of a dual-environment computing device. The detection module may detect, during an initialization sequence, a power state transition of an operating environment of the dual-environment computing device. The regeneration module may regenerate one or more integrity values from a stored integrity metric log in response to detecting the power state transition of the operating environment of the dual-environment computing device. | 2011-09-29 |
| 20110238968 | FUNCTION PROVIDING APPARATUS AND COMPUTER READABLE MEDIUM - A function providing apparatus includes a first reading unit, a second reading unit, a first initializing unit, a second initializing unit, a first receiving unit, a second receiving unit, and a control unit. The first reading unit reads a first control program relating to a first function provided by a particular device. The second reading unit reads a second control program relating to a second function provided by data processing without using the particular device. The first initializing unit causes the processor to initialize the first control program. The second initializing unit causes the processor to initialize the second control program. The first receiving unit receives a first instruction. The second receiving unit receives a second instruction. The control unit establishes a power saving state in which power is supplied to the memory is continued, and makes a transition from the power saving state to the ordinary state. | 2011-09-29 |
| 20110238969 | INTELLIGENT BOOT DEVICE SELECTION AND RECOVERY - Techniques for recovering virtual machine state and boot information used to boot an installed guest operating system on systems where the information has either been lost or is not present are described. | 2011-09-29 |
| 20110238970 | System and method to lock electronic device - A method to lock an electronic device comprising an operating system comprises placing the electronic device in a disable state in which the processor is blocked from accessing the operating system, receiving a first unlock password from a remote source during a power-up operation of the electronic device, and placing the electronic device in a temporary unlock state which allows the processor to boot the operating system for a predetermined period of time when the first unlock password matches a password stored in the electronic device. Other embodiments may be described. | 2011-09-29 |
| 20110238971 | Method of managing a solid state drive, associated systems and implementations - One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during an initialization operation of the computing system. The initialization operation initializes components of the computing system. | 2011-09-29 |
| 20110238972 | Secure Bootstrapping for Wireless Communications - A mutual authentication method is provided for securely agreeing application-security keys with mobile terminals supporting legacy Subscriber Identity Modules (e.g., GSM SIM and CDMA2000 R-UIM, which do not support 3G AKA mechanisms). A challenge-response key exchange is implemented between a bootstrapping server function (BSF) and mobile terminal (MT). The BSF generates an authentication challenge and sends it to the MT under a server-authenticated public key mechanism. The MT receives the challenge and determines whether it originates from the BSF based on a bootstrapping server certificate. The MT formulates a response to the authentication challenge based on keys derived from the authentication challenge and a pre-shared secret key. The BSF receives the authentication response and verifies whether it originates from the MT. Once verified, the BSF and MT independently calculate an application security key that the BSF sends to a requesting network application function to establish secure communications with the MT. | 2011-09-29 |
| 20110238973 | METHOD, APPARATUS, AND SYSTEM FOR OPTIMIZING FREQUENCY AND PERFORMANCE IN A MULTIDIE MICROPROCESSOR - With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status. | 2011-09-29 |
| 20110238974 | METHODS AND APPARATUS TO IMPROVE TURBO PERFORMANCE FOR EVENTS HANDLING - Embodiments of an apparatus for improving performance for events handling are presented. In one embodiment, the apparatus includes a number of processing elements and task routing logic. If at least one of the processing elements is in a turbo mode, the task routing logic selects a processing element for executing a task based at least on a comparison of performance losses. | 2011-09-29 |
| 20110238975 | INFORMATION PROCESSING DEVICE, ROUTE CONTROL DEVICE, AND DATA RELAY METHOD - A server notifies a route control device of a session ID indicating a session and generated for a user of a terminal device together with its own IP address. The terminal device notifies a route control device of data for a connection to a relay device together with a session ID. The route control device associates the data for the connection with the IP address of the server using the session ID, and sets the associated combination as relay setting information in the relay device. Thus, the relay device refers to the relay setting information using data for a connection extracted from a message when the message is received from the terminal device, and determines a destination of the message. | 2011-09-29 |
