39th week of 2011 patent applcation highlights part 18 |
Patent application number | Title | Published |
20110233677 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having an ESD protection MOS transistor including a plurality of transistors combined together, in which a plurality of drain regions and a plurality of source regions disposed alternately and a gate electrode disposed between each pair of adjacent regions constituted of one of the plurality of drain regions and one of the plurality of source regions, in which a distance between a salicide metal region, which is formed on each of the plurality of drain regions, and the gate electrode is determined according to contact holes in the plurality of drain regions and a distance of the contact holes from substrate contacts. | 2011-09-29 |
20110233678 | JUNCTION VARACTOR FOR ESD PROTECTION OF RF CIRCUITS - An ESD protection device includes a first well of a first semiconductor type disposed in a substrate of a second semiconductor type forming a first diode. A second well of the second semiconductor type is formed in the substrate to form a second diode with the first well. A first plurality of doped regions of the first semiconductor type are formed in an upper surface of the first well. A second plurality of doped regions of the second semiconductor type are formed in the upper surface of the first well forming a third diode with the first well. A plurality of STI regions are formed in the upper surface of the first well. Each STI region is disposed between a doped region of the first and second semiconductor types. The third diode provides a current bypass when an ESD voltage spike is received at one of the first or second plurality of doped regions. | 2011-09-29 |
20110233679 | INTEGRATED CIRCUIT INCLUDING FINFETS AND METHODS FOR FORMING THE SAME - An integrated circuit including a plurality of Fin field effect transistors (FINFETs) is provided. The integrated circuit includes a plurality of fin-channel bodies over a substrate. The fin-channel bodies include a first fin-channel body and a second fin-channel body. A gate structure is disposed over the fin-channel bodies. At least one first source/drain (S/D) region of a first FINFET is adjacent the first fin-channel body. At least one second source/drain (S/D) region of a second FINFET is adjacent the second fin-channel body. The at least one first S/D region is electrically coupled with the at least one second S/D region. The at least one first and second S/D regions are substantially free from including any fin structure. | 2011-09-29 |
20110233680 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device including MOS transistors formed in a surface of one semiconductor substrate is provided. The device includes a first and second MOS transistors. The first MOS transistor includes a first source and drain regions spaced from each other, a first gate insulating film provided on the surface, a first gate electrode provided on the first gate insulating film, and a first channel region located immediately below the first gate insulating film and containing impurities of both conductivity types. The second MOS transistor includes a second source and drain regions spaced from each other, a second gate insulating film provided on the surface, a second gate electrode provided on the second gate insulating film, and a second channel region located immediately below the second gate insulating film and having an identical concentration profile of the impurity to the first channel region. | 2011-09-29 |
20110233681 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes: columnar gate electrodes that are separated from one another in a row on a semiconductor substrate; a gate insulating film that covers side faces of the columnar gate electrodes; a first semiconductor layer of a first conductivity type that is formed on the semiconductor substrate between the adjacent columnar gate electrodes; a insulating layer that is formed on the first semiconductor layer between the adjacent columnar gate electrodes; and a second semiconductor layer of a second conductivity type, which is different from the first conductivity type, that is formed on the insulating layer between the adjacent columnar gate electrodes. In the semiconductor device, a first MOSFET of the first conductivity type that uses the first semiconductor layer as a channel is formed, and a second MOSFET of the second conductivity type that uses the second semiconductor layer as a channel is formed. | 2011-09-29 |
20110233682 | Reducing Device Performance Drift Caused by Large Spacings Between Active Regions - A method of forming an integrated circuit structure includes providing a semiconductor substrate; and forming a first and a second MOS device. The first MOS device includes a first active region in the semiconductor substrate; and a first gate over the first active region. The second MOS device includes a second active region in the semiconductor substrate; and a second gate over the second active region. The method further include forming a dielectric region between the first and the second active regions, wherein the dielectric region has an inherent stress; and implanting the dielectric region to form a stress-released region in the dielectric region, wherein source and drain regions of the first and the second MOS devices are not implanted during the step of implanting. | 2011-09-29 |
20110233683 | CHEMICAL MECHANICAL POLISHING (CMP) METHOD FOR GATE LAST PROCESS - A method for fabricating a semiconductor device is provided which includes providing a semiconductor substrate, forming a plurality of transistors, each transistor having a dummy gate structure, forming a contact etch stop layer (CESL) over the substrate including the dummy gate structures, forming a first dielectric layer to fill in a portion of each region between adjacent dummy gate structures, forming a chemical mechanical polishing (CMP) stop layer over the CESL and first dielectric layer, forming a second dielectric layer over the CMP stop layer, performing a CMP on the second dielectric layer that substantially stops at the CMP stop layer, and performing an overpolishing to expose the dummy gate structure. | 2011-09-29 |
20110233684 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first main electrode, a base layer of a first conductivity type, a barrier layer of the first conductivity type, a diffusion layer of a second conductivity type, a base layer of the second conductivity type, a first conductor layer, a second conductor layer, and a second main electrode. The base layer of the first conductivity type is provided on the first main electrode. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are provided on the base layer of the first conductivity type. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are arranged alternately. The base layer of the second conductivity type is provided on the barrier layer of the first conductivity type. The first conductor layer and the second conductor layer are provided between the base layer of the second conductivity type and the diffusion layer of the second conductivity type and between the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type. The first conductor layer and the second conductor layer are provided with trench configurations with an interposed insulating film. The second main electrode is connected to the base layer of the second conductivity type. Bottom faces of the barrier layer of the first conductivity type and the diffusion layer of the second conductivity type are positioned on the first main electrode side of lower ends of the first conductor layer and the second conductor layer. The barrier layer of the first conductivity type and the diffusion layer of the second conductivity type form a super junction proximally to tips of the first conductor layer and the second conductor layer. | 2011-09-29 |
20110233685 | SEMICONDUCTOR INTEGRATED CIRCUIT - According to embodiments, there is provided a semiconductor device, including: a first area including plural transistors formed therein; and a second area including plural dummy transistors formed therein, the second area surrounding the first area, wherein a pitch of the dummy transistors is equal to or less than a central wavelength of a light used to form the transistors. | 2011-09-29 |
20110233686 | INTERCONNECTING BIT LINES IN MEMORY DEVICES FOR MULTIPLEXING - An embodiment of a memory device has a plurality of conductive plugs formed on a semiconductor substrate and a pair of successively adjacent first and second bit lines overlying and in contact with each of the conductive plugs. | 2011-09-29 |
20110233687 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device manufacturing method includes forming a channel dope layer having a first electric conductive-type inside of a semiconductor substrate, the channel dope layer being formed in a region except for a drain impurity region where dopant impurities for forming a low-concentration drain region are introduced, and the channel dope layer being separated from the drain impurity region; forming a gate electrode on the semiconductor substrate via a gate insulating film; and forming a low-concentration source region inside of the semiconductor substrate on a first side of the gate electrode, and forming a low-concentration drain region in the drain impurity region of the semiconductor substrate on a second side of the gate electrode, by introducing second electric conductive dopant impurities inside of the semiconductor substrate with the gate electrode as a mask. | 2011-09-29 |
20110233688 | NOVEL DEVICES WITH VERTICAL EXTENSIONS FOR LATERAL SCALING - A method of forming a semiconductor device is provided, in which extension regions are formed atop the substrate in a vertical orientation. In one embodiment, the method includes providing a semiconductor substrate doped with a first conductivity dopant. Raised extension regions are formed on first portions of the semiconductor substrate that are separated by a second portion of the semiconductor substrate. The raised extension regions have a first concentration of a second conductivity dopant. Raised source regions and raised drain regions are formed on the raised extension regions. The raised source regions and the raised drain regions each have a second concentration of the second conductivity dopant, wherein the second concentration is greater than the first concentration. A gate structure is formed on the second portion of the semiconductor substrate. | 2011-09-29 |
20110233689 | SEMICONDUCTOR DEVICE, PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, AND PROCESS FOR PRODUCING SEMICONDUCTOR SUBSTRATE - There is provided a semiconductor device that includes a III-V Group compound semiconductor having a zinc-blende-type crystal structure, an insulating material being in contact with the (111) plane of the III-V Group compound semiconductor, a plane of the III-V Group compound semiconductor equivalent to the (111) plane, or a plane that has an off angle with respect to the (111) plane or the plane equivalent to the (111) plane, and an MIS-type electrode being in contact with the insulating material and including a metal conductive material. | 2011-09-29 |
20110233690 | SEMICONDUCTOR CHIP ARRANGEMENT WITH SENSOR CHIP AND MANUFACTURING METHOD - On a carrier ( | 2011-09-29 |
20110233691 | HF-MEMS SWITCH - A high frequency-MEMS switch with a bendable switching element, whose one end is placed on a high resistivity substrate provided with an insulator, furthermore with a contact electrode to supply charge carriers to the substrate, wherein an electrical field can be produced to create an electrostatic bending force on the switching element between the switching element and the substrate, wherein at least one implantation zone is formed in the substrate, essentially directly beneath the insulator, the implantation zone is contacted with the contact electrode, which is located above the insulator, through an opening in the insulator, and also has ohmic contact with the substrate. | 2011-09-29 |
20110233692 | MICROPHONE UNIT AND VOICE INPUT DEVICE USING SAME - A microphone unit converts voice into an electric signal based on the vibration of a diaphragm contained in an MEMS chip. The microphone unit includes a substrate on which the diaphragm is mounted (the MEMS chip is mounted); a cover member, having sound holes, that is disposed above the substrate so that the diaphragm is contained within the inner space formed between the cover member and the substrate; and a holding member that holds only the substrate or both of the substrate and the cover member. | 2011-09-29 |
20110233693 | ELECTROMECHANICAL TRANSDUCER DEVICE AND METHOD OF FORMING A ELECTROMECHANICAL TRANSDUCER DEVICE - A micro or nano electromechanical transducer device formed on a semiconductor substrate comprises a movable structure which is arranged to be movable in response to actuation of an actuating structure. The movable structure comprises a mechanical structure comprising at least one mechanical layer having a first thermal response characteristic and a first mechanical stress response characteristic, at least one layer of the actuating structure, the at least one layer having a second thermal response characteristic different to the first thermal response characteristic and a second mechanical stress response characteristic different to the first mechanical stress response characteristic, a first compensation layer having a third thermal response characteristic and a third mechanical stress characteristic, and a second compensation layer having a fourth thermal response characteristic and a fourth mechanical stress response characteristic. The first and second compensation layers are arranged to compensate a thermal effect produced by the different first and second thermal response characteristics of the mechanical structure and the at least one layer of the actuating structure such that movement of the movable structure is substantially independent of variations in temperature and to adjust a stress effect produced by the different first and second stress response characteristics of the mechanical structure and the at least one layer of the actuating structure such that the movable structure is deflected a predetermined amount relative to the substrate when the electromechanical transducer device is in an inactive state. | 2011-09-29 |
20110233694 | MANUFACTURING METHOD OF ELECTRONIC DEVICE PACKAGE, ELECTRONIC DEVICE PACKAGE, AND OSCILLATOR - A manufacturing method of an electronic device package includes: forming concave portions that later form the cavities in one surface of a cover substrate; forming a first metal film on the cover substrate on a surface opposite to the surface in which the concave portions are formed; forming a second metal film on the cover substrate on the surface in which the concave portions are formed; bonding a base substrate and the cover substrate together via the second metal film. It thus becomes possible to provide an electronic device package in which the base substrate and the cover substrate are boned together via the metal film in a stable manner by minimizing warping of the substrate even when the substrate is made thinner. | 2011-09-29 |
20110233695 | Magnetoresistive Random Access Memory (MRAM) With Integrated Magnetic Film Enhanced Circuit Elements - A Magnetoresistive Random Access Memory (MRAM) integrated circuit includes a substrate, a magnetic tunnel junction region, a magnetic circuit element, and an integrated magnetic material. The magnetic tunnel junction region is disposed on the substrate, and includes a first magnetic layer and a second magnetic layer separated by a tunnel barrier insulating layer. The magnetic circuit element region is disposed on the substrate, and includes a plurality of interconnected metal portions. The integrated magnetic material is disposed on the substrate adjacent to the plurality of interconnected metal portions. | 2011-09-29 |
20110233696 | Perpendicular Magnetic Tunnel Junction Structure - In a particular illustrative embodiment, a method of fabricating a semiconductor device is disclosed that includes forming a metal layer over a device substrate, forming a via in contact with the metal layer, and adding a dielectric layer above the via. The method further includes etching a portion of the dielectric layer to form a trench area, and depositing a perpendicular magnetic tunnel junction (MTJ) structure within the trench area. | 2011-09-29 |
20110233697 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory according to an embodiment includes a magnetoresistive effect element and a fourth magnetic layer which is provided on the side surface of the magnetoresistive effect element via an insulating film. The magnetoresistive effect element has a first magnetic layer of which the magnetization direction is variable, a second magnetic layer of which the magnetization direction fixed, a third magnetic layer of which the magnetization direction parallel to a film plane is variable, and an intermediate layer between the first magnetic layer and the second magnetic layer. The fourth magnetic layer collects a magnetic field generated from the end of the third magnetic layer. | 2011-09-29 |
20110233698 | MAGNETIC MEMORY DEVICES - Provided is a magnetic memory device and a method of forming the same. A first magnetic conductive layer is disposed on a substrate. A first tunnel barrier layer including a first metallic element and a first non-metallic element is disposed on the first magnetic conductive layer. A second magnetic conductive layer is disposed on the first tunnel barrier layer. A content of an isotope of the first metallic element having a non-zero nuclear spin quantum number is lower than a natural state. | 2011-09-29 |
20110233699 | MAGNETIC MEMORY ELEMENT AND MAGNETIC MEMORY DEVICE - Magnetic memory element includes recording layer changing magnetization direction by external magnetic field, having easy-axis and hard-axis crossing easy-axis, first conductive layer forming magnetic field in direction crossing direction of easy-axis at layout position of recording layer, second conductive layer extending in direction crossing first conductive layer and forming magnetic field in direction crossing direction of hard-axis at layout position of recording layer. Recording layer has at least part between first conductive layer and second conductive layer. Planar-shaped recording layer viewed from direction where first and second conductive layers and recording layer are laminated, has portion located on side and other portion located on other side, with respect to virtual first center line of first conductive layer along direction where first conductive layer extends viewed from lamination direction. Area of portion viewed from lamination direction is less than or equal to one-third area of other portion. | 2011-09-29 |
20110233700 | MAGNETORESISTANCE EFFECT ELEMENT AND MAGNETIC MEMORY CELL AND MAGNETIC RANDOM ACCESS MEMORY USING SAME - Disclosed are a magnetoresistance effect element equipped with an magnesium oxide passivation layer, and a high-speed, ultra-low power consumption nonvolatile memory using said element. A tunnel magnetoresistance effect (TMR) film comprised of a ferromagnetic free layer, an insulation layer, and a ferromagnetic fixed layer is provided, and an MgO passivation layer is provided on the side walls of a protective layer and an orientation control layer, thus suppressing elemental diffusion of a tunnel magnetoresistance effect (TMR) element from each layer due to thermal processing at 350° or higher and obtaining a magnetic memory cell and magnetic random access memory having stable, high-output reading and a low current writing characteristics. Furthermore, when CoFeB is used in the ferromagnetic layer and MgO is used in the insulation layer, it is preferable that the MgO passivation layer have an (001) orientation. | 2011-09-29 |
20110233701 | PHOTOELECTRIC CONVERSION DEVICE AND SOLID-STATE IMAGING DEVICE - A photoelectric conversion device comprising a photoelectric conversion part including a first electrode layer, a second electrode layer and a photoelectric conversion layer provided between the first electrode layer and the second electrode layer, wherein light is made incident from an upper part of the second electrode layer into the photoelectric conversion layer; the photoelectric conversion layer generates a charge containing an electron and a hole corresponding to the incident light from the upper part of the second electrode layer; and the first electrode layer works as an electrode for extracting the hole. | 2011-09-29 |
20110233702 | SEMICONDUCTOR APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS, METHOD OF DESIGNING SEMICONDUCTOR APPARATUS, AND ELECTRONIC APPARATUS - A semiconductor device including a first material layer adjacent to a second material layer, a first via passing through the first material layer and extending into the second material layer, and a second via extending into the first material layer, where along a common cross section parallel to an interface between the two material layers, the first via has a cross section larger than that of the second via. | 2011-09-29 |
20110233703 | PHOTO DETECTOR DEVICE, PHOTO SENSOR AND SPECTRUM SENSOR - A photodetector device includes: a first semiconductor region of a first conductivity type electrically connected to a first external electrode: a second semiconductor region of a second conductivity type formed on the first semiconductor region; a third semiconductor region of the first conductivity type formed on the second semiconductor region; and a plurality of fourth semiconductor regions of the second conductivity type formed on the second semiconductor region, each of the plurality of fourth semiconductor regions being surrounded by the third semiconductor region, including a second conductivity type impurity having a concentration higher than a concentration of the second semiconductor region, and electrically connected to a second external electrode. | 2011-09-29 |
20110233704 | SOLID-STATE IMAGING DEVICE AND SOLID-STATE IMAGING DEVICE MANUFACTURING METHOD - A solid-state imaging device | 2011-09-29 |
20110233705 | WAFER PROCESSING - Methods, devices, and systems for wafer processing are described herein. One method of wafer processing includes modifying a peripheral edge of a wafer to create a number of edge surfaces substantially perpendicular to a number of dicing paths and dicing the wafer along the number of dicing paths. In one or more embodiments, the method includes modifying the peripheral edge of the wafer with a first tool and dicing the wafer with a second tool different from the first tool. | 2011-09-29 |
20110233706 | Method For Wafer Level Package and Semiconductor Device Fabricated Using The Same - Provided is a wafer level packaging method and a semiconductor device fabricated using the same. In the method, a substrate comprising a plurality of chips is provided. An adhesive layer is formed on the substrate corresponding to boundaries of the plurality of chips. A cover plate covering an upper portion of the substrate and having at least one opening exposing the adhesive layer or the substrate at the boundaries among the plurality of chips is attached to the adhesive layer. | 2011-09-29 |
20110233707 | SOLID-STATE IMAGE PICKUP ELEMENT, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A solid-state image pickup element includes: a photoelectric conversion region formed in a semiconductor substrate; an electric charge holding region formed in the semiconductor substrate for holding electric charges accumulated in the photoelectric conversion region until the electric charges are read out; a transfer gate formed on the semiconductor substrate for transferring electric charges generated by photoelectric conversion in the photoelectric conversion region to the electric charge holding region, and a light blocking film formed on an upper surface of the transfer gate. In this case, a portion between the semiconductor substrate and the light blocking film is thinly formed as a light made incident to the photoelectric conversion region has a longer wavelength in a wavelength region. | 2011-09-29 |
20110233708 | SEMICONDUCTOR LIGHT RECEIVING DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor light receiving device including: a semiconductor substrate; a semiconductor layer laminated on the semiconductor substrate and including an upper surface portion; a reflecting film formed to cover the upper surface portion of the semiconductor layer and including a principal reflecting region and an upper surface; and an upper electrode formed to cover at least one portion of the upper surface of the reflecting film, and including a junction portion extending through the reflecting file to be provided in contact with the upper surface portion of the semiconductor layer, the junction portion of the upper electrode surrounding a portion of a circumference of the principal reflecting region of the reflecting film, the principal reflecting region being connected to a region of the reflecting film located outside the junction portion, in which the semiconductor light receiving device detects light entering from another side of the semiconductor substrate. | 2011-09-29 |
20110233709 | SUB-PIXEL NBN DETECTOR - A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area. | 2011-09-29 |
20110233710 | PYROELECTRIC DETECTOR, PYROELECTRIC DETECTION DEVICE, AND ELECTRONIC INSTRUMENT - A pyroelectric detector includes a support member, a capacitor and a fixing part. The support member includes a first side and a second side opposite from the first side, with the first side facing a cavity. The capacitor includes a pyroelectric body between a first electrode and a second electrode such that an amount of polarization varies based on a temperature. The capacitor is mounted and supported on the second side of the support member with the first electrode being disposed on the second side of the support member. A thermal conductance of the first electrode is less than a thermal conductance of the second electrode. The fixing part supports the support member. | 2011-09-29 |
20110233711 | METHOD FOR LOCAL CONTACTING AND LOCAL DOPING OF A SEMICONDUCTOR LAYER - A method for local contacting and local doping of a semiconductor layer including the following process steps: A) Generation of a layer structure on the semiconductor layer through i) application of at least one intermediate layer on one side of the semiconductor layer, and ii) application of at least one metal layer onto the intermediate layer last applied in step i), wherein the metal layer at least partly covers the last applied intermediate layer, B) Local heating of the layer structure in such a manner that in a local region a short-time melt-mixture of at least partial regions of at least the layers: metal layer, intermediate layer and semiconductor layer, forms. After solidification of the melt-mixture, a contacting is created between metal layer and semiconductor layer. It is essential that in step A) i) at least one intermediate layer designed as dopant layer is applied, which contains a dopant wherein the dopant has a greater solubility in the semiconductor layer than the metal of the metal layer. | 2011-09-29 |
20110233712 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - According to a method for fabricating a semiconductor device, a first semiconductor layer made of a first nitride semiconductor is formed over a substrate. Thereafter, a mask film covering part of the upper surface of the first semiconductor layer is selectively formed on the first semiconductor layer. A multilayer film, in which second and third nitride semiconductors having different band gaps are stacked, is selectively formed on the first semiconductor layer with the mask film used as a formation mask. On the multilayer film, an ohmic electrode is formed. | 2011-09-29 |
20110233713 | SCHOTTKY DIODE AND METHOD FOR FABRICATING THE SAME - A Schottky diode includes a deep well formed in a substrate, an isolation layer formed in the substrate, a first conductive type guard ring formed in the deep well along an outer sidewall of the isolation layer and located at a left side of the isolation layer, a second conductive type well formed in the deep well along the outer sidewall of the isolation layer and located at a right side of the isolation layer, an anode electrode formed over the substrate and coupled to the deep well and the guard ring, and a cathode electrode formed over the substrate and coupled to the well. A part of the guard ring overlaps the isolation layer. | 2011-09-29 |
20110233714 | SEMICONDUCTOR DEVICE - Aspects of the invention are related to a semiconductor device including a first conductivity type n-type drift layer, a second conductivity type VLD region which is formed on a chip inner circumferential side of a termination structure region provided on one principal surface of the n-type drift layer and which is higher in concentration than the n-type drift layer, and a second conductivity type first clip layer which is formed on a chip outer circumferential side of the VLD region so as to be separated from the VLD region and which is higher in concentration than the n-type drift layer. The invention can also include a first conductivity type channel stopper layer which is formed on a chip outer circumferential side of the first clip layer so as to be separated from the first clip layer and which is higher in concentration than the n-type drift layer. | 2011-09-29 |
20110233715 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to the present invention includes: a cell active region including a p-base layer being an active layer of a second conductivity type that is diffused above a high concentration n-type substrate being a semiconductor substrate of a first conductivity type; and a p-well layer being a first well region of the second conductivity type having a ring shape, which is adjacent to the p-base layer, is diffused above the high concentration n-type substrate so as to surround the cell active region, and serves as a main junction part of a guard ring structure, wherein in a region on a surface of the p-well layer other than both ends, a trench region that is a ring-shaped recess having a tapered side surface is formed along the ring shape of the p-well layer | 2011-09-29 |
20110233716 | CIRCUIT STRUCTURE OF AN ULTRA HIGH VOLTAGE LEVEL SHIFTER - A circuit structure of an ultra high voltage level shifter includes a low voltage substrate having the electronic elements of the ultra high voltage level shifter thereon, an ultra high voltage redistribution layer, and a passivation layer between the substrate and the redistribution layer to prevent dielectric breakdown between the redistribution layer and the substrate. | 2011-09-29 |
20110233717 | INTEGRATED CIRCUIT GUARD RINGS - Integrated circuits with guard rings are provided. Integrated circuits may include internal circuitry that is sensitive to external noise sources. A guard ring may surround the functional circuitry to isolate the circuitry from the noise sources. The guard ring may include first, second, and third regions. The first and third regions may include p-wells. The second region may include an n-well. Stripes of diffusion regions may be formed at the surface of a substrate in the three regions. Areas in the guard ring that are not occupied by the diffusion regions are occupied by shallow trench isolation (STI) structures. Stripes of dummy structures may be formed over respective STI structures and may not overlap the diffusion regions. The diffusion regions in the first and third regions may be biased to a ground voltage. The diffusion regions in the second section may be biased to a positive power supply voltage. | 2011-09-29 |
20110233718 | Heterogeneous Technology Integration - A heterogeneous integrated circuit having at least one tier made of multiple technologies and a method of making the heterogeneous integrated circuit. The heterogeneous integrated circuit includes a package substrate, a first die of a first technology, and a second die of a second technology, where the two dies are located in the same tier. One die can surround the other die. The heterogeneous integrated circuit can also include a wire-bond and/or horizontal micro-bump coupling the two dies. The heterogeneous integrated circuit can also include a wire bond or vertical micro-bump coupling one of the dies to the package substrate. The vertical micro-bump coupling can include a through-via. The two technologies can be any of various technologies including CMOS, glass, sapphire and quartz. One die can also be adjacent to the other die on the same tier and the two dies coupled using a horizontal micro-bump. | 2011-09-29 |
20110233719 | TEST METHOD ON THE SUPPORT SUBSTRATE OF A SUBSTRATE OF THE "SEMICONDUCTOR ON INSULATOR" TYPE - The invention relates to a test method comprising an electrical connection contact on the support of a substrate of the semiconductor-on-insulator type. | 2011-09-29 |
20110233720 | TREATMENT FOR BONDING INTERFACE STABILIZATION - A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process. | 2011-09-29 |
20110233721 | SEMICONDUCTOR COMPONENT AND METHODS FOR PRODUCING A SEMICONDUCTOR COMPONENT - A semiconductor component includes a semiconductor body, in which are formed: a substrate of a first conduction type, a buried semiconductor layer of a second conduction type arranged on the substrate, and a functional unit semiconductor layer of a third conduction type arranged on the buried semiconductor layer, in which at least two semiconductor functional units arranged laterally alongside one another are provided. The buried semiconductor layer is part of at least one semiconductor functional unit, the semiconductor functional units being electrically insulated from one another by an isolation structure which permeates the functional unit semiconductor layer, the buried semiconductor layer, and the substrate. The isolation structure includes at least one trench and an electrically conductive contact to the substrate, the contact to the substrate being electrically insulated from the functional unit semiconductor layer and the buried layer by the at least one trench. | 2011-09-29 |
20110233722 | CAPACITOR STRUCTURE AND METHOD OF MANUFACTURE - The presented application discloses a capacitor structure and a method for manufacturing the same. The capacitor structure comprises a plurality of sub-capacitors formed on a substrate, each of which comprises a top capacitor plate, a bottom capacitor plate and a dielectric layer sandwiched therebetween; and a first capacitor electrode and a second capacitor electrode connecting the plurality of sub-capacitors in parallel, wherein the plurality of sub-capacitors includes a plurality of first sub-capacitors and a plurality of second sub-capacitors stacked in an alternate manner, each of the first sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying second sub-capacitor, with the overlapping plate being a first electrode layer; and each of the second sub-capacitors has a bottom capacitor plate overlapping with a top capacitor plate of an underlying first sub-capacitor, with the overlapping plate being a second electrode layer, the capacitor structure is characterized in that the first electrode layer and the second electrode layers are made of different conductive materials. The capacitor structure has a small footprint on the chip and a large capacitance value, and can be used as an integrated capacitor in an analogous circuit, an RF circuit, an embedded memory, and the like. | 2011-09-29 |
20110233723 | DIELECTRIC FILM AND SEMICONDUCTOR DEVICE - Disclosed is a dielectric film having a high dielectric constant and an excellent leakage breakdown. The dielectric film includes a TiO | 2011-09-29 |
20110233724 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor capacitor including: a capacitor device forming region having a trapezoidal trench which is formed on a surface of a first conductivity type semiconductor substrate; a second conductivity type lower electrode layer provided along the trapezoidal trenches of the capacitor device forming region; a capacitor insulating film formed at least on a surface of the second conductivity type lower electrode layer; and a second conductivity type upper electrode formed on a surface of the capacitor insulating film. | 2011-09-29 |
20110233725 | SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING THE SAME - A semiconductor device includes a first wiring layer, a second wiring layer and an insulating layer provided between the first wiring layer and the second wiring layer. A capacitor has a first electrode formed on the first wiring layer and a second electrode formed on the second wiring layer in such a manner that the second electrode overlaps with the first electrode. To the first electrode, two connection wirings are connected and, to the second electrode, two connection wirings are connected. The two connection wirings are connected to each other with low DC impedance substantially only through the first electrode. Similarly, the two connection wirings are connected to each other with low DC impedance substantially only through the second electrode. | 2011-09-29 |
20110233726 | Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors - A semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant. | 2011-09-29 |
20110233727 | VERTICAL SOI BIPOLAR JUNCTION TRANSISTOR AND MANUFACTURING METHOD THEREOF - The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density. Furthermore, the present invention utilizes side-wall spacer process to improve the compatibility of SOI BJT and SOI CMOS, which simplifies the SOI BiCMOS process and thus reduce the cost. | 2011-09-29 |
20110233728 | SEMICONDUCTOR COMPONENT - A method for producing a semiconductor component is proposed. The method includes providing a semiconductor body having a first surface; forming a mask on the first surface, wherein the mask has openings for defining respective positions of trenches; producing the trenches in the semiconductor body using the mask, wherein mesa structures remain between adjacent trenches; introducing a first dopant of a first conduction type using the mask into the bottoms of the trenches; carrying out a first thermal step; introducing a second dopant of a second conduction type, which is complementary to the first conduction type, at least into the bottoms of the trenches; and carrying out a second thermal step. | 2011-09-29 |
20110233729 | CDTE SEMICONDUCTOR SUBSTRATE FOR EPITAXIAL GROWTH AND SUBSTRATE CONTAINER - Provided is a CdTe-based semiconductor substrate for epitaxial growth, which is capable of growing good-quality epitaxial crystals without urging a substrate user to implement etching treatment before the epitaxial growth. | 2011-09-29 |
20110233730 | REACTIVE CODOPING OF GaAlInP COMPOUND SEMICONDUCTORS - A GaAlInP compound semiconductor and a method of producing a GaAlInP compound semiconductor are provided. The apparatus and method comprises a GaAs crystal substrate in a metal organic vapor deposition reactor. Al, Ga, In vapors are prepared by thermally decomposing organometallic compounds. P vapors are prepared by thermally decomposing phosphine gas, Zn vapors are prepared by thermally decomposing an organometallic group IIA or IIB compound. Group VIB vapors are prepared by thermally decomposing a gaseous compound of group VIB. The Al, Ga, In, P, group II, and group VIB vapors grow a GaAlInP crystal doped with group IIA or IIB and group VIB elements on the substrate wherein the group IIA or IIB and group VIB vapors produce a codoped GaAlInP compound semiconductor with a group IIA or IIB element serving as a p-type dopant having low group II atomic diffusion. | 2011-09-29 |
20110233731 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor device, in which a plurality of crystal defects for controlling the life time of carries are distributed in a silicon substrate, is characterized in that the total number of the crystal defects that cause a trap level that differs from the energy level of the center of the band gap by less than 0.2 eV, is less than the number of the crystal defects that cause the trap level that is the closest to the energy level of the center of the band gap among trap levels that differ from the energy level of the center of the band gap by 0.2 eV or more. | 2011-09-29 |
20110233732 | SUBSTRATE FOR AN ELECTRONIC OR ELECTROMECHANICAL COMPONENT AND NANO-ELEMENTS - A substrate configured to support at least one electronic or electromechanical component and one or more nano-elements, formed with a base support, with a catalytic system, with a barrier layer, and with a layer configured to receive the electronic or electromechanical component, in single-crystal Si or in Ge or in a mixture of these materials. The catalytic system lies on the base support without any contact with the layer configured to receive electronic or electromechanical component and the barrier layer is sandwiched between the catalytic system and the layer configured to receive the electronic or electromechanical component. This barrier layer is without any contact with the base support. | 2011-09-29 |
20110233733 | METHOD OF FABRICATING A RELEASE SUBSTRATE - The invention relates to a release substrate produced from semiconductor materials, and which includes a first substrate release layer having a surface in contact with a connecting layer, and a second substrate release layer having a surface in contact with the connecting layer opposite the first substrate release layer so that the connecting layer is located between the first substrate release layer and second substrate release layer; and a concentrated zone of solid nanoparticles located within the connecting layer to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment while also facilitating breaking of the connecting layer by mechanical action. | 2011-09-29 |
20110233734 | Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-On-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 2011-09-29 |
20110233735 | SEMICONDUCTOR WAFER AND ITS MANUFACTURE METHOD, AND SEMICONDUCTOR CHIP - A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between the first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including a lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of the first semiconductor chip area relative to the outer side wall of the lower metal layer. | 2011-09-29 |
20110233736 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a rounded interconnect on the package carrier; mounting a conductive shield over the package carrier, the conductive shield having an elevated portion and a hole adjacent to the elevated portion with the elevated portion over the integrated circuit and the rounded interconnect exposed from the hole; and forming an encapsulation between the conductive shield and the package carrier with the rounded interconnect exposed. | 2011-09-29 |
20110233737 | METHOD FOR MANUFACTURING 3-DIMENSIONAL STRUCTURES USING THIN FILM WITH COLUMNAR NANO PORES AND MANUFACTURE THEREOF - Disclosed is a method for manufacturing 3-dimensional structure using a thin film with a columnar nano pores and a manufacture thereof. A method for packaging an MEMS device or an NEMS device in accordance with an embodiment of the present invention includes:
| 2011-09-29 |
20110233738 | SEMICONDUCTOR DEVICE AND LEAD FRAME - A semiconductor device including a semiconductor element, a die pad of a plane size smaller than that of the semiconductor element, a plurality of hanging leads extending from the die pad, and sealing resin for covering the semiconductor element, the die pad, and the hanging leads. The width of a first main surface of each hanging lead, integrated with the mounting surface of the die pad, is smaller than the width of a second main surface thereof, integrated with the opposite surface of the die pad. | 2011-09-29 |
20110233739 | SEMICONDUCTOR STRUCTURE, MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR DEVICE - Disclosed is a semiconductor structure including a semiconductor substrate including an electronic circuit which is provided in a predetermined region of the semiconductor substrate, a wiring provided on the semiconductor substrate in a region outside of the predetermined region, an external connection electrode provided on the wiring, a sealing resin which covers a side surface of the external connection electrode and a wall which intervenes between the electronic circuit and the sealing resin. | 2011-09-29 |
20110233740 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die. | 2011-09-29 |
20110233741 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device including an organic substrate with an external connection terminal and a semiconductor memory chip. The semiconductor memory device further includes a lead frame having a bonded portion and an installation portion. It further includes a resin mold for sealing the semiconductor memory chip. The lead frame is provided with a plurality of extensions at least from one of the installation portion and the bonded portion, in a way of extending at least to two or more sides of the resin mold. | 2011-09-29 |
20110233742 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF, CIRCUIT BOARD AND ELECTRONIC APPARATUS - A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings. | 2011-09-29 |
20110233743 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADFRAME AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a leadframe strip system, having a stress relief slot and a leadframe unit, the stress relief slot is at a frame corner of the leadframe strip system and spans adjacent sides of the leadframe unit, the leadframe unit includes a paddle, a tie bar therefrom, and a lead finger; connecting an integrated circuit and the lead finger; forming an encapsulation covering the integrated circuit; and singulating the integrated circuit in the encapsulation from the leadframe strip system with a package corner of the encapsulation free of micro-cracks with an inspection of the package corner at least 50× view. | 2011-09-29 |
20110233744 | INTEGRATED CIRCUIT PROTRUDING PAD PACKAGE SYSTEM AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package system includes: providing a leadframe; forming a protruding pad on the leadframe; attaching a die to the leadframe; electrically connecting the die to the leadframe; and encapsulating at least portions of the leadframe, the protruding pad, and the die in an encapsulant. | 2011-09-29 |
20110233745 | Integrated Circuit Packages - Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages. | 2011-09-29 |
20110233746 | Dual-leadframe Multi-chip Package and Method of Manufacture - A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe. | 2011-09-29 |
20110233747 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKING OPTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: fabricating a base package substrate having a component side and a system side; coupling a first integrated circuit die on the component side; coupling stacking interconnects on the component side around the first integrated circuit die; forming a package body on the component side, the first integrated circuit die, and the stacking interconnects; forming vertical insertion cavities through the package body and on the stacking interconnects; and forming a trench, in the package body, adjacent to the vertical insertion cavities for reducing a package warping stress. | 2011-09-29 |
20110233748 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing an interposer having an interposer first side and an interposer second side opposing the interposer first side; mounting an integrated circuit to the interposer first side, the integrated circuit having a non-active side and an active side with the non-active side facing the interposer; connecting first interconnects between the active side and the interposer first side, the first interconnects having a first density on the interposer first side; mounting the interposer over a package carrier with the interposer first side facing the package carrier; connecting second interconnects between the package carrier and the interposer second side, the second interconnects having a second density on the interposer second side, the second density that is approximately the same as the first density; and forming an encapsulation over the package carrier covering the interposer and the second interconnects. | 2011-09-29 |
20110233749 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a first chip, a jumper chip, a plurality of first bonding wires and a plurality of second bonding wires. The substrate has a plurality of contact pads. The first chip is disposed and electrically connected to the substrate via the first bonding wires. The jumper chip is disposed on the first chip and has a plurality of metal pads. Each of the metal pads is electrically connected to two contact pads of the substrate via two second bonding wires, respectively. | 2011-09-29 |
20110233750 | Arrangement of Two Substrates having an SLID Bond and Method for Producing such an Arrangement - An arrangement having a first and a second substrate is disclosed, wherein the two substrates are connected to one another by means of an SLID (Solid Liquid InterDiffusion) bond. The SLID bond exhibits a first metallic material and a second metallic material, wherein the SLID bond comprises the intermetallic Al/Sn-phase. | 2011-09-29 |
20110233751 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ENCAPSULATION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a rounded interconnect on a package carrier having an integrated circuit attached thereto, the rounded interconnect having an actual center; forming an encapsulation over the package carrier covering the rounded interconnect; removing a portion of the encapsulation over the rounded interconnect with an ablation tool; calculating an estimated center of the rounded interconnect; aligning the ablation tool over the estimated center; and exposing a surface area of the rounded interconnect with the ablation tool. | 2011-09-29 |
20110233752 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH AN INTERMEDIATE PAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming an elevated contact above and between a lead and a die pad that is coplanar with the lead; connecting an integrated circuit and the lead; attaching a jumper interconnect between the elevated contact and the lead; and forming an encapsulant over the integrated circuit, the lead, the die pad, the elevated contact, and the jumper interconnect, the encapsulant having a recess in a base side with the elevated contact exposed in the recess and the lead exposed from the base side. | 2011-09-29 |
20110233753 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH LEADS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a paddle, an inner post adjacent to the paddle, a jumper pad, and an outer post, with the jumper pad between the inner post and the outer post; mounting an integrated circuit over a paddle first side, the paddle first side co-planar with the outer post; connecting a first jumper interconnect between the integrated circuit and the jumper pad; connecting a second jumper interconnect between the jumper pad and the outer post; and forming an encapsulation over paddle, the integrated circuit, the first jumper interconnect, the jumper pad, and the second jumper interconnect. | 2011-09-29 |
20110233754 | Encapsulated Semiconductor Chip with External Contact Pads and Manufacturing Method Thereof - A method includes providing a carrier; applying a dielectric layer to the carrier; applying a metal layer to the dielectric layer; placing a first semiconductor chip on the metal layer with contact pads of the first semiconductor chip facing the metal layer; covering the first semiconductor chip with an encapsulation material; and removing the carrier. | 2011-09-29 |
20110233755 | Semiconductor Housing Package, Semiconductor Package Structure Including The Semiconductor Housing Package, And Processor-Based System Including The Semiconductor Package Structure - A semiconductor housing package may be provided. The semiconductor housing package may include a mold layer, a housing chip, a redistribution structure, and a housing node. The mold layer may surround and partially expose the housing chip. The redistribution structure may be electrically connected to the housing chip and may be disposed on the mold layer. The housing node may be in contact with the redistribution structures. The semiconductor housing package may be disposed on a semiconductor base package and may constitute a semiconductor package structure along with the semiconductor base package. The semiconductor package structure may be disposed on a processor-based system. | 2011-09-29 |
20110233756 | WAFER LEVEL PACKAGING WITH HEAT DISSIPATION - A heat dissipating wafer level package and method for manufacturing a heat dissipating wafer level package is provided. The heat dissipating wafer level package has a thermally conductive coating integrated thereon which facilitates the dissipation of heat from a device into the surrounding air and/or the thermal transfer of heat away from the device toward a heat spreader or heat sink. Additionally, the coating enhances the structural integrity and strength of the wafer during the manufacturing process as well as the resulting WLP. | 2011-09-29 |
20110233757 | Method for Facilitating the Stacking of Integrated Circuits Having Different Areas and an Integrated Circuit Package Constructed by the Method - An integrated circuit package comprises a package substrate, an application specific integrated circuit (ASIC) having a first area and formed on a first wafer made from a select semiconductor material, a second wafer of the select semiconductor material, and a supplemental-integrated circuit. The supplemental-integrated circuit has a second area different from the first area. The first wafer includes a through-wafer via to couple the ASIC to the package substrate. An active surface of the ASIC is coupled to the second wafer. The second wafer is arranged with a window there through that is sized to closely receive and align one or more bonding interfaces of the supplemental-integrated circuit to respective bonding interfaces of the ASIC. A corresponding method for assembling a die-stacked integrated circuit package is disclosed. | 2011-09-29 |
20110233758 | SEMICONDUCTOR DEVICE - A semiconductor devices includes a first die pad having the conductivity connected to one end of a DC power source, a second die pad having the conductivity connected to the other end of the DC power source, a first switching element provided on the first die pad, receiving DC power from the DC power source via the first die pad, and having a terminal opposite to the first die pad connected to a first output terminal, and a second switching element provided on the second die pad, receiving the DC power from the DC power source via the second die pad, and connected to the first output terminal, and having a terminal opposite to the second die pad. | 2011-09-29 |
20110233759 | SEMICONDUCTOR DEVICE - All lead terminals | 2011-09-29 |
20110233760 | SEMICONDUCTOR DEVICE - A power semiconductor chip (first semiconductor chip) | 2011-09-29 |
20110233761 | CU PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE - Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof. | 2011-09-29 |
20110233762 | WAFER LEVEL INTEGRATED INTERCONNECT DECAL AND MANUFACTURING METHOD THEREOF - A wafer level integrated interconnect decal manufacturing method and wafer level integrated interconnect decal arrangement. In accordance with the technology concerning the soldering of integrated circuits and substrates, and particularly providing for solder decal methods forming and utilization, in the present instance there are employed underfills which consist of a solid film material and which are applied between a semiconductor chip and the substrate in order to enhance the reliability of a flip chip package. In particular, the underfill material increases the resistance to fatigue of controlled collapse chip connect (C4) bumps. | 2011-09-29 |
20110233763 | INTEGRATED CIRCUIT SYSTEM WITH STRESS REDISTRIBUTION LAYER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate having a transistor and a metallization layer; forming a metal pad in direct contact with the metallization layer of the substrate; forming a passivation layer in direct contact with the metal pad and covering the substrate; forming a routing trace above the passivation layer in direct contact with the metal pad, and the routing trace is substantially larger than the metal pad, and the routing trace is not electrically insulated by a subsequent layer; and forming a bump connected to the metal pad with the routing trace. | 2011-09-29 |
20110233764 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor device package and a method of fabricating the same are disclosed. The semiconductor device package includes a substrate, a buffer structure, two active chips and a bridge chip. The substrate has a cavity, a first surface and a second surface opposite to the first surface. The cavity is extended from the first surface toward the second surface, and the buffer structure is disposed in the cavity. The active chips are mechanically disposed on and electrically connected to the first surface and around the cavity, wherein the active chips both have a first active surface. The bridge chip is disposed in the cavity and above the buffer structure, wherein the bridge chip has a second active surface, the second active surface faces the first active surfaces and is partially overlapped with the first active surfaces, the bridge chip is used for providing a proximity communication between the active chips. | 2011-09-29 |
20110233765 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first bump that is located over a surface of a semiconductor element, and is formed on a first bump formation face distanced from a back surface of the semiconductor element at a first distance, and a second bump that is located over the surface of the semiconductor element, and is formed on a second bump formation face distanced from the back surface of the semiconductor element at a second distance being longer than the first distance, the second bump having a diameter larger than a diameter of the first bump. | 2011-09-29 |
20110233766 | Semiconductor Device and Method of Forming a Dual UBM Structure for Lead Free Bump Connections - A semiconductor device has a substrate with a contact pad. A first insulation layer is formed over the substrate and contact pad. A first under bump metallization (UBM) is formed over the first insulating layer and is electrically connected to the contact pad. A second insulation layer is formed over the first UBM. A second UBM is formed over the second insulation layer after the second insulation layer is cured. The second UBM is electrically connected to the first UBM. The second insulation layer is between and separates portions of the first and second UBMs. A photoresist layer with an opening over the contact pad is formed over the second UBM. A conductive bump material is deposited within the opening in the photoresist layer. The photoresist layer is removed and the conductive bump material is reflowed to form a spherical bump. | 2011-09-29 |
20110233767 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - The semiconductor device manufacturing method includes the steps of attaching two or more solder particles on at least one electrode among a plurality of electrodes of an electronic component, arranging the electrode of the electronic component and an electrode of a circuit board so as to oppose each other, abutting the solder particles attached on a surface of the electrode of the electronic component to the electrode of the circuit board and heating the solder particles, and connecting electrically the electrode of the electronic component and the electrode of the circuit board via two or more solder joint bodies made by melting the solder particles. | 2011-09-29 |
20110233768 | SEMICONDUCTOR DEVICE - A semiconductor device includes: an interconnection substrate on which a semiconductor chip is mounted; electrodes formed on a surface of the interconnection substrate; and solder bumps formed on the electrodes. The solder bump includes a base section and a surface layer section that covers the base section. The surface layer section includes conductive metal selected from the group consisting of Cu, Ni, Au, and Ag, and Sn at least and a ratio of the number of atoms of the conductive metal to the number of Sn atoms per a unit volume is more than 0.01. | 2011-09-29 |
20110233769 | SEMICONDUCTOR DEVICE PROVIDED WITH TIN DIFFUSION INHIBITING LAYER, AND MANUFACTURING METHOD OF THE SAME - A semiconductor device is disclosed wherein a tin diffusion inhibiting layer is provided above the land of a wiring line, and a solder ball is provided above the tin diffusion inhibiting layer. Thus, even when this semiconductor device is, for example, a power supply IC which deals with a high current, the presence of the tin diffusion inhibiting layer makes it possible to more inhibit the diffusion of tin in the solder ball into the wiring line. | 2011-09-29 |
20110233770 | CHIP PACKAGE - A chip package includes: a substrate having a first and a second surfaces; an optical device on the first surface; a conducting layer on the second surface; a passivation layer on the second surface and the conducting layer, wherein the passivation layer has an opening exposing the conducting layer; a conducting bump on the second surface and having a bottom and an upper portions, wherein the bottom portion is disposed in the opening and electrically contacts the conducting layer, and the upper portion is located outside of the opening and extends along a direction away from the opening; a recess extending from a surface of the conducting bump toward an inner portion of the conducting bump; and a light shielding layer on the second surface, extending under the upper portion, and partially located in the recess and overlapping a portion of the conducting bump. | 2011-09-29 |
20110233771 | SEMICONDUCTOR PACKAGES HAVING WARPAGE COMPENSATION - A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package. | 2011-09-29 |
20110233772 | SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor element includes: a substrate having an integrated circuit; and a wire connection electrode and a bump connection electrode which are provided on a same main surface of the substrate as electrodes having a same connection function to the integrated circuit. The wire connection electrode is provided in a periphery of the main surface. The bump connection electrode is provided inside the wire connection electrode on the main surface. When a straight line dividing the main surface into two regions is determined, the wire connection electrode and the bump connection electrode are located opposite to each other with respect to the straight line. | 2011-09-29 |
20110233773 | MANUFACTURING PROCESS AND STRUCTURE OF THROUGH SILICON VIA - A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions. | 2011-09-29 |
20110233774 | ELECTRONIC DEVICES FORMED OF TWO OR MORE SUBSTRATES CONNECTED TOGETHER, ELECTRONIC SYSTEMS COMPRISING ELECTRONIC DEVICES, AND METHODS OF FORMING ELECTRONIC DEVICES - Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at least substantially parallel to each other through at least a portion of the first substrate. A plurality of bond pads is positioned on a surface of the first substrate and comprises a width extending over at least two of the plurality of conductive traces. A plurality of vias extends from adjacent at least some of the conductive traces to the plurality of bond pads. The second substrate is bonded to the first substrate and comprises support circuitry coupled to the plurality of bond pads on the first substrate with a plurality of conductive bumps. Memory devices and related methods of forming electronic devices and memory devices are also disclosed, as are electronic systems. | 2011-09-29 |
20110233775 | Three-Dimensional Multichip Module - A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips. | 2011-09-29 |
20110233776 | SEMICONDUCTOR CHIP WITH COIL ELEMENT OVER PASSIVATION LAYER - A method for fabricating a circuitry component includes providing a semiconductor substrate, a first coil over said semiconductor substrate, a passivation layer over said first coil; and depositing a second coil over said passivation layer and over said first coil. Said second coil may be deposited by forming a first metal layer over said passivation layer, forming a pattern defining layer over said first metal layer, a first opening in said pattern defining layer exposing said first metal layer, forming a second metal layer over said first metal layer exposed by said first opening, removing said pattern defining layer, and removing said first metal layer not under said second metal layer. | 2011-09-29 |