39th week of 2011 patent applcation highlights part 17 |
Patent application number | Title | Published |
20110233577 | LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a light emitting device and a method for manufacturing the same. The light emitting device includes a substrate having a lead frame, a light emitting diode mounted on the substrate, a mold member formed on the substrate and the light emitting diode, and a reflecting member having an opening portion at one side thereof and being inclined at an outer portion of the mold member. | 2011-09-29 |
20110233578 | REFLECTOR LED LAMP - A reflector LED lamp comprises: a reflector | 2011-09-29 |
20110233579 | LEADFRAME-BASED PACKAGES FOR SOLID STATE LIGHT EMITTING DEVICES AND METHODS OF FORMING LEADFRAME-BASED PACKAGES FOR SOLID STATE LIGHT EMITTING DEVICES - A modular package for a light emitting device includes a leadframe having a top surface and including a central region having a bottom surface and having a first thickness between the top surface of the leadframe and the bottom surface of the central region. The leadframe may further include an electrical lead extending away from the central region. The electrical lead has a bottom surface and has a second thickness from the top surface of the leadframe to the bottom surface of the electrical lead. The second thickness may be less than the first thickness. The package further includes a package body on the leadframe surrounding the central region and exposing the bottom surface of the central region. The package body may be at least partially provided beneath the bottom surface of the lead and adjacent the bottom surface of the central region. Methods of forming modular packages and leadframes are also disclosed. | 2011-09-29 |
20110233580 | CARRIER FOR A LIGHT EMITTING DEVICE - A semiconductor light emitting device is mounted on a support substrate. The support substrate is disposed in an opening in a carrier. In some embodiments, the support substrate is a ceramic tile and the carrier is a low cost material with a lateral extent large enough to support a lens molded over or attached to the carrier. | 2011-09-29 |
20110233581 | SOLID STATE LIGHTING DEVICES WITH CELLULAR ARRAYS AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting (“SSL”) devices with cellular arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode includes a semiconductor material having a first surface and a second surface opposite the first surface. The semiconductor material has an aperture extending into the semiconductor material from the first surface. The light emitting diode also includes an active region in direct contact with the semiconductor material, and at least a portion of the active region is in the aperture of the semiconductor material. | 2011-09-29 |
20110233582 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate and an epitaxy layer positioned on the substrate. In one embodiment of the present disclosure, the substrate includes an upper surface and a plurality of bumps positioned on the upper surface, and each of the bumps includes a top plane substantially parallel to the upper surface and a plurality of wall surfaces between the top plane and the upper surface. In one embodiment of the present disclosure, the epitaxy layer has the same crystal orientation on the upper surface of the substrate and the wall surfaces of the bumps to reduce defect density and increase protection from electrostatic discharge. | 2011-09-29 |
20110233583 | HIGH-POWER LED PACKAGE - A high-power LED package includes a thermal conductive substrate, a circuit layer formed on the top wall of the thermal conductive substrate, a LED chip mounted on the top wall of the thermal conductive substrate, lead wires electrically connected between the LED chip and the circuit layer, and a packaging layer covering the LED chip, the lead wires and the connection areas between the lead wires and the circuit layer outside the bottom wall of the thermal conductive substrate for enabling waste heat to be directly transferred from the LED chip to the thermal conductive substrate and then rapidly dissipated into the outside open air by the thermal conductive substrate during operation of the LED chip. | 2011-09-29 |
20110233584 | LIGHT EMITTING DIODE CHIP AND MANUFACTURING METHOD THEREOF - A light emitting diode chip includes a thermal conductive substrate, an epi-layer, a thin-type ohmic contacting film, a transparent conducting layer, and an electrode pad. The epi-layer includes a p-type semiconductor layer, an n-type semiconductor layer, and an active layer. The n-type semiconductor layer includes a stepped surface at a side thereof facing away from the substrate, and the stepped surface includes a central portion and a peripheral portion surrounding the central portion. The n-type semiconductor layer has a thickness decreasing along directions from a center thereof to opposite lateral peripheries thereof. The ohmic contacting film is arranged on the stepped surface. The conducting layer is arranged on the ohmic contacting film. The electrode pad is arranged on the conducting layer and located corresponding to the central portion of the stepped surface. | 2011-09-29 |
20110233585 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a first electrode, a second electrode, an insulating film, a first interconnection, a second interconnection, a first metal pillar, a second metal pillar, a resin, and a fluorescent layer. The semiconductor layer has a first major surface, a second major surface formed on an opposite side to the first major surface, and a light emitting layer. The first electrode and the second electrode are provided on the second major surface of the semiconductor layer. The fluorescent layer faces to the first major surface of the semiconductor layer and includes a plurality of kinds of fluorescent materials having different peak wavelengths of emission light. | 2011-09-29 |
20110233586 | METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE AND LIGHT EMITTING DEVICE - According to one embodiment, a light emitting device includes a stacked body, a p-side and n-side electrodes, an insulating film, a p-side extraction electrode, an n-side extraction electrode, a resin layer and a phosphor layer. The stacked body has a first and a second surface opposite to each other and includes a light emitting layer. A p-side and an n-side electrode are provided on the second surface. An insulating film has openings to which the p-side and n-side electrodes are exposed. A p-side extraction electrode includes a p-side seed metal and a p-side metal wiring layer. An n-side extraction electrode includes an n-side seed metal and an n-side metal wiring layer. A resin layer is filled around the p-side and n-side extraction electrodes, and a phosphor layer is provided on a side of the first surface. Emission light from the light emitting layer is emitted through the first surface. | 2011-09-29 |
20110233587 | LIGHT EMITTING DIODE - A light emitting diode is provided, comprising: a substrate; a metal wiring layer disposed on the substrate; alight emitting element provided on the metal wiring layer; wherein the light emitting element comprises: a semiconductor light emitting layer having a first semiconductor layer, an active layer, and a second semiconductor layer formed from the substrate side sequentially; a transparent insulating layer provided on the substrate side of the semiconductor light emitting layer; a first electrode part and a second electrode part provided on the substrate side of the transparent insulating layer in such a manner as being separated from each other, and joined to the metal wiring layer; a first contact part provided so as to pass through the transparent insulating layer and electrically connecting the first electrode part and the first semiconductor layer; and a second contact part provided so as to pass through the transparent insulating layer, the first semiconductor layer, and the active layer, and electrically connecting the second electrode part and the second semiconductor layer. | 2011-09-29 |
20110233588 | Semiconductor light-emitting device - A first intermediate electrode | 2011-09-29 |
20110233589 | LIGHT-EMITTING DEVICE, LIGHT-EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - Disclosed is a light-emitting device including a substrate, a light-emitting structure on the substrate, the light-emitting structure including a first semiconductor layer, an active layer and a second semiconductor layer, a light-transmitting electrode layer on the second semiconductor layer, and a first reflective layer on the light-transmitting electrode layer, wherein the first reflective layer comprises a first layer having a first index of refraction and a second layer having a second index of refraction different from the first index of refraction. Based on this configuration, it is possible to protect the light-emitting device and improve luminous efficiency thereof. | 2011-09-29 |
20110233590 | LIGHT EMITTING DEVICE, METHOD FOR FABRICATING LIGHT EMITTING DEVICE, AND LIGHT EMITTING DEVICE PACKAGE - Provided are a light emitting device, a method for fabricating the light emitting device, a light emitting device package, and a lighting system. The light emitting device includes a first conductive type semiconductor layer having a first top surface and a second top surface under the first top surface, an active layer on the first top surface of the first conductive type semiconductor layer, a second conductive type semiconductor layer on the active layer, a first electrode on the second top surface of the first conductive type semiconductor layer, an intermediate refractive layer on the second top surface of the first conductive type semiconductor layer, and a second electrode connected to the second conductive type semiconductor layer. | 2011-09-29 |
20110233591 | PHASE MODULATION DEVICE, PHASE MODULATION DEVICE FABRICATION METHOD, CRYSTALLIZATION APPARATUS, AND CRYSTALLIZATION METHOD - A phase shifter which modulates the phase of incident light has a light-transmitting substrate such as a glass substrate, and a phase modulator such as a concavity and convexity pattern which is formed on the laser beam incident surface of the light-transmitting substrate and modules the phase of incident light. A light-shielding portion which shields light in the peripheral portion where the optical intensity distribution decreases of the phase modulator is formed on the laser beam incident surface or exit surface of the phase shifter, thereby shielding the peripheral light in the irradiation surface of the incident laser beam. | 2011-09-29 |
20110233592 | DEVICE AND METHOD FOR LIGHTING - It is presented a method for producing a lighting device ( | 2011-09-29 |
20110233593 | ILLUMINATING APPARATUS - Provided is a lighting apparatus that is suitable as a substitute for a conventional halogen lamp when positively utilizing leaked light. The lighting apparatus comprises: a heat dissipator | 2011-09-29 |
20110233594 | LIGHT-EMITTING DIODE PACKAGE - An LED package including a lead-frame, at least an LED chip and an encapsulant is provided. The lead-frame has a roughened surface, the LED chip is disposed on the lead-frame and electrically connected to the lead-frame, and the roughened surface is suitable to scatter the light emitted from the LED chip. In addition, the encapsulant encapsulates the LED chip and a part of the lead-frame, and the rest part of the lead-frame is exposed out of the encapsulant. | 2011-09-29 |
20110233595 | Semiconductor Device and Method for Manufacturing the Same - The invention relates to a semiconductor device and a method for manufacturing the semiconductor device, which includes: an insulating film over a substrate; a first pixel electrode embedded in the insulating film; an island-shaped single-crystal semiconductor layer over the insulating film; a gate insulating film and a gate electrode; an interlayer insulating film which covers the island-shaped single-crystal semiconductor layer and the gate electrode; a wiring which electrically connects a high-concentration impurity region and the first pixel electrode to each other; a partition which covers the interlayer insulating film, the island-shaped single-crystal semiconductor layer, and the gate electrode and has an opening in a region over the first pixel electrode; a light-emitting layer formed in a region which is over the pixel electrode and surrounded by the partition; and a second pixel electrode electrically connected to the light-emitting layer. A surface of the first pixel electrode, which is in contact with the light-emitting layer, is flat, and a surface where the insulating film is in contact with the island-shaped single-crystal semiconductor layer roughly coincides with a surface where the first pixel electrode is in contact with the light-emitting layer. | 2011-09-29 |
20110233596 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - The present invention provides a light emitting element capable or realizing at least one of lower resistance, higher output, higher power efficiency (1 m/W), higher mass productivity and lower cost of the element using a light transmissive electrode for an electrode arranged exterior to the light emitting structure. A semiconductor light emitting element includes a light emitting section, a first electrode and a second electrode on a semiconductor structure including first and second conductive type semiconductor layers, the first and the second electrodes respectively including at least two layers of a first layer of a light transmissive conductive film conducting to the first and the second conductive type semiconductor and a second layer arranged so as to conduct with the first layer. First and second light transmissive insulating films are respectively arranged so as to overlap at least one part of the first and the second layers. | 2011-09-29 |
20110233597 | Light-Emitting Element and Light-Emitting Device - It is an object of the present invention to provide a light-emitting element having a layer containing a light-emitting material and a transparent conductive film between a pair of electrodes, in which electric erosion of the transparent conductive film and metal can be prevented, and also to provide a light-emitting device using the light-emitting element. According to one feature of the invention, a light-emitting element includes a first layer | 2011-09-29 |
20110233598 | LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF - A light emitting diode package includes a metallic substrate, a light emitting diode chip, and a buffer layer. The light emitting diode chip is arranged on the metallic substrate. The buffer layer is located between and connected to the metallic substrate and the light emitting diode chip. The buffer layer includes a base material and a number of conducting particles essentially mixed in the base material. The base material is soft epoxy. Each of the conducting particles includes a resin core and a metallic layer formed on an exterior surface of the resin core. The conducting particles are configured for electrically connecting the light emitting diode chip to the metallic substrate. | 2011-09-29 |
20110233599 | LIGHT-EMITTING DEVICE - According to one embodiment, a light-emitting device includes a semiconductor stacked body and a pad electrode. The semiconductor stacked body has a surface and includes a light-emitting layer. The surface has protruding portions. The pad electrode is provided on one of a top surface of the protruding portions and a bottom surface around the protruding portions. | 2011-09-29 |
20110233600 | WHITE ORGANIC LIGHT-EMITTING DIODE - A white organic light-emitting diode (WOLED) includes a transparent electrode, a blue-complementary light-emitting layer, a translucent electrode, a blue light-emitting layer, and a non-transparent electrode. The blue-complementary light-emitting layer is disposed on the transparent electrode. The transparent electrode and the translucent electrode include a first voltage. The blue light-emitting layer is disposed on the translucent layer. The non-transparent electrode is disposed on the blue light-emitting layer. The translucent electrode and the non-transparent electrode include a second voltage. | 2011-09-29 |
20110233601 | SUBSTRATE FOR LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DEVICE - To provide a substrate for light-emitting element, which is capable of sufficiently dissipating heat generation of a light-emitting element solely by a heat dissipation layer disposed in parallel with a light-emitting element-mounting surface of the substrate, which is economically advantageous as compared with thermal vias. | 2011-09-29 |
20110233602 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE AND LIGHTING SYSTEM - Disclosed are a light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises a substrate; a light emitting structure including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer, which are formed on the substrate such that a part of the first conductive semiconductor layer is exposed upward; schottky contact regions on the second conductive semiconductor layer; a second electrode on the second conductive semiconductor layer; and a first electrode on the exposed first conductive semiconductor layer, wherein a distance between the schottky contact regions narrowed as the schottky contact regions are located closely to a mesa edge region. | 2011-09-29 |
20110233603 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - The present disclosure relates to a semiconductor light-emitting device including: a plurality of semiconductor layers having a first semiconductor layer with a first conductivity, a second semiconductor layer with a second conductivity different from the first conductivity, and an active layer interposed between the first semiconductor layer and the second semiconductor layer and generating light by recombination of electrons and holes; a bonding pad electrically connected to the plurality of semiconductor layers; a first electrode spread over the plurality of semiconductor layers; and a second electrode extended from the bonding pad to the first electrode and electrically connecting the bonding pad to the first electrode. | 2011-09-29 |
20110233604 | ORGANIC ELECTROLUMINESCENCE DEVICE - According to one embodiment, an organic electroluminescence device including an anode, a cathode, an emitting layer positioned therebetween and including a first host material and a first dopant, and an organic layer in contact with the emitting layer between the cathode and the emitting layer and including a second host material and a second dopant. The first host material has a hole-transporting property. The first dopant has a blue-fluorescent property and fluorescence thereof exhibits the maximum intensity at a first wavelength. The second host material has an electron-transporting property. The second host material has an ionization energy higher than an ionization energy of the first host material. The second dopant has an ionization energy lower than the ionization energy of the first host material. The second dopant has fluorescent and/or phosphorescent properties and luminescence thereof exhibits the maximum intensity at a second wavelength shorter than the first wavelength. | 2011-09-29 |
20110233605 | Semiconductor power device layout for stress reduction - A semiconductor power device layout with stripe cell structures is disclosed. The inventive structure applies horizontal gate trenches array and vertical gate trenches array alternatively arranged in single device (one or two directions) to balance out the stress caused from one direction. Furthermore, the inventive semiconductor power device provides gate connection trenches connecting to vertical gate trenches and/or horizontal trenches to reduce gate resistance Rg when gate trench length is long. | 2011-09-29 |
20110233606 | Avalanche capability improvement in power semiconductor devices - A power semiconductor device with improved avalanche capability structures is disclosed. By forming at least an avalanche capability enhancement doped regions with opposite conductivity type to epitaxial layer underneath an ohmic contact doped region which surrounds at least bottom of trenched contact filled with metal plug between two adjacent gate trenches, avalanche current is enhanced with the disclosed structures. | 2011-09-29 |
20110233607 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type, a second semiconductor region of the first conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a control electrode. The first semiconductor region is provided selectively on a first major surface of the first semiconductor layer. The second semiconductor region is provided selectively on the first major surface in contact with the first semiconductor region. The third semiconductor region is provided selectively on a surface of the first semiconductor region. The fourth semiconductor region is provided to face a projecting surface between a side surface and a bottom surface of the first semiconductor region with the second semiconductor region interposed. The control electrode is provided on the first semiconductor layer, the first semiconductor region, the second semiconductor region, and the third semiconductor region via an insulating film. | 2011-09-29 |
20110233608 | CONNECTION ARRANGEMENT FOR SEMICONDUCTOR POWER MODULES - A semiconductor power module includes at least two sub modules. The sub modules include at least one respective transistor having a collector, an emitter, and a gate. The module includes a connection arrangement having a collector terminal unit for connecting the collectors of the at least two sub modules collectively to external circuit components, at least two emitter terminal units for connecting the respective emitters of the at least two sub modules individually to external circuit components, and at least two gate terminal units for connecting the respective gates of the at least two sub modules individually to external circuit components. | 2011-09-29 |
20110233609 | Method for Producing Infrared-Photosensitive Matrix Cells Adhering to an Optically Transparent Substrate by Molecular Adhesion, and Related Sensor - The invention relates to a method for producing an infrared radiation sensor, said sensor comprising an infrared photodiode array formed in a first material and a reading circuit formed in a second material, said method comprising the steps of: sticking, through molecular adhesion, a first material side surface onto an optically transparent crystalline material side surface having infrared radiation and a coefficient of thermal expansion similar to that of the second material, give or take 20%; thinning the body of the first material side surface so that the latter is less that 25 μm; producing infrared-sensitive photodiodes onto the thus-thinned first material side surface; depositing contact ball bearings onto the infrared photodiodes; and mounting the reading circuit onto the first material side surface through flip chip technology. | 2011-09-29 |
20110233610 | Nonvolatile Memory Devices Having Memory Cell Transistors Therein with Lower Bandgap Source/Drain Regions - Nonvolatile memory devices include a plurality of nonvolatile memory cell transistors having respective channel regions within a semiconductor layer formed of a first semiconductor material and respective source/drain regions formed of a second semiconductor material, which has a smaller bandgap relative to the first semiconductor material. The source/drain regions can form non-rectifying junctions with the channel regions. The source/drain regions may include germanium (e.g., Ge or SiGe regions), the semiconductor layer may be a P-type silicon layer and the source/drain regions of the plurality of nonvolatile memory cell transistors may be P-type germanium or P-type silicon germanium. | 2011-09-29 |
20110233611 | SEMICONDUCTOR DEVICE HAVING ANALOG TRANSISTOR WITH IMPROVED OPERATING AND FLICKER NOISE CHARACTERISTICS AND METHOD OF MAKING SAME - A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1. | 2011-09-29 |
20110233612 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device having a High Electron Mobility Transistor (HEMT) structure allowing for enhanced performance and a method of manufacturing the same. The semiconductor device includes a base substrate; a semiconductor layer provided on the base substrate; a source electrode, a gate electrode and a drain electrode provided on the semiconductor layer to be spaced apart from one another; and an ohmic-contact layer partially provided at an interface between the drain electrode and the semiconductor layer. | 2011-09-29 |
20110233613 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There are provided a semiconductor device and a method for manufacturing the same. The semiconductor device according to the present invention includes a base substrate; a semiconductor layer that includes a receiving groove and a protrusion part formed on the base substrate, a first carrier injection layer and at least two insulating layers formed to traverse the first carrier injection layer formed in the semiconductor layer, and a second carrier injection layer spaced apart from the first carrier injection layer formed on the protrusion part; a source electrode and a drain electrode that are disposed to be spaced apart from each other on the semiconductor layer; and a gate electrode that is insulated from the source electrode and the drain electrode and has a recess part recessed into the receiving groove, wherein the lowest end portion of the receiving groove contacts the uppermost layer of the first carrier injection layer and the insulating pattern disposed at the innermost side of the semiconductor layer among the insulating patterns traverses the entire layer forming the first carrier injection layer and is disposed at the outer side of both side end portions in the thickness direction of the receiving groove. | 2011-09-29 |
20110233614 | COMPOUND SEMICONDUCTOR EPITAXIAL SUBSTRATE AND MANUFACTURING METHOD THEREOF - A compound semiconductor epitaxial substrate having a pseudomorphic high electron mobility field effect transistor structure including an InGaAs layer as a strained channel layer and an AlGaAs layer containing n type impurities as a front side electron-donating layer, wherein said substrate contains an InGaP layer in an orderly state on the front side of the above described InGaAs layer as the strained channel layer. | 2011-09-29 |
20110233615 | SEMICONDUCTOR DEVICE - To provide a semiconductor device in which a rectifying element capable of reducing a leak current in reverse bias when a high voltage is applied and reducing a forward voltage drop Vf and a transistor element are integrally formed on a single substrate. | 2011-09-29 |
20110233616 | GERMANIUM BASED METAL-INSULATOR TRANSITION THIN FILM, METAL-INSULATOR TRANSITION DEVICE INCLUDING THE METAL-INSULATOR TRANSITION THIN FILM, AND METHOD OF FABRICATING THE METAL-INSULATOR TRANSITION DEVICE - Provided are a germanium (Ge) based metal-insulator transition (MIT) thin film which is formed of a Ge single-element material instead of a compound material of two or more elements and by which material growth may be easily performed and a problem of a second phase characteristic in accordance with a structural defect and an included impurity may be solved, an MIT device including the MIT thin film, and a method of fabricating the MIT device. The MIT device includes a substrate; a germanium (Ge) based MIT thin film which is formed of a Ge single-element material on the substrate and in which a discontinuous MIT occurs at a predetermined transition voltage; and at least two thin film electrodes contacting the Ge based MIT thin film, wherein the discontinuous MIT occurs in the Ge based MIT thin film due to a voltage or a current which is applied through the thin film electrodes. | 2011-09-29 |
20110233617 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors. | 2011-09-29 |
20110233618 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor memory device and a method of manufacturing the same of the embodiments are provided. The non-volatile semiconductor memory device includes: drain contact plugs formed in memory cell regions and having bottom ends joined to drain diffusion layers of the respective memory cells; a local interconnect provided to extend in a WL direction across the memory cell regions and a shunt region, and having a bottom end joined commonly to plural source diffusion layers; drain via plugs formed in the memory cell regions and having bottom ends joined to the top ends of the respective drain contact plugs; and a power supply via for source formed in the shunt region to extend in a BL direction, and having a bottom end joined to the top end of the local interconnect. | 2011-09-29 |
20110233619 | EXPOSURE MASK USED FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING IMPURITY LAYER AND A SEMICONDUCTOR DEVICE - An exposure mask according to an embodiment of the invention includes a first transmission region where a plurality of dots through which light is shielded or transmitted are arrayed into a matrix form having rows and columns and a second transmission region where a plurality of dots through which the light is shielded or transmitted are arrayed into a matrix form having rows and columns and is disposed adjacent to the first transmission region. | 2011-09-29 |
20110233620 | PHOTOELECTRIC CONVERSION APPARATUS, IMAGE PICKUP SYSTEM, AND MANUFACTURING METHOD THEREFOR - A photoelectric conversion apparatus includes a semiconductor substrate on which a photoelectric conversion element and a transistor are arranged and a plurality of wiring layers including a first wiring layer and a second wiring layer above the first wiring layer, in which a connection between the semiconductor substrate and any of the plurality of wiring layers, between a gate electrode of the transistor and any of the plurality of wiring layers, or between the first wiring layer and the second wiring layer, has a stacked contact structure. | 2011-09-29 |
20110233621 | Wafer Level Packaging Bond - The present disclosure provides a method of bonding a plurality of substrates. In an embodiment, a first substrate includes a first bonding layer. The second substrate includes a second bonding layer. The first bonding layer includes silicon; the second bonding layer includes aluminum. The first substrate and the second substrate are bonded forming a bond region having an interface between the first bonding layer and the second bonding layer. A device having a bonding region between substrates is also provided. The bonding region includes an interface between a layer including silicon and a layer including aluminum. | 2011-09-29 |
20110233622 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device comprises an active area extending in a first direction, a contact plug located on a first portion of the active area, and a transistor located on a second portion adjacent to the first portion of the active area in the first direction. A width of a top surface area of the first portion in a second direction perpendicular to the first direction is smaller than that of a top surface area of the second portion in the second direction. | 2011-09-29 |
20110233623 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided a semiconductor device and a method of manufacturing the same. The semiconductor device includes a base substrate; a semiconductor layer having a receiving groove, a protrusion part, a first carrier injection layer, at least two insulating patterns, and a second carrier injection layer provided on the base substrate, the insulating patterns being disposed to traverse the first carrier injection layer and the second carrier injection layer being spaced apart from the first carrier injection layer and disposed on a lower portion of the protrusion part; a source electrode and a drain electrode disposed to be spaced apart from each other on the semiconductor layer; and a gate electrode insulated from the source electrode and the drain electrode and having a recess part recessed into the receiving groove, wherein a lowest portion of the receiving groove contacts an uppermost layer of the first carrier injection layer or is disposed above the uppermost layer thereof, and an insulating pattern, disposed at an innermost portion of the semiconductor layer among the insulating patterns, traverses the first carrier injection layer and is disposed at the outside of both sides of the receiving groove in a thickness direction thereof. | 2011-09-29 |
20110233624 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - One aspect of the present invention is a semiconductor device includes: source and drain regions; a gate electrode formed on the source and drain regions; a sidewall formed on a side surface of the gate electrode; a first silicide film formed on the source and drain regions a predetermined distance away from the sidewall; and a second silicide film formed on the gate electrode a predetermined distance away from the sidewall. | 2011-09-29 |
20110233625 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor chip; and a scribe line disposed in an adjacent way to and around the semiconductor chip. The scribe line comprises an interlayer insulating film and an accessory. The accessory comprises a first portion with a layer shape formed on the interlayer insulating film and a second portion extending downward from the first portion into the interlayer insulating film in a thickness direction thereof. | 2011-09-29 |
20110233626 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device capable of improving the driving power and a manufacturing method therefor are provided. In a semiconductor device, a gate structure formed by successively stacking a gate oxide film and a silicon layer is arranged over a semiconductor substrate. An oxide film is arranged long the lateral side of the gate structure and another oxide film is arranged along the lateral side of the oxide film and the upper surface of the substrate. In the side wall oxide film comprising these oxide films, the minimum value of the thickness of the first layer along the lateral side of the gate structure is less than the thickness of the second layer along the upper surface of the substrate. | 2011-09-29 |
20110233627 | MOS STRUCTURES THAT EXHIBIT LOWER CONTACT RESISTANCE AND METHODS FOR FABRICATING THE SAME - MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. With the gate stack serving as a mask, impurity dopants are implanted into a semiconductor material having a first surface and disposed proximate to the gate stack. A trench is etched into the semiconductor material such that the semiconductor material has a trench surface within the trench. Further, a metal silicide layer is formed on the first surface of the semiconductor material and on the trench surface. Also, a contact to at least a portion of the metal silicide layer on the first surface and at least a portion of the metal silicide layer on the trench surface is fabricated. | 2011-09-29 |
20110233628 | FIELD EFFECT TRANSISTOR SWITCH FOR RF SIGNALS AND METHOD OF MAKING THE SAME - A switching device has an input node, an output node, and a control node. The device includes: a substrate having a first side and a second side with a ground plane on the first side of the substrate and a mesa on the second side of the substrate. The mesa is made of a normally-conductive semiconductor material, and an isolation region substantially surrounds the mesa. A field effect transistor (FET) is on the mesa. The FET has an input terminal connected to the input node, an output terminal connected to the output node, and a gate. A capacitor is connected in series between the output terminal of the FET and the gate, and a resistor is connected in series between the control node and the gate. A gate electrode is directly connected to the gate. The gate electrode is disposed substantially entirely on the mesa. | 2011-09-29 |
20110233629 | Integrated Circuit Devices Having High Density Logic Circuits Therein Powered Using Multiple Supply Voltages - Integrated circuit devices include a substrate having a semiconductor substrate region therein containing multiple well regions of different conductivity type. A first semiconductor well region of first conductivity type is provided in the semiconductor substrate region. This first semiconductor well region has a first plurality of transistor regions therein arranged in a first zig-zag pattern extending across the semiconductor substrate region. A second semiconductor well region of second conductivity type is also provided in the semiconductor substrate region. This second semiconductor well region has a second plurality of transistor regions therein arranged in a second zig-zag pattern extending across the semiconductor substrate region. This second zig-zag pattern is intertwined with the first zig-zag pattern. A plurality of first transistors of second conductivity type are provided in the first plurality of transistor regions and a plurality of second transistors of first conductivity type are provided in the second plurality of transistors regions. | 2011-09-29 |
20110233630 | INTEGRATED CIRCUIT HAVING A SEMICONDUCTOR SUBSTRATE WITH BARRIER LAYER - An integrated circuit having a semiconductor substrate with a barrier layer is disclosed. The arrangement includes a semiconductor substrate and a metallic element. A carbon-based barrier layer is disposed between the semiconductor substrate and the metallic element. | 2011-09-29 |
20110233631 | VERTICALLY STACKED FUSION SEMICONDUCTOR DEVICE - A vertically stacked fusion semiconductor device includes a channel portion which extends in a first direction with respect to a surface of a semiconductor layer, a common source line which extends in a second direction different from the first direction and is electrically connected to the channel portion, a first gate structure which is electrically connected to the common source line via the channel portion and a second gate structure which is electrically connected to the common source line via the channel portion and is on an opposite side of the common source line to the first gate structure. | 2011-09-29 |
20110233632 | SEMICONDUCTOR SEAL-RING STRUCTURE AND THE MANUFACTURING METHOD THEREOF - A seal-ring structure includes a substrate, a source/drain layer, a first dielectric layer, a first lower metal layer, a gate layer and a second lower metal layer. The source/drain layer is disposed within the substrate. The first dielectric layer is disposed over the substrate. The first lower metal layer is disposed over the first dielectric layer and coupled to the source/drain layer via a first contact. The gate layer is disposed within the first dielectric layer. The second lower metal layer is disposed over the first dielectric layer and coupled to the gate layer via a second contact. | 2011-09-29 |
20110233633 | Semiconductor Device and Electronic Apparatus Having the Same - With an offset circuit including transistors of the same conductivity type, offset of an input signal is performed. Then, the input signal after the offset is supplied to a logic circuit including transistors of the same conductivity type as that of the offset circuit, thereby H and L levels of the input signal can be shifted at the same time. Further, since the offset circuit and the logic circuit are formed using the transistors of the same conductivity type, a display device can be manufactured at a low cost. | 2011-09-29 |
20110233634 | Embedded DRAM Integrated Circuits with Extremely Thin Silicon-On-Insulator Pass Transistors - Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor. | 2011-09-29 |
20110233635 | SEMICONDUCTOR TRENCH STRUCTURE HAVING A SEALING PLUG - In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core. | 2011-09-29 |
20110233636 | Semiconductor Memory Device and Method of Manufacturing the Same - A non-volatile memory device and a method of manufacturing the non-volatile memory device are disclosed. The non-volatile memory device includes a substrate, at least two gate structures on the substrate, and at least one impurity region in portions of the substrate between the at least two gate structures. The center of the at least one impurity region is horizontally offset from the center of a region between the at least two gate structures. | 2011-09-29 |
20110233637 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a method for manufacturing a semiconductor device comprises forming a first insulating film on a semiconductor substrate, processing the first insulating film into a predetermined pattern, forming a first gate electrode structure on the first insulating film, the first gate electrode structure having a smaller width than that of the processed first insulating film in a channel length direction, introducing a first impurity of a first conductivity type into the semiconductor substrate via the processed first insulting film using the first gate electrode structure as a mask, and introducing a second impurity of the first conductivity type into the semiconductor substrate using the first gate electrode structure and the first insulating film as a mask. | 2011-09-29 |
20110233638 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - The present invention provides a semiconductor device including a semiconductor substrate provided with a trench section; a tunnel insulating film covering an inner surface of the trench section; a trap layer provided in contact with the tunnel insulating film on an inner surface of an upper portion of the trench section; a top insulating film provided in contact with the trap layer; a gate electrode embedded in the trench section, and provided in contact with the tunnel insulating film at a lower portion of the trench section and in contact with the top insulating film at the upper portion of the trench section, in which the trap layer and the top insulating film, in between the lower portion of the trench section and the upper portion of the trench section, extend and protrude from both sides of the trench section so as to be embedded in the gate electrode, and a method for manufacturing thereof. | 2011-09-29 |
20110233639 | SEMICONDUCTOR DEVICE - To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device. | 2011-09-29 |
20110233640 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a substrate; a gate insulating film; first trenches in a cell array region; first embedded insulating films in the first trenches; second trenches in a peripheral circuit region; second embedded insulating films in the second trenches; a third trench in an isolation region; a third embedded insulating film in the third trench; gate structures; and inter-gate insulating films between the gate structures covering the first, second and third embedded insulating films. An upper surface of the third embedded insulating film covered with the inter-gate insulating film is substantially flat. Upper surfaces of the first, second, and third embedded insulating films are higher than an upper surface of the gate insulating film. The upper surfaces of the first and third embedded insulating films are lower than the upper surfaces of the second embedded insulating films. | 2011-09-29 |
20110233641 | NON-VOLATILE MEMORY CELL DEVICES AND METHODS - A method of fabricating a memory cell including forming nanodots over a first dielectric layer and forming an intergate dielectric layer over the nanodots, where the intergate dielectric layer encases the nanodots. To form sidewalls of the memory cell, a portion of the intergate dielectric layer is removed with a dry etch, where the sidewalls include a location where a nanodot has been deposited. A spacing layer is formed over the sidewalls to cover the location where a nanodot has been deposited and the remaining portion of the intergate dielectric layer and the nanodots can be removed with an etch selective to the intergate dielectric layer. | 2011-09-29 |
20110233642 | SEMICONDUCTOR DEVICE - One or more embodiments relate to a memory device, comprising: a substrate; a gate stack disposed over the substrate, the gate stack comprising a control gate disposed over a charge storage layer; and a spacer select gate disposed over the substrate and laterally disposed from the gate stack, the select gate comprising a carbon allotrope. | 2011-09-29 |
20110233643 | PMOS Flash Cell Using Bottom Poly Control Gate - A two-transistor PMOS memory cell has a selective gate (SG) PMOS and a floating gate (FG) PMOS is provided. A control gate, overlapping the floating gate of the FG PMOS, of the memory cell is made by a polysilicon layer and located on an isolation structure. | 2011-09-29 |
20110233644 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars. The fifth interconnection is connected to the third interconnection on a side opposite to the selection unit stacked structural body. | 2011-09-29 |
20110233645 | MANUFACTURING METHOD OF NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a manufacturing method of a nonvolatile semiconductor storage device, includes: forming a plurality of structures above a semiconductor substrate, each of the plurality of structures being such that in a stacked film where a plurality of first semiconductor films and a plurality of second semiconductor films are stacked alternately at least the second semiconductor films are held by a semiconductor or conductor pillar member via a gate dielectric film; selectively removing the first semiconductor films from the stacked film while maintaining a state where the second semiconductor films are held by the pillar member for each of the structures; oxidizing an exposed surface for each of the structures after removing the first semiconductor films; and embedding an inter-layer dielectric film between the plurality of structures in which the exposed surface is oxidized. | 2011-09-29 |
20110233646 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device is provided in which memory strings, which are formed by providing a plurality of transistors having gate electrode films on sides of columnar semiconductor films in a height direction of the columnar semiconductor films via charge storage layers, are substantially perpendicularly arranged in a matrix shape on a substrate. A coupling section made of a semiconductor material that connects lower portions of the columnar semiconductor films forming a pair of the memory strings adjacent to each other in a predetermined direction is provided. Each of the columnar semiconductor films is formed of a generally single-crystal-like germanium film or silicon germanium film. | 2011-09-29 |
20110233647 | METHODS FOR FORMING A MEMORY CELL HAVING A TOP OXIDE SPACER - Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer. | 2011-09-29 |
20110233648 | Three-Dimensional Semiconductor Memory Devices And Methods Of Fabricating The Same - Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns. | 2011-09-29 |
20110233649 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes: a charge accumulation layer (CAL) on a substrate; a memory gate formed onto the substrate through the CAL; a first side gate formed through a first insulating film on a first side of the memory gate; a second side gate formed through a second insulating film on a second side opposite to the first side; a first impurity implantation region (IIR | 2011-09-29 |
20110233650 | NONVOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - Provided are nonvolatile memory devices and methods of forming nonvolatile memory devices. Nonvolatile memory devices include a device isolation layer that defines an active region in a substrate. Nonvolatile memory devices further include a first insulating layer, a nonconductive charge storage pattern, a second insulating layer and a control gate line that are sequentially disposed on the active region. The charge storage pattern includes a horizontal portion and a protrusion disposed on an upper portion of an edge of the horizontal portion. | 2011-09-29 |
20110233651 | METHOD TO SEPERATE STORAGE REGIONS IN THE MIRROR BIT DEVICE - Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line. | 2011-09-29 |
20110233652 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers. | 2011-09-29 |
20110233653 | NON-VOLATILE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR DEVICES - A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate. | 2011-09-29 |
20110233654 | NANO-CRYSTAL GATE STRUCTURE FOR NON-VOLATILE MEMORY - A non-volatile memory device is disclosed having a charge storage layer that incorporates a plurality of nano-crystals. A substrate having a source region and a drain region is provided. Select and control gates are formed on the substrate. The charge storage layer is provided between the control gate and the substrate. The nano-crystals in the charge storage layer have a size of about 1 nm to about 10 nm, and may be formed of Silicon or Germanium. Writing operations are accomplished via hot electron injection, FN tunneling, or source-side injection. Erase operations are accomplished using FN tunneling. The control gate is formed of a single layer of polysilicon, which reduces the total number of processing steps required to form the device, thus reducing cost. | 2011-09-29 |
20110233655 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, in a semiconductor memory device, a source region and a drain region are disposed away from each other in the semiconductor layer. A tunnel insulating film is formed between the source region and the drain region on the semiconductor layer. A charge accumulating film includes an oxide cluster and is formed on the tunnel insulating film. A block insulating film is formed on the charge accumulating film. A gate electrode is formed on the block insulating film. The oxide cluster includes either Zr or Hf, and further contains at least one element selected from Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, Ta, W, Re, Os, Ir, Pt, Au and Hg. | 2011-09-29 |
20110233656 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type, first semiconductor pillar regions of the first conductivity type and second semiconductor pillar regions of a second conductivity type, a semiconductor region of the first conductivity type, a base region of the second conductivity type, a source region, a first main electrode, a second main electrode and a control electrode. The second semiconductor pillar region includes a plurality of semiconductor regions of the second conductivity type. A difference is provided between peak values of impurity concentration profiles of an uppermost and a lowermost semiconductor regions of the plurality of semiconductor regions, and in the alternately arranging direction of the first and second semiconductor pillar regions, maximum width of the uppermost semiconductor region is generally equal to or narrower than maximum width of the lowermost semiconductor region. | 2011-09-29 |
20110233657 | High-voltage vertical transistor with a varied width silicon pillar - In one embodiment, a vertical HVFET includes a pillar of semiconductor material a pillar of semiconductor material arranged in a loop layout having at least two substantially parallel and substantially linear fillet sections each having a first width, and at least two rounded sections, the rounded sections having a second width narrower than the first width, a source region of a first conductivity type being disposed at or near a top surface of the pillar, and a body region of a second conductivity type being disposed in the pillar beneath the source region. First and second dielectric regions are respectively disposed on opposite sides of the pillar, the first dielectric region being laterally surrounded by the pillar, and the second dielectric region laterally surrounding the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. | 2011-09-29 |
20110233658 | ELECTRONIC DEVICE INCLUDING AN INSULATING LAYER HAVING DIFFERENT THICKNESSES AND A CONDUCTIVE ELECTRODE AND A PROCESS OF FORMING THE SAME - An electronic device includes a transistor, wherein the electronic device can include a semiconductor layer having a primary surface, a channel region, a gate electrode, a source region, a conductive electrode, and an insulating layer lying between the primary surface of the semiconductor layer and the conductive electrode. The insulating layer has a first region and a second region, wherein the first region is thinner than the second region. The channel region, gate electrode, source region, or any combination thereof can lie closer to the first region than the second region. The thinner portion can allow for faster switch of the transistor, and the thicker portion can allow a relatively large voltage difference to be placed across the insulating layer. Alternative shapes for the transitions between the different regions of the insulating layer and exemplary methods to achieve such shapes are also described. | 2011-09-29 |
20110233659 | SEMICONDUCTOR POWER DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor power device is provided, and a manufacturing method thereof includes the following steps. First, a substrate is provided, and an epitaxial layer is formed on the substrate. Then, at least a first trench and at least a second trench are formed in the epitaxial layer. Subsequently, a shield electrode and a termination electrode are respectively formed in the first trench and the second trench, and upper sidewalls of the first trench and the second trench are exposed. Following that, a gate dielectric layer is covered. Then, a second conductive layer is deposited to fill up the first trench and partially fill in the second trench. Subsequently, the second conductive layer is etched to remove the second conductive layer in the second trench and form a gate electrode in the first trench. Accordingly, the present invention can reduce the number of masks. | 2011-09-29 |
20110233660 | SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF - A downwardly convex bowed shape is given to an upper edge Tw | 2011-09-29 |
20110233661 | SEMICONDUCTOR MEMORY DEVICE WITH FIN - According to one embodiment, a semiconductor memory device includes a fin-shaped active area, a gate electrode, a silicide layer, and a contact. The fin-shaped active area is provided in a semiconductor substrate and has a first side, a second side parallel to the first side, and a top face connecting the first and second sides. The gate electrode is formed in a trench formed in the active area such that it crosses the trench and is a part of a word line insulated from the active area. The silicide layer is located in the active area on either side of the gate electrode and is formed at least on the first side of the active area serving as a source and a drain region. The contact is connected to the silicide layer and connects at least a storage element. | 2011-09-29 |
20110233662 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate; a bit line; and a contact portion. The semiconductor substrate has a first groove having at least first and second side surfaces facing each other. The bit line is positioned in the first groove. The bit line is insulated from the semiconductor substrate. The contact portion is positioned in the first groove. The contact portion is electrically connected to the bit line. The contact portion contacts the first side surface of the first groove. The contact portion is insulated from the second side surface of the first groove. | 2011-09-29 |
20110233663 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A body contact layer | 2011-09-29 |
20110233664 | Semiconductor device and a method of manufacturing the same - A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p | 2011-09-29 |
20110233665 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate trench | 2011-09-29 |
20110233666 | OXIDE TERMINATED TRENCH MOSFET WITH THREE OR FOUR MASKS - An oxide termination semiconductor device may comprise a plurality of gate trenches, a gate runner, and an insulator termination trench. The gate trenches are located in an active region. Each gate trench includes a conductive gate electrode. The insulator termination trench is located in a termination region that surrounds the active region. The insulator termination trench is filled with an insulator material to form an insulator termination for the semiconductor device. The device can be made using a three-mask or four-mask process. | 2011-09-29 |
20110233667 | DUAL GATE OXIDE TRENCH MOSFET WITH CHANNEL STOP TRENCH AND THREE OR FOUR MASKS PROCESS - A semiconductor device and fabrication methods are disclosed. The device includes a plurality of gate electrodes formed in trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the substrate and electrically connected to the gate electrodes, wherein the first gate runner surrounds the active region. A second gate runner is connected to the first gate runner and located between the active region and a termination region. A termination structure surrounds the first and second gate runners and the active region. The termination structure includes a conductive material in an insulator-lined trench in the substrate, wherein the termination structure is electrically shorted to a source or body layer of the substrate thereby forming a channel stop for the device. | 2011-09-29 |
20110233668 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a base region of a second conductivity type, a drift region of a first conductivity type, an insulating layer, a drain region of the first conductivity type, a gate oxide film, a gate electrode, a first main electrode, and a second main electrode. The base region includes a source region of the first conductivity type. The drift region is adjacent to the base region. The insulating layer is provided from a surface to inside of the drift region. The drain region is provided in the surface of the drift region and opposed to the source region across the base region and the insulating layer. The gate oxide film is provided on a surface of the base region. The gate electrode is provided on the gate oxide film. The first main electrode is connected to the source region. The second main electrode is connected to the drain region. As viewed in a direction perpendicular to the surface of the base region, the source region and at least a part of the drain region extend generally parallel in a line shape, and a length of a portion of the drift region sandwiched between the insulating layer and the base region is shorter in the generally parallel extending direction than in a direction generally perpendicular to the generally parallel extending direction. | 2011-09-29 |
20110233669 | Semiconductor device having depletion type MOS transistor - Provided is an improved depletion type MOS transistor for a semiconductor device, including: a first conductivity type well region on a semiconductor substrate; a gate insulating film formed on the well region; a gate electrode formed on the gate insulating film; second conductivity type source/drain regions formed on both sides of the gate electrode; a low concentration second conductivity type impurity region formed below the gate insulating film between the source/drain regions; and a low concentration first conductivity type impurity region formed below the low concentration second conductivity type impurity region between the source/drain regions. | 2011-09-29 |
20110233670 | METHOD OF FORMING A REGION OF GRADED DOPING CONCENTRATION IN A SEMICONDUCTOR DEVICE AND RELATED APPARATUS - A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile. | 2011-09-29 |
20110233671 | THRESHOLD VOLTAGE ADJUSTMENT OF A TRANSISTOR - A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed. | 2011-09-29 |
20110233672 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor structure is provided. A second conductivity type well region is formed on a first conductivity type substrate. A second conductivity type diffused source and second conductivity type diffused drain are formed on the first conductivity type substrate. A gate structure is formed on the second conductivity type well region between the second conductivity type diffused source and the second conductivity type diffused drain. First conductivity type buried rings are arranged in a horizontal direction, and formed in the second conductivity type well region, and divide the second conductivity type well region into an upper drift region and a lower drift region. | 2011-09-29 |
20110233673 | LATERAL-DIFFUSION METAL-OXIDE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a lateral-diffusion metal-oxide semiconductor (LDMOS) device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a first region and a second region both having a first conductive type in the semiconductor substrate, wherein the first region not contacting the second region; and performing a thermal process to diffuse the dopants within the first region and the second region into the semiconductor substrate to form a deep well, wherein the doping concentration of the deep well is less than the doping concentration of the first region and the second region. | 2011-09-29 |
20110233674 | Design Structure For Dense Layout of Semiconductor Devices - A semiconductor structure, and a method of making, includes: a substrate; and at least one layer of silicon overlying the substrate, the layer of silicon including at least one active region having at least one device, a design layout of the active region in accordance with design layout rules including: a multiple-fingered device is mapped to a symmetric device or an asymmetric body-tied device; a single-fingered device is mapped to an asymmetric device; an active region having a single-fingered device is entirely source-up or source-down; and an active region falls into one of two categories: the active region does not include any symmetric devices or the active region does not include any asymmetric devices. In another exemplary embodiment, a design structure tangibly embodied on a computer readable medium, for use by a machine in the design, manufacture or simulation of an integrated circuit having the above semiconductor structure. | 2011-09-29 |
20110233675 | SRAM-TYPE MEMORY CELL - An SRAM-type memory cell that includes a semiconductor on insulator substrate having a thin film of semiconductor material separated from a base substrate by an insulating layer; and six transistors such as two access transistors, two conduction transistors and two charge transistors arranged so as to form with the conduction transistors two back-coupled inverters. Each of the transistors has a back control gate formed in the base substrate below the channel and able to be biased in order to modulate the threshold voltage of the transistor, with a first back gate line connecting the back control gates of the access transistors to a first potential and a second back gate line connecting the back control gates of the conduction transistors and charge transistors to a second potential. The first and second potentials can be modulated according to the type of cell control operation. | 2011-09-29 |
20110233676 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors. | 2011-09-29 |