39th week of 2013 patent applcation highlights part 35 |
Patent application number | Title | Published |
20130250668 | MAGNETIC MEMORY ELEMENT, MAGNETIC MEMORY, AND MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory element includes: a magnetic wire, a stress application unit, and a recording/reproducing unit. The magnetic wire includes a plurality of domain walls and a plurality of magnetic domains separated by the domain walls. The magnetic wire is a closed loop. The stress application unit is configured to cause the domain walls to circle around along the closed loop a plurality of times by applying stress to the magnetic wire. The recording/reproducing unit is configured to write memory information by changing magnetizations of the circling magnetic domains as the domain walls circle around and to read the written memory information by detecting the magnetizations of the circling magnetic domains. | 2013-09-26 |
20130250669 | Scalable Magnetic Memory Cell With Reduced Write Current - One embodiment of a magnetic random access memory includes a magnetic memory cell comprising a magnetoresistive element including a free ferromagnetic layer comprising a reversible magnetization direction directed substantially perpendicular to a film plane in its equilibrium state, a pinned ferromagnetic layer comprising a fixed magnetization direction directed substantially perpendicular to the film plane, a tunnel barrier layer disposed between the free and pinned layers, and an assist ferromagnetic layer disposed adjacent to the free layer; means for providing a bias magnetic field pulse along a magnetic hard axis of the free layer, means for providing a spin-polarized current pulse through the magnetoresistive element in a direction perpendicular to the film plane, wherein the magnetization direction in the free layer is reversed by a collective effect of the bias magnetic field pulse and the spin-polarizing current pulse. Other embodiments are described and shown. | 2013-09-26 |
20130250670 | MAGNETORESISTIVE ELEMENT AND WRITING METHOD OF MAGNETIC MEMORY - According to one embodiment, a magnetoresistive element includes a first magnetic layer, a second magnetic layer, a non-magnetic layer formed between the first magnetic layer and the second magnetic layer, a charge storage layer having a first surface and a second surface different from the first surface, the first surface facing the second magnetic layer, a first insulating layer formed between the second magnetic layer and the first surface of the charge storage layer, and a second insulating layer formed on the second surface of the charge storage layer. | 2013-09-26 |
20130250671 | THERMALLY ASSISTED MAGNETIC WRITING DEVICE - A thermally assisted magnetic writing device including a first magnetic layer known as the “reference layer,” a second magnetic layer known as the “storage layer” that presents a variable magnetization direction, a spacer situated between the reference layer and the storage layer and a first antiferromagnetic layer in contact with the storage layer, the first antiferromagnetic layer being able to trap the magnetization direction of the storage layer. The magnetic device also includes a stabilization layer made of a ferromagnetic material, the stabilization layer being in contact with the first antiferromagnetic layer. | 2013-09-26 |
20130250672 | SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BIT LINES - An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. | 2013-09-26 |
20130250673 | Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bit Lines - An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. | 2013-09-26 |
20130250674 | REFRESHING DATA OF MEMORY CELLS WITH ELECTRICALLY FLOATING BODY TRANSISTORS - A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle. | 2013-09-26 |
20130250675 | Method and Apparatus for Reducing Erase Disturb of Memory By Using Recovery Bias - A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part. | 2013-09-26 |
20130250676 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has a nonvolatile storage region, a voltage generating circuit that generates an operational voltage for the storage region, and a control circuit that sends the voltage generated by the voltage generating circuit to the storage region. The voltage generating circuit has a transistor, a first resistance element, a second resistance element, and a comparator. The first resistance element and the second resistance element have wiring structure for resistance. The resistance wiring in the wiring structure has the same line width as the finest line width in the wiring formed in the storage region. | 2013-09-26 |
20130250677 | NONVOLATILE MEMORY DEVICE, NONVOLATILE MEMORY SYSTEM, AND PROGRAM METHOD OF THE SAME - Disclosed is a method for programming a nonvolatile memory device, which includes memory cells arranged in a plurality of rows. The programming method includes alternately selecting word lines to program data at a first page portion and a second page portion associated with the memory cells. After the first and second page portions are programmed, the method includes programming data at a third page portion associated with the memory cells according to an order in which word lines are arranged. The word lines may be sequentially selected one by one from a word line adjacent to a ground selection line. | 2013-09-26 |
20130250678 | PAGE BUFFER, MEMORY DEVICE COMPRISING PAGE BUFFER, AND RELATED METHOD OF OPERATION - A page buffer comprises a static latch configured to store data received from an external device, and a dynamic latch configured to receive the data stored in the static latch through a floating node, the dynamic latch comprising a storage capacitor, a write transistor configured to write the data of the floating node to the storage capacitor, and a read transistor configured to read the data of the storage capacitor, and the write transistor and the read transistor sharing the floating node. | 2013-09-26 |
20130250679 | NAND STEP UP VOLTAGE SWITCHING METHOD - Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired. | 2013-09-26 |
20130250680 | METHODS OF PROGRAMMING SEMICONDUCTOR MEMORY DEVICES - To program a semiconductor memory device, a plurality of target threshold voltage groups are set by dividing target threshold voltages representing states of memory cells. The target threshold voltage groups are substantially simultaneously programmed by applying a plurality of program voltages to a word line. Program end times for the target threshold voltage groups are adjusted. | 2013-09-26 |
20130250681 | NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value. | 2013-09-26 |
20130250682 | METHOD OF PROGRAMMING A MULTI-BIT PER CELL NON-VOLATILE MEMORY - A method of programming a multi-bit per cell non-volatile memory is disclosed. In one embodiment, the non-volatile memory is read to obtain a first data of a most-significant-bit (MSB) page on a current word line that succeeds in data reading, wherein the current word line follows a preceding word line on which data reading fails. At least one reference voltage is set. The MSB page on the current word line is secondly programmed with a second data according to the reference voltage, the second data being different from the first data. | 2013-09-26 |
20130250683 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver. | 2013-09-26 |
20130250684 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device includes memory cells arranged into memory strings with word lines each connected to a different memory cell of the memory strings. The device also includes bit lines each connected to a different memory string and a column decoder connected to the bit lines. The column decoder includes sense amplifiers, data latches, and a data bus connecting sense amplifiers and data latches. The data bus is divided into at least two portions and includes a first portion connected to a second portion by a switch. | 2013-09-26 |
20130250685 | Semiconductor Memory Having Both Volatile and Non-Volatile Functionality and Method of Operating - Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted. | 2013-09-26 |
20130250686 | SEMICONDUCTOR MEMORY DEVICE, INFORMATION PROCESSING SYSTEM AND CONTROL METHOD - According to an embodiment, a semiconductor memory device includes a first storage unit, a receiving unit, an acquiring unit, and an output control unit. The first storage unit is configured to store a value and address information in which a key address generated on the basis of a key associated with the value and a physical address of the value are associated with each other. The receiving unit is configured to receive a request for acquisition of the value associated with the key. The request contains the key. The acquiring unit is configured to acquire the physical address associated with the key address of the key contained in the request for acquisition on the basis of the address information. The output control unit is configured to acquire the value at the acquired physical address from the first storage unit and output the acquired value in response to the request. | 2013-09-26 |
20130250687 | SHARED-BIT-LINE BIT LINE SETUP SCHEME - Methods for operating a non-volatile storage system utilizing a shared-bit-line NAND architecture are described. A shared-bit-line NAND architecture includes one or more pairs of NAND strings, wherein each pair of the one or more pairs of NAND strings shares a common bit line. In some embodiments, a pair of NAND strings includes an odd NAND string adjacent to an even NAND string. Prior to programming a memory cell associated with the even NAND string, an odd channel associated with the odd NAND string (i.e., the NAND string of the pair that is not selected for programming) is precharged to a bit line inhibit voltage, floated, and then boosted to a second voltage greater than the bit line inhibit voltage as an even channel associated with the even NAND string is precharged. Subsequently, the odd channel may be boosted (e.g., via self-boosting) prior to programming the memory cell. | 2013-09-26 |
20130250688 | SELECTED WORD LINE DEPENDENT PROGRAMMING VOLTAGE - Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The duration of a programming pulse may depend on the word line that is selected for programming. This could be a physical characteristic of the word line or its location on a NAND string. As one example, a shorter pulse width may be used for the programming signal when programming edge word lines. | 2013-09-26 |
20130250689 | SELECTED WORD LINE DEPENDENT SELECT GATE DIFFUSION REGION VOLTAGE DURING PROGRAMMING - Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The voltage applied to a common source line may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction, which may prevent or reduce program disturb. The voltage applied to bit lines of unselected NAND strings may depend on the location of the word line that is selected for programming. This may prevent or reduce punch-through conduction. | 2013-09-26 |
20130250690 | SELECTED WORD LINE DEPENDENT SELECT GATE VOLTAGE DURING PROGRAM - Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the location of the word line that is selected for programming, which may reduce or eliminate program disturb. The voltage applied to the gate of a select transistor of a NAND string may depend on the location of the selected word line. This could be either a source side or drain side select transistor. This may prevent or reduce program disturb that could result due to DIBL. This may also prevent or reduce program disturb that could result due to GIDL. A negative bias may be applied to the gate of a source side select transistor when programming at least some of the word lines. In one embodiment, progressively lower voltages are used for the gate of the drain side select transistor when programming progressively higher word lines. | 2013-09-26 |
20130250691 | METHOD OF PROVIDING AN OPERATING VOLTAGE IN A MEMORY DEVICE AND A MEMORY CONTROLLER FOR THE MEMORY DEVICE - A method of providing an operating voltage in a memory device includes applying a read voltage to a selected word line while applying a first pass voltage to at least one unselected word line among word lines adjacent to the selected word line; and while applying a second pass voltage to the remaining unselected word lines (other than the at least one unselected word line to which the first pass voltage is applied). The level of the first pass voltage is higher than the level of the second pass voltage. The level of the first pass voltage may be set based on the level of the read voltage. | 2013-09-26 |
20130250692 | Adaptive Programming For Non-Volatile Memory Devices - Systems and techniques for performing write operations on non-volatile memory are described. A described system includes a memory structure including non-volatile memory cells that are arranged on word lines and bit lines and a microcontroller that is communicatively coupled with the memory structure. The memory structure can include non-volatile memory cells that are arranged on word lines and bit lines. The microcontroller can be configured to receive data to write to the memory structure, write the data to the memory structure using a selected word line of the word lines, detect a failure to write the data, apply, based on the failure, a negative bias voltage to one or more unselected word lines of the word lines during a negative bias period, and write the data to the portion of the memory cells using the selected word line during the negative bias period. | 2013-09-26 |
20130250693 | MEMORY SYSTEM - According to one embodiment, a memory system includes a first semiconductor memory and a controller. The first semiconductor memory receives a first clock, and outputs, in accordance with the first clock, a second clock and a data signal in synchronization with the second clock. The controller includes a detection circuit which detects a shift of a duty ratio of the second clock which is output from the first semiconductor memory. The controller also includes an adjustment circuit which adjusts a duty ratio of the first clock based on the shift detected by the detection circuit. | 2013-09-26 |
20130250694 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first P-well. | 2013-09-26 |
20130250695 | METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE - A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal. | 2013-09-26 |
20130250696 | METHOD OF PROGRAMMING NONVOLATILE MEMORY DEVICE - A method of programming a nonvolatile memory device comprises programming target memory cells among a plurality of memory cells connected to a wordline, performing a first sensing operation on the plurality of memory cells, and selectively performing a second sensing operation on the target memory cells based on a result of the first sensing operation. | 2013-09-26 |
20130250697 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - A semiconductor memory device and the operating method thereof use a low pass voltage to boost a channel of unselected cell strings during a program operation, and boost the channel of the cell string by using the GIDL phenomenon, thereby reducing a disturbance influence on the memory cells connected to the unselected cell strings due to a high pass voltage. | 2013-09-26 |
20130250698 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes strings configured to include a drain select transistor, memory cells, and a source select transistor coupled in series between a bit line and a common source line and peripheral circuits configured to precharge a bit line so that the precharge level of the bit line varies depending on whether an adjacent unselected memory cell is in the program or erase states, by supplying a first voltage to the adjacent unselected memory cell arranged toward the drain select transistor, a second voltage to the remaining memory cells, and a third voltage higher than a bit line precharge voltage to the common source line and perform a read operation of supplying a read voltage lower than the second voltage to the selected memory cell, the second voltage to the remaining memory cells including the adjacent unselected memory cell, and a ground voltage to the common source line. | 2013-09-26 |
20130250699 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region. | 2013-09-26 |
20130250700 | NONVOLATILE MEMORY COMPRISING MINI WELLS AT A FLOATING POTENTIAL - The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells. | 2013-09-26 |
20130250701 | WRITE COMMAND AND WRITE DATA TIMING CIRCUIT AND METHODS FOR TIMING THE SAME - Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write command latch signal. The internal write command latch releases the latched write command in response to the write command latch signal after a latency delay. The timing circuit further includes a write leveling flip-flop (FF) circuit and a write data register. One such method includes generating and latching an internal write command. The latched internal write command is released after a latency delay responsive to the memory clock signal. The internal write command is propagated over an internal write command path. Write data is captured and internal write command latched in response to a write clock signal. The captured write data is released to be written to memory. | 2013-09-26 |
20130250702 | SEMICONDUCTOR MEMORY AND VOLTAGE OUTPUT MEASURING METHOD OF THE SEMICONDUCTOR MEMORY - A semiconductor memory device includes a first comparative device, to which first and second voltages are input; a first capacitor, which accumulates the electrical potential of a first node; a power source, which outputs the first electric current to a second node; a resistor, which generates a third voltage in the second node; a second capacitor, which accumulates the electric potential of the second node; first switches, which make a common connection at a third node possible for the first node and the second node, to which the first capacitor and the second capacitor are connected respectively; and a second comparison device, which uses as an input voltage a fourth voltage, which is obtained as a result of the charge share between the first and the second capacitors and the electrical potential of a fourth node, and equalizes the electrical potential of the fourth node with the fourth voltage. | 2013-09-26 |
20130250703 | OUTPUT DRIVER CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - An output driver circuit includes an on/off-timing control circuit that outputs first and second driving signals based on an input data signal, such that the transition of the second driving signal is faster than the transition of the first driving signal when the input data signal transitions from high level to low level, and the transition of the second driving signal is slower than the transition of the first driving signal when the input data signal transitions from low level to high level. The output driver circuit is further provided with pull-down and pull-up pre-drivers that output pull-down and pull-up signals, respectively, in accordance with the first and second driving signals. The output driver circuit is further provided with pull-down and pull-up main drivers that pull down and pull up the voltage of an output terminal, respectively, in accordance with the pull-down signal and the pull-up signal. | 2013-09-26 |
20130250704 | SEMICONDUCTOR DEVICE HAVING LEVEL SHIFTER - Disclosed herein is a semiconductor device that includes: an internal voltage generator configured to produce an internal voltage in a first mode and stop producing the internal voltage in a second mode; a level shifter configured to receive the internal voltage, a first voltage and a first signal, in order to convert the first signal from a voltage level of internal voltage to a voltage level of the first voltage and output the first signal with the voltage level of the first voltage; and a logic circuit configured to produce the first signal, the logic circuit being supplied with the internal voltage in the first mode and supplied with the first voltage in the second mode. | 2013-09-26 |
20130250705 | CLOCK SIGNAL GENERATION APPARATUS FOR USE IN SEMICONDUCTOR MEMORY DEVICE AND ITS METHOD - A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address. | 2013-09-26 |
20130250706 | MEMORY MODULE - A memory module having memory components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective memory components, and the address/control signal path and clock signal path are coupled in common to all the memory components. The address/control signal path extends along the memory components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective memory components at progressively later times corresponding to relative positions of the memory components. | 2013-09-26 |
20130250707 | REPLACING DEFECTIVE MEMORY BLOCKS IN RESPONSE TO EXTERNAL ADDRESSES - An apparatus has a controller. The controller is configured to address a non-defective memory block of a sequence of memory blocks in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is a proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. The controller is configured to apply a voltage-delay correction to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block. | 2013-09-26 |
20130250708 | MEMORY ELEMENT AND METHOD FOR DETERMINING THE DATA STATE OF A MEMORY ELEMENT - One embodiment of the present invention is directed to an electronic memory ( | 2013-09-26 |
20130250709 | TESTING SYSTEM AND TESTING METHOD THEREOF - A testing system for a wafer having a plurality of flash memory dies is provided. The testing system includes a testing apparatus and a probe card coupled to the testing apparatus via a specific transmission line. The testing apparatus provides a testing requirement. The probe card includes a plurality of probes and a controller. The probes contact with at least one of the flash memory dies of the wafer. The controller writes a testing data to the flash memory die according to the testing requirement and reads the testing data from the flash memory die via the probes. The controller provides a testing result to the testing apparatus according to the read testing data. | 2013-09-26 |
20130250710 | Non-Volatile Memory Device, Circuit Board, Printing Material Container And Printer - A non-volatile memory device includes first and second memory regions to store data and a memory control unit. Each of the first and second memory regions is configured by a plurality of physical pages. Each of the physical pages is configured by a plurality of regions corresponding to a plurality of logical addresses. The memory control unit performs control of batch erasing and batch writing on every physical page. When a first physical page in the first memory region includes a first region corresponding to a first logical address, which is a target to be written, and when a second physical page in the second memory region includes a second region corresponding to the first logical address, which is a target to be written, the memory control unit selects either the first physical page or the second physical page as a physical page for writing. | 2013-09-26 |
20130250711 | MEMORY AND METHOD OF REFRESHING A MEMORY - A memory includes a determination circuit, a plurality of refresh counters, and a plurality of banks. The determination circuit receives a refresh command. The plurality of refresh counters are coupled to the determination circuit. Each refresh counter of the plurality of refresh counters corresponds to one bank of the plurality of banks. The determination circuit detects whether a first bank of the plurality of banks is enabled or a number counted by a first refresh counter of the plurality of refresh counters corresponding to the first bank is equal to a predetermined value. Then, the determination circuit optionally refreshes one bank of the plurality of banks according to a detection result. Thus, the memory still refreshes an idle bank according to a refresh command even if the plurality of banks are not all idle. | 2013-09-26 |
20130250712 | SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin. | 2013-09-26 |
20130250713 | CAULKING TUBE ASSEMBLY AND METHOD FOR TINTING CAULKING - A caulking tube assembly is provided having a cap and an auger component. The auger component has an auger engagement head portion and a helical or spiral portion. The helical portion is compressible and sized to be fitted in a tube for holding caulk. The auger engagement head has a hexagonal shaft housing sized to receive a mixing shaft therein. A dye or tint color formula is added to caulk disposed in the tube and the mixing shaft engages the auger component mixing the caulk and dye or tint color formula to produce tinted caulk. The caulk is colored to satisfy the requirements of virtually any application and dispensed from a caulking gun. In another preferred embodiment there is a caulking tube assembly with having a closed cap and a mixing component. The mixing component has a shaft engagement portion and a shaftless auger portion. | 2013-09-26 |
20130250714 | MIXING DEVICE FOR A CLOSED RESIN INFUSION PROCESS - A mixing device is provided for a closed resin infusion process. The mixing device includes a bulk mixing head with a mixing cavity, at least two separate non-return valves for opening and closing a respective channel for providing material to be mixed running into the mixing cavity. A removable flange is provided for closing the mixing cavity comprising a fitting for mounting the mixing device to a static mixer. At least one heating element is provided for curing the hardable material mixture in the mixing cavity if need be. | 2013-09-26 |
20130250715 | METHOD AND SYSTEM FOR ADJUSTING FOOD AND BAKING FORMULAS - Method and system for automatically adjusting a formula for producing a food product from a plurality of ingredients includes at least one sensor that measures a property of an ingredient used in the formula or an ambient condition around equipment producing the food product. A processor determines an adjusted quantity of at least one ingredient used in the formula based on the measurement by the sensor(s) and a quantity of that ingredient set forth in the formula. The adjusted quantity of this ingredient is mixed together with remaining ingredients in the formula. The sensor may be a sensor that measures temperature of the at least one ingredient, a sensor that measures moisture content of the at least one ingredient, a sensor that measures ambient temperature around the equipment, or a sensor that measures relative humidity around the equipment. | 2013-09-26 |
20130250716 | PROCESS AND APPARATUS FOR MIXING TWO STREAMS OF CATALYST - A process and apparatus for mixing streams of regenerated and carbonized catalyst involves passing a catalyst stream around an insert in a lower section of a riser. The insert fosters mixing of the catalyst streams to reduce their temperature differential before contacting hydrocarbon feed. | 2013-09-26 |
20130250717 | PROCESS AND APPARATUS FOR MIXING TWO STREAMS OF CATALYST - A process and apparatus for mixing streams of regenerated and carbonized catalyst utilizes a ramp or bend provided on only one of the catalyst conduits to provide mixing advantages. | 2013-09-26 |
20130250718 | MIXING ELEMENT AND MIXING MODULE FOR TWO AIR FLOWS INTERSECTING IN AN AIR CONDITIONER - Disclosed herein is a mixing element for two air flows intersecting in an air conditioner with a main wall of a mixing region for mixing first and second air flows. The main wall is disposed such that an inflow direction of the first and second air flows into the mixing region run longitudinally with respect to a main extension plane of the main wall. The mixing element includes first and second auxiliary walls of the mixing region, each having a main surface at opposite side edges of the main wall, and disposed such that the inflow direction of the first air flow runs past a side edge of the first auxiliary wall and transverse to the main surface of the first auxiliary wall. The inflow direction of the second air flow into the mixing region runs longitudinally with respect to the main surface of the first auxiliary wall. | 2013-09-26 |
20130250719 | Surface Visualization System for Indicating Inconsistencies - A method and apparatus for indicating an inconsistency. An apparatus comprises a platform, a location system, a transducer system, a projector system, and a data processing system. The platform is configured to move on a surface of an object. The location system is configured to generate location information for the platform on the surface of the object. The transducer system is configured to send signals into the object and receive a response to the signals. The projector system is configured to project an image onto the surface of the object. The data processing system is configured to generate the image using the response. An indication of an inconsistency in the image projected onto the surface of the object corresponds to a location of the inconsistency in the object. The data processing system is configured to control the projector system to project the image onto the surface of the object. | 2013-09-26 |
20130250720 | METHOD FOR ACQUIRING MARINE SEISMIC DATA - A method for acquiring marine seismic data includes towing a seismic energy source in a body of water and towing a seismic sensor at a selected distance from the seismic energy source. The seismic energy source is actuated a plurality of positions, a distance between each of the plurality of actuations being randomly different than any other such distance. Seismic energy detected by the seismic sensor is substantially continuously recorded through a plurality of actuations of the at least one seismic energy source. The recording includes recording a geodetic position of the at least one seismic energy source and the at least one seismic sensor at each actuation. | 2013-09-26 |
20130250721 | MARINE SEISMIC SURVEYING EMPLOYING INTERPOLATED MULTICOMPONENT STREAMER PRESSURE DATA - It is described a method of interpolating and extrapolating seismic recordings, including the steps of deriving particle velocity related data from seismic recordings obtained by at least one streamer carrying a plurality of multi-component receivers and using the particle velocity related data to replace higher derivatives of pressure data in an expansion series. | 2013-09-26 |
20130250722 | SEISMIC METHODS AND SYSTEMS EMPLOYING FLANK ARRAYS IN WELL TUBING - Systems and method described herein provide for obtaining information which can be used to create a seismic image of a portion of the earth surrounding a well. A device for obtaining information for creating a seismic image proximate a well includes at least one set of acoustic transducers mounted to an exterior surface of a well tubing and configured to transmit at least one acoustic signal, at least one set of hydrophones mounted to the exterior surface of the well tubing and configured to receive at least one reflected acoustic signal; and a cable configured to convey information to and from the at least one set of acoustic transducers and the at least one set of hydrophones. | 2013-09-26 |
20130250723 | SWEEP SEQUENCE DETERMINATION FOR OVERLAPPING SWEEPS - An embodiment of the invention includes combining pseudorandom sweeps with an independent, or nearly independent, survey acquisition technique. Targeted design of pseudorandom sweeps can direct the majority of cross-correlation noise to lie outside key time-lags of the record (i.e., windows of interest). Embodiments of the invention are described herein. | 2013-09-26 |
20130250724 | RETRIEVABLE VERTICAL HYDROPHONE CABLE AND METHOD - Method and retrievable vertical hydrophone cable for collecting seismic data underground. The retrievable vertical hydrophone cable includes an envelope having a first end at which a connector mechanism is provided to close the envelope; plural hydrophones distributed inside the envelope at predetermined positions; and a fluid provided inside the envelope and around the plural hydrophones. The envelope increases its volume when the fluid is pressurized through the connector mechanism. | 2013-09-26 |
20130250725 | RETRIEVABLE VERTICAL GEOPHONE CABLE AND METHOD - A method and a retrievable vertical geophone cable for collecting seismic data underground. The retrievable vertical geophone cable includes an envelope having a first end at which a connector mechanism is provided to close the envelope; plural geophones distributed inside the envelope at predetermined positions; and a first expansion mechanism attached to a geophone of the plural geophones and configured to expand the envelope when actuated with a first fluid under pressure. | 2013-09-26 |
20130250726 | QUANTITATIVE ANALYSIS OF TIME-LAPSE SEISMIC DATA - A method for quantitative analysis of time-lapse seismic data of a reservoir, including: obtaining a plurality of compressional and shear velocities from a seismic inversion analysis; selecting a rock physics model based on a property of the reservoir; calculating a transform function using the rock physics model, where the transform function transforms variations in the plurality of compressional and shear velocities into variations in saturation and pore pressure; calculating a transform grid performing a domain transformation of the transform function; obtaining a plurality of cloud points from the seismic inversion analysis and the transform grid; and overlaying the plurality of cloud points onto the transform grid to estimate a plurality of reservoir parameters of the reservoir. | 2013-09-26 |
20130250727 | METHOD OF SEISMIC SOURCE SYNCHRONIZATION - A method of controlling communications relating to seismic data acquisition may include synchronizing the start of one or more seismic energy sources via a communication protocol. The protocol may be generated at a seismic recording system, source control software running on a processor, or generated from a seismic energy source encoder. The protocol may consist of an encoder message that includes start information and that is combined with a request for information contained at the seismic energy source. The requested information may be sent in a decoder message that is returned in synchronized manner. | 2013-09-26 |
20130250728 | ROTARY PULSER AND METHOD FOR TRANSMITTING INFORMATION TO THE SURFACE FROM A DRILL STRING DOWN HOLE IN A WELL - A rotary pulser for transmitting information to the surface from down hole in a well by generating pressure pulses encoded to contain information. The pulser includes a rotor having blades that are capable of imparting a varying obstruction to the flow of drilling fluid through stator passages, depending on the circumferential orientation of the rotor, so that rotation of the rotor by a motor generates the encoded pressure pulses. A spring biases the rotor toward the stator so as to reduce the axial gap between the rotor and stator. When the pressure drop across the rotor becomes excessive, such as when increasing drilling fluid flow rate or switching from a high data rate to a low data rate transmission mode, the spring bias is overcome so as to increase the axial gap and reduce the pressure drop across the rotor, thereby automatically reducing the thrust load on the bearings. | 2013-09-26 |
20130250729 | METHOD AND SYSTEM FOR MONITORING FIRE BASED ON DETECTION OF SOUND FIELD VARIATION - Disclosed are a method and a system for monitoring a fire based on a detection of sound field variation. The system for monitoring a fire based on a detection of sound field variation includes: a sound generator outputting a sound wave within a defined space according to input voltage; a sound receiver receiving the sound wave within the defined space and obtaining a sound pressure from the received sound wave; and a fire monitor using a sound transfer function representing a ratio of the sound pressure obtained by the sound receiver to input voltage of the sound generator in a preparation mode to calculate reference sound pressure information, using the sound transfer function in a monitoring mode to calculate current sound pressure information, and comparing the reference sound pressure information with the current sound pressure information to determine whether a fire occurs. | 2013-09-26 |
20130250730 | METHOD FOR EVALUATING THE INSTALLATION OF BLIND RIVETS, METHOD AND SYSTEM FOR INSTALLING BLIND RIVETS, METHOD AND SYSTEM FOR OBTAINING A PATTERN, AND AIRCRAFT - A method for evaluating installation of blind rivets including measuring the “cycle time” represented “y | 2013-09-26 |
20130250731 | WIND DIRECTION DETECTING SYSTEM AND METHOD USING SAME - A wind direction detecting system of electronic apparatus includes an audio collecting module, a direction detecting module, and an analyzing module. The audio collecting module controls an audio collector to collect audio data at predetermined time intervals. The direction detecting module controls a direction sensor to detect a facing direction of electronic apparatus in relation to terrestrial magnetism each time the audio collector collects audio data. The analyzing module determines the facing direction where a greatest amplitude of the graph of audio data is recorded as the wind direction. | 2013-09-26 |
20130250732 | ULTRASONIC-TRANSDUCER MOUNTING STRUCTURE - The ultrasonic-transducer mounting structure includes: a housing including: a body part which is formed into a hollow cylindrical shape and is provided at its front surface with a transmission surface allowing an ultrasonic wave to pass therethrough and is designed to accommodate an ultrasonic transducer therein; and plural connection pieces provided to a side surface of the body part; and a holder fixed to a rear surface of a bumper and designed to hold the housing such that the transmission surface of the housing is exposed via an opening of the bumper. The holder includes plural reception pieces to which the plural connection pieces are detachably coupled respectively. The plural reception pieces are fixed to the rear surface of the bumper to surround the opening. | 2013-09-26 |
20130250733 | SEISMIC FREQUENCY SWEEP ENHANCEMENT - A method of performing a seismic sweep includes forming a composite force profile; constructing a target seismic frequency sweep using the composite force profile; and operating a seismic source using the constructed target frequency seismic sweep. | 2013-09-26 |
20130250734 | Suspendable alarms - Disclosed herein are methods for temporarily disabling alarms by suspending alarms on computing devices for given days or for a specific period of time. The alarms will automatically be re-enabled after the specific period or after the specified days. | 2013-09-26 |
20130250735 | INFORMATION NOTIFYING DEVICE AND ELECTRONIC TIMEPIECE - The present invention provides an information notifying device including an hour plate with a display opening, a vibrating motor which is placed on a lower side of the hour plate and causes vibration with eccentric rotation of an eccentric rotation section for information notification, and a rotary plate which rotates with the eccentric rotation of the eccentric rotation section of the vibrating motor and exposes a function display section from the display opening for information notification. | 2013-09-26 |
20130250736 | ATTACHABLE TIMEPIECE - A timepiece, comprising first and second arms connected at one end at an acute angle, and a bar locking system located in a wedge area of the timepiece where the arms are connected at the acute angle, wherein the first and second arms are hollow such that they can house electrical components, and wherein the bar locking system is employed to attach the timepiece to a leash plug of a surfboard. | 2013-09-26 |
20130250737 | MECHANISM FOR DISPLAYING AND CORRECTING THE STATE OF TWO DIFFERENT TIME MEASURABLE QUANTITIES - Mechanism ( | 2013-09-26 |
20130250738 | CLOCK - A clock includes a display including a plurality of planar portions and a plurality of bending portions disposed between the plane portions. The display is configured to display at least one of time, day, or day of the week. The clock also includes a bottom support for supporting one end of the display. | 2013-09-26 |
20130250739 | METHOD AND APPARATUS FOR PROVIDING AN ALARM SERVICE IN MOBILE TERMINAL - A method of providing an alarm service in a mobile terminal is provided. The method includes setting a first alarm and one or more alarm functions for the first alarm, determining whether the first alarm should be operated based on the set alarm function when it is time to operate the first alarm, and operating the first alarm or restricting the operation of the first alarm based on the result of the determination. | 2013-09-26 |
20130250740 | TIMEPIECE WHEEL SET WITH PERIPHERAL GUIDING - Timepiece wheel set ( | 2013-09-26 |
20130250741 | ANALOG ELECTRONIC WATCH - The analog electronic watch includes: a crystal oscillator; an oscillator circuit; a frequency divider circuit; an output control circuit; a constant voltage circuit; and a cell. The constant voltage circuit and the output control circuit are powered from the cell. The oscillator circuit and the frequency divider circuit are powered from the constant voltage circuit. The constant voltage circuit is capable of outputting a first constant voltage and a second constant voltage in a switchable manner. The second constant voltage is a voltage which is equal to or lower than a cell voltage. The first constant voltage is a voltage which is smaller than the second constant voltage. The constant voltage is switched to the second constant voltage in a period of outputting the motor drive pulse. | 2013-09-26 |
20130250742 | THERMALLY-ASSISTED MAGNETIC RECORDING HEAD, HEAD GIMBALS ASSEMBLY, HEAD ARM ASSEMBLY, MAGNETIC DISK UNIT, AND LIGHT TRANSMISSION UNIT - The thermally-assisted magnetic recording head includes: a laser light source having an emission surface, the emission surface allowing laser light to be emitted therefrom; a waveguide having a core and a cladding, the core allowing the laser light emitted from the laser light source to propagate therethrough, and the cladding surrounding the core; a magnetic pole; and a plasmon generator. Each of the core and the cladding has an end surface facing the emission surface, and the end surface of the cladding suppresses returning of the laser light to the laser light source. | 2013-09-26 |
20130250743 | MULTILAYER OPTICAL RECORDING MEDIUM, DRIVE DEVICE, REPRODUCING AND RECORDING APPARATUS, AND INSPECTION METHOD FOR MULTILAYER OPTICAL RECORDING MEDIUM - According to one embodiment, a multilayer optical recording medium including a substrate, a guide layer group that is provided on the substrate and has guide layers in which positional information in a radial direction is recorded, and a recording layer group that is provided on the substrate and has recording layers in which information can be recorded. In the recording layer group, positional information of the recording layers associated with the positional information recorded in the guide layers and control information of the optical device where reflected light volumes of the laser beams on the guide layers and the recording layers become maximum at the positions in the radial direction are recorded at the positions in the radial direction of the recording layers. | 2013-09-26 |
20130250744 | RECORDING DEVICE AND STRAY LIGHT SIGNAL COMPONENT CANCELLATION METHOD - Provided is a recording device, including a light irradiation/receiving unit that irradiates an optical recording medium with first light and second light, and that receives backpropagating light of the second light from the optical recording medium, a recording unit that carries out recording on the optical recording medium, a playback signal generating unit that obtains a playback signal of a signal, and a stray light signal component canceling unit that generates, based on recording data, a stray light cancel signal for canceling a stray light signal component. | 2013-09-26 |
20130250745 | Systems and Methods for Improved Servo Data Operation - Various embodiments of the present invention provide systems, methods and media formats for efficiently determining a position error of a head in relation to a storage medium. In one case, a system is disclosed that includes a storage medium with a series of data. The series of data includes a first defined marker and a second defined marker located a distance from the first defined marker, and position location data. The systems further include a first detector circuit that is operable to detect the first defined marker and to establish a location of the first defined marker, and a second detector circuit that is operable to detect the second defined marker and to establish a location of the second defined marker. The systems further include an error calculation circuit and an interpolation circuit. The error calculation circuit is operable to calculate an interpolation offset based at least in part on the location of the first defined marker and the location of the second defined marker. The interpolation circuit is operable to interpolate the position location data and to provide an interpolated position location data. | 2013-09-26 |
20130250746 | EJECTING MODULE FOR HARD DISK DRIVES - An ejecting module is used in a server and includes a connector, a holder, a hard disk drive, a detecting circuit, a current output circuit, a first electromagnet and a second electromagnet. The hard disk drive is received in the holder. The detecting circuit detects whether the hard disk drive is electronically connected to the connector to output a control signal. The current output circuit receives the control signal and outputs a current. The first electromagnet is adjacent to the connector, and the second electromagnet faces the first electromagnet, the first electromagnet and the second electromagnet being electronically connected to the current output circuit. The current magnetizes the first electromagnet and the second electromagnet, a repulsion force is produced between the first electromagnet and the second electromagnet for moving the second electromagnet from the first electromagnet to be spaced from each other. | 2013-09-26 |
20130250747 | Method and Apparatus Relating to HARQ Processes - A method in a radio receiver arrangement for receiving data blocks of radio signalling. The method comprises receiving a plurality of data blocks over a radio interface from a transmitting side. The method also comprises applying a single hybrid automatic repeat request (HARQ) process to the plurality of data blocks, whereby it is determined that at least one of the plurality of data blocks has been received ok and that at least one of the plurality of data blocks has not been received ok. The method also comprises generating a negative acknowledgement (NAK) for the plurality of data blocks in response to the at least one of the plurality of data blocks having not been received ok. The method also comprises outputting, from the receiver arrangement, at least one symbol obtained from the at least one of the plurality of data blocks which has been received ok. | 2013-09-26 |
20130250748 | APPARATUS AND METHOD FOR PROVIDING MULTI-RAB SERVICE IN COMMUNICATION SYSTEM - An apparatus implements a method for maintaining a voice call in a communication system providing a multi-Radio Access Bearer (RAB). In the method for maintaining a voice call in an electronic device, a data call and a voice call with a wireless network are connected. When an error of the data call is detected, the connection of the data call with the wireless network is released. | 2013-09-26 |
20130250749 | CONTROL METHOD FOR ACCESS GATEWAY AND COMMUNICATION SYSTEM - In order to provide a redundancy configuration to an access gateway apparatus in which a control plane and a user plane are separated, the access gateway apparatus includes: a control computer for receiving control signals from the networks to establish the communication path, thereby determining packet transfer information for the data; and a transfer computer for receiving the packet transfer information from the control computer to transfer the data through the communication path. The transfer computer includes: a plurality of first transfer computers for executing the transfer of the data; and a second transfer computer for taking over, when a fault occurs in any one of the plurality of first transfer computers. The control computer includes: a first control computer for processing the control signals received from the networks; and a second control computer for taking over, when a fault occurs in the first control computer. | 2013-09-26 |
20130250750 | MOBILE COMMUNICATION METHOD, GATEWAY APPARATUS, MOBILITY MANAGEMENT NODE, AND CALL SESSION CONTROL SERVER APPARATUS - A mobile communication method according to the present invention includes a step A of re-establishing, by IMS (P-CSCF), association among a PDN connection, a PCC connection #1 and a PCC connection #2 in case of detecting a specified event after detecting a failure in PCRF. | 2013-09-26 |
20130250751 | ACCELERATED RECOVERY DURING NEGOTIATION BETWEEN A MEDIA GATEWAY AND A MEDIA GATEWAY CONTROLLER - A method is disclosed that enables an improved technique for recovering from an error scenario encountered during a call setup involving a malfunctioning media gateway and corresponding media gateway controller. The media gateway first detects a malfunction that affects a digital signal processing resource, and then proactively selects a processing resource available elsewhere at the gateway. The media gateway selects the new processing resource based on criteria including: i) the capabilities that were identified to handle the packet stream at the affected (faulty) processor; ii) the capabilities of the IP terminal originating the packet stream that is being moved; and iii) the Internet Protocol address of the affected processing resource. Advantageously, an effort is made to avoid having to inform the media gateway controller of the move, thereby minimizing any discontinuity in each packet stream and minimizing the time and processing that are required to establish the call. | 2013-09-26 |
20130250752 | DATA FORWARDING METHOD AND ROUTER - A data forwarding method and a router are provided. The router includes: forwarding engines FEs, physical interface cards PICs, a first switch device and a second switch device, where the first switch device includes a primary first switch device and a standby first switch device, all the FEs are connected with each other via the first switch device, the FEs are connected to the PICs via the second switch device, the number of the FEs is at least two, the number of the PICs is at least two, and the number of the FEs is equal to the number of the PICs. Embodiments of the present invention could improve reliability of a system. | 2013-09-26 |
20130250753 | METHOD FOR PROTECTION SWITCHING IN ETHERNET RING NETWORK - A method for protection switching in an Ethernet ring network is provided. According to an aspect, the protection switching method includes: at a first node on the Ethernet ring network, detecting link failure; at the first node, determining whether a port through which a protection switching message has to be transmitted is on a forwarding path; and at the first node, generating a protection switching message based on the result of the determination; and at the first node, transmitting the protection switching message. | 2013-09-26 |
20130250754 | PROACTIVE TIMER-BASED LOCAL REPAIR PATH COMMUNICATION IN REACTIVE ROUTING NETWORKS - In one embodiment, an intermediate device may determine a source route in use from a source to a destination in a reactive routing computer network, and may also determine a request to provide local repair for the source route for duration of a timer set by the source. In response to the request (e.g., and in response to a poor/failed connection), the device may discover a local repair path based on a limited-scope discovery, and maintains the local repair path for the source route until expiration of the timer. | 2013-09-26 |
20130250755 | Real-Time Dynamic Failover For Redundant Data Communication Network - Systems, methods and computer program products for facilitating real-time, dynamic failover in a redundant data communication network are disclosed. In an aspect of the present disclosure, a service provider offers and monitors a single redundant data communication network that enables a business to have a large number of the business' personnel simultaneously receive primary and secondary data communication services from primary and secondary service providers, respectively. Such a single, redundant data communication network maintains one internet protocol (IP) address, which preserves—and does not drop—the business' in-progress operations during a failover. Additionally, the single data communications network synchronizes data communication services from a variety of data communication service providers thereby ensuring the business can perform all operations when switching from the primary service provider to the secondary service provider during real-time, dynamic failover. | 2013-09-26 |
20130250756 | Restoring Aggregated Circuits with Circuit Integrity Checks in a Hierarchical Network - A system and method is disclosed that assures component circuits transported in aggregated circuits restore correctly after an aggregated circuit fault. The system and method implements component circuit tail segment integrity checks whenever an aggregated circuit is restored in a higher level of a network hierarchy. Switches at both ends of an aggregated circuit perform circuit integrity checks of the tail segments of every component circuit. A failure of the component circuit integrity check on any component circuit causes that component circuit to be released and restored end-to-end. | 2013-09-26 |
20130250757 | Reducing Headroom - The various embodiments of the invention provide mechanisms to reduce headroom size while minimizing dropped packets. In general, this is done by using a shared headroom space between all ports, and providing a randomized delay in transmitting a flow-control message. | 2013-09-26 |
20130250758 | BASE STATION, WIRELESS END DEVICE, AND TRANSMISSION BARRING METHODS THEREOF - A base station, a wireless end device, and transmission barring methods are provided. The base station is configured to receive a special event notification message from a core network, generate a barring message after receiving the special event notification message, and transmit the barring message to the wireless end device. The base station is not overloaded when the barring message is generated and transmitted. After receiving the barring message, the wireless end device is suspended from transmitting data to the base station for a barring time interval. | 2013-09-26 |
20130250759 | Method for Processing Service and Apparatus - Embodiments of the present invention disclose a method for processing service and apparatus, relating to the field of communication technologies, and invented for effectively reducing signaling interactions and optimizing the performance of a communication system. The method for processing service includes: receiving a packet data protocol PDP deactivation request message or a signaling connection release indication SCRI message sent from a user equipment; and maintaining a bearer corresponding to the user equipment. The present invention may be used in global systems for mobile communications and long term evolution communication systems. | 2013-09-26 |
20130250760 | COMMUNICATION LINK WITH INTRA-PACKET FLOW CONTROL - A method for communication includes transmitting a data packet from a first port to a second port over a communication link. After transmission of a first portion of the data packet, the transmission is temporarily suspended, a flow-control message is sent from the first port to the second port over the communication link while the transmission is temporarily suspended, and then the transmission is resumed so as to transmit a second portion of the data packet. | 2013-09-26 |
20130250761 | SYSTEM AND METHOD FOR MODIFYING MEDIA PROTOCOL FEEDBACK LOOP BASED ON MOBILE SYSTEM INFORMATION - Systems and methods for modifying a media protocol based on subscriber and network performance information is disclosed. Media protocols such as adaptive bitrate protocol can adjust bit rates based on conditions perceived at the mobile device and with a goal of obtaining the highest bit rate possible. The media protocols residing on the mobile device do not have access to network performance information that can change rapidly and impact the experience at the mobile device. For example, congestion, radio air link interference, handoffs, and quality of service parameters can all impact the experience a user has when accessing media files from a mobile device. The requests made by a mobile device can be modified to take into account these factors to enhance the user experience. | 2013-09-26 |
20130250762 | Method and apparatus for Lossless Behavior For Multiple Ports Sharing a Buffer Pool - Packets are colored and stored in a shared packet buffer without assigning fixed page allocations per port. The packet buffer is divided into three areas—an unrestricted area, an enforced area, and a headroom area. Regardless of the fullness level, when a packet is received it will be stored in the packet buffer. If the fullness level is in the unrestricted area, no flow control messages are generated. If the fullness level is in the enforced region, a probabilistic flow control generation process is used determine if a flow control messages will be generated. If the fullness level is in the headroom area, flow control is automatically generated. Quanta timers are used to control regeneration of flow control messages. | 2013-09-26 |
20130250763 | Method and Apparatus for Control Plane CPU Overload Protection - Control packets received at a network element are pre-classified to enable out of profile traffic to be traced to an offending port. Pre-classified control packets are metered at a desired granularity using dynamically configured meters which adjust as ports are put into service or removed from service, and as services are applied to ports. CPU metering is implemented on a per-CPU core basis, but the per-CPU meters are used to perform flow control rather than as thresholds for ejecting errant control traffic. The combination of these three aspects provides robust CPU overload protection while allowing appropriate levels of control traffic to be provided to the control plane for processing, even in the event of a control traffic burst on one or more ports of the network element. | 2013-09-26 |
20130250764 | ALMOST BLANK SUBFRAME DUTY CYCLE ADAPTATION IN HETEROGENEOUS NETWORKS - A method of setting an almost blank subframe (ABS) duty cycle in a heterogeneous network including a macro cell and one or more small cells, the one or more small cells being underlaid with respect to the macro cell includes obtaining, at a network element, loading information corresponding to each of the macro cell and the one or more small cells, the loading information including, for each of the macro cell and the one or more small cells, an indication of an amount of information buffered at the cell for each user attached to the cell; and determining the ABS duty cycle based on the obtained loading information. | 2013-09-26 |
20130250765 | DELAY BASED ACTIVE QUEUE MANAGEMENT FOR UPLINK TRAFFIC IN USER EQUIPMENT - A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus stores data packets in a buffer. In addition, the apparatus determines a delay of at least one data packet of the data packets in the buffer. Furthermore, the apparatus controls a TCP data flow rate based on the determined delay. The apparatus may also store ACKs in a second buffer and drop an ACK of the stored ACKs when one of a number of stored ACKs is greater than a first threshold or a size of the stored ACKs is greater than a second threshold. | 2013-09-26 |
20130250766 | SYSTEM AND METHOD FOR BALANCING UPLINK BANDWIDTH UTILIZATION IN A RELAY ASSISTED CELLULAR NETWORK - A system and method for balancing uplink (UL) bandwidth utilization in a relay assisted cellular network are disclosed. In one embodiment, scheduler context data associated with one or more mobile users/devices connected to the relay assisted cellular network is obtained. Further, static and dynamic load values of data packets coming from the one or more mobile users/devices are computed using the obtained scheduler context data. Furthermore, UL bandwidth utilization between the one or more mobile users/devices and a base station in the relay assisted cellular network is balanced using the computed static and dynamic load values. | 2013-09-26 |
20130250767 | Method and Device for Data Transmission - An embodiment of the present invention provides a method and apparatus for data transmission, wherein the method comprises: establishing a buffer for TCP/IP data packets, and the TCP/IP data packets including TCP payloads and TCP ACKs; adjusting a queue of the buffered TCP/IP data in accordance with header information of the TCP/IP data packets; and transmitting sequentially the buffered TCP/IP data packets being adjusted. According to the embodiments of the present invention, the IP data packets of TCP ACKs transmitted by the receiving side are processed, so that the amount of the TCP ACK responses is significantly reduced and the IP data packets of TCP ACKs are transmitted with priority, thereby the round-trip time delay for data transmitting can be reduced, and the data transmission efficiency can be improved. | 2013-09-26 |