39th week of 2013 patent applcation highlights part 17 |
Patent application number | Title | Published |
20130248868 | DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - A display panel includes a base substrate, a common electrode, a liquid crystal layer, a pixel electrode, a gate line, a data line, a switching element, a color filter and a light blocking pattern. The base substrate includes a trench. The common electrode is disposed in the trench. The liquid crystal layer is disposed in the trench and disposed on the common electrode. The pixel electrode is disposed on the base substrate and the liquid crystal layer. The gate line, the data line and the switching element are disposed on the base substrate and the pixel electrode. The color filter and the light blocking pattern are disposed on the gate line, the data line and the switching element. | 2013-09-26 |
20130248869 | DISPLAY SUBSTRATE - A display substrate includes a gate line extended in one direction of a base substrate, a first data line extended in a direction crossing the gate line, a transverse storage line extended in the extending direction of the gate line and crossing the first data line, a longitudinal storage line extended in the extending direction of the first data line and crossing the transverse storage line, a portion of an overlapping area between the longitudinal storage line and the transverse storage line is exposed in a contact part region having an opening partially exposing the transverse storage line. A contact electrode covers the contact part opening and makes electrical contact with each of the transverse storage line and the longitudinal storage line. | 2013-09-26 |
20130248870 | ARRAY SUBSTRATE FOR FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display includes: forming an auxiliary insulating layer on a second passivation layer and having a first thickness; forming first and second photoresist patterns on the auxiliary insulating layer and having second and third thicknesses, respectively, the second thickness greater than the third thickness; etching the auxiliary insulating layer, the second passivation layer and a first passivation layer to form a drain contact hole; performing an ashing to remove the second photoresist pattern and expose the auxiliary insulating layer therebelow; performing a dry etching to remove the auxiliary insulating layer not covered by the first photoresist pattern and expose the first passivation layer and to form an insulating pattern below the first photoresist pattern, the insulating pattern and the first photoresist pattern forming an undercut shape; forming a transparent conductive material layer having a fourth thickness less than the first thickness; and performing a lift-off process to remove the first photoresist pattern and the transparent conductive material layer thereon together and form a pixel electrode as a remaining portion of the transparent conductive material layer. | 2013-09-26 |
20130248871 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, an insulating film, and a control electrode. The first semiconductor region includes a silicon carbide of a first conductivity type. The second semiconductor region is provided on the first semiconductor region, includes a silicon carbide of a second conductivity type, and has a first main surface. The third semiconductor region is provided on the second semiconductor region and includes the silicon carbide of the first conductivity type. The film is provided on the surface. The electrode is provided on the film, and has a first region close to the third semiconductor region side, and a second region closer to the first semiconductor region side than the first region. An effective work function of is the first region is larger than an effective work function of the second region. | 2013-09-26 |
20130248872 | SEMICONDUCTOR DEVICE, NITRIDE SEMICONDUCTOR CRYSTAL, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR CRYSTAL - A semiconductor device includes: a nucleation layer formed over a substrate; a buffer layer formed over the nucleation layer; a first nitride semiconductor layer formed over the buffer layer; and a second nitride semiconductor layer formed over the first nitride semiconductor layer, wherein the ratio of yellow luminescence emission to band edge emission in photoluminescence is 400% or less and the twist value in an X-ray rocking curve is 1,000 arcsec or less. | 2013-09-26 |
20130248873 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nitride semiconductor device includes a substrate; semiconductor stacked layers including a nitride semiconductor provided on the substrate, and having a buffer layer, a carrier running layer provided on the buffer layer, and a barrier layer provided on the carrier running layer; a source electrode and a drain electrode provided on the semiconductor stacked layers and in contact with the semiconductor stacked layers; and a gate electrode provided on the semiconductor stacked layers and provided between the source electrode and the drain electrode. | 2013-09-26 |
20130248874 | NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device includes semiconductor stacked layers provided on a substrate and including a nitride semiconductor; a source electrode and a drain electrode provided on the layers and being in contact with the layers; and a gate electrode provided on the layers and provided between the source electrode and the drain electrode. The layers have a first barrier layer, a second barrier layer, and a carrier running layer interposed between the first barrier layer and the second barrier layer. The second barrier layer and the carrier running layer are removed in a region in which the source electrode on the layers is provided. A part of the source electrode is in contact with the first barrier layer. And another part of the source electrode other than the part of the source electrode is in contact with the second barrier layer. | 2013-09-26 |
20130248875 | LIGHT-EMITTING DIODE COMPRISING STACKED-TYPE SCATTERING LAYER AND MANUFACTURING METHOD THEREOF - Disclosed is a light-emitting diode with a semiconductor layer including stacked-type scattering layer, and a manufacturing method thereof. The semiconductor layer includes a non-flat structure and at least two scattering layers disposed therein. The scattering layers are stacked on the non-flat structure. The top surface of each layer of the scattering layers is non-flat having an undulating fashion, and refractive indices of two adjacent layers of the scattering layers are different from each other. Photons emitted from the active layer are scattered by the scattering layers as photon scattering structure so that the probability of photons escaping from the light-emitting diode is increased, and thus total internal reflection is reduced, thereby increasing the extraction efficiency; in addition, the lateral epitaxial growth mode is enhanced, resulting in direction change of threading dislocations or formation of dislocation loops, and thus the defect density is reduced, thereby increasing the internal quantum efficiency. | 2013-09-26 |
20130248876 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME - In a vertical semiconductor device including a channel in an opening, a semiconductor device whose high-frequency characteristics can be improved and a method for producing the semiconductor device are provided. The semiconductor device includes n-type GaN-based drift layer | 2013-09-26 |
20130248877 | GALLIUM NITRIDE BASED SEMICONDUCTOR LIGHT-EMITTING ELEMENT, LIGHT SOURCE, AND METHOD FOR FORMING UNEVENNESS STRUCTURE - The light extraction surface of a nitride semiconductor light-emitting element, including a crystal plane other than a c plane, is subjected to a surface modification process to control its wettability, and then covered with a layer of fine particles. By etching that layer of fine particles after that, an unevenness structure, in which roughness curve elements have an average length (RSm) of 150 nm to 800 nm, is formed on the light extraction surface. | 2013-09-26 |
20130248878 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE AND THE SAME MANUFACTURED THEREOF - Disclosed is a nitride semiconductor device and a method for manufacturing the same and the method for manufacturing the nitride semiconductor device comprising: growing a buffer layer including a first semiconductor on a substrate; growing a first barrier layer including a second semiconductor different from the first semiconductor; forming an oxide film layer on a portion where a recess is to be formed; growing a second barrier layer including the second semiconductor; forming a recess by removing the oxide film layer; and forming a gate electrode on the recess. | 2013-09-26 |
20130248879 | DIRECT GROWTH OF DIAMOND IN BACKSIDE VIAS FOR GAN HEMT DEVICES - A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via. | 2013-09-26 |
20130248880 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first, a second, a third, and a fourth semiconductor region, a control electrode, a floating electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench formed in the fourth, the third, and the second region. The floating electrode is provided between the control electrode and a bottom surface of the trench. The insulating film is provided between the trench and the control electrode, between the trench and the floating electrode, and between the control electrode and the floating electrode. | 2013-09-26 |
20130248881 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first, a second, a third, a fourth semiconductor region, a control electrode, and an insulating film. The first region contains silicon carbide. The second region is provided on the first region and contains silicon carbide. The third region is provided on the second region and contains silicon carbide. The fourth region is provided on the third region and contains silicon carbide. The control electrode is provided in a trench. The trench is formed in the fourth, the third, and the second semiconductor region. The insulating film is provided between a side surface of the trench and the control electrode. The insulating film contains a high-dielectric constant region. The high-dielectric constant region contacts with at least the third semiconductor region. The high-dielectric constant region has a higher dielectric constant than a dielectric constant of silicon oxide. | 2013-09-26 |
20130248882 | SEMICONDUCTOR DEVICE - In a semiconductor device, transistor cells and diode cells are formed on a single semiconductor substrate of a first conductivity type. A first semiconductor layer of a second conductivity type is formed in a transistor cell region and at a lower side of the substrate. A second semiconductor layer of the first conductivity type is formed in a region adjacent to the transistor cell region and at the lower side of the substrate. Gate electrodes are formed at an upper side of the substrate. A third semiconductor layer of the second conductivity type and a fourth semiconductor layer of the first conductivity type are formed between the gate electrodes. A fifth semiconductor layer of the first conductivity type is formed above the first semiconductor layer in the transistor cell region. A first and a second electrode are formed on both sides of the substrate. | 2013-09-26 |
20130248883 | HIGH PERFORMANCE POWER MODULE - The present disclosure relates to a power module that has a housing with an interior chamber and a plurality of switch modules interconnected to facilitate switching power to a load. Each of the plurality of switch modules comprises at least one transistor and at least one diode mounted within the interior chamber and both the at least one transistor and the at least one diode are majority carrier devices, are formed of a wide bandgap material system, or both. The switching modules may be arranged in virtually any fashion depending on the application. For example, the switching modules may be arranged in a six-pack, full H-bridge, half H-bridge, single switch or the like. | 2013-09-26 |
20130248884 | III-Nitride Power Device - A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof. | 2013-09-26 |
20130248885 | Transistors Comprising a SiC-Containing Channel - A memory device includes an array of memory cells and peripheral devices. At least some of the individual memory cells include carbonated portions that contain SiC. At least some of the peripheral devices do not include any carbonated portions. A transistor includes a first source/drain, a second source/drain, a channel including a carbonated portion of a semiconductive substrate that contains SiC between the first and second sources/drains and a gate operationally associated with opposing sides of the channel. | 2013-09-26 |
20130248886 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE - In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, and including a first semiconductor layer of a first conductivity type in the substrate, a second semiconductor layer of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, a third semiconductor layer of the first conductivity type on a surface of the second semiconductor layer, and a fourth semiconductor layer of the second conductivity type on a surface of the first semiconductor layer on a second main surface side. The device further includes a control electrode and a first main electrode on the first main surface side of the substrate, and a second main electrode and a junction termination portion on the second main surface side of the substrate, the junction termination portion having an annular planar shape surrounding the fourth semiconductor layer. | 2013-09-26 |
20130248887 | OPTICAL ELECTRONIC PACKAGE - An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip. | 2013-09-26 |
20130248888 | LED PACKAGE STRUCTURE - An LED package structure comprises a 3D substrate, LED chips, wires, and resin encapsulants. The 3D substrate has a stepped contour and includes a first chip accommodation region and at least one second chip accommodation region surrounding the first chip accommodation region. A first electric contact and a second electric contact are arranged in the first chip accommodation region. The LED chips are arranged in the border of the 3D substrate. The wires are used to connect the LED chips in series or in series firstly and in parallel next. One of the wires connects the first electric contact and one of the LED chips. Another one of the wires connects the second electric contact and another one of the LED chips. The resin encapsulants respectively encapsulate the LED chips. The LED package structure is characterized in using a 3D substrate to facilitate wiring and increase the beam angle. | 2013-09-26 |
20130248889 | LIGHT EMITTING DEVICE - An embodiment of the present invention provides a light emitting device including: a transparent substrate; a wiring layer disposed on the transparent substrate; a plurality of light emitting diode chips disposed on the transparent substrate and electrically connected to the wiring layer; and an opposite substrate disposed on the transparent substrate to sandwich the light emitting diode chips and the wiring layer, wherein no wiring layer is disposed on a surface of the opposite substrate facing the light emitting diode chips. | 2013-09-26 |
20130248890 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode (OLED) display is provided. The OLED display includes a substrate, an organic light emitting element on the substrate, and a thin film encapsulation layer on the substrate and covering the organic light emitting element. The thin film encapsulation layer includes at least one conductive layer having a voltage application pad. | 2013-09-26 |
20130248891 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting display device and a method of manufacturing the same are proposed. The organic light emitting display device includes: a first film formed of an organic material, and having first and second surfaces facing each other and a third surface perpendicular to the first and second surfaces; a second film formed on the first film to cover the second and third surfaces of the first film; an organic light emitting unit disposed on the second film; a third film disposed on the second film to cover the organic light emitting unit; and a fourth film disposed on the third film, formed of an organic material, and having fourth and fifth surfaces facing each other, wherein the fifth surface faces the third film. | 2013-09-26 |
20130248892 | LIGHT-EMITTING DEVICE - A-light-emitting device which realizes a high aperture ratio and in which the quality of image is little affected by the variation in the characteristics of TFTs. The channel length of the driving TFTs is selected to be very larger than the channel width of the driving TFTs to improve current characteristics in the saturated region, and a high V | 2013-09-26 |
20130248893 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor light emitting device includes a plurality of chips, and a phosphor layer. Each of the plurality of chips includes a semiconductor layer, a p-side electrode, and an n-side electrode. The semiconductor layer has a first surface, a second surface opposite to the first surface, and a light emitting layer. The p-side electrode is provided in an emitting region on the second surface. The n-side electrode is provided in an non-emitting region on the second surface. The phosphor layer is provided on the first surface side of the chips. The phosphor layer includes a transparent body and a phosphor dispersed in the transparent body. A gap not including the phosphor is provided in the phosphor layer. The plurality of chips includes a plurality of chips for which the gap has different sizes. | 2013-09-26 |
20130248894 | LIGHT-EMITTING ELEMENT MOUNTING PACKAGE, MANUFACTURING METHOD OF THE SAME, AND LIGHT-EMITTING ELEMENT PACKAGE - A light-emitting element mounting package including a first wiring forming a first light-emitting element mounting portion, which is provided on one surface of a substrate to mount a light-emitting element, and a first through wiring having one end and another end, the one end being electrically connected to the first light-emitting element mounting portion so as to be thermally transferable, and the other end protruding from another surface of the substrate. | 2013-09-26 |
20130248895 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate elongated in a lengthwise direction; a plurality of LED chips disposed on the substrate in an intermediate region in widthwise direction, and aligned along the lengthwise direction at a distance of 80 μm or less; and interconnection wirings formed on regions outside the intermediate region in the widthwise direction; wherein each of the LED chips has a p-side electrode disposed on the substrate, a p-type semiconductor layer disposed on the p-side electrode, an active layer formed on the p-type semiconductor layer, and an n-type semiconductor layer formed on the active layer, and has a region in which the n-type semiconductor layer, the active layer, and the p-type semiconductor layer are patterned, and an n-side electrode formed selectively on a surface of the n-type semiconductor layer and connected to the p-side electrode of an adjacent LED chip through the interconnection wiring. | 2013-09-26 |
20130248896 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT INCLUDING THE SAME - Disclosed are a light emitting device package and a light unit including the same. The light emitting device package includes a body; a first lead frame having a first cavity in a first region of the body; a second lead frame having a second cavity in a second region of the body; a first bonding part adjacent to a first lateral side of the body and extended from the first cavity of the first lead frame; a second bonding part adjacent to a second lateral side of the body, which is opposite to the first lateral side of the body, and extended from the second cavity of the second lead frame; a first light emitting device in the first cavity; a second light emitting device in the second cavity; a third cavity adjacent to the first bonding part; a first protective device in the third cavity. | 2013-09-26 |
20130248897 | LIGHT EMITTING DIODE WAFER-LEVEL PACKAGE WITH SELF-ALIGNING FEATURES - Several embodiments of light emitting diode packaging configurations including a substrate with a cavity are disclosed herein. A patterned wafer has a plurality of individual LED attachment sites, and an alignment wafer has a plurality of individual cavities. The patterned wafer and the alignment wafer are superimposed with the LED attachment sites corresponding generally to the cavities of the alignment wafer. At least one LED is placed in the cavities using the cavity to align the LED relative to the patterned wafer. The LED is electrically connected to contacts on the patterned wafer, and a phosphor layer is formed in the cavity to cover at least a part of the LED. | 2013-09-26 |
20130248898 | Liquid Crystal Display Device - A liquid crystal display device includes a TFT substrate with gate lines and drain lines, and pixel electrodes each formed in a region surrounded by the gate lines and drain lines. Protrusions are formed below the gate lines, each of the protrusions having an upper surface and at least one inclined side surface. A gate insulating film is formed over the gate lines, a semiconductor layer formed on the gate insulating film, and drain electrodes formed and source electrodes formed over the semiconductor layer. Channel portions are defined by the space between the drain electrodes and the source electrodes, each of the channel portions being formed covering the upper surface and at least one of the at least one inclined side surface of one of the protrusions, the pixel and source electrode being in contact with each other on at least one inclined side surface of the protrusion. | 2013-09-26 |
20130248899 | Display Device - A display device in which the current load of wirings are distributed and display variations due to voltage drop are suppressed. An active matrix display device of the invention comprises a first current input terminal, a second current input terminal, and a plurality of current supply lines extending parallel to each other. Each current supply line is connected to a plurality of driving transistors in a line. One end of each current supply line is connected to the first current input terminal via a first wiring intersecting with the current supply lines, and the other end thereof is connected to the second current input terminal via a second wiring intersecting with the current supply lines. Accordingly, a current is supplied to each current supply line from both the first and. the second current input terminals. The first and the second current input terminals are provided separately from each other. | 2013-09-26 |
20130248900 | LIGHT-EMITTING DEVICE HAVING LIGHT-EMITTING ELEMENTS - A light-emitting device operating on a high drive voltage and a small drive current. LEDs ( | 2013-09-26 |
20130248901 | LIGHT-EMITTING DIODE COMPRISING DIELECTRIC MATERIAL LAYER AND MANUFACTURING METHOD THEREOF - Disclosed is a light-emitting diode with a semiconductor layer including dielectric material layer, and a manufacturing method thereof for increasing the external quantum efficiency. The semiconductor layer includes a non-flat structure having a plurality of recess regions, and at least one dielectric material layer disposed within each recess region, the dielectric material layer has a generally inverted pyramid shape or a ball shape, and a portion of the non-flat structure is exposed outside the dielectric material layer. Photons emitted from the active layer are scattered by the dielectric material layer as photon scattering structure, and are guided by the inclined internal side faces of the recess regions so that the probability of photons escaping from the light-emitting diode is increased, and thus total internal reflection is reduced, thereby increasing the extraction efficiency and hence the external quantum efficiency. | 2013-09-26 |
20130248902 | LIGHT EMITTING ELEMENT AND METHOD OF MAKING SAME - A light emitting element has a substrate of gallium oxides and a pn-junction formed on the substrate. The substrate is of gallium oxides represented by: (Al | 2013-09-26 |
20130248903 | LED PACKAGE MODULE STRUCTURE - A light emitting diode package module structure comprises a LED module received in a reflection cup, a light transmitting color conversion member disposed on an annular surface of the reflection cup, a stationary package sleeved on the reflection cup in such a manner that the press portion of the stationary package is pressed against the light transmitting color conversion member, and the stop portions of the positioning legs of the stationary package are positioned against the bottom of the reflection cup. In this way, the light transmitting color conversion member is fixed to the reflection cup by the stationary package without the use of adhesive agents, which consequently simplifies the packaging procedure and reduces the package cost. | 2013-09-26 |
20130248904 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes: a semiconductor layer including a first face, a second face, a side face, and a light emitting layer; a p-side electrode provided on the second face; an n-side electrode provided on the side face; a first p-side metal layer provided on the p-side electrode; a first n-side metal layer provided on the periphery of the n-side electrode; a first insulating layer provided on a face on the second face side in the first n-side metal layer; a second p-side metal layer connected with the first p-side metal layer on the first p-side metal layer, and provided, extending from on the first p-side metal layer to on the first insulating layer; and a second n-side metal layer provided on a face on the second face side in the first n-side metal layer in a peripheral region of the semiconductor layer. | 2013-09-26 |
20130248905 | LED PACKAGE AND METHOD OF MANUFACTURING THE SAME - A light-emitting diode (LED) package and related method of manufacturing are provided. The LED package includes a resin blocking portion to prevent a transparent resin from reaching a contact terminal of the LED package during the formation of the lens for the LED package. | 2013-09-26 |
20130248906 | LIGHT EMITTING DIODE PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - The invention provides a light emitting diode package structure and a method for fabricating the same. The package structure includes: a light emitting diode chip formed on a substrate; a first hydrophobic rib layer formed on the substrate and surrounding the light emitting diode; and a first cover layer formed on the substrate and covering the light emitting diode, wherein the first hydrophobic rib layer is used as a border of the first cover layer and an angle between the facet of the first cover layer and the substrate is about 60-90 degrees. | 2013-09-26 |
20130248907 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor light-emitting device is provided with a semiconductor layer including a first surface, a second surface opposite to the first surface, a luminous layer, and a first electrode formed on the first surface. The first surface has flat and rough portions. The first electrode has a pad and a fine wire electrode that is narrower than the pad. The fine wire electrode is formed on the flat portions but not on the rough portions. One or more metal contacts are disposed on the second surface to be under the rough portions. | 2013-09-26 |
20130248908 | Radiation-Emitting Component - The invention relates to a radiation-emitting component comprising a semiconductor body which emits electromagnetic radiation from a radiation exit surface during operation. The semiconductor body is arranged in a component housing having a cutout. The component further comprises an optical element which is connected to the component housing in a mechanically stable manner by means of a joining layer. The modulus of elasticity of the joining layer is lower than or equal to 30 MPa. | 2013-09-26 |
20130248909 | RED PHOSPHOR, METHOD FOR PREPARING SAME, AND LIGHT-EMITTING DEVICE COMPRISING SAME - Provided is a red phosphor having superior thermal and chemical stability and excellent luminous efficiency, wherein the red phosphor comprises a compound expressed in the composition formula: A | 2013-09-26 |
20130248910 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device includes a light emitting unit, a first and second conductive pillar, a sealing unit, and a first and second terminal. The light emitting unit includes a first and second semiconductor layer and a light emitting layer. The light emitting layer is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting layer. The first conductive pillar is provided on the first semiconductor layer. The second conductive pillar is provided on the second semiconductor layer. The sealing unit covers side faces of each of the light emitting unit, the first conductive pillar, and the second conductive pillar. The first terminal is provided on the first conductive pillar and on the sealing unit. The second terminal is provided on the second conductive pillar and on the sealing unit. | 2013-09-26 |
20130248911 | LIGHT-EMITTING DEVICE INCLUDING NITRIDE-BASED SEMICONDUCTOR OMNIDIRECTIONAL REFLECTOR - A light-emitting device includes a nitride-based semiconductor reflector. The light-emitting device includes a nitride-based reflector and a light-emitting unit that is disposed on the nitride-based reflector. The nitride-based reflector includes undoped nitride semiconductor layers and heavily-doped nitride semiconductor layers that are alternately stacked. The heavily doped nitride semiconductor layers are etched at their edges to form air layers between adjacent undoped nitride semiconductor layers. | 2013-09-26 |
20130248912 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - According to one embodiment, a semiconductor light emitting element includes a stacked body and an optical layer. The stacked body has a major surface and includes a light emitting layer. The optical layer is in contact with the surface and includes a dielectric body, first particles, and second particles. The optical layer includes a first region including the dielectric body and the first particles and does not include the second particles and a second region including the dielectric body and the second particles. A sphere-equivalent diameter of the first particle is not less than 1 nanometer and not more than 100 nanometers. A sphere-equivalent diameter of the second particle is more than 300 nanometers and less than 1000 nanometers. An average refractive index of the first region is larger than a refractive index of the stacked body and smaller than a refractive index of the second particle. | 2013-09-26 |
20130248913 | HIGHLY REFLECTIVE COATING ON LED SUBMOUNT - A submount for a light emitting stack includes a substrate and a metallization layer having circuit traces and a planar dielectric layer that fills regions between the circuit traces. The planar dielectric layer serves to minimize the amount of light lost/absorbed by the substrate and preferably reflects the internally reflected light back toward the desired light output element. To facilitate efficient manufacture, a dielectric paste is applied over the metallized layer, then planed to expose at least portions of the metal conductors for the subsequent coupling to the light emitting stack. Pedestal elements are preferably provided at select locations on the circuit traces to facilitate this coupling while allowing the remainder of the circuit traces to be covered with the dielectric layer. | 2013-09-26 |
20130248914 | PACKAGED OPTOELECTRONIC DEVICE AND PROCESS FOR MANUFACTURING - A packaged optoelectronic device and a method for manufacturing is provided. The packaged optoelectronic device includes at least one optoelectronic device with two electrodes sandwiched between a first barrier layer and a second barrier layer. At least one of the barrier layers comprises at least one aperture. Further, the packaged device includes a plurality of thin electrically conductive connectors. Each of the thin connectors extends out through the at least one aperture and is coupled to the anode or the cathode. Further, the thin connectors are connected to an external power source to provide power to the anode and the cathode. | 2013-09-26 |
20130248915 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, an insulating film, a p-side interconnection section, an n-side interconnection section, a phosphor layer, and a metal film. The semiconductor layer is formed on a substrate which is then removed. The p-side interconnection section is provided on the insulating film and electrically connected to the p-side electrode. The n-side interconnection section is provided on the insulating film and electrically connected to the n-side electrode. The phosphor layer is provided on the first surface and includes a step portion continued to the side surface of the semiconductor layer. The metal film is provided on the side surface of the semiconductor layer and a side surface of the step portion of the phosphor layer. | 2013-09-26 |
20130248916 | SOLID-STATE DEVICE AND METHOD OF MANUFACTURING THE SAME - A solid-state device includes a metal pattern formed on a substrate, a conductive bump connected to the metal pattern so as to be contact with a side surface of the metal pattern, and a solid-state element connected to the metal pattern via the conductive bump. A bottom surface level of at least a portion of the conductive bump is substantially equal to a bottom surface level of a portion of the metal pattern at which the metal pattern is connected to the conductive bump. | 2013-09-26 |
20130248917 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device includes a light emitting unit, a first and second electrode, a first and second metal pillar, a sealing unit, a rectifying element, and a first and second interconnection. The light emitting unit includes a first and second semiconductor layer, and a light-emitting layer. The light-emitting layer is provided on the first semiconductor layer. The second semiconductor layer is provided on the light-emitting layer. The first electrode is provided on the first semiconductor layer. The second electrode is provided on the second semiconductor layer. The first metal pillar is electrically connected to the first electrode. The second metal pillar is electrically connected to the second electrode. The sealing unit seals the first metal pillar and the second metal pillar. The rectifying element is provided below the first semiconductor layer, including a rectifying unit. | 2013-09-26 |
20130248918 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element has a cross-sectional structure comprising a support substrate, a semiconductor lamination located over the support substrate, and a joint layer located between the semiconductor lamination and the support substrate, containing a first jointing layer located on the semiconductor lamination side and a second jointing layer located on the support substrate side. In the plan view, the semiconductor lamination has corner portions and side portions along the periphery, the first jointing layer is encompassed by the second jointing layer, the second jointing layer is encompassed by the semiconductor lamination, and an annular region defined between outlines of the semiconductor lamination and of the first jointing layer has first portions corresponding to the corner portions of the semiconductor lamination and second portions corresponding to the side portions of the semiconductor lamination, widths of the first portions being narrower than widths of the second portions. | 2013-09-26 |
20130248919 | Method for Manufacturing Light-Emitting Element, Light-Emitting Element, Light-Emitting Device, Lighting Device, and Electronic Appliance - One object is to provide a light-emitting element which overcomes the problems of electrical characteristics and a light reflectivity have been solved. The light-emitting element is manufactured by forming a first electrode including aluminum and nickel over a substrate; by forming a layer including a composite material in which a metal oxide is contained in an organic compound so as to be in contact with the first electrode after heat treatment is performed with respect to the first electrode; by forming a light-emitting layer over the layer including a composite material; and by forming a second electrode which has a light-transmitting property over the light-emitting layer. Further, the first electrode is preferably formed to include the nickel equal to or greater than 0.1 atomic % and equal to or less than 4.0 atomic %. | 2013-09-26 |
20130248920 | Semiconductor Device and Manufacturing Method Thereof - As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film. | 2013-09-26 |
20130248921 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked structural body, a first electrode, and a second electrode. The stacked structural body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and a light emitting portion. The stacked structural body has a first major surface on a side of the second semiconductor layer. The first electrode is provided on the first semiconductor. The second electrode is provided on the second semiconductor layer. The first electrode includes a first pad portion and a first extending portion that extends from the first pad portion along a first extending direction. The first extending portion includes a first width-increasing portion. A width of the first width-increasing portion along a direction orthogonal to the first extending direction is increased from the first pad portion toward an end of the first extending portion. | 2013-09-26 |
20130248922 | FLIP-CHIP SEMICONDUCTOR OPTOELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating flip-chip semiconductor optoelectronic devices initially flip-chip bonds a semiconductor optoelectronic chip attached to an epitaxial substrate to a packaging substrate. The epitaxial substrate is then separated using lift-off technology. | 2013-09-26 |
20130248923 | BI-DIRECTIONAL SWITCH USING SERIES CONNECTED N-TYPE MOS DEVICES IN PARALLEL WITH SERIES CONNECTED P-TYPE MOS DEVICES - A bi-directional switch circuit includes a pair of N-type MOS devices connected in series with a common source terminal, and a pair of P-type MOS devices connected in series with a common source terminal. The series connected N-type devices are connected in parallel with the series connected P-type devices in a configuration that includes a first input/output (I/O) point of the switch circuit being connected to a drain of a first one of the N-type devices and a drain of a first one of the P-type devices. The parallel configuration also includes a second I/O point of the switch circuit being connected to a drain of a second one of the N-type devices and a drain of a second one of the P-type devices. | 2013-09-26 |
20130248924 | SEMICONDUCTOR DEVICE - A semiconductor device includes a reverse-conducting insulated gate bipolar transistor (IGBT), wherein the thickness of the semiconductor layer underlying the diode region of the device is thinner than the thickness of the semiconductor layer underlying the IGBT portion of the device. In one aspect, the semiconductor layer is a continuous layer, and trenches defining the anodes in the diode region extend further inwardly of the semiconductor layer than does the base regions of the IGBT portion of the device. | 2013-09-26 |
20130248925 | POWER SEMICONDUCTOR DEVICE - According to an embodiment, a power semiconductor device includes a semiconductor substrate, a base layer, a device portion, a guard ring, and an insulator. The semiconductor substrate includes a drift layer with a first conductive type. The base layer has a second conductive type and is selectively formed in a surface of the drift layer. The device portion is formed on the surfaces of the base layer and the drift layer. The guard ring has a second conductive type and is disposed in plural and is selectively formed in the surface of the drift layer around the device portion. The insulator is buried in at least one of the guard rings. | 2013-09-26 |
20130248926 | SEMICONDUCTOR DEVICE - A horizontal semiconductor device having multiple unit semiconductor elements, each of said unit semiconductor element formed by an IGBT including: a semiconductor substrate of a first conductivity type; a semiconductor region of a second conductivity type formed on the semiconductor substrate; a collector layer of the first conductivity type formed within the semiconductor region; a ring-shaped base layer of the first conductivity type formed within the semiconductor region such that the base layer is off said collector layer but surrounds said collector layer; and a ring-shaped first emitter layer of the second conductivity type formed in said base layer, wherein movement of carriers between the first emitter layer and the collector layer is controlled in a channel region formed in the base layer, and the unit semiconductor elements are disposed adjacent to each other. | 2013-09-26 |
20130248927 | CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE - A contact structure for a semiconductor device includes a substrate comprising a major surface and a cavity. A bottom surface of the cavity is lower than the major surface. The contact structure also includes a strained material in the cavity, and a lattice constant of the strained material is different from lattice constant of the substrate. The contact structure also includes a first metal layer over the strained material, a dielectric layer over the first metal layer, and a second metal layer over the dielectric layer. The dielectric layer has a thickness ranging from 1 nm to 10 nm. | 2013-09-26 |
20130248928 | SEMICONDUCTOR DEVICE HAVING NITRIDE LAYERS - According to one embodiment, a semiconductor device having a semiconductor substrate, first to fourth semiconductor layers of nitride, first to third electrodes and a gate electrode is provided. The first semiconductor layer is provided directly on the semiconductor substrate or on the same via a buffer layer. The second semiconductor layer is provided so as to be spaced apart from the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer and has a band gap wider than that of the second semiconductor layer. The fourth semiconductor layer insulates the first and second semiconductor layers. The first electrode forms an ohmic junction with the first to the third semiconductor layers. The second electrode is provided on the third semiconductor layer. The gate electrode is provided between the first and the second electrodes. The third electrode forms a Schottky junction with the first semiconductor layer. | 2013-09-26 |
20130248929 | Reducing Source/Drain Resistance of III-V Based Transistors - An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode. | 2013-09-26 |
20130248930 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate. | 2013-09-26 |
20130248931 | NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device has an electroconductive substrate, a first nitride semiconductor layer provided directly on the electroconductive substrate or provided on the electroconductive substrate through a buffer layer and formed of a non-doped nitride semiconductor, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, first and second element isolation insulating layers, and a frame electrode. The frame electrode is electrically connected to the source electrode and the electroconductive substrate, and surrounds outer peripheries of the heterojunction field effect transistor and the Schottky barrier diode. | 2013-09-26 |
20130248932 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR CRYSTAL GROWTH SUBSTRATE - A method of manufacturing a semiconductor device includes grinding a back side of a substrate; and forming a nitride semiconductor layer on a front side of the substrate after the grinding. Compressive stress is generated in the nitride semiconductor layer that is formed. | 2013-09-26 |
20130248933 | NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device including a device region and a guard ring formation region surrounding the device region, the nitride semiconductor device includes a first nitride semiconductor layer provided in the device region and the guard ring formation region; a second nitride semiconductor layer provided on the first nitride semiconductor layer and forming a hetero-junction with the first nitride semiconductor layer; and a shielding layer provided on the second nitride semiconductor layer in the guard ring formation region and electrically protecting the device region. A two-dimensional electron gas is present near an interface between the first nitride semiconductor layer and the second nitride semiconductor layer within the first nitride semiconductor layer below the shielding layer, and the shielding layer is in ohmic contact with the two-dimensional electron gas. | 2013-09-26 |
20130248934 | COMPOUND SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - An AlN layer ( | 2013-09-26 |
20130248935 | SIGE HETEROJUNCTION BIPOLAR TRANSISTOR WITH A SHALLOW OUT-DIFFUSED P+ EMITTER REGION - A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region. | 2013-09-26 |
20130248936 | Programmable substrate and applications thereof - An integrated circuit die includes a semiconductor substrate and a plurality of electronic circuits on the semiconductor substrate. The semiconductor substrate is divided into a plurality of regions. A first region of the substrate supports a first type of electronic circuit and has first permittivity, permeability, and conductivity characteristics. A second region of the substrate supports a second type of electronic circuit and has second permittivity, permeability, and conductivity characteristics. | 2013-09-26 |
20130248937 | ENTRENCHED TRANSFER GATE - An image sensor pixel includes a semiconductor layer, a photosensitive region to accumulate photo-generated charge, a floating node, a trench, and an entrenched transfer gate. The photosensitive region and the trench are disposed within the semiconductor layer. The trench extends into the semiconductor layer between the photosensitive region and the floating node and the entrenched transfer gate is disposed within the trench to control transfer of the photo-generated charge from the photosensitive region to the floating node. | 2013-09-26 |
20130248938 | PN-Structured Gate Demodulation Pixel - A novel photo-sensitive element for electronic imaging purposes and, in this context, is particularly suited for time-of-flight 3D imaging sensor pixels. The element enables charge-domain photo-detection and processing based on a single gate architecture. Certain regions for n and p-doping implants of the gates are defined. This kind of single gate architecture enables low noise photon detection and high-speed charge transport methods at the same time. A strong benefit compared to known pixel structures is that no special processing steps are required such as overlapping gate structures or very high-ohmic poly-silicon deposition. In this sense, the element relaxes the processing methods so that this device may be integrated by the use of standard CMOS technology for example. Regarding time-of-flight pixel technology, a major challenge is the generation of lateral electric fields. The element allows the generation of fringing fields and large lateral electric fields. | 2013-09-26 |
20130248939 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus includes a plurality of pixels, each pixel including: a photoelectric conversion unit; an amplification element; a first signal holding unit and a second signal holding unit arranged on an electric pathway between the photoelectric conversion unit and an input node of the amplification element; a first electric charge transfer unit configured to transfer an electron of the photoelectric conversion unit to the first signal holding unit; and a second electric charge transfer unit configured to transfer an electron held by the first signal holding unit to the second signal holding unit, wherein a voltage supplied to a first control electrode when the electron of the photoelectric conversion unit is transferred to the first signal holding unit is lower than a voltage supplied to a second control electrode when the electron held by the first signal holding unit is transferred to the second signal holding unit. | 2013-09-26 |
20130248940 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus of the present invention includes: a plurality of photoelectric conversion elements arranged on a substrate; a transistor for transferring a signal charge; and a plurality of transistors for reading out the signal charge transferred. The plurality of photoelectric conversion elements include a first photoelectric conversion element and a second photoelectric conversion element adjacent to each other. The photoelectric conversion apparatus of the present invention includes: a first semiconductor region having a first conductivity type arranged between the first photoelectric conversion element and the second photoelectric conversion element; and a second semiconductor region having the first conductivity type that is arranged on a region where the plurality of transistors are arranged and that has a width larger than that of the first semiconductor region of the first conductivity type. | 2013-09-26 |
20130248941 | SPIN TRANSISTORS AND MEMORY - A spin transistor according to an embodiment includes: a semiconductor layer including a p | 2013-09-26 |
20130248942 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a channel region formed on a first side surface of a fin-type semiconductor and a source/drain region formed on a second side surface, plane orientation of which is different from that of the first side surface, so that the channel region is interposed in the fin-type semiconductor. | 2013-09-26 |
20130248943 | EPITAXIAL SILICON GROWTH - Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer. | 2013-09-26 |
20130248944 | JUNCTION TYPE FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - According to one embodiment, a junction type field effect transistor includes a first conductive type semiconductor substrate, a first conductive type drift layer, a second conductive type gate region, a first conductive type channel layer, a first conductive type source region, a source electrode, a drain electrode, a second conductive type gate contact layer, and a gate electrode. The drift layer is provided on a first main surface of the semiconductor substrate. The gate region is provided on a surface of the drift layer. The channel layer is provided on the drift layer and the gate region. The source region is provided on a surface of the channel layer to face the gate region, and has an impurity concentration higher than the channel layer. The source electrode is provided on the channel layer with Schottky contact and on the source region with ohmic contact. | 2013-09-26 |
20130248945 | Electronic Circuits including a MOSFET and a Dual-Gate JFET - Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths. | 2013-09-26 |
20130248946 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The fin semiconductor device includes a fin formed on a substrate and an insulating material layer formed on the substrate and surrounding the fin. The fin has a semiconductor layer that has a source region portion and a drain region portion. The fin includes a first channel control region, a second channel control region, and a channel region between the two channel control regions, all of which are positioned between the source region portion and the drain region portion. The two channel control regions may have the same conductivity type, different from the channel region. | 2013-09-26 |
20130248947 | METHODS AND APPARATUS RELATED TO A DIODE DEVICE INCLUDING A JFET PORTION - In one general aspect, an apparatus can include an anode terminal, and a cathode terminal. The apparatus can include a junction field-effect transistor (JFET) portion having a channel disposed within a semiconductor substrate and defining a first portion of an electrical path between the anode terminal and the cathode terminal. The apparatus can also include a diode portion formed within the semiconductor substrate and defining a second portion of the electrical path between the anode terminal and the cathode terminal. The diode portion can be serially coupled to the channel of the JFET device. | 2013-09-26 |
20130248948 | Source/Drain Profile for FinFET - An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is raised above a substrate. The first source/drain region and the second source/drain region are in the fin. The channel region is laterally between the first and second source/drain regions. The channel region has facets that are not parallel and not perpendicular to a top surface of the substrate. | 2013-09-26 |
20130248949 | INTEGRATED CIRCUIT HAVING CHEMICALLY MODIFIED SPACER SURFACE - A method of fabricating an integrated circuit includes depositing a first dielectric material onto a semiconductor surface of a substrate having a gate stack thereon including a gate electrode on a gate dielectric. The first dielectric material is etched to form sidewall spacers on sidewalls of the gate stack. A top surface of the first dielectric material is chemically converted to a second dielectric material by adding at least one element to provide surface converted sidewall spacers. The second dielectric material is chemically bonded across a transition region to the first dielectric material. | 2013-09-26 |
20130248950 | SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURING THE SAME - Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer. | 2013-09-26 |
20130248951 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device is disclosed. The semiconductor device includes: a substrate; a gate structure disposed on the substrate, wherein the gate structure has a high-k dielectric layer; a first seal layer disposed on a sidewall of the gate structure, wherein the first seal layer is an oxygen-free seal layer and is non-L-shaped; and a second seal layer disposed on a sidewall of the first seal layer, wherein the second seal layer is an L-shaped seal layer. | 2013-09-26 |
20130248952 | CAPPING DIELECTRIC STRUCTURE FOR TRANSISTOR GATES - The present description relates to the field of fabricating microelectronic transistors, including non-planar transistors, for microelectronic devices. Embodiments of the present description relate to the formation a recessed gate electrode capped by a substantially void-free dielectric capping dielectric structure which may be formed with a high density plasma process. | 2013-09-26 |
20130248953 | SOLID-STATE IMAGE PICKUP APPARATUS AND IMAGE PICKUP SYSTEM - An apparatus according to the present invention in which a first substrate including a photoelectric conversion element and a gate electrode of a transistor, and a second substrate including a peripheral circuit portion are placed upon each other. The first substrate does not include a high-melting-metal compound layer, and the second substrate includes a high-melting-metal compound layer. | 2013-09-26 |
20130248954 | Unit Pixel of Image Sensor and Image Sensor Including the Same - Unit pixels included in an image sensor are provided. The unit pixel including a photoelectric conversion region in a semiconductor substrate, the photoelectric conversion region configured to generate photo-charges corresponding to incident light; a transfer gate on a first surface of the semiconductor substrate, the transfer gate configured to transmit the photo-charges from the photoelectric conversion region to a floating diffusion region in the semiconductor substrate; and a suppression gate on the first surface of the semiconductor substrate, the suppression gate configured to correspond to the photoelectric conversion region, the suppression gate including polysilicon and a negative voltage applied to the suppression gate to reduce dark currents is generated adjacent to the first surface of the semiconductor substrate. | 2013-09-26 |
20130248955 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE PHOTOELECTRIC CONVERSION APPARATUS - In a photoelectric conversion apparatus including a charge holding portion, a part of an element isolation region contacting with a semiconductor region constituting the charge holding portion extends from a reference surface including the light receiving surface of a photoelectric conversion element into a semiconductor substrate at a level equal to or deeper than the depth of the semiconductor region in comparison with the semiconductor region. | 2013-09-26 |
20130248956 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include active patterns of pillar-shapes disposed on a substrate and spaced apart from each other in one direction; a gate electrode extending in the one direction and overlapped with sidewalls of the active patterns; a gate insulating layer disposed between the gate electrode and the active patterns; bit lines connected to bottom surfaces of respective active patterns; and/or capacitors connected to top surfaces of the respective active patterns. Each of the active patterns may have no p-type/n-type (PN) junctions. A semiconductor device may include a substrate; active patterns on the substrate that are spaced apart from each other; a gate electrode configured to overlap sidewalls of the active patterns; and/or gate insulating layers between the gate electrode and respective active patterns. The active patterns may be doped with dopants of a same conductivity type. | 2013-09-26 |
20130248957 | DECOUPLING CAPACITOR CELL, CELL-BASED IC, CELL-BASED IC LAYOUT SYSTEM AND METHOD, AND PORTABLE DEVICE - A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring. | 2013-09-26 |
20130248958 | MEMORY WITH ISOLATION STRUCTURE - A recessed transistor construction is formed between a first access transistor construction and a second access transistor construction to provide isolation between the access transistor constructions of a memory device. In some embodiments, a gate of the recessed transistor construction is grounded. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell. | 2013-09-26 |
20130248959 | PROGRAMMABLE LOGIC SWITCH - According to one embodiment, a programmable logic switch includes first and second word lines above a first path transistor, a first pillar passing through the first and second word lines and connected to the first path transistor, a second pillar passing through the first and second word lines and connected to the first path transistor, a first memory device between the first pillar and the first word line, a second memory device between the first pillar and the second word line, a third memory device between the second pillar and the first word line, and a fourth memory device between the second pillar and the second word line. | 2013-09-26 |
20130248960 | SYSTEM AND METHOD OF UV PROGRAMMING OF NON-VOLATILE SEMICONDUCTOR MEMORY - A semiconductor memory storage device includes first and second doped regions of a first type disposed in a semiconductor substrate. The first and second doped regions of the first type being laterally spaced from one another. A gate dielectric extends over the semiconductor substrate between the first and second doped regions, and a floating gate is disposed on the gate dielectric. An ultraviolet (UV) light blocking material is vertically disposed above the floating gate and has a size that covers the floating gate such that the floating gate remains electrically charged after the semiconductor memory storage device is exposed to UV light. | 2013-09-26 |
20130248961 | Embedded Flash Memory - An embedded flash memory cell and a corresponding method for fabricating the embedded flash memory cell are disclosed. In some embodiments, the flash memory cell comprises a floating gate that has been formed using a metal gate and local interconnect metal. For some embodiments, the embedded flash memory can be fabricated with little-to-no additional processes than what one would normally employ in fabricating a metal-oxide semiconductor field-effect transistor (MOSFET). | 2013-09-26 |
20130248962 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; an organic molecular layer formed on the semiconductor layer, the organic molecular layer including a plurality of organic molecules, each of the organic molecules includes a tunnel insulating unit of alkyl chain having one end bonded to the semiconductor layer, a charge storing unit, and a bonding unit configured to bond the other end of the alkyl chain to the charge storing unit; a block insulating film formed on the organic molecular layer; and a gate electrode formed on the block insulating film. | 2013-09-26 |
20130248963 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - A memory cell array including a plurality of memory cell units arrayed in a matrix configuration along a first direction and a second direction which is perpendicular direction to the first direction, each memory cell unit including a plurality of memory cell transistors, a first select gate transistor and a second select gate transistor, word lines extending to the first direction, and a first insulating film formed on an upper surface of the memory cell array, a first embedded wiring layer embedded in the first embedded wiring layer, the first embedded wiring layer including a wiring portion commonly connected to a source region of each first select gate transistor, wherein the first embedded wiring layer has an inclined pattern which extends in a direction not parallel to either of the first and the second directions. | 2013-09-26 |
20130248964 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation film formed on a semiconductor substrate, a charge storage film formed on the first insulation film, a second insulation film formed on the charge storage film, and a control electrode formed on the second insulation film. The first insulation film is formed on the semiconductor substrate, and has a lower layer film containing silicon, and an upper layer film formed on the lower layer film, the upper layer film having a concentration of transition metal atoms containing at least one of hafnium, titanium, zirconium, tantalum or lanthanum from 1e13 atoms/cm | 2013-09-26 |
20130248965 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a nonvolatile semiconductor memory device including a substrate, a laminated film which has a configuration where first insulating layers and first electrode layers are alternately laminated in a first direction vertical to the substrate, a second insulating layer formed on an inner wall of a first through hole pierced in the first insulating layers and the first electrode layers along the first direction, an intermediate layer formed on a surface of the second insulating layer, a third insulating layer formed on a surface of the intermediate layer, and a pillar-like first semiconductor region which is formed on a surface of the third insulating layer and extends along the first direction. | 2013-09-26 |
20130248966 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a first floating gate electrode on the tunnel insulating film, an inter-floating gate insulating film on the first floating gate electrode, a second floating gate electrode on the inter-floating gate insulating film, an inter-electrode insulating film on the second floating gate electrode, and a control gate electrode on the inter-electrode insulating film. The inter-floating gate insulating film includes a main insulating film, and a first fixed charge layer between the main insulating film and the second floating gate electrode and having negative fixed charges. | 2013-09-26 |
20130248967 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a first memory cell on the first fin-type active area, and a second memory cell on the second fin-type active area. Each of widths of charge storage layers of the first and second memory cells becomes narrower upward from below. Each of inter-electrode insulating layers of the first and second memory cells has a contact portion through which both are in contact with each other. | 2013-09-26 |