39th week of 2008 patent applcation highlights part 61 |
Patent application number | Title | Published |
20080235481 | Managing memory in a system that includes a shared memory area and a private memory area - A method and apparatus for auto-tuning memory is provided. Memory on a computer system comprises at least one shared memory area and at least one private memory area. Addresses in the shared memory area are accessible to multiple processes. Addresses in the private memory area are dedicated to individual processes. Initially, a division in the amount of memory is established between the shared and private memory areas. Subsequently, a new division is determined. Consequently, memory from one memory area is “given” to the other memory area. In one approach, such sharing is achieved by causing the shared and private memory areas to be physically separate from each other both before and after a change in the division. The division of the amount of memory may be changed to a new division by deallocating memory from one of the memory areas and allocating that memory to the other of the memory areas. | 2008-09-25 |
20080235482 | Live Migration of a Logical Partition - A partition migration mechanism migrates a logical partition executing an operating system and resumes the logical partition before all resources in the logical partition have been migrated. When a partition is being migrated, a call checkpoint mechanism creates checkpoints of the state of the operating system when the partition manager is called. Before performing the call to the partition manager, a check is made to determine if all resources required by the call are available. If so, the partition manager call is executed. If all resources required by the call are not available, a resource fault is indicated, which causes the operating system state from the last checkpoint to be restored and a corresponding virtual CPU to be preempted until the resource that caused the fault becomes available. Exceptions that do not require the missing resource may be performed while the virtual CPU awaits the resource to become available. | 2008-09-25 |
20080235483 | STORAGE DEVICE AND METHOD FOR PROTECTING ITS PARTITION - The present invention provides a storage device and a method for protecting its protected partition in which the storage device comprises a master boot record unit and a protected partition, the protected partition comprises an application data area and a system data area for storing application data and system data to be provided to a user, respectively, and the system data area is in a customized data format of nonstandard file system. With the storage device and the method for protecting its protected partition, security of system data in the protected partition of the storage device is enhanced. | 2008-09-25 |
20080235484 | Method and System for Host Memory Alignment - Certain aspects of a method and system for host memory alignment may include splitting a received read and/or write I/O request at a first of a plurality of memory cache line boundaries to generate a first portion of the received I/O request. A second portion of the received read and/or write I/O request may be split into a plurality of segments so that each of the plurality of segments is aligned with one or more of the plurality of memory cache line boundaries. A cost of memory bandwidth for accessing host memory may be minimized based on the splitting of the second portion of the received read and/or write I/O request. | 2008-09-25 |
20080235485 | ECC implementation in non-ECC components - A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC. | 2008-09-25 |
20080235486 | Non-volatile memory devices, systems including same and associated methods - A memory device, system and method of editing a file in a non-volatile memory device is described. The memory device includes a controller and a memory array configured to copy an existing first file into a second file during editing and to maintain the first file while applying edits to the second file. When editing is completed, a first cluster pointer of the first file is redirected to point at the first cluster of the second file which has been edited. | 2008-09-25 |
20080235487 | Applying quality of service (QoS) to a translation lookaside buffer (TLB) - In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to store a priority level associated with an agent that requested storage of the data in the TLB, and an identifier field to store an identifier of the agent, where the TLB is apportioned according to a plurality of priority levels. Other embodiments are described and claimed. | 2008-09-25 |
20080235488 | Splash Tables: An Efficient Hash Scheme for Processors - A computer implemented method, data processing system, and computer usable program code are provided for storing data items in a computer. A plurality of hash functions of data values in a data item are computed. A corresponding memory location is determined for one of the plurality of hash functions. The data item and a key portion and a payload portion of all data items are stored contiguously within the memory location. | 2008-09-25 |
20080235489 | Systems for forcing an update block to remain sequential - A non-volatile memory system comprises a non-volatile memory cell array and a processor in communication with the non-volatile memory cell array. The processor is configured to provide a sequential update block, preexisting data associated with the sequential update block, and an option to convert the sequential update block to a chaotic update block. The processor is further configured to receive a write command to write data following a previous write command, where the write command and the previous write command have a discontinuity in logical addresses. If a logical address of the write command is different from the logical addresses of the preexisting data, data are written to the sequential update block. However, if the logical address of the write command matches one of the logical addresses of the preexisting data, then the sequential update block is converted to a chaotic update block. | 2008-09-25 |
20080235490 | SYSTEM FOR CONFIGURING A PROCESSOR ARRAY - Embodiments of the invention are directed to a system for configuring a processor array using configuration chains streamed down communication channels. | 2008-09-25 |
20080235491 | Techniques for Maintaining a Stack Pointer - A technique for reducing stack pointer adjustment operations when stack dependent operations, which correspond to stack dependent instructions, are encountered includes setting a stack pointer to an initial value for a stack. A number of bytes associated with the stack dependent operation is determined. A stack pointer delta is then modified based upon the number of bytes associated with the stack dependent operation. A current location in the stack is determined based on the stack pointer and the stack pointer delta. | 2008-09-25 |
20080235492 | APPARATUS FOR COMPRESSING INSTRUCTION WORD FOR PARALLEL PROCESSING VLIW COMPUTER AND METHOD FOR THE SAME - An apparatus and a method are provided for a parallel processing very long instruction word (VLIW) computer. The apparatus includes: an index code generation unit sequentially generating an index code, which is associated with a number of no operation (NOP) instruction word between effective instruction words, with respect to each of instruction word groups to be executed in a VLIW computer; an instruction compression unit sequentially deleting the NOP instruction word which corresponds to the index code with respect to each of instruction word groups; and an instruction word conversion unit converting the effective instruction words to include the index code, the effective instruction words corresponding to the NOP instruction words. | 2008-09-25 |
20080235493 | INSTRUCTION COMMUNICATION TECHNIQUES FOR MULTI-PROCESSOR SYSTEM - A method for communicating instructions to slave processors in a multi-processor system having a master processor and pipelined slave processors controlled by the master processor is described. The method uses a pass-through command having (i) a header block coded using a computer language understood by the slave processors and (ii) a payload block including instructions coded in a computer language understood by a destined slave processor. The pass-through command is transmitted to an outermost slave processor and then forwarded, without recoding, by intermediate downstream slave processors until the command reaches the destined slave processor. In one application, the method is used in a system adapted for processing video data or rendering graphics. | 2008-09-25 |
20080235494 | MUSICAL INSTRUMENT DIGITAL INTERFACE HARDWARE INSTRUCTION SET - Generating a digital waveform for a Musical Instrument Digital Interface (MIDI) voice using a set of machine-code instructions that is specialized for the generation of digital waveforms for MIDI voices. For example, a processor may execute a software program that generates a digital waveform for a MIDI voice. The instructions of the software program may be machine code instructions from an instruction set that is specialized for the generation of digital waveforms for MIDI voices. | 2008-09-25 |
20080235495 | Method and Apparatus for Counting Instruction and Memory Location Ranges - A method, apparatus, and computer instructions in a data processing system for processing instructions and monitoring accesses to memory location ranges. An instruction for execution is identified. A determination is made as to whether the instruction is within a contiguous range of instructions. Execution information relating to the instruction is identified if the instruction is within the contiguous range of instructions. With memory location accesses, an access to a memory location is identified. A determination of whether the memory location is within a contiguous range of memory locations is made. Access information is identified if the memory location is within the contiguous range of memory locations. | 2008-09-25 |
20080235496 | Methods and Apparatus for Dynamic Instruction Controlled Reconfigurable Register File - A scalable reconfigurable register file (SRRF) containing multiple register files, read and write multiplexer complexes, and a control unit operating in response to instructions is described. Multiple address configurations of the register files are supported by each instruction and different configurations are operable simultaneously during a single instruction execution. For example, with separate files of the size 32×32 supported configurations of 128×32 bit s, 64x64 bit s and 32×128 bit s can be in operation each cycle. Single width, double width, quad width operands are optimally supported without increasing the register file size and without increasing the number of register file read or write ports. | 2008-09-25 |
20080235497 | Parallel Data Output - Multiple processing threads operate in parallel to convert data, produced by one or more electronic design automation processes in an initial format, into another data format for output. A processing thread accesses a portion of the initial results data produced by one or more electronic design automation processes in an initial format and in an initial organizational arrangement. The processing thread will then store data within this portion of the initial results data belonging to a target category of the desired output organizational arrangement, such as a cell, at a memory location corresponding to that target category. It will also convert the stored data from a first data format to another data format for output. The first data format may use a relatively low amount of compression, with the second data format may use a relatively high level of compression. Each of a plurality of processing threads may operate in this manner in parallel upon portions of the initial results data, until all of the initial results data has been converted to the desired data format for output. A processing thread can then collect the converted data from the various memory locations, and provide it as output data for the electronic design automation process or processes. | 2008-09-25 |
20080235498 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus for testing a device under test. The test apparatus includes an instruction storing section that stores thereon a test instruction sequence, a pattern generating section that sequentially reads and executes an instruction from the test instruction sequence, and outputs a test pattern associated with the executed instruction, a test signal output section that generates a test signal in accordance with the test pattern, and supplies the generated test signal to the device under test, and a result register that stores thereon a value having a predetermined number of bits. Here, the instruction storing section stores thereon the test instruction sequence including therein a result register update instruction to update a value of a designated bit position in the result register with a predetermined value, and when executing the result register update instruction, the pattern generating section updates, with the predetermined value, the value of the bit position in the result register which is designated by the result register update instruction. | 2008-09-25 |
20080235499 | APPARATUS AND METHOD FOR INFORMATION PROCESSING ENABLING FAST ACCESS TO PROGRAM - A main memory stores cache blocks obtained by dividing a program. At a position in a cache block where a branch to another cache block is provided, there is embedded an instruction for activating a branch resolution routine for performing processing, such as loading of a cache block of the branch target. A program is loaded into a local memory in units of cache blocks, and the cache blocks are serially stored in first through nth banks, which are sections provided in the storage area. Management of addresses in the local memory or processing for discarding a copy of a cache block is performed with reference to an address translation table, an inter-bank reference table and a generation number table. | 2008-09-25 |
20080235500 | STRUCTURE FOR INSTRUCTION CACHE TRACE FORMATION - A design structure embodied in a machine readable storage medium for at least one of designing, manufacturing, and testing a design for a single unified level one instruction cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instructions consistent with conventional cache lines is provided. Instruction branches are predicted taken or not taken using a highly accurate branch history table (BHT). Branches that are predicted not taken are appended to a trace buffer and the next basic block is constructed from the remaining instructions in the fetch buffer. Branches that are predicted taken flush the remaining fetch buffer and the next address is determined using a Branch Target Address Register (BTAC). | 2008-09-25 |
20080235501 | Method For Detecting and Correcting Firmware Corruption - A method for detecting and correcting firmware corruption in a system having a host communicatively coupled to an electronic apparatus, the electronic apparatus having a hardware unit communicatively coupled to a non-volatile memory, includes determining via the hardware unit whether firmware on the non-volatile memory is corrupted; if the firmware is determined to be corrupted, then: invoking a communication driver resident in the hardware unit to establish bi-directional communications between the host and the electronic apparatus; and initiating a firmware download from the host to update the firmware on the non-volatile memory to an uncorrupted state. | 2008-09-25 |
20080235502 | Using a live operating system to set up and configure an active management technology device - An active management technology device may be provisioned using a live operating system stored on a disk, in one embodiment. After disk insertion, no further operator involvement may be needed in some cases. | 2008-09-25 |
20080235503 | Event-based dynamic tunables - Various approaches are disclosed for run-time update of a configurable kernel parameter that controls runtime operations of in an operating system kernel. In one approach, a first request is received to change a current value of a first configurable kernel parameter to a first new value. The first new value is not equal to the current value. The kernel continues to operate with the current value until occurrence of an un-timed event detected by the kernel. In response to occurrence of the event, the first new value is stored as the current value of the first configurable kernel parameter, and the kernel operates with the first new value as the current value. The receiving, delaying, storing, and operating are performed without rebooting the operating system. | 2008-09-25 |
20080235504 | FIRMWARE CONTROLLED DYNAMIC VOLTAGE ADJUSTMENT - Methods, apparatus, articles of manufacture, and systems for providing a supply voltage to an electronic component, such as a processor, are provided. An executable software component, such as system firmware, may access a voltage selection value embedded in the component and retrieve a voltage setting, from a table of voltage settings, using the embedded voltage selection value as an index. The software component may then configure a power supply, based on the voltage setting retrieved from the voltage selection table, to supply the component with an optimal supply voltage. For some embodiments, the voltage selection table may be replaced by downloading a new voltage selection table, thus, allowing changes to the component supply voltage without changing hardware. | 2008-09-25 |
20080235505 | METHODS AND SYSTEMS TO SELECTIVELY SCRUB A SYSTEM MEMORY - A computer system is provided, the computer system having a processor and a system memory coupled to the processor. The computer system also includes a Basic Input/Output System (BIOS) in communication with the processor. The BIOS selectively scrubs the system memory during a shutdown process of the computer system. | 2008-09-25 |
20080235506 | METHOD, SYSTEM, AND PRODUCT FOR IDENTIFYING PROVISIONING OPERATIONS VIA PLANNING METHODS - A method, system, and computer program product are disclosed for automatically determining a valid ordering of provisioning operations, and their needed parameters, so that a provisioning system can configure a desired resource state. This is accomplished by formally describing the pre-conditions and effects of provisioning operations, the current state of managed resources and the desired final state. A planning algorithm is then used to determine the provisioning operations, a valid ordering and appropriate parameters to bring the system from the current state to the desired state. | 2008-09-25 |
20080235507 | Encrypted Communication Method - A DNS Proxy unit (A | 2008-09-25 |
20080235508 | Reducing processing load in proxies for secure communications - In one embodiment, a method for providing secure communications using a proxy is provided. The proxy negotiates with a client and a server to determine a session key to use with communications between the client and the proxy and between the proxy and the server. Encrypted data may then be received from the client at the proxy. The proxy can decrypt the encrypted data for processing using the session key. In one embodiment, the decrypted data is not altered. The proxy then sends the encrypted data that was received from the client to the server without re-encrypting the data that was decrypted. Because the proxy did not alter the data in its processing of the decrypted data and the same session key is used between communications for the proxy and the server, the encrypted data stream that was received from the client can be forwarded to the server. | 2008-09-25 |
20080235509 | METHOD FOR EXCHANGING MESSAGES AND VERIFYING THE AUTHENTICITY OF THE MESSAGES IN AN AD HOC NETWORK - A method for exchanging messages containing reliable information between nodes in an ad hoc network, such as a vehicle ad hoc network. The method includes the steps of providing a public key for a PKI encrypted certificate authority signature to all nodes known to transmit reliable information. Each node transmits a signal containing node identification information and the PKI encrypted certificate authority signature associated with that node. Each node also receives like signals from other nodes and then decrypts the certificate authority signatures from the received signals by using the certificate authority public key to ascertain the authenticity of the received certificate authority signatures and the reliability of the received message. Thereafter, the nodes receive and accept messages with a TESLA encrypted signature only with nodes identified to have authentic certificate authority signatures until the occurrence of a subsequent predefined event, such as a new node in the network or the elapse of a predetermined time period. | 2008-09-25 |
20080235510 | MULTI-PARTY ENCRYPTION SYSTEMS AND METHODS - A cryptographic communication system and method having a first plurality of stations, each of the first plurality of stations having at least one encryption key K | 2008-09-25 |
20080235511 | DEVICE AUTHENTICATION AND SECURE CHANNEL MANAGEMENT FOR PEER-TO-PEER INITIATED COMMUNICATIONS - A method and system for providing secure access to a device initiating communications using a peer-to-peer signaling protocol, such as a SIP or H.323. In a device registration phase, the device contacts a secure access server, and authenticates to the secure access server by providing an identification, such as its factory ID. The secure access server then issues a device ID and private key to the authenticated device. A client can then initiate a further communication session and be authenticated by the secure access server. The secure access server returns the device identification and the device's public key to the client. The client and device can then perform a symmetrical key exchange for their current communication session, and can communicate with appropriate encryption. The device's private key can be set to expire after one or more uses. | 2008-09-25 |
20080235512 | PRINT DATA COMMUNICATION WITH DATA ENCRYPTION AND DECRYPTION - A printing job containing printing data is transmitted to a specified image forming apparatus through a communications medium so that the printing data can be printed by the specified image forming apparatus. The printing data is encrypted in an encrypting method specified for printing the printing job, the information about the destination for the image forming apparatus is obtained, and the information about the destination obtained by the obtaining means is decrypted by the disclosed method, apparatus, and medium. | 2008-09-25 |
20080235513 | Three Party Authentication - A trust provider uses established relationships with a client device and a server of an e-commerce merchant or service provider to assure the identity of each to the other. The e-commerce merchant can request an encrypted token from the client. The client may use a trust-provider key to generate the encrypted token. The server then passes the token to the trust provider, who only accepts tokens from known, authenticated entities. The trust provider then verifies the token and returns a response to the server. The response may include a client verification for use by the server and an encrypted server verification that is forwarded by the server to the client. In this fashion, both the server and client may be authenticated without prior knowledge of each other. | 2008-09-25 |
20080235514 | SAFEGUARDING ROUTER CONFIGURATION DATA - Systems for safeguarding router configuration data are described herein. Some illustrative embodiments include a system that includes a network router, a configuration device comprising configuration data used to configure the network router, and a connector capable of detachably coupling the configuration device to the network router and further capable of detachably coupling a second device to the network router (the connector routes electrical power provided by the network router to a coupled device). The electrical power is set to a voltage level usable to operate the configuration device, while capable of rendering the second device inoperative. | 2008-09-25 |
20080235515 | Pre-processing Biometric Parameters before Encoding and Decoding - Biometric parameters acquired from human faces, voices, fingerprints, and irises are used for user authentication and access control. Because the biometric parameters are continuous and vary from one reading to the next, syndrome codes are applied to determine biometric syndrome vectors. The biometric syndrome vectors can be stored securely, while tolerating an inherent variability of biometric data. The stored biometric syndrome vector is decoded during user authentication using biometric parameters acquired at that time. The syndrome codes can also be used to encrypt and decrypt data. The biometric parameters can be pre-processed to form a binary representation, in which the binary representation has a set of predetermined statistical properties enforced imposed by a set of binary logical conditions. | 2008-09-25 |
20080235516 | Portable electronic door opener device and method for secure door opening - A portable computing device for opening a door (an electronic door opener) and a method for its use is disclosed. The computing device has a shared secret key, a standard certificate, means for communicating with the door, and a processor adapted for performing operations with shared secret keys and standard certificates. The door also possesses the same shared secret key. Under normal operation, messages encoded with the shared secret key serve to establish a right to open the door. The portable computing device's standard certificate is used to respond to occasional challenges by the door, and to generate the shared secret key. Biometric capabilities of the portable computing device add an additional layer of security in screening the identity of the user of the device. A security system for controlling access, involving a first plurality of computing devices and a second plurality of doors, and operating based on shared secret keys and occasional challenges is also disclosed. | 2008-09-25 |
20080235517 | Update System for Cipher System - There is a demand for a device handling information with the use of encryption technology to safely and simply update the encryption schemes. The present invention offers an information security device having a plurality of encryption schemes and handling information safely and reliably, characterized by selecting one of the plurality of encryption schemes as an application encryption scheme and installing a different encryption scheme from the plurality of encryption schemes based on the application encryption scheme. | 2008-09-25 |
20080235518 | APPLICATION PROTECTION SYSTEMS AND METHODS - Application protection systems and methods. The system comprises a security platform device comprising a storage unit and a processing unit. The storage unit comprises a root security key and an application security key. The security platform device receives a unique key from an application. The processing unit encrypts the unique key using the root security key, and determines whether the encrypted unique key conforms to the application security key. If so, the application is allowed to execute. | 2008-09-25 |
20080235519 | Data processing method and data processing device - An object is to achieve improvement in efficiency in a case where encoding processing of data and encryption processing are executed in parallel with each other. A program of a first accelerator core out of multiple accelerator cores is reconfigured for encryption processing in order to perform encryption processing on encoded data. At this time, control is extended so that the time required for encoding processing of data for one frame and the total time of the program rewrite time for the first accelerator core and the time which the first accelerator core requires for implementing encryption processing of accumulated encoded data will be nearly equal to each other. The control is performed by a first general-purpose processor out of multiple general-purpose processors. By minimizing a wasted time during which hardware does not execute any arithmetic and logic operation, improvement in efficiency in a case where encoding processing of data and encryption processing are executed in parallel with each other is achieved. | 2008-09-25 |
20080235520 | Transportable, Configurable Data Carrier For Exchanging Data Between Electrical Devices, and Method Therefor - Adequately designed transportable data carriers are used for different applications. In order to allow for individual, particularly automatically adjustable, interactive configuration and allow also inexperienced users to rapidly transfer data, the invention relates to a data carrier comprising a single interface circuit to be connected to the respective device, a data memory for temporarily storing the data fed by the respective device, input and display means for user-controlled operation and user guidance, and a control unit that is connected to the same and is provided with a program memory for executing application programs and communication functions such that an authentication process is carried out, the transfer mode (master/slave) and the direction of the data transfer are automatically detected, and the adequate transmission type/speed/protocol for downloading the data are selected according to said authentication and identification processes with the aid of the control units for configuration purposes when the data carrier is connected to the respective device, and memory areas of the data memory can be read in and out and deleted only once the authentication process has been successful. | 2008-09-25 |
20080235521 | METHOD AND ENCRYPTION TOOL FOR SECURING ELECTRONIC DATA STORAGE DEVICES - The present invention relates to a method and an encryption tool for securing electronic data storage devices. The method and encryption tool of the present invention install a file system on the electronic data storage device. Then, an input module of the encryption tool receives a user password. A key cryptography unit generates, from the user password, at least one key. A storage module stores the at least one key on the electronic data storage device. All data that is to be stored on the electronic data storage devices is encrypted using one of the at least one key. In accordance with some embodiments of the invention, the electronic data storage device is further filled with insignificant data. | 2008-09-25 |
20080235522 | CONTENT PLAYBACK METHOD AND RECORDING AND PLAYBACK DEVICE - Where a follow-up playback is realized for content data that is recorded by changing an encryption key at predetermined intervals for copyright protection, fast feed and playback operations are provided that can get close to a video scene of a present point of time. There are two areas on the memory in which to manage key information. The key information and seed information being written into a hard disk drive are held in memory in order to allow access to the key information and seed information even as they are written. | 2008-09-25 |
20080235523 | Power Over Ethernet Connector With Integrated Power Source Equipment (PSE) Controller Supporting High Power Applications - In a Power over Ethernet (POE) system, a power source equipment (PSE) device configured to deliver power to one or more powered devices (PDs) over a plurality of Ethernet transmission lines. The PSE interface includes a multi-port transmission line connector capable connecting to multiple Ethernet transmission lines, and a power source equipment (PSE) controller module integrated with the multi-port transmission line connector. The PSE controller module is capable of high power operation beyond that specified by IEEE standard 802.3af™ for powered devices. More specifically, the PSE controller is configured to deliver over 15.4 Watts, and up to 36 Watts of power, to meet the needs of high powered devices such as IP Phones, and access points. Further, the PSE controllers can utilize, currently unused, class 4 of IEEE standard 802.3af™ to identify, initiate, and classify the high power operation mode. Or it could use multiple event physical layer classification and Data Link Layer Classification for this high power PD detection as described in the latest draft from ‘at’ task force from IEEE. | 2008-09-25 |
20080235524 | System for peripheral re-enumeration - The present invention reduces the need for peripherals to be physically removed and re-installed when a malfunction occurs. In one embodiment, a device is placed in series between the system and the peripheral. This device controls the passage of power to the peripheral. When the peripheral malfunctions, the device disallows passage of power to the peripheral, and at some later point restores power, effectively emulating a physical removal and re-installation. In a second embodiment, additional software is added to the software driver for the peripheral. In this scenario, the additional software, upon detecting that the peripheral is incommunicative, would remove power being supplied to the peripheral by the system. Again, at some later point, power is restored, thereby emulating a disconnect/reconnect sequence. | 2008-09-25 |
20080235525 | PERSONAL ELECTRONIC DEVICE WITH APPLIANCE DRIVE FEATURES - A novel personal electronic device includes a first (embedded) and second (non-embedded) processors including associated operating systems and functions. In one aspect, the first processor performs relatively limited functions, while the second processor performs relatively broader functions under control of the first processor. Often the second processor requires more power than the first processor and is selectively operated by the first processor to minimize overall power consumption. Protocols for functions to be performed by the second processor may be provided directly to the second processor and processed by the second processor. In another aspect, a display controller is designed to interface with both processors. In another aspect, the operating systems work with one another. In another aspect, the first processor employs a thermal control program. Advantages of the invention include a broad array of functions performed by a relatively small personal electronics device. | 2008-09-25 |
20080235526 | POWER-SAVING CLOCKING TECHNIQUE - A method and system for providing a clock signal having reduced power consumption is provided, called the hybrid clock system. The hybrid clock system uses a PLL for high-speed data transfers, but provides a power-saving mode for transferring data while consuming less power. In the normal mode, the hybrid clock system contains a reference clock that operates at a low frequency that drives a PLL. The PLL multiplies the reference clock frequency to a much higher frequency, and supplies the clock signal to a data transfer circuit. In the power-saving mode, the hybrid clock system turns off the PLL and connects the reference clock directly to the data transfer circuit. | 2008-09-25 |
20080235527 | Operation of computer display using auxiliary display controller - A computing apparatus includes a display, a Central Processing Unit (CPU) having active and switched-off operational states and an auxiliary display controller, which is active when the CPU is in the switched-off operational state. The computing apparatus further includes a switch, which is operative to connect the CPU to the display when the CPU is in the active operational state, so as to display first information produced by the CPU, and to connect the auxiliary display controller to the display when the CPU is in the switched-off operational state, so as to display second information produced by the auxiliary display controller. | 2008-09-25 |
20080235528 | PROGRESSIVE POWER CONTROL OF A MULTI-PORT MEMORY DEVICE - A method and system for progressively reducing the power consumption of a serial memory device is provided, called the power control system. The power control system monitors the ports of a multi-port serial memory so that they can be enabled or disabled on a per-port basis. When data is not being transmitted or received on a port, a series of steps are taken to progressively de-power portions of the port and cause the port to enter into a low-power state. By disabling certain ports and placing ports in a low-power state, the power consumption of the overall serial port memory is significantly reduced. | 2008-09-25 |
20080235529 | Information processing apparatus and cellular phone - According to an aspect of the invention, there is provided an information processing apparatus including: a control unit configured to allow a device to perform an operation consuming a first amount of electrical power when the processing unit uses the device and allow the device to perform an operation consuming a second amount of electrical power less than the first amount of electrical power when the device is not used for a predetermined period of time after the device use, the control unit configured to determine the predetermined period of time in accordance with a request of the processing unit; and a plurality of processing units configured to use the device and request a length of the predetermined period of time to the control unit. | 2008-09-25 |
20080235530 | FILE INFORMATION GENERATING METHOD, FILE INFORMATION GENERATING APPARATUS, AND STORAGE MEDIUM STORING FILE INFORMATION GENERATION PROGRAM - A method and apparatus for generating file information including setting clock information regarding a clock condition and a clock speed to be used by a speed conversion circuit block, reconstructing the clock circuit block including a new clock for accommodating insertion of the speed conversion circuit block, and associating connection terminal information indicating a connection relationship of connection terminals with speed conversion object information having set, as a speed conversion object, a connection terminal requiring connection speed conversion. The connection terminal information of the connection terminal set as the speed conversion object is extracted, speed conversion circuit information indicating a connection relationship of the connection terminals in the speed conversion circuit block and connection terminal information having the connection relationship of the connection terminals reconstructed is generated, and file information in which the speed conversion circuit block is inserted between the clock circuit block and the interface block is generated. | 2008-09-25 |
20080235531 | Apparatus and Computer Program Product for Testing Ability to Recover From Cache Directory Errors - A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache entry is stored into a cache that is accessed using the cache directory. The cache entry includes information and cache parity that is associated with that information. The directory parity is altered to imply bad parity. The bad parity implies that the address tag that is associated with this parity is invalid. The information included in the cache entry is altered to be incorrect information. However, although the information is now incorrect, the cache parity continues to imply good parity which implies that the data is good. This good parity implies that the information that is associated with the parity is valid, even though it is not. The data processing system's ability to recover from errors is tested using the directory entry and the cache entry. | 2008-09-25 |
20080235532 | REDUCING OVERPOLLING OF DATA IN A DATA PROCESSING SYSTEM - A computer implemented method, apparatus, and computer usable program code for reducing overpolled data in a data processing system is provided. A controller identifies a set of redundant measurements in a cycle. The controller then identifies a number of measurements repeated in the set of redundant measurements. The controller the computes a percentage of redundant polls based on the number of measurements repeated in the set of redundant measurements. The controller then computes a new polling period by reducing an original polling period by the percentage of redundant polls. | 2008-09-25 |
20080235533 | Fall over method through disk take over and computer system having failover function - When a primary server executing a task fails in a computer system where a plurality of servers are connected to an external disk device via a network and the servers boot an operation system from the external disk device, task processing is taken over from the primary server to a server that is not executing a task in accordance with the following method. The method for taking over a task includes the steps of detecting that the primary server fails; searching the computer system for a server that has the same hardware configuration as that of the primary server and that is not running a task; enabling the server, searched for as a result of the search, to access the external disk device; and booting the server from the external disk device. | 2008-09-25 |
20080235534 | INTEGRITY PROTECTION IN DATA PROCESSING SYSTEMS - A method for protecting the integrity of a set of memory pages to be accessed by an operating system of a data processing system, includes running the operating system in a virtual machine (VM) of the data processing system; verifying the integrity of the set of memory pages on loading of pages in the set to a memory of the data processing system for access by the operating system; in response to verification of the integrity, designating the set of memory pages as trusted pages and, in a page table to be used by the operating system during the access, marking non-trusted pages as paged; and in response to a subsequent page fault interrupt for a non-trusted page, remapping the set of pages to a region of the data processing system memory which is inaccessible to the virtual machine. | 2008-09-25 |
20080235535 | WRITING DATA PROCESSING CONTROL APPARATUS, WRITING METHOD, AND WRITING APPARATUS - A writing data processing control apparatus includes an assignment part configured to assign processing of a plurality of pieces of writing data of predetermined divided writing regions, stored in a storage device, one by one to one of a plurality of processing apparatuses in which processing is performed in parallel, and a separation part configured, when a processing error occurred as a result of processing of writing data read from the storage device by a first processing apparatus assigned, to separate the first processing apparatus in which the processing error occurred from assigning targets of subsequent writing data processing, wherein the assignment part reassigns the processing of the writing data in which the processing error occurred to a second processing apparatus being different from the first processing apparatus. | 2008-09-25 |
20080235536 | SYSTEM AND METHOD OF PREVENTING A WEB BROWSER PLUG-IN MODULE FROM GENERATING A FAILURE - The present invention improves the stability of a Web browser by identifying plug-in modules that cause failures. Data in memory at the time of a failure is analyzed, and a failure signature is generated. The failure signature is compared to a database of known failure signatures so that the source of the failure may be identified. If a plug-in module to a Web browser is identified as the source of a failure, options are presented to the user who may update the plug-in module with code that does not produce a failure or disable the plug-in module altogether. | 2008-09-25 |
20080235537 | System and method for electronic testing of multiple memory devices - A testing device may include a memory controller managing a transfer of data; and a plurality of interface boards. Each interface board includes a controller buffer. Each controller buffer transfers data between the memory controller and at least one memory module. The memory controller tests the at least one memory module. The testing device is operable to test the at least one memory module independent of an operating rate of the at least one memory module. The memory controller receives operating data of the at least one memory module. | 2008-09-25 |
20080235538 | Techniques for generating a trace stream for a data processing apparatus - A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data elements. The trace logic has trace generation logic operable to generate trace elements for inclusion in the stream, and is further arranged to generate trace timing indicators for inclusion in the stream. Each trace timing indicator indicates the elapse of one or more processing timing intervals, the processing timing interval being a predetermined plurality of clock cycles. | 2008-09-25 |
20080235539 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus that tests a device under test. The test apparatus includes a main memory that stores a test instruction stream determining a test sequence for testing the device under test, a sequence cache memory that caches the test instruction stream, a transfer section that reads the test instruction stream stored on the main memory and writes the read stream into the sequence cache memory in accordance with a described sequence, a pattern generating section that sequentially reads and executes instructions from the test instruction stream cached on the sequence cache memory and outputs a test pattern corresponding to the executed instruction, and a test signal output section that generates a test signal according to the test pattern and supplies the generated signal to the device under test, in which the transfer section overwrites the instruction read from the main memory on a space area on the sequence cache memory or an area on which executed instructions are stored and prohibits overwriting the read instruction on an area on which instructions in a predetermined range is stored, the instructions being located in the predetermined range forward from a final instruction among the executed instructions according to the described sequence. | 2008-09-25 |
20080235540 | TEST APPARATUS AND ELECTRONIC DEVICE - A test apparatus for testing a memory under test is provided, including a pattern generator generating a read address from which data is read from the memory under test and an expected value of the data read from the read address, a logical comparator comparing the read data read from the read address of the memory under test to the expected value and outputting fail data indicating pass/fail of every bit of the read data, a first fail memory storing a grouping of the read address and the fail data in a case where the read data and the expected value are not the same, a second fail memory storing fail data concerning addresses corresponding to each address of the memory under test, and an updating section updating fail data stored in the second fail memory and corresponding to the read address based on the grouping of the address and the fail data read from the first fail memory. | 2008-09-25 |
20080235541 | METHOD FOR TESTING A WORD LINE FAILURE - A method for testing a word line failure of a memory device is provided. The memory device comprises a memory cell with a transistor connecting to a word line and a bit line. The method comprises driving the word line to a predetermined voltage level by a word line driver so as to turn off or on the transistor of the memory cell; and reducing the driving ability of the word line drive. | 2008-09-25 |
20080235542 | Electronic testing device for memory devices and related methods - Described are an electronic testing device for memory devices and related methods. The testing device, comprises a memory controller managing a transfer of data and a controller buffer disposed within the memory controller. The controller buffer transfers data between the memory controller and a memory module. The memory controller tests the memory module. The testing device is operable to test the memory module independent of an operating rate of the memory module. The memory controller receives operating data of the memory module. | 2008-09-25 |
20080235543 | CONVERSION DEVICE, CONVERSION METHOD, PROGRAM, AND RECORDING MEDIUM - Provided are a conversion device and others for converting a test vector set so as to reduce a logic value difference generated before and after scan capture in outputs of scan cells included in a full scan sequential circuit. A conversion device | 2008-09-25 |
20080235544 | Built-in self-test of integrated circuits using selectable weighting of test patterns - A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides test patterns to the scan chains. Weight select logic is positioned between the scan chains and the pseudo random pattern generator and controls the weightings of the test patterns that are loaded in the scan chains. In another aspect, the weight select logic can switch the weightings of the test patterns on a per-scan-cell basis. Thus, as the scan chains are loading, the weight select logic can effectively switch between test patterns being loaded into the scan chains. | 2008-09-25 |
20080235545 | Re-using production test scan paths for system test of an integrated circuit - Mission circuitry provided to implement desired data processing operations in an integrated circuit apparatus is tested by using a plurality of scan paths to subject the mission circuitry to production testing before the integrated circuit apparatus is deployed in a mission environment. The plurality of scan paths are re-used to subject the mission circuitry to further testing while the integrated circuit apparatus is deployed in a mission environment. | 2008-09-25 |
20080235546 | SYSTEM AND METHOD FOR DETECTING A WORK STATUS OF A COMPUTER SYSTEM - A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset and a device driver. The device driver is configured for driving the Super I/O chipset to generate and send a start signal to the CPLD, and is further configured for driving the Super I/O chipset to periodically generate and send a test signal to the CPLD. The CPLD is configured for receiving the start signal and triggering a clock to start timing from an initial time, monitoring whether a predetermined amount of test signals have been received in a predetermined time, and is further configured for sending a reboot signal to the South Bridge chipset when the predetermined amount of test signals have not been received in the predetermined time. The South Bridge chipset is configured for rebooting the computer system when receiving the reboot signal. A related method is also provided. | 2008-09-25 |
20080235547 | SELF-TEST OUTPUT FOR HIGH-DENSITY BIST - A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories, a BIST controller coupled to the one or more memories to perform write operation and to receive a PASS/FAIL signal from each embedded memory and one or more comparators coupled to the one or more memories latch mutually identical outputted data coming from the memories upon a rising edge of an ORDY signal. In addition, the comparators may compare the latched mutually identical outputted data and output associated PASS/FAIL signal to the BIST controller. The BIST controller registers the received PASS/FAIL result upon receiving the PASS/FAIL signal from the comparators. The integrated circuit may include output registers coupled to the BIST controller and the comparators output a data log substantially serially upon receiving a SHIFT/CLK signal from the BIST controller. | 2008-09-25 |
20080235548 | TEST APPARATUS, AND ELECTRONIC DEVICE - A test apparatus is provided. The test apparatus includes: a main memory that stores pattern data including at least one pattern bit defining a test signal provided to each of a plurality of terminals of the device under test; a pattern cache memory that caches the pattern data read from the main memory; a pattern generation control section that reads pattern data from the main memory and writes the same to the pattern cache memory; a pattern generating section that sequentially reads the pattern data stored in each cache entry of the pattern cache memory and outputs the same; and a channel circuit that generates a test signal corresponding to each of the plurality of terminals based on the pattern data outputted from the pattern generating section and provides the same to the device under test. | 2008-09-25 |
20080235549 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus that tests a device under test. The test apparatus includes a pattern memory that stores a test instruction stream determining a test sequence for testing the device under test, an interval register that stores a repeated interval in response to the fact that the repeated interval showing at least one instruction to be repeatedly executed in the test instruction stream has been specified, an instruction cache that caches the test instruction stream read from the pattern memory, a memory control section that reads the test instruction stream from the pattern memory and writes the read stream into the instruction cache, a pattern generating section that sequentially reads and executes instructions included in the test instruction stream from the instruction cache and generates a test pattern corresponding to the executed instruction, and a signal output section that generates a test signal based on the test pattern and supplies the generated signal to the device under test. The pattern generating section repeatedly executes an instruction stream within the repeated interval in the test instruction stream when the repeated interval is stored on the interval register. | 2008-09-25 |
20080235550 | TEST APPARATUS AND ELECTRONIC DEVICE - There is provided a test apparatus for testing a device under test. The test apparatus includes a main instruction storing section that stores thereon a main test instruction sequence, a sub instruction storing section that stores thereon a sub test instruction sequence which is executed when a subroutine call instruction included in the main test instruction sequence is executed, a pattern generating section that (i) sequentially reads and executes an instruction from the main test instruction sequence and outputs (I) a test pattern associated with the executed instruction and (II) timing set information designating a combination of timings for output of the test pattern, (ii) under a condition of executing the subroutine call instruction, sequentially reads and executes an instruction from the sub test instruction sequence designated by the executed subroutine call instruction and outputs (1) a test pattern associated with the executed instruction and (2) timing set information for a test pattern associated with the subroutine call instruction or an instruction which precedes the subroutine call instruction in the main test instruction sequence, and a test signal output section that generates a test signal in accordance with the test pattern, and supplies the test signal to the device under test at a timing designated by the timing set information. | 2008-09-25 |
20080235551 | ERROR CORRECTION CIRCUIT AND METHOD THEREOF - An error correction circuit and method applicable to a DisplayPort receiver is disclosed. While decoding errors occur at a decoding stage, the invention actively adjusts settings of a physical layer by using an ANSI10B/8B decoder and performs data recovery by using a correcting unit that improves the reliability of input data. | 2008-09-25 |
20080235552 | PACKET-ASYNCHRONOUS HYBRID-ARQ - Aspects described a low receiver complexity approach for reliable packet decoding when Hybrid ARQ protocol is employed with persistent assignment and potentially an erasure sequence transmission. Multiple hypotheses packet decoding performance is achieved while mitigating multiple hypotheses receiver complexity. A reference number is utilized to perform hypotheses. The reference number is independent of a start of packet. A sequence of reference numbers can be utilized, which may not necessarily be sequential numbers. The reference numbers are pre-defined. | 2008-09-25 |
20080235553 | Data Link Layer Tunneling Technique for High-Speed Data in a Noisy Wireless Environment - In accordance with the invention, a data link layer tunneling technique is disclosed for improving the throughput of high speed data in noisy wireless environments. The method for recovering lost frames transmitted between a packet sending unit and a packet receiving unit in a data communications system, and generally comprises the steps of: (a) identifying a failure to successfully receive a missed frame at the packet receiving unit; (b) establishing a logical tunnel channel at the packet receiving unit to acknowledge the next successfully received frame; (c) starting a first timer at the packet receiving unit; (c) upon receiving a tunnel establishment request from the packet receiving unit, the packet sending unit resending the missed frame on the logical tunnel channel and starting a second timer; and (d) the packet sending unit resending the missed frame a specified number of times until receiving an acknowledgement from the packet receiving unit. | 2008-09-25 |
20080235554 | DEVICE AND METHOD FOR IMPROVED LOST FRAME CONCEALMENT - Various embodiments are described herein that make use of a lost frame concealment method for processing data frames received from transmission over a communications channel. The method involves determining whether a current data frame is a bad frame, performing source decoding on the current data frame with one or more parameters that are limited by a first set of one or more values if the current data frame is a bad frame, and performing source decoding on the current data frame with one or more parameters that are not limited if the current data frame is a good frame. | 2008-09-25 |
20080235555 | METHOD, APPARATUS, AND SYSTEM FOR RETENTION-TIME CONTROL AND ERROR MANAGEMENT IN A CACHE SYSTEM COMPRISING DYNAMIC STORAGE - Methods, systems, and apparatuses are provided for operating a cache comprising dynamic storage having an array of cells. At a refresh interval, the array of cells of the cache is refreshed. A determination is made whether an error is found in the cache at the refresh interval. If no error is found in the cache, the refresh interval is repeatedly increased by a predetermined amount until an error is found. If an error is found, the error is recovered from. A determination is made if a number of line deletions for the cache is a maximum number of line deletions for the cache. If the maximum number of line deletions is not attained, a line having the error is deleted, and the number of line deletions for the cache is increased. If the maximum number of line deletions for the cache is attained, the refresh interval is decreased by the predetermined amount. | 2008-09-25 |
20080235556 | REVERSE CONCATENATION FOR PRODUCT CODES - A system is provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media. | 2008-09-25 |
20080235557 | Semiconductor memory device - A semiconductor memory device includes: a plurality of error correction code (ECC) groups, each ECC group including plural data configured to be read from and written to the semiconductor memory device and plural parity data configured to correct an error of the plural data, wherein at least one of the ECC groups includes the plural data allocated in dispersed memory cells, not adjacent. | 2008-09-25 |
20080235558 | Subsystem and Method for Encoding 64-bit Data Nibble Error Correct and Cyclic-Redundancy Code (CRC) Address Error Detect for Use in a 76-bit Memory Module - A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are concatenated with 64 data bits and 2 flag bits to generate a 72-bit check word. The 72-bit check word is input to an error-correction code (ECC) generator that generates 12 check bits that are stored in memory with the 64 data bits. A 76-bit memory module can store the 64 data and 12 check bits. Nibble errors can be corrected, and all nibble+1 bit errors can be detected. Also, a 6-bit error in a sequence of bits can be detected. This allows all errors in the 6-bit CRC of the address to be detected. The CRC code and ECC are ideal for detecting double-bit errors common with multiplexed-address DRAMs. | 2008-09-25 |
20080235559 | Strengthening parity check bit protection for array-like LDPC codes - An LDPC parity check matrix originated using an array code provides more protection against errors for parity bits 1 through 1-p, which can, during decoding, allow faster convergence to a higher LLR value for those bits as well as higher overall reliability of other parity check bits. The present parity check matrix provides an upper triangular sub-matrix (H | 2008-09-25 |
20080235560 | Flash Error Correction - A data processing device for detecting and correcting data errors of a re-writable memory via an error correction algorithm. In one embodiment, the data processing device includes a coding unit implemented in hardware and an error correction unit implemented in software. In one embodiment, the coding unit is capable receiving a first set of data to be written to the memory and processing that data in accordance with an error correction algorithm to form a second set of data. The second set of data may be output to memory. In one embodiment, the coding unit receives data from the memory and processes that data in accordance with the error correction algorithm to determine whether the data contains an error. In one embodiment, the error correction unit receives data that contains an error and produces corrected data via an error correction algorithm. The corrected data may be output to the memory. | 2008-09-25 |
20080235561 | Methodology and apparatus for soft-information detection and LDPC decoding on an ISI channel - A system comprising a plurality of channel detectors (CDs) receiving quantized and equalized ISI channel information indicative of an LDPC codeword. The channel information is split for input to the CDs, such that each CD receives channel information indicative of a portion of the LDPC codeword. Each CD outputs at least first soft information for bits of the codeword portion of that CD. The first soft information for the codeword is received by an LDPC decoder, which uses the soft information to produce a user bit sequence and second soft information about the user bit sequence. The system can cause the second soft information to be input to the plurality of CDs, such that iterative processing can occur for the codeword. Other aspects include a system providing clocking of one or more CDs at a frequency selected to balance codeword throughput of the CDs with codeword throughput of an LDPC decoder clocked by a second clock, and methods according to each system. | 2008-09-25 |
20080235562 | REVERSE CONCATENATION FOR PRODUCT CODES - Method and computer program product are provided to encode data for recording onto media whereby modulation and linear constraints from a concatenated code or product code are imposed. A first array of unencoded user data is generated. Each row is modulation encoded to enforce a first modulation constraint; the array is transformed into a second array which is transformed into a third array having predetermined empty locations in each column interleaved with the modulated data. A C2-parity byte is computed for at least some of the empty locations of the third array and a fourth array is generated. C1-parity symbols in each row are computed, generating a fifth array. A second modulation constraint is enforced on each C1-parity symbol in each row of the fifth array, generating a sixth array. The rows of the sixth array are assembled with header and sync fields for recording onto a recording media. | 2008-09-25 |
20080235563 | Document displaying apparatus, document displaying method, and computer program product - A document displaying apparatus includes a document acquiring unit that acquires a structured document containing a plurality of structured document elements, a display-size acquiring unit that acquires a display size of a display area where the structured document is to be displayed, a sectionalizing unit that sectionalizes the structured document into pages based on the display size and an amount of the document elements, an information arranging unit that arranges the pages in the display area, and a document displaying unit that displays the pages in switchable manner. | 2008-09-25 |
20080235564 | METHODS FOR CONVERTING ELECTRONIC CONTENT DESCRIPTIONS - A method, apparatus and article of manufacture for creating visualizations of electronic audiovisual compositions are described. In one embodiment, a method comprises: receiving an electronic composition description; rendering a visual representation of electronic visual composition description; generating a content description that includes semantic information and location information for elements within the electronic audiovisual composition description; identifying one or more audible, visual, and audiovisual elements from the content description; and generating a multimedia overview of the electronic composition description that includes a selected set of the identified one or more audible, visual, and audiovisual elements. | 2008-09-25 |
20080235565 | System and Method for Reference Validation in Word Processor Documents - Systems and methods are provided for supporting the use of hypertext links in documents such as word processor documents. A given word processor document is scanned for link representations to sources that are external to the word processor document. These identified link representations are then checked for validity and functionality, and the external sources are also checked for content and accessibility. In order to facilitate checking the content of the external sources, the word processor document is appended to include all or part of the content of each linked external source. The appended information is then used for subsequent content comparisons. Checking of the link representations and external sources is used to produce a current validity status for each link representations. The validity status of the links within a given document are indicated to an author or reader using visual queues by modifying non-link aspects of the word processor document, by modifying the appearance of a file name or file folder associated with the word processor document or by modifying the appearance of a cursor used in conjunction with the word processor document. | 2008-09-25 |
20080235566 | PRESENTATION OF MEDIA IN AN APPLICATION - A method and apparatus for presenting timed media represented by data in a markup language (e.g., HTML) including examining a tag or metadata which is capable of specifying more than one form or representation of timed media, such as different versions of a video encoded according to different video codec standards. | 2008-09-25 |
20080235567 | INTELLIGENT FORM FILLER - Automatically determining values for fields in an electronic document. In one embodiment, an intelligent form filler automatically fills in at least some of the fields based on as set of rules associated with a domain. A particular set of domain rules may have class definitions that define how to classify a field for that domain and group definitions that define how to group fields. The domain rules also describe how values can be determined for the fields, based on the classifications, groupings, and other factors. In one embodiment, the intelligent form filler submits more than one form such that different combinations of values are submitted. The values that were used to fill in the form(s) may be provided to an extraction tool, which use the values to facilitate extraction of information from a document returned in response to submitting the form. | 2008-09-25 |
20080235568 | METHOD AND APPARATUS FOR VISUALIZING MULTIDIMENSIONAL DATA SETS USING EXPANDABLE GRIDS WITH HIERARCHICALLY-LABELED AXES - A system and methodology for visualizing large multidimensional data sets on a display device using an expandable/retractable grid that displays the nodes of multiple levels of a hierarchy simultaneously. The data set is displayed as a grid having at least one hierarchically-labeled axis, each of the grid's at least one labeled axes having labels that represent values or categories of the values of an indexing dimension corresponding to the data set. The method includes selecting a label of at least one of the hierarchically-labeled axes representing an unexpanded hierarchical category and, in response, displaying a hierarchy expansion of a portion of the hierarchy represented by the selected label. Additionally, the method displays a grid expansion relating to the expanded hierarchy portion. Each grid cell of the grid expansion displays a visual representation of one or more data records having values represented by those labels that indicate axis partitions to which the grid cell corresponds. | 2008-09-25 |
20080235569 | AUTO-GENERATION AND AUTO-VERSIONING OF A MULTI-SOURCED DYNAMIC DOCUMENT - A computer-implementable method, system and computer media for auto-generating and auto-versioning a dynamic document are presented. In a preferred embodiment, the computer-implementable method includes populating a dynamic document with content from multiple sources. The dynamic document is then version named in accordance with a nomenclature rule that identifies a source and version of content from the multiple sources. In response to a content from one or more of the multiple sources changing at a source, the dynamic document is updated with updated content, and a version name of the dynamic document is updated to reflect the updated content. | 2008-09-25 |
20080235570 | System for communication through spatial bulletin board - A spatial bulletin board input device converts a movement of drawing a memo content in an actual space to three-dimensional coordinate information and acquires positional information which specifies a place in which the memo is written and saves the information in a spatial communication server. In the image-pickup place in the actual space, the picked-up image in the actual space is displayed on a spatial bulletin board display device and a browsing request is sent to the spatial communication server. The spatial bulletin board display device acquires the three-dimensional coordinate information and the memo positional information of the memo content near the image-taking place from the spatial communication server and displays the memo content on the picked-up image. | 2008-09-25 |
20080235571 | Display device - A display device includes a display area displaying information therein, an information storing unit storing therein a plurality of pieces of predetermined information displayable in the display area, an abbreviation storing unit storing therein an abbreviation corresponding to each of the predetermined information, an information detecting unit configured to detect first information of the predetermined information as a subject to be displayed in the display area, a judging unit judging whether the first information includes a plurality of pieces of information, and a first control unit configured to acquire each of the first information and an abbreviation thereof from the information storing unit and the abbreviation storing unit, respectively, and to display each of the first information and the abbreviation thereof in the display area, in case where it is judged that the first information includes a plurality of pieces of information. | 2008-09-25 |
20080235572 | System and method for processing dynamic data sets in web applications - Large data sets are displayed and processed. User mark-up language display provides a plurality of line items, each line item including a checkbox. A name/value pair is generated and stored to a text string responsive to the user selecting a checkbox of a line item. The name/value pairs are parsed into a parameter names array and a parameter values array responsive to the user selecting a submit command. The parameter names array is processed to identify each parameter name containing a checkbox indicia, and for each parameter name containing a checkbox indicia, line item detail is retrieved from the detail arrays corresponding for display to the user, who may store a current document as a draft. The user selects or deselects a line item, and the parameter names array is again processed to identify new data available in, or old data no longer available in, the detail arrays. | 2008-09-25 |
20080235573 | Content Markup Transformation - Methods of correcting and transcoding markup language content for mobile devices are described. In an example, mobile device capabilities are determined. Content is processed to correct malformed tags in the content based on the determination. The corrected content is transcoded from a first mark-up language which is not supported by a mobile device into a second markup language which is supported by the mobile device. | 2008-09-25 |
20080235574 | Multi-frame display system with semantic image arrangement - Methods and systems for managing presentation of digital images using multiple separate digital media frames each positioned in a separate location and providing images that are viewable within a presentation space, the method comprising the steps of providing access to a source of a plurality of digital images; determining a semantic type defining at least one semantic element of the digital images to be presented; determining the number of the multiple separate digital media frames that are available to be used for presenting the digital images; determining the semantic content of the accessed digital images; selecting digital images for presentation having determined semantic content that corresponds to the determined semantic type; determining a manner for presenting the selected digital images using the determined number of number of digital media frames; and, presenting the selected digital images in the determined manner. | 2008-09-25 |
20080235575 | System and technique for editing and classifying documents - Embodiments of a computer system which determines information associated with documents are described. During operation, this computer system receives documents (such as images). Then, the computer system determines a first set of editing instructions and classification information associated with the documents using image-processing software. Next, the computer system receives a second set of editing instructions and classification information associated with the documents. Note that the second set of editing instructions and classification information are generated by a group of individuals and include modifications and additions to the first set of editing instructions and classification information. | 2008-09-25 |
20080235576 | METHOD AND SYSTEM FOR AUTOMATIC COMPUTATION CREATIVITY AND SPECIFICALLY FOR STORY GENERATION - A computer-implemented method (and system) of automatically generating a story, includes selecting a theme of the story, examining elements of the theme and instantiating the theme, and using the theme to select and control other aspects of the story. | 2008-09-25 |
20080235577 | SYSTEM AND METHOD FOR EMBEDDING A WRITTEN SIGNATURE INTO A SECURE ELECTRONIC DOCUMENT - A system and method for embedding a written signature into a secure electronic document is disclosed. The method includes forming a placeholder electronic document containing content to be attested to by a signature. A signing individual can be selected from a signer list. A signature tag can be placed into the placeholder electronic document at a selected signature location. The signature tag is associated with the signing individual and defines the signature location for the signing individual to sign. The placeholder electronic document can be secured to form a secure electronic document having content configured to be uneditable. A signature can be captured with a signature capture device configured to enable the signing individual to write the signature to be embedded into the secure electronic document at the location indicated by the signature tag to mimic a real world experience of signing paper documents. | 2008-09-25 |
20080235578 | INLINE EDITING OF WEB PAGE INPUT FIELDS USING A VISIBLY PROMINENT FIELD - A device, such as a mobile terminal, may display a web page to a user that includes an input field. The device may display, in response to selection of the input field by the user, a graphical overlay of the input field in which the graphical overlay covers at least a portion of the input field and text entered in the graphical overlay is more visibly prominent than text entered in the input field. A user of the device may enter text for the input field via the graphical overlay. | 2008-09-25 |
20080235579 | COMPARING AND MERGING MULTIPLE DOCUMENTS - Provided are a method, system, and article of manufacture for comparing and merging multiple documents. A determination is made of a plurality of merge documents to merge, wherein each merge document includes content element locations, wherein content in the content element locations comprises user content or indication that the content element location is empty. A determination is made for each content element location in the determined merge documents content element locations in the merge documents having a same content and content element locations in at one of the determined merge documents having different content than the other determined merge documents. An aggregate document is generated including content element locations corresponding to the content element locations in the determined merge documents. A content graphical indicator is rendered with content element locations in the aggregate document for which at least one of the determined merge documents provide different content. User selection is received of one content element location for which the graphical indicator is rendered. Information is rendered for the content in the plurality of the merge documents provided for the selected content element location, wherein at least one of the merge documents provide different content for the selected content element location. | 2008-09-25 |
20080235580 | BROWSER INTERPRETABLE DOCUMENT FOR CONTROLLING A PLURALITY OF MEDIA PLAYERS AND SYSTEMS AND METHODS RELATED THERETO - A browser interpretable document comprising a first media file or a pointer to the first media file; a graphical user interface definition, or a pointer to the graphical user interface definition, the graphical user interface definition comprising a first user interface element and a function associated with the first user interface element; and, a set of commands, or a pointer to the set of commands, for controlling the operation of a plurality of media players; wherein, when the browser interpretable document is rendered by a conventional web browser, the web browser can render a graphical user interface based on the graphical user interface definition, and wherein the rendered graphical user interface controls one of the plurality of media players to facilitate playing of the first media file. | 2008-09-25 |