39th week of 2009 patent applcation highlights part 55 |
Patent application number | Title | Published |
20090240826 | Using RTCP Statistics For Media System Control - Methods for using communication network statistics in the operation of a real-time communication system are disclosed. Embodiments of the invention may provide improved playback of real-time media streams by incorporating into the algorithms used for playback of the media stream network statistics typically calculated by some transport protocols. | 2009-09-24 |
20090240827 | METHODS FOR TRANSMITTING MULTIMEDIA FILES AND ADVERTISEMENTS - The invention is directed to a method of transmitting a file having an advertising portion and a requested portion different from the advertising portion. The method includes receiving a request to transmit the file, via a streaming protocol allowing non-sequential access, transmitting the advertising portion of the file, receiving a request to transmit a portion of the requested portion of the file prior to completing transmitting the advertising portion of the file, completing the transmission of the advertising portion of the file, and transmitting the requested portion of the file. | 2009-09-24 |
20090240828 | METHODS FOR TRANSMITTING MULTIMEDIA FILES AND ADVERTISEMENTS - The invention is directed to a method of transmitting a file having an advertising portion and a requested portion different from the advertising portion. The method includes receiving a request to transmit the file, via a streaming protocol allowing non-sequential access, transmitting the advertising portion of the file, receiving a request to transmit a portion of the requested portion of the file prior to completing transmitting the advertising portion of the file, completing the transmission of the advertising portion of the file, and transmitting the requested portion of the file. | 2009-09-24 |
20090240829 | TRANSLATING BETWEEN IMPLICIT AND EXPLICIT PUBLISH-SUBSCRIBE PROTOCOLS - In one embodiment, a translating publish-subscribe (pub-sub) server may be configured to receive a subscribe request from a subscriber device according to an original pub-sub model. The server may then convert the received subscribe request into a pub-sub subscribe request of a second pub-sub model, and may transmit the converted received subscribe request to publisher servers operating according to the second pub-sub model. | 2009-09-24 |
20090240830 | METHODS FOR TRANSMITTING MULTIMEDIA FILES AND ADVERTISEMENTS - The invention is directed to a method of transmitting a file having an advertising portion and a requested portion different from the advertising portion. The method includes receiving a request to transmit the file, via a streaming protocol allowing non-sequential access, transmitting the advertising portion of the file, receiving a request to transmit a portion of the requested portion of the file prior to completing transmitting the advertising portion of the file, completing the transmission of the advertising portion of the file, and transmitting the requested portion of the file. | 2009-09-24 |
20090240831 | Method, device, and communication system for adjusting data rates in a network - A method for adjusting data rate in a network is disclosed. In the method, when a device is added to the network, a data rate controlling parameter is configured, and when there is a new service or the requirements of a service have been changed, the data rate will be adjusted by modifying the data rate controlling parameter of a source device and/or a transfer device. Therefore, the fairness among these devices would be guaranteed, and the congestion over the network would be mitigated. The present invention also discloses a wireless communication system, a data rate adjusting device, and a topologic server. | 2009-09-24 |
20090240832 | RECEIVING APPARATUS, TRANSMITTING APPARATUS, COMMUNICATION SYSTEM, AND METHOD OF DETECTING BUFFER SETTING OF RELAY SERVER - A receiving apparatus of the present invention includes: a relayed dummy data receiving unit for receiving relayed dummy data including dummy data of n bytes (n≧1) and/or dummy data of N bytes (N≧n) sequentially and repetitively transmitted from a transmitting apparatus to a relay server from the relay server; and a buffer setting detecting unit for detecting a buffer setting of the relay server based on a first size value indicative of data size of relayed dummy data received for the first time by the relayed dummy data receiving unit and a second size value indicative of not larger data size of relayed dummy data received for the second time and relayed dummy data received for the third time. | 2009-09-24 |
20090240833 | Method and Apparatus for Realizing Positioning Play of Content Stream in Peer-to-Peer Network - A method of content transmission in peer-to-peer network includes the following steps: dividing contents to be transmitted into a plurality of stripes in time sequence ( | 2009-09-24 |
20090240834 | MANAGEMENT APPARATUS, COMMUNICATION PATH CONTROL METHOD, COMMUNICATION PATH CONTROL SYSTEM, AND COMPUTER-READABLE STORAGE MEDIUM - A management apparatus manages relay apparatus information about communication of a relay apparatus, and connection information about a relay apparatus to which a communication apparatus is connected, and controls change of a communication path between communication apparatuses based on information including the relay apparatus information and the connection information. | 2009-09-24 |
20090240835 | INTERACTIVE WHOIS - A Registering Entity or another entity may provide a framework for collecting WHOIS Business Information from a Non-Controlling Party of a domain name and entering it into WHOIS. The framework may include a website, webpage, web service, web resource, software, API, or another technological solution suitable for collecting WHOIS Business Information from Non-Controlling Party. The website, webpage, web service, or the web resource may be located at URL associated with a Controlling Party's domain name, e.g. an active or a parked page for the domain name. WHOIS Business Information will be typically available for viewing to everyone along with the traditional WHOIS information. | 2009-09-24 |
20090240836 | SUPPORT APPARATUS, DESIGN SUPPORT METHOD, AND DESIGN SUPPORT PROGRAM - The configuration data obtaining unit obtains a network configuration data, and the actual-apparatus collection result data obtaining unit obtains an actual-apparatus collection result data. Then, the comparing unit compares a network address in the network configuration data corresponding to a network apparatus with a network address in the actual-apparatus collection result data corresponding to the network apparatus, and determines whether the network address is normally set to the network apparatus based on the comparison result. | 2009-09-24 |
20090240837 | METHOD FOR TRANSMITTING DATA - A data transmission method suitable for transmitting a first data table from a server to a mobile device is provided, wherein the first data table has a plurality of first data fields. The data transmission method includes following steps. A maximum used bit number of each of the first data fields is identified, wherein when the maximum used bit number of one of the first data fields is 0, the first data field is deleted so as to form a second data table. The second data table is then transmitted to the mobile device. | 2009-09-24 |
20090240838 | Broadcasting A Message In A Parallel Computer - Methods, systems, and products are disclosed for broadcasting a message in a parallel computer. The parallel computer includes a plurality of compute nodes connected together using a data communications network. The data communications network optimized for point to point data communications and is characterized by at least two dimensions. The compute nodes are organized into at least one operational group of compute nodes for collective parallel operations of the parallel computer. One compute node of the operational group assigned to be a logical root. Broadcasting a message in a parallel computer includes: establishing a Hamiltonian path along all of the compute nodes in at least one plane of the data communications network and in the operational group; and broadcasting, by the logical root to the remaining compute nodes, the logical root's message along the established Hamiltonian path. | 2009-09-24 |
20090240839 | DATA STORAGE DEVICE - A storage device for storing data includes: an interface controller connectable to a host via a interface, the interface controller having an active state capable of transmitting data to the host and an inactive state having a lower power consumption than the active state; a medium for storing data; a head for read out data stored in the medium; and a processor for executing a process including receiving a command for reading out data stored in the medium from the host, determining timing when the data read out from the medium reaches the interface controller, and starting transition of the interface controller from the inactive state into the active state before the determined timing. | 2009-09-24 |
20090240840 | METHODS AND APPARATUS FOR CONFIGURING INTERFACE UNITS - A toolset comprising a set of computer software programs that support a family of configurable remote interface units for use in an aircraft. The software includes configuration data as to the function each unit is to perform, generic function templates defining how a function should be structured and template instances derived from the generic function templates. Specific template instances are selected that are compatible with a specific interface unit. | 2009-09-24 |
20090240841 | PORTABLE MEMORY DRIVE WITH PORTABLE APPLICATIONS AND CROSS-COMPUTER SYSTEM MANAGEMENT APPLICATION - A system and method for transporting the look, feel, and function of one's personalized computer preferences across multiple host computers, including the appearance, settings, programs, and user data. This system and method uses a portable memory device and a data management system that maintains a consistent interface and data file structure on multiple host computers, including a common visual desktop interface. The portable memory solution also provides mobile access to the user's applications and personal data files. The memory device is capable of being connected to multiple host computers via a standard interface such as a USB port. | 2009-09-24 |
20090240842 | PORTABLE ELECTRONIC APPARATUS - The present invention provides a portable electronic apparatus. The portable electronic apparatus includes an input unit, a first controller, a second controller, a human interface device (HID), and a switch unit. The input unit generates input signals from a user. The first controller performs a first group of functional applications and generates a first group of functional interfaces. The second controller performs a second group of functional applications and also generates a second group of functional interfaces. The HID receives the input signals generated from the input unit and generates a control instruction. The switch unit receives the control instruction from the HID to switch between the first controller and the second controller. Accordingly, the first controller and the second controller perform corresponding functions. | 2009-09-24 |
20090240843 | APPARATUS FOR DETECTING A USB HOST - A multi-interface integrated circuit (IC) comprises a plurality of transistors, and a level detection block. At least one transistor of the plurality of transistors is in communication with a first terminal and either a first or a second lead of the multi-interface IC, and at least one of the plurality of transistors is in communication with the first terminal, a second terminal and either the first or a second lead of the multi-interface IC. The level detection block is in communication with at least one of the plurality of transistors and the first and second leads. | 2009-09-24 |
20090240844 | METHOD FOR ADDING HARDWARE - A method for adding hardware is provided. The method is adapted for connecting a Plug-and-Play (PNP) device to a computer through a universal serial bus port (USB port). The method includes activating an enumeration process. According to the enumeration process, a filter driver identifies a device type of the PNP device. If the device type is an excluded device type, the filter driver terminates the enumeration process. If the device type is an allowable device type, the enumeration process continuously progresses to add the PNP device onto the computer. | 2009-09-24 |
20090240845 | Audio help system - A communication system includes a communication device and a controller that detects input supplied to a vehicle subsystem. The controller consequently causes the communication device to output operational instruction information about the subsystem. | 2009-09-24 |
20090240846 | UNIVERSAL SERIAL BUS MASS STORAGE DEVICE ASYNCHRONOUS FILE AND FILE SYSTEM UPDATE WHILE CONNECTED TO A PC OR OTHER DEVICE - A system and method for universal serial bus mass storage device asynchronous file and file system update while connected to a pc or other device employs setting error flags and timestamp change flags when a file is changed, and returning the error conditions in reply to a REQUEST_SENSE command. | 2009-09-24 |
20090240847 | High Speed Memory Access in an Embedded System - Data is processed in an embedded system by writing data read from a peripheral device in response to an event to memory external to the embedded system. The data or a portion of the data is copied to memory internal to the embedded system. Which portion of the data is stored in both the external memory and the internal memory is tracked. The copied data is retrieved from the internal memory by a processor included in the embedded system. The processor has one or more caches logically and physically separated from the internal memory. The processor uses the copied data it retrieved to begin servicing the event. | 2009-09-24 |
20090240848 | Method and Device for the Transfer of a Data Flow a Data Source to a Data Sink - In the transfer of AV data flows, especially in a network environment, a delayed transition from one operating mode to the other operating mode will be possible when changing the operating mode from e.g. normal replay to fast forward search. This is due to the fact that—in the transfer from data source to data sink different buffer memory stages must be passed before the transferred data finally come to decoding. When the request for changing the operating mode comes, the data already present in the buffer memories must first be processed before the actually requested new data come to be decoded. For the solution of the problem described, it is suggested according to the invention that—after the request of changing the operating mode—the undesirable data in the buffer memories are quickly eliminated through suitable measures so that the desired data can then be decoded faster. To do that, an identifier for the new operating mode is inserted in the data flow on the part of the data source device. The decoder driver of the decoder in the data sink device will search for the inserted identifier in the data flow and reject all data packets which are not combined with this identifier. Thus, the buffer memory stages are discharged fast and a smooth transition with the change of operating mode will be realized. | 2009-09-24 |
20090240849 | System and Method for Distributing Virtual Input/Output Operations Across Multiple Logical Partitions - The Distributed Virtual I/O Tool replaces dedicated VIO server LPARs by distributing the virtual I/O functions across several application LPARs connected by a high-speed communication channel. The physical I/O devices are distributed across available LPARs. The Distributed Virtual I/O Tool assigns each I/O request to an appropriate I/O device. The Distributed Virtual I/O Tool monitors each I/O request and reassigns I/O devices when performance drops on a specific device or when a device is no longer available. | 2009-09-24 |
20090240850 | INSTRUCTION SET FOR PROGRAMMABLE QUEUING - A traffic manager includes an execution unit that is responsive to instructions related to queuing of data in memory. The instructions may be provided by a network processor that is programmed to generate such instructions, depending on the data. Examples of such instructions include (1) writing of data units (of fixed size or variable size) without linking to a queue, (2) re-sequencing of the data units relative to one another without moving the data units in memory, and (3) linking the previously-written data units to a queue. The network processor and traffic manager may be implemented in a single chip. | 2009-09-24 |
20090240851 | USB CONTROLLER AND BUFFER MEMORY CONTROL METHOD - A USB controller according to one aspect of the present invention is a USB controller incorporated in a USB device, the USB controller including a RAM that stores data transferred through a USB port or a CPU bus, and a register that holds a setting for determining to which one of a region for host used for a host function and a region for peripheral used for a peripheral function a part of the RAM is allocated. | 2009-09-24 |
20090240852 | UART/USB CONVERTING APPARATUS - A UART/USB converting apparatus includes a UART connector, a UART/USB converting chip and a USB connector. The UART connector is for transceiving a UART signal ranging from 0 to 3.3 volts. The UART/USB converting chip electrically connected to the UART connector is for converting between the UART signal and a USB signal. The USB connector electrically connected to the UART/USB converting chip is for transmitting the USB signal. | 2009-09-24 |
20090240853 | Method and apparatus for configuring a bus network in an asset management system - A method and system for managing assets includes a controller area network bus having a first end and a second end. One or more sensor systems are connected to the network bus. The sensor systems are connected to one or more assets to obtain at least one of operational data and condition data for the one or more assets. A self-healing bridge is connected to the first end and the second end of the network bus and is adapted to minimize a loss of connectivity in the network bus. | 2009-09-24 |
20090240854 | Multiple Removable Non-Volatile Memory Cards Serially Communicating With a Host - Two or more very small encapsulated electronic circuit cards to which data are read and written are removably inserted into two or more sockets of a host system that is wired to the sockets. According to one aspect of the disclosure, command and response signals are normally communicated between the host and the cards by a single circuit commonly connected between the host and all of the sockets but during initialization of the system a unique relative card address is confirmed to have been written into each card inserted into the sockets by connecting the command and status circuit to each socket one at a time in sequence. This is a fast and relatively simple way of setting card addresses upon initialization of such a system. According to a second aspect of the disclosure, the host adapts to transferring data between it and different cards of the system over at least two different number of the data lines commonly connected between the host and all of one or more sockets, each card permanently storing a host readable indication of the number of parallel data lines the card is capable of using. This allows increasing the rate of data transfer when the need justifies an increased card circuit complexity. According to a third aspect of the disclosure, a serial stream of data is sent over a number of data lines from one to many by alternately connecting bits of the stream to a particular number of individual lines. | 2009-09-24 |
20090240855 | METHOD AND APPARATUS FOR CONTROL IN RECONFIGURABLE ARCHITECTURE - An apparatus and method for control in a reconfigurable architecture is shown and described. In one example, an integrated circuit configured to implement a plurality of communications standards includes a plurality of upper level controllers and a plurality of lower level controllers. The upper level controller are configured to operate according to a portion of a communications standard and implement upper level control functions for the associated standard. The low level controllers are capable of communicating with each of the upper level controllers and can be assigned to each of the upper level controls to implement low level functions of each of the plurality of communications standards. | 2009-09-24 |
20090240856 | VIRTUAL HOST ISOLATION AND DETECTION OF EMBEDDED OPERATIONAL FLIGHT PROGRAM (OFP) CAPABILITIES - The present invention relates to an object oriented architecture that includes a plurality of host aircraft interface objects that enable a plurality of different host aircraft or variants to be attached or interfaced to an associated store, such as a targeting pod or a weapon system. The union of all aircraft hosts and variants are packaged and maintained as one executable capable of adapting to the predetermined suite of identified hosts and host variants. At least one or more interface objects provide a virtual translation layer which is dynamically determined and allocated during instantiation. Auto detection of the host aircraft/host aircraft variant provides the specific interface protocol by which the store can process and provide status via a predetermined signal format. | 2009-09-24 |
20090240857 | Method and device for controlling a bus system and a corresponding bus system - Method for controlling a bus system having at least two users, a first user repeatedly transmitting a reference message in at least one predeterminable time interval over the bus system, the reference message being triggered by time trigger information when the time information reaches a time mark assigned to the trigger information, wherein the time mark is altered at least once in such a way that when the time information reaches the altered time mark, time shifting of the trigger information occurs. | 2009-09-24 |
20090240858 | WIRELESS COMMUNICATION APPARATUS - A wireless communication apparatus including a master unit and a slave unit. The master unit includes a transmitter configured to transmit a beacon periodically and a receiver. A detector is provided that is configured to output a detected signal, and the slave unit is configured to receive the detected signal from the detector. The slave unit includes a receiver configured to receive the beacon periodically at a receiving timing determined based on the beacon, and a transmitter configured to transmit the detected signal to the master unit receiver at a transmitting timing determined based on the beacon if a value of the detected signal changes by a threshold amount. | 2009-09-24 |
20090240859 | AUTOMATIC ADDRESS SETTING SYSTEM - An automatic address setting system and method includes a master device, first and second slave devices. Each slave device includes a peripheral interface controller (PIC), a counter, and a pulse generator. When the first slave device is connected to the master device, the pulse generator generates a first pulse signal to the master device and the corresponding counter. The counter sends an address signal to the corresponding PIC as an identification address of the PIC. When the second slave device is subsequently connected to the master device, the pulse generator generates a second pulse signal to the master device, and the counters of the first and second slave devices. The counter sends an address signal to the corresponding PIC as an identification address of the PIC. The counter of the first slave device changes the identification address of the first slave device. | 2009-09-24 |
20090240860 | Lock Mechanism to Enable Atomic Updates to Shared Memory - A system and method for locking and unlocking access to a shared memory for atomic operations provides immediate feedback indicating whether or not the lock was successful. Read data is returned to the requestor with the lock status. The lock status may be changed concurrently when locking during a read or unlocking during a write. Therefore, it is not necessary to check the lock status as a separate transaction prior to or during a read-modify-write operation. Additionally, a lock or unlock may be explicitly specified for each atomic memory operation. Therefore, lock operations are not performed for operations that do not modify the contents of a memory location. | 2009-09-24 |
20090240861 | Method and system for controlling an operation time of a computer - A method and system for controlling computer operation time is provided for counting how long the time for using the computer lasts. The steps of the time counting method are as following. First step is counting an operation time period for using the computer at the computer powered on; second step is determining the operation time period equal to a predetermined operating-time limit; third step is controlling the computer into an interrupted operating state when the operation time period is equal to the predetermined operating-time limit, wherein an interrupted time period for the computer stayed in the interrupted operating state is counted; fourth step is determining the interrupted time period equal to a predetermined suspension time; and fifth step is controlling the computer back to a normal operating state when the interrupted time period is equal to the predetermined suspension time, wherein the operation time period is re-counted. | 2009-09-24 |
20090240862 | System Design for a Digital Electronic Sign Board - A system design for a digital electronic sign board comprises a main circuit module, an adapter module and a computer module; wherein the adapter module is fixed between the main circuit module and the computer module. The main circuit module and the adapter module are fixed in the digital electronic sign board. The computer module is externally inserted into the digital electronic sign board. Therefore the computer module and the main circuit module are electrically connected through the adapter module. The system design of the present invention removable and attached the computer module with the main circuit module. As a result, when a maintenance worker needs to perform maintenance on the computer module, he or she can conveniently pull out the computer module from the digital electronic sign board and insert the computer module back to the digital electronic sign board after maintenance is done so as to improve the efficiency and quality of maintenance. | 2009-09-24 |
20090240863 | DISTRIBUTED POWER REGULATION - Distributed power regulation in a handheld device is provided. A system for power regulation in a handheld electronic device having a battery, includes: an expansion interface for receiving a battery power from the battery; and a peripheral interface system releasably coupled to the expansion interface and communicating with a peripheral device for generating one or more predetermined operation powers for the peripheral device, based on the battery power provided through the expansion interface. | 2009-09-24 |
20090240864 | INTERFACE ADAPTER FOR A PORTABLE MEDIA PLAYER DEVICE - A “smart cable” that connects one or more peripheral devices to a digital media player having multiple, different types of input and/or output connections. | 2009-09-24 |
20090240865 | Dual-Mode Switch for Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program. | 2009-09-24 |
20090240866 | Multi-port memory and computer system provided with the same - A multi-port memory, comprising: m (m≧2) input/output ports independent of one another; n (n≧2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data between the m input/output ports and the n memory banks, wherein the route switching circuit allocates p (1≦p≦m) input/output ports optionally selected from the m input/output ports to a memory bank optionally selected from the n memory banks. | 2009-09-24 |
20090240867 | Data processing system and storage area allocation method thereof - When creating a storage pool with external volumes, it is not possible to put together the volumes that have the same level of reliability if consideration is only given to the physical attributes of such volumes. Further, the reliability demanded between a host computer and a storage apparatus does not necessarily match the reliability between storage apparatuses. When creating a storage pool in the data processing system of this invention, not only is consideration given to the characteristics of the physical disks themselves, consideration is also given to the connection status of the backend network between a storage apparatus and a switch loaded with external storage function, and an external storage apparatus. What is more, volumes are allocated to a host machine after said system considers both the redundancy of a backend network of between storage apparatuses and that of a network path between the host machine and storage apparatus. | 2009-09-24 |
20090240868 | MANAGEMENT METHOD, MANAGEMENT APPARATUS, AND CONTROLLER FOR MEMORY DATA ACCESS - A management method, a management apparatus, and a controller for memory data access are provided. The management apparatus is disposed between a host and a device for managing the data transmitted between the host and the device, wherein the management apparatus includes a control unit and a storage unit. When the control unit receives a data writing command from the host, it searches for a set mapped to the data in the storage unit and updates the data in the set. Then, the control unit collects the other parts of the data in the storage unit and the device, integrates all parts of the data, and writes the integrated data into the device. Accordingly, the efficiency in data transmission can be improved, and the number of data writing operations can be reduced so that the lifespan of the device can be prolonged. | 2009-09-24 |
20090240869 | Sharing Data Fabric for Coherent-Distributed Caching of Multi-Node Shared-Distributed Flash Memory - A Sharing Data Fabric (SDF) causes flash memory attached to multiple compute nodes to appear to be a single large memory space that is global yet shared by many applications running on the many compute nodes. Flash objects stored in flash memory of a home node are copied to an object cache in DRAM at an action node by SDF threads executing on the nodes. The home node has a flash object map locating flash objects in the home node's flash memory, and a global cache directory that locates copies of the object in other sharing nodes. Application programs use an applications-programming interface (API) into the SDF to transparently get and put objects without regard to the object's location on any of the many compute nodes. SDF threads and tables control coherency of objects in flash and DRAM. | 2009-09-24 |
20090240870 | STORAGE APPARATUS WITH A PLURALITY OF NONVOLATILE MEMORY DEVICES - According to one embodiment, a counter counts bits having a predetermined logical value contained in accessed data to be written or read in an access process of accessing any of the physical blocks provided in a selected one of the nonvolatile memory devices. A timer measures an access busy period in the access process. A control module updates an access busy period data item stored in a busy period storage module and concerning the selected one, in accordance with a count value of the counter, whereby the access busy period data item represents the access busy period measured. | 2009-09-24 |
20090240871 | MEMORY SYSTEM - A system includes: a first input buffer that functions as an input buffer for a third storing area; and a second input buffer that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area. In the system, a plurality of data written in a first storing area or a second storing area are flushed to the first input buffer in units of logical blocks. Also, a plurality of data written in the first input buffer are relocated to the third storing area in units of logical blocks. | 2009-09-24 |
20090240872 | MEMORY DEVICE WITH MULTIPLE-ACCURACY READ COMMANDS - A method for data storage includes defining at least first and second read commands for reading storage values from analog memory cells. The first read command reads the storage values at a first accuracy, and the second read command reads the storage values at a second accuracy, which is finer than the first accuracy. A condition is evaluated with respect to a read operation that is to be performed over a given group of the memory cells. One of the first and second read commands is selected responsively to the evaluated condition. The storage values are read from the given group of the memory cells using the selected read command. | 2009-09-24 |
20090240873 | Multi-Level Striping and Truncation Channel-Equalization for Flash-Memory System - Truncation reduces the available striped data capacity of all flash channels to the capacity of the smallest flash channel. A solid-state disk (SSD) has a smart storage switch salvages flash storage removed from the striped data capacity by truncation. Extra storage beyond the striped data capacity is accessed as scattered data that is not striped. The size of the striped data capacity is reduced over time as more bad blocks appear. A first-level striping map stores striped and scattered capacities of all flash channels and maps scattered and striped data. Each flash channel has a Non-Volatile Memory Device (NVMD) with a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory in the NVMD. Wear-leveling and bad block remapping are preformed by each NVMD. Source and shadow flash blocks are recycled by the NVMD. Two levels of smart storage switches enable three-level controllers. | 2009-09-24 |
20090240874 | FRAMEWORK FOR USER-LEVEL PACKET PROCESSING - A method of processing network packets can include allocating a first portion of a physical memory device to kernel-space control and allocating a second portion of the physical memory device to direct user-space process control. Network packets can be received from a computer network, and the received network packets can be written to the second portion of the physical memory without writing the received packets to the first portion of the physical memory. The network packets can be processed with a user-space application program that directly accesses the packets that have been written to the second portion of physical memory, and the processed packets can be sent over the computer network | 2009-09-24 |
20090240875 | CONTENT ADDRESSABLE MEMORY WITH HIDDEN TABLE UPDATE, DESIGN STRUCTURE AND METHOD - Disclosed are embodiments of memory circuit having two discrete memory devices with two discrete memory arrays that store essentially identical data banks. The first device is a conventional memory adapted to perform all maintenance operations that require read functions (i.e., all update and refresh operations). The second device is a DRAM-based CAM device adapted to perform parallel search and overwrite operations only. Performance of overwrite operations by the second device occurs in conjunction with performance of maintenance operations by the first device so that corresponding memory cells in the two devices store essentially identical data values. Since the data banks in the memory devices are essentially identical and since maintenance and parallel search operations are not performed by the same device, the parallel search operations can be performed without interruption. Also disclosed are embodiments of an associated design structure and method. | 2009-09-24 |
20090240876 | Information processing apparatus, information processing method and storage system - Provided is an information processing apparatus including a local memory for storing a control program, a flash memory for storing a boot program, a processor for controlling the overall controller, a chipset for relaying the transfer of data among the respective components, and a logical control circuit arranged between the chipset and the flash memory. The logical control circuit performs information conversion processing to accommodate the logical configuration of the chipset and the flash memory when sending and receiving information between the chipset and the flash memory. This information conversion processing includes the steps of translating a serial address signal output from the chipset into a parallel address signal, translating a serial data signal output from the chipset into a parallel data signal, and translating a parallel data signal output from the flash memory into a serial data signal. | 2009-09-24 |
20090240877 | VIRTUAL TAPE DEVICE AND METHOD FOR CONTROLLING THE SAME - A virtual tape device in between a host and a library device is provided. The virtual tape device includes a physical tape volume and that stores data sent from the host on a logical tape volume includes, a receiver that receives a mount/unmount command and a job identifier relating to the command which are sent from the host, a storage device that stores the logical tape volume, a storage table that stores the job identifier and a logical tape volume to be accessed by a job indicated by the job identifier, and a controller that controls, based on the storage table, transfer of data relating to the job identifier between the logical tape volume and the physical tape volume. | 2009-09-24 |
20090240878 | DISK APPARATUS AND ADVANCE DATA READING METHOD - Upon receipt of a read command or a write command from an external device, a disk apparatus stores an obtained address as a primary address and a secondary address in an address storing unit, increments a counter value of the secondary address, and selects the secondary address of which the counter value indicates the largest number. Upon receipt of the read command for the primary address, the disk apparatus reads data specified by the primary address from a disk and stores it in a buffer memory in advance. Upon receipt of the read command, the disk apparatus sends the data from the buffer to the external device. | 2009-09-24 |
20090240879 | Disk array system - A technique to distribute processing to meet a request from other system without partializing the processing to specific processor and can execute processing efficiently while adopting configuration to control one port unit by multiple processors at channel adapter of disk array system. CHA of a controller has a port unit carrying out interface operation and multiple host processor units having host processors. Multiple processors operate in parallel and control the port unit. When the port unit receives a request from other system, the first processor takes charge of the processing on the basis of the judgment of the processing load condition in processors including itself and in the event that the second processor is assigned the processing, the first processor communicates with the protocol unit and transfers the request to the second processor unit to enable the second processor to take charge of the processing. | 2009-09-24 |
20090240880 | HIGH AVAILABILITY AND LOW CAPACITY THIN PROVISIONING - A data storage system and method for simultaneously providing thin provisioning and high availability. The system includes external storage volume and two storage subsystems coupled together and to external storage volume. Each of storage subsystems includes disk drives and a cache area, each of the storage subsystems includes at least one virtual volume and at least one capacity pool. The virtual volume is allocated from storage elements of the at least one capacity pool. The capacity pool includes the disk drives and at least a portion of external storage volume. The storage elements of the capacity pool are allocated to the virtual volume in response to a data access request. The system further includes a host computer coupled to the storage subsystems and configured to switch input/output path between the storage subsystems. Each of the storage subsystems is adapted to copy received write I/O request to other storage subsystems. Upon receipt of request from another storage subsystem, storage element of the capacity pool of storage subsystem is prevented from being allocated to the virtual volume of that storage subsystem. | 2009-09-24 |
20090240881 | System and Method for Information Handling System Operation With Different Types of Permanent Storage Devices - A storage controller, such as a RAID controller arbitrates storage tasks between a hard disk drive and a solid state drive based on predetermined factors, such as the type of information associated with a read or a write or the power available for running the storage devices. For example, a RAID controller on a portable information handling system performs writes and reads for sequential information with a hard disk drive. If power is limited, such as from a battery, the storage controller powers down the hard disk drive and performs storage tasks with the solid state drive with periodic power ups of the hard disk drive to mirror stored information. | 2009-09-24 |
20090240882 | Method of extension of storage capacity and storage system using the method - Provided are a storage system and a method of controlling a storage system in which respective real storage areas of a plurality of disk drives contained in the storage system contain management units, and a control device of the storage system assigns a real storage area of a plurality of first disk drives to the virtual storage area, distributedly stores the data in the plurality of management units of the assigned real storage area, distributedly stores, upon receiving a request for adding a second disk drive, the data stored in the plurality of management units of the plurality of first disk drives in the plurality of management units of the plurality of first disk drives and the second disk drive, and assigns the real storage area of the plurality of first disk drives and the second disk drive to an unused virtual storage area. | 2009-09-24 |
20090240883 | STORAGE APPARATUS AND CONFIGURATION SETTING METHOD - This storage apparatus has a plurality of physical devices for storing data sent from a host system, and includes a physical device group setting unit for setting a physical device group from the plurality of physical devices based on a policy file which lists matters to be operated and set by an administrator as parameters in advance, and information on the physical devices, a first logical device setting unit for setting a first logical device from the physical device group based on information on the physical device group and the policy file set with the physical device group setting unit, and a second logical device setting unit for setting a second logical device from the first logical device based the information on the first logical device and the policy file set with the first logical device setting unit. | 2009-09-24 |
20090240884 | PLAYBACK APPARATUS FOR MULTIPLE MEMORY CARDS OF THE SAME TYPE - A playback apparatus for multiple memory cards of the same type. The apparatus comprises of a plurality of memory card slots of the same type, a memory card selecting unit, a microprocessor unit and a multimedia processor. The microprocessor unit electronically connects to the memory card selecting unit, receiving a memory card detecting signal from the memory card selecting unit and sending a memory card selecting signal to the memory card selecting unit. The multimedia processor electronically connects to the processor unit and the memory card selecting unit, reading the data from one memory card through the memory card selecting unit under the control of the microprocessor unit. Hence the playback apparatus selects one of the multiple memory cards of the same type, playing audio/video signals stored in the memory card. User therefore can select multiple memory cards of the same type for playing. | 2009-09-24 |
20090240885 | MEMORY CARD COMPLYING WITH A PLURALITY OF STANDARDS - A memory card includes a control device, a nonvolatile memory, and a program-storage memory, wherein the program-storage memory is arranged to store a plurality of control programs corresponding to respective standards for controlling data access between the nonvolatile memory and an external device. | 2009-09-24 |
20090240886 | PLUGIN INFRASTRUCTURE FOR HIERARCHICAL TEMPORAL MEMORY (HTM) SYSTEM - A system for implementing a hierarchical temporal memory (HTM) network using a plugin infrastructure. The plugin infrastructure registers the plugins to be used in instantiating the HTM network. The plugin may include one or more functions for creating one or more components of the HTM network in a runtime engine. The plugin is associated with a component specification describing the components of the HTM network created by invoking the functions of the plugin. After the plugin is registered, the plugin infrastructure allows functions of the plugin to be invoked to instantiate The HTM network on a runtime engine. After the HTM network is instantiated, the runtime engine may run the instance of the HTM network to learn and infer the causes of input data. The system may also include one or more external programs to provide various supporting operations associated with the runtime engine by referencing the component specification. The supporting operations that can be performed by the external programs include, among others, validating a netlist defining the structure of the HTM network, build help information for the component, and generating a graphical user interface associated with the HTM network. | 2009-09-24 |
20090240887 | INFORMATION PROCESSING UNIT, PROGRAM, AND INSTRUCTION SEQUENCE GENERATION METHOD - An information processing unit includes at least one cache memory provided between an instruction execution section and a storage section and a control section controlling content of address information based on a result of comparison processing between an address requested by a hardware prefetch request issuing section for memory access and address information held in an address information holding section, wherein when the control section causes the address information holding section to hold address information or address information in the address information holding section is updated, overwrite processing on the address information is inhibited for a predetermined time. | 2009-09-24 |
20090240888 | SYSTEM AND METHOD FOR OBSCURING HAND-HELD DEVICE DATA TRAFFIC INFORMATION - Increasing security for a hand-held data processing device with communication functionality where such a device includes an access-ordered memory cache relating to communications carried out by the device. The hand-held data processing device has a locked state that is entered by the device receiving or initiating a trigger. On occurrence of the trigger to enter the locked state the memory cache is reordered so as to disrupt the access-ordering of the cache to obscure device traffic information and thus increase the security of the device in the locked state. | 2009-09-24 |
20090240889 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR CROSS-INVALIDATION HANDLING IN A MULTI-LEVEL PRIVATE CACHE - A method, system, and computer program product for cross-invalidation handling in a multi-level private cache are provided. The system includes a processor. The processor includes a fetch address register logic in communication with a level 1 data cache, a level 1 instruction cache, a level 2 cache, and a higher level cache. The processor also includes a set of cross-invalidate snapshot counter implemented in the fetch address register. Each cross-invalidate snapshot counter tracks an amount of pending higher level cross-invalidations received before new data for the corresponding cache miss is returned from the higher-level cache. The processor also includes logic executing on the fetch address register for handling level 1 data cache misses and interfacing with the level 2 cache. In response to the new data, and upon determining that older cross-invalidations are pending, the new data is prevented from being used by the processor. | 2009-09-24 |
20090240890 | PROGRAM THREAD SYNCRONIZATION - A barrier for synchronizing program threads for a plurality of processors includes a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized. The filter is configured to monitor and selectively block fill requests for instruction cache lines. A method for synchronizing program threads for a plurality of processors includes configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized. | 2009-09-24 |
20090240891 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DATA BUFFERS PARTITIONED FROM A CACHE ARRAY - Systems, methods and computer program products for data buffers partitioned from a cache array. An exemplary embodiment includes a method in a processor and for providing data buffers partitioned from a cache array, the method including clearing cache directories associated with the processor to an initial state, obtaining a selected directory state from a control register preloaded by the service processor, in response to the control register including the desired cache state, sending load commands with an address and data, loading cache lines and cache line directory entries into the cache and storing the specified data in the corresponding cache line. | 2009-09-24 |
20090240892 | SELECTIVE INTERCONNECT TRANSACTION CONTROL FOR CACHE COHERENCY MAINTENANCE - A data processing system ( | 2009-09-24 |
20090240893 | Information processing device, memory control method, and memory control device - The present invention provides an information processing device, a memory control method, and a memory control device. In the information processing device that includes nodes each having a main memory and a processor including a cache memory, the system controller of at least one of the nodes is designed to include a holding unit that holds specific information about primary data present in the main memory of its subject node, with the cache data corresponding to the primary data not present in the cache memory of the nodes other than its subject node. With this structure, the latency of each memory access is shortened, and the throughput of each snoop operation is improved. | 2009-09-24 |
20090240894 | METHOD AND APARATUS FOR THE SYNCHRONIZATION OF DISTRIBUTED CACHES - A method and apparatus for the synchronization of distributed caches. More particularly, the present invention to cache memory systems and more particularly to a hierarchical caching protocol suitable for use with distributed caches, including use within a caching input/output (I/O) hub. | 2009-09-24 |
20090240895 | SYSTEMS AND METHODS FOR COALESCING MEMORY ACCESSES OF PARALLEL THREADS - One embodiment of the present invention sets forth a technique for efficiently and flexibly performing coalesced memory accesses for a thread group. For each read application request that services a thread group, the core interface generates one pending request table (PRT) entry and one or more memory access requests. The core interface determines the number of memory access requests and the size of each memory access request based on the spread of the memory access addresses in the application request. Each memory access request specifies the particular threads that the memory access request services. The PRT entry tracks the number of pending memory access requests. As the memory interface completes each memory access request, the core interface uses information in the memory access request and the corresponding PRT entry to route the returned data. When all the memory access requests associated with a particular PRT entry are complete, the core interface satisfies the corresponding application request and frees the PRT entry. | 2009-09-24 |
20090240896 | MICROPROCESSOR COUPLED TO MULTI-PORT MEMORY - A microprocessor being coupled to a dual-port memory is disclosed. The microprocessor has two or more external memory controllers, being coupled to a system bus. Each of the external memory controllers can be individually coupled to an external memory through its respective port. With the present invention, a plurality of elements (e.g. process module) can access the external memory at the same time, enabling a quick process of data. | 2009-09-24 |
20090240897 | Multi-port memory and system using the same - A multi-port memory, comprising: a memory array made of a plurality of memory cells arranged at intersection points between a plurality of bit lines and a plurality of word lines, the memory array being divided into n (an integer of 2 or greater) memory banks; m (an integer of 2 or greater) input/output ports, each independently performing input and output of a command, an address, data to and from each of the memory banks; and a route switching circuit that sets signal for the command, address, and data between the memory banks and the input/output ports, the route switching circuit controlling a connection state of signal lines between the plurality of input/output ports and the plurality of memory banks. | 2009-09-24 |
20090240898 | Storage System and Method of Taking Over Logical Unit in Storage System - A storage apparatus includes a drive unit in which a logical unit is formed, and a controller unit for accessing the logical unit by controlling the drive unit according to an access request sent from a host apparatus. The storage apparatus issues a logical unit takeover request to the other storage apparatuses, allocates a logical unit of another storage apparatus that will accept the transfer of the logical volume to its own logical unit according to a takeover approval sent from other storage apparatuses in response to the takeover request, and thereafter migrates data of the own logical unit to a logical unit of another storage apparatus. Subsequently, the path is switched so that the access request from the host apparatus is given to one of the other storage apparatuses. | 2009-09-24 |
20090240899 | Storage device and method of controlling same - A storage device having a volume for storing data sent from a host computer and transferring the data stored in the volume to a sub storage device via a network, comprises: a retrieval unit for retrieving a snapshot retaining change data generated in the volume during a time period between a given time and another given time, and a maximum transfer size of the network between the storage device and the sub storage device; and a control unit for controlling so as to store data exceeding a maximum transfer size in the area of another snapshot, when the size of a created snapshot exceeds the maximum transfer size. | 2009-09-24 |
20090240900 | MEMORY APPARATUS AND MEMORY CONTROL METHOD - A memory includes a plurality of blocks that each include a plurality of memory cell arrays connected to divided bit lines, a first decoder that generates a block select signal for selecting any of the blocks based on an inputted address signal, read/write portions disposed for the respective blocks, each of the read/write portions executes read or write of the memory cell array belonging to the block of its own, and signal generation portions each generates an operation control signal for bringing the read/write portion that belongs to the selected block into an operating state when the block thereof has been selected by the block select signal. Each of the signal generation portions generates an operation control signal for bringing the read/write portion that belongs to the block thereof into a non-operating state when the block thereof is not selected by the block select signal. | 2009-09-24 |
20090240901 | INFORMATION PROCESSING APPARATUS, STORAGE CONTROL DEVICE AND CONTROL METHOD - A computer, which includes multiple memory modules each of which is provided with an SPD for storing setting information about the memory, a setting information acquisition section of an SPD controller of a memory controller, obtains setting information from the SPD of each memory module, and the setting information is held in a setting information holding section. The storage control device of the computer compares the acquired pieces of setting information. When the contents of the pieces of setting information are different from one another, the storage control device overwrites setting information in the SPD's of the memory modules other than the memory module corresponding to the setting information by using the contents of any one of the pieces of setting information. | 2009-09-24 |
20090240902 | Computer system and command execution frequency control method - A computer system of the present invention can adjust the execution frequencies of a command issued from a host and a command issued from a storage. An external manager disposed in the host configures a priority for a host command issued from a command issuing module inside the host. An internal manager disposed in the storage configures a priority for an internal command issued from a command issuing module inside the storage. The internal manager adjusts the execution frequency of the host command and the execution frequency of the internal command based on the host command priority and the internal command priority. | 2009-09-24 |
20090240903 | Methods and Apparatus for Translating a System Address - A method for translating a system address includes providing a first system address to a firmware and retrieving a first translation data corresponding to a memory configuration from storage. The first system address is translated into a first physical location utilizing the first translation data, and the first physical location is outputted. | 2009-09-24 |
20090240904 | LOOSE SYNCHRONIZATION OF VIRTUAL DISKS - Computer implemented methods, computer program products and computer systems synchronize copies of a virtual disk. A record of blocks that are modified during an access session of a copy of the virtual disk is maintained. For each partition of the virtual disk, a file system level indication of currently relevant blocks is obtained. Only those blocks that were modified during the access session and are currently relevant are copied to at least one additional copy of the virtual disk. | 2009-09-24 |
20090240905 | Real-time backup method for single storage medium - The present invention provides a real-time backup method for single storage medium which partitions a single storage medium into multiple logic units, and then the logic unit is designated as a backup logic unit or a normal storage logic unit, and the backup logic unit is partitioned into two or more unit blocks. Data with backup demand are simultaneously written into two individual stripe blocks belonging in the two selected unit blocks respectively in the backup logic unit for real-time backup function. Therefore the storage medium is used efficiently and the real-time backup function is achieved. | 2009-09-24 |
20090240906 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND RECORDING MEDIUM THAT RECORDS HISTORY INFORMATION CONTROL PROGRAM - A method and an apparatus include storing history information into a first storage section that accumulates history information concerning a process performed, transmitting a received acquisition request of the history information accumulated into the first storage section, transmitting the accumulated history information to the history information accumulation section having transmitted the acquisition request, transmitting the history information to the another history information accumulation section, transmitting the acquisition request to the first history information accumulation section at a time of startup, and storing the transmitted history information into a second storage section. | 2009-09-24 |
20090240907 | REMOTE STORAGE ACCESS CONTROL SYSTEM - An authorization method includes recognizing a request to access a data storage unit from a user, providing user identification and identifying information of the data storage unit, receiving a response from the authorization module, and passing the request to the data storage unit if the user is authorized to access the data storage unit. An access control system includes the authorization module configured to receive the request to access the data storage unit from the client device and determine whether the user is authorized to access the data storage unit. | 2009-09-24 |
20090240908 | FILTERING PROCESSOR REQUESTS BASED ON IDENTIFIERS - Processing within a computing environment is facilitated by filtering requests of the computing environment. A processing unit that receives a request determines whether it is to perform the request. This determination is made by, for instance, comparing an identifier of the request with an identifier of the processing unit making the determination. If there is a mismatch, then the request is blocked. Other processing within the computing environment is also facilitated by selectively using buffer entries. The selection criteria is based, for instance, on identifier information. | 2009-09-24 |
20090240909 | System and Method for Auditing Memory - According to one embodiment of the invention, a method of auditing memory in a system comprises receiving a request for memory from an application and populating a memory tag with a stack depth component and a traceback stack component. The traceback stack component contains a pointer to a traceback stack. The stack depth component defines a size of the traceback stack. The traceback stack contains information from a program stack associated with the application. The embodiment may further comprise determining if a memory pool has enough free memory to satisfy the request and allocating, from the memory pool, a memory allocation unit if the memory pool has enough free memory to satisfy the request. The memory allocation unit may include a data area and a footer. The data area defines an area to which the application may write data and the footer bounds the data area with a special code. | 2009-09-24 |
20090240910 | Storage system, volume allocation method and management apparatus - This storage system includes a virtual storage selection unit for selecting a virtual storage unit to be allocated to a virtual server unit according to a virtual storage search policy table for searching the virtual storage unit based on a parameter input by a user when a command is issued for allocating the volume to the virtual server unit, a volume selection unit for selecting the type of volume to be allocated to the virtual storage unit allocated to the virtual server unit with the virtual storage allocation unit according to a volume type search policy table for searching the type of volume based on the parameter, and a volume allocation unit for creating the volume selected with the volume selection unit based on the parameter and allocating the created volume to the virtual storage unit allocated to the virtual server unit with the virtual storage allocation unit. | 2009-09-24 |
20090240911 | Information processing apparatus and informaiton processing method - An information processing apparatus and an information processing method capable of assigning, to an application, a volume having a performance required by the application while simplifying administration are proposed. A performance and a capacity of each first storage area respectively provided by each storage device as well as a performance and a capacity required for a volume respectively assigned to each application running on a host system are managed, and based on the performance and the capacity of each first storage area and the performance and the capacity required for the volume to be respectively assigned to each application, the volume having the performance and the capacity required by the application is assigned to the application, and when a plurality of the volumes are assigned to one of the applications, the volumes provided in the same storage device are preferentially assigned. | 2009-09-24 |
20090240912 | SYSTEM AND METHOD FOR SELECTIVELY STORING AND UPDATING PRIMARY STORAGE - A method and system is disclosed for selectively storing and updating data in primary storage. The primary storage may initially be evenly partitioned into a predetermined number of partitions. As a user selects a program, the partitions dedicated to programs not selected are reduced in size. As subsequent selections are made by the user, the partitions of the primary storage are adjusted to accurately represent the next set of possible selections available to a user. A second selective storing technique involves storing a list of assets for display in one of the partitions. This list is a predetermined portion of an entire list of assets available for selection by the user. User input, such as scrolling through the assets, allows a user to sort through the partial list. Once the user input is completed, the asset list may be repopulated with predetermined assets corresponding to the portion of the list selected by the user. | 2009-09-24 |
20090240913 | UNIVERSAL-HASH-FUNCTION-FAMILY CALCULATION UNIT AND SHARED-KEY GENERATION SYSTEM - An input data enlarging unit ( | 2009-09-24 |
20090240914 | RECYCLING LONG MULTI-OPERAND INSTRUCTIONS - A pipelined microprocessor configured for long operand instructions is disclosed. The microprocessor includes a memory unit and a load-store unit. The load store unit is coupled to the memory unit and includes a data formatter receiving information from the memory unit and including an operand selector and a shift register portion. The microprocessor also includes an execution unit coupled to the load-store unit and receiving operand information there from. The execution unit includes output latches coupled to a storage location within the execution unit for storing output information from the execution unit. | 2009-09-24 |
20090240915 | Broadcasting Collective Operation Contributions Throughout A Parallel Computer - Methods, systems, and products are disclosed for broadcasting collective operation contributions throughout a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors for use in collective parallel operations on the parallel computer. Broadcasting collective operation contributions throughout a parallel computer according to embodiments of the present invention includes: transmitting, by each processor on each compute node, that processor's collective operation contribution to the other processors on that compute node using intra-node communications; and transmitting on a designated network link, by each processor on each compute node according to a serial processor transmission sequence, that processor's collective operation contribution to the other processors on the other compute nodes using inter-node communications. | 2009-09-24 |
20090240916 | Fault Resilient/Fault Tolerant Computing - A fault tolerant/fault resilient computer system includes a first coserver and a second coserver. The first coserver includes a first application environment (AE) processor and a first I/O subsystem processor on a first common motherboard. The second coserver includes a second AE processor and a second I/O subsystem processor on a second common motherboard. | 2009-09-24 |
20090240917 | Method and apparatus for matrix decomposition in programmable logic devices - A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values. | 2009-09-24 |
20090240918 | METHOD, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR ELIMINATING OR REDUCING OPERAND LINE CROSSING PENALTY - Eliminating or reducing an operand line crossing penalty by performing an initial fetch for an operand from a data cache of a processor. The initial fetch is performed by allowing or permitting the initial fetch to occur unaligned with reference to a quadword boundary. A plurality of subsequent fetches for a corresponding plurality of operands from the data cache are performed wherein each of the plurality of subsequent fetches is aligned to any of a plurality of quadword boundaries to prevent each of a plurality of individual fetch requests from spanning a plurality of lines in the data cache. A steady stream of data is maintained by placing an operand buffer at an output of the data cache to store and merge data from the initial fetch and the plurality of subsequent fetches, and to return the stored and merged data to the processor. | 2009-09-24 |
20090240919 | PROCESSOR AND METHOD FOR SYNCHRONOUS LOAD MULTIPLE FETCHING SEQUENCE AND PIPELINE STAGE RESULT TRACKING TO FACILITATE EARLY ADDRESS GENERATION INTERLOCK BYPASS - A pipelined processor including an architecture for address generation interlocking, the processor including: an instruction grouping unit to detect a read-after-write dependency and to resolve instruction interdependency; an instruction dispatch unit (IDU) including address generation interlock (AGI) and operand fetching logic for dispatching an instruction to at least one of a load store unit and an execution unit; wherein the load store unit is configured with access to a data cache and to return fetched data to the execution unit; wherein the execution unit is configured to write data into a general purpose register bank; and wherein the architecture provides support for bypassing of results of a load multiple instruction for address generation while such instruction is executing in the execution unit before the general purpose register bank is written. A method and a computer system are also provided. | 2009-09-24 |
20090240920 | Execution Unit with Data Dependent Conditional Write Instructions - An execution unit supports data dependent conditional write instructions that write data to a target only when a particular condition is met. In one implementation, a data dependent conditional write instruction identifies a condition as well as data to be tested against that condition. The data is tested against that condition, and the result of the test is used to selectively enable or disable a write to a target associated with the data dependent conditional write instruction. Then, a write is attempted while the write to the target is enabled or disabled such that the write will update the contents of the target only when the write is selectively enabled as a result of the test. By doing so, dependencies are typically avoided, as is use of an architected condition register that might otherwise introduce branch prediction mispredict penalties, enabling improved performance with z-buffer test and similar types of algorithms. | 2009-09-24 |
20090240921 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR SUPPORTING PARTIAL RECYCLE IN A PIPELINED MICROPROCESSOR - A computer processing system is provided. The computer processing system includes a first datastore that stores a subset of information associated with an instruction. A first stage of a processor pipeline writes the subset of information to the first datastore based on an execution of an operation associated with the instruction. A second stage of the pipeline initiates reprocessing of the operation associated with the instruction based on the subset of information stored in the first datastore. | 2009-09-24 |
20090240922 | METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR - Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction. | 2009-09-24 |
20090240923 | Computing Device with Entry Authentication into Trusted Execution Environment and Method Therefor - A computing device ( | 2009-09-24 |
20090240924 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND COMPUTER PRODUCT - An information processing device disclosed includes a plurality of executing units for executing various processes. The information processing device and method thereof acquire setting information that indicates an operating condition with respect to each executing unit from information an operation of a main process executed by the plurality of executing units, and sets an operating state of each of the executing units based on the acquired setting information. | 2009-09-24 |
20090240925 | DEVICE, METHOD, AND COMPUTER PROGRAM PRODUCT THAT PROCESS MESSAGE - A first arithmetic unit performs a network process for transmission and reception of a message. A second arithmetic unit performs a network process and a specific process that is predetermined to be performed on the message in relation with the network process. An alternate process management table stores therein process information in which associated identification information with an instruction sequence, the identification information being information for identifying a type of the message, the instruction sequence being a sequence for sequentially performing a network process and a specific process. The first arithmetic unit includes an identification information detector that detects the identification information from the message, and a controller that retrieves, from the alternate process management table, an instruction sequence corresponding to the identification information detected, so as to control the second arithmetic unit to perform the instruction sequence retrieved. | 2009-09-24 |