39th week of 2009 patent applcation highlights part 26 |
Patent application number | Title | Published |
20090237923 | LED LAMP ASSEMBLY - An LED lamp assembly includes a pair of LED lamps facing opposite directions. Each LED lamp includes a heat sink having a heat absorbing portion and a heat dissipating portion. The heat absorbing portion has opposite first and second surfaces. The heat dissipating portion extends rearwards from the first surface of the heat absorbing portion. An outmost end of the heat dissipating portion defines a plurality of apertures and is located beyond an outmost end of the heat absorbing portion. The heat dissipating portions of the heat sinks are oriented towards each other and define a channel therebetween. The LED modules are mounted at the second surfaces the heat absorbing portions. Heat generated by the LED modules is absorbed by the heat absorbing portions and then transferred to the apertures and the channel via the heat dissipating portions, from where the heat is dissipated to surrounding air. | 2009-09-24 |
20090237924 | BEAM ADJUSTMENT MECHANISM FOR AN LED LIGHT FIXTURE - A beam adjustment mechanism for a light fixture includes a frame assembly having an aperture substantially within the center thereof. Multiple peripheral lighting units engage the sides of the frame assembly. Each lighting unit includes an LED, a heat sink, and a reflector member. A central connecting member and/or a central lighting unit is at least partially surrounded by the peripheral lighting units. The central connecting member and/or central lighting unit is hingedly connected to at least one of the peripheral lighting units. An adjustment shaft extends through and is moveably engaged with the aperture of the frame assembly. Movement of the adjustment shaft relative to the aperture exerts a force on the central connecting member and/or central lighting unit, which causes the hingedly connected peripheral lighting units to pivot relative to the central connecting member and/or central lighting unit. | 2009-09-24 |
20090237925 | White-light light-emitting diode (LED) road lamp composed of red, green and blue leds - The invention provides a white-light LED road lamp composed of red, green, and blue LED's. The road lamp includes a road lamp body, a heat-dissipating element, a constant-current source, and an LED board. The road lamp body is suspended at a specific height above the ground. Inside the road lamp body is disposed with the LED board connected with the heat-dissipating element. The side surface of the LED board opposite to the heat-dissipating element is electrically connected with a plurality of red, green, and blue LED's. The LED's are connected in series or parallel and driven by the constant-current source. | 2009-09-24 |
20090237926 | Illiminating device - The illuminating device of the invention comprises at least one lighting component, red lighting component, current limiting component and fluorescent body, wherein said red lighting component is first series connected with said current limiting component, and further parallel connected with said lighting component, so that input current to red lighting component is controlled by said current limiting component to be smaller than input current to lighting component, thereby said fluorescent body receiving and triggering the light emitted by said lighting component is mixed with the light emitted by said red lighting device to emit a white light with high lighting efficient and high color rendering white light. | 2009-09-24 |
20090237927 | LED LAMP ASSEMBLY - An LED lamp assembly includes a central member and a plurality of lamps each having an LED module and a heat sink in thermal connection with the LED module. The central member has a plurality of inserting extrusions formed at a circumference thereof. The lamps each have a receiving tube projecting from an end thereof. The inserting extrusions are respectively inserted into the receiving tubes of the lamps to assemble the lamps onto the circumference of the central member. The lamps are tilted from the central portion along a radially outward direction. | 2009-09-24 |
20090237928 | LED TRAFFIC SIGNAL WITH SUN PHANTOM REDUCTION - An LED signal that mitigates the “sun phantom” effect includes a lens having an optical segment configured to direct at least some of the incoming generally collimated light rays from the sun passing through the lens away from an LED found in the traffic signal. | 2009-09-24 |
20090237929 | STREET ILLUMINATING DEVICE - A street illuminating device includes a retaining frame, a light source module, and a heat dissipating module. The light source module includes a printed circuit board retained in the retaining frame, a number of solid state lighting elements, and a light reflecting plate. The printed circuit board has a first surface and an opposite second surface. The solid state lighting elements are arranged on the first surface of the printed circuit board. The light reflecting plate includes a number of through holes with inner reflecting surfaces. The light reflecting plate is disposed on the first surface of the printed circuit board with the solid state lighting elements received in the respective through holes. The heat dissipating module is in thermal contact with the second surface of the printed circuit board. | 2009-09-24 |
20090237930 | LED STREET LAMP - A combined LED street lamp ( | 2009-09-24 |
20090237931 | LED LAMP ASSEMBLY - An LED lamp assembly includes a receiving member and a pair of LED lamps. The receiving member has a pair of opposite slope surfaces. The LED lamps are mounted on the opposite slope surfaces of the receiving member. Each of the LED lamps includes a heat sink having a bottom defining a plurality of differently-angled planar surfaces. A plurality of LED modules is mounted on the planar surfaces of the heat sink, respectively. | 2009-09-24 |
20090237932 | LED LIGHTING DEVICE HAVING HEAT CONVECTION AND HEAT CONDUCTION EFFECTS AND HEAT DISSIPATING ASSEMBLY THEREFOR - An LED lighting device having heat convection and heat conduction effects has a heat dissipating assembly, a substrate, multiple LEDs and a base. The heat dissipating assembly has a housing and an outer cover. The housing has multiple air holes. The outer cover is mounted on an open top of the housing and has multiple through holes and an exterior flue protruding from the outer cover and extending into the housing. The substrate is mounted inside the housing against the outer cover and has a hole allowing the exterior flue to extend therethrough. The LEDs are mounted on the substrate and respectively correspond to the through holes. The base is attached to a bottom of the housing. The exterior flue encourages heated air to move through the exterior flue and flow out of the housing via the air holes. With such continuous and directional air movement, the LED lighting device obtains good heat-dissipating efficiency. | 2009-09-24 |
20090237933 | LED ILLUMINATION DEVICE AND LIGHT ENGINE THEREOF - An LED illumination device includes an optical section at a front end thereof, an electrical section at a rear end thereof, and a heat dissipation section between the optical section and the electrical section. The optical section includes a plurality of LEDs electrically connecting with the electrical section, and a light output housing around the LEDs. The heat dissipation section includes a plurality of L-shaped heat pipes, a heat sink and a mounting seat. Each of the heat pipes includes an evaporation section and a condensation section substantially perpendicular thereto. The condensation sections of the heat pipes are received in the heat sink. The mounting seat attaches to the evaporation sections of the heat pipes. The LEDs thermally connect with evaporation sections via the mounting seat. | 2009-09-24 |
20090237934 | LED LAMP ASSEMBLY - An LED lamp assembly includes an LED lamp and a supporting member supporting the LED lamp. The LED lamp includes a plurality of LED modules and a heat sink supporting and cooling the LED modules. The supporting member includes a pair of supporting arms supporting the LED lamp and pivotably engaging with the heat sink of the LED lamp. The heat sink is rotatable relative to the supporting arms of the supporting member to vary an illumination angle of the LED lamp assembly. | 2009-09-24 |
20090237935 | LIGHT EMITTING DEVICE HAVING LIGHT EMITTING ELEMENTS - A light-emitting device operating on a high drive voltage and a small drive current. LEDs ( | 2009-09-24 |
20090237936 | LED UNIT WITH INTERLOCKING LEGS - An LED unit includes a plurality of LEDs, each of which includes a base, an LED die mounted on the base, a pair of leads penetrating the base to electrically connect with the LED die, a plurality of legs extending radially from a periphery of the base, a plurality of cutouts defined in the base and an encapsulant enveloping the LED die. The pair of leads of each LED are joined to corresponding leads of adjacent LEDs to realize electrical connections of the LEDs, while the legs of each LED are fitted into corresponding cutouts of the bases of adjacent LEDs to realize mechanical connections of the LEDs. | 2009-09-24 |
20090237937 | LED ILLUMINATING DEVICE AND LIGHT ENGINE THEREOF - An LED illuminating device includes an optical section ( | 2009-09-24 |
20090237938 | LIGHT SOURCE MODULE AND VEHICULAR LAMP - A light source module includes a circuit board on which a circuit pattern is formed; a semiconductor light emitting element; an electrode pad; and a connecting body. The semiconductor light emitting element includes a first surface formed into an oblong shape, and a second surface positioned facing opposite the first surface. The second surface is connected with a second part of the circuit pattern. The electrode pad is provided on the first surface of the semiconductor light emitting element and includes a connecting portion. The connecting body is connected with the connecting portion of the electrode pad and a first part of the circuit pattern. The electrode pad is provided on a portion of the semiconductor light emitting element that includes one end portion of the first surface. The connecting portion of the electrode pad is provided at a position in one of a continuous and spaced manner in the lengthwise direction of the electrode pad. | 2009-09-24 |
20090237939 | INDICATION PLATE - Disclosed herein is an indication plate including: a plate member including a light-transmitting material; and an indication part provided at a surface on one side with respect to the thickness direction of the plate member, wherein the indication part includes a light-shielding part including a light-shielding material and covering the surface on one side, and a convex portion including the light-transmitting material, the convex portion projecting from the surface on one side and being exposed from the light-shielding part; the convex portion has a circumferential surface projecting from the light-shielding part, and an end face connecting tip portions of the circumferential surface to each other, and a metallic foil having a light-transmitting property is attached to the end face. | 2009-09-24 |
20090237940 | ADJUSTABLE LIGHTING DEVICE - An adjustable lighting device having a main body, a light generation device inserted into a receptacle, a movable lens, a base electrically connected to the light generation device, and an adjustor cover rotatably mounted to and covering the outside of the main body so that rotation of the adjustor cover causes the lens to extend/retract within the receptacle so that the extension/retraction of the lens can be controlled by the rotation of the adjustor cover for realizing focus adjustment. | 2009-09-24 |
20090237941 | Illumination Optics - Luminaire optics ( | 2009-09-24 |
20090237942 | Package structure for light emitting diode - A package structure for light emitting diode (LED) comprises a base, an LED die, an optical lens and a lens holder. The base comprises at least one holder cavity formed on its surface and at least one chase formed on its side surface. The lens holder comprises an opening, at least one holder stem and at least one wedge. The optical lens is arranged between the lens holder and the base, and also through the opening. The lens holder is fastened on the base by wedging the wedge with the chase and positioned on the base by embedding the holder stem into the holder cavity to enhance the positioning between the optical lens and the base, such that the optical lens can generate a desired light pattern. Therefore, the required time of a packaging process can be reduced, and the lens holder can be removed simply for replacing the optical lens, so the objective of changing the light pattern quickly can be achieved. | 2009-09-24 |
20090237943 | FLUSH MOUNT READING LIGHT - A lighting system comprising a generally conical shaped optical housing having a focal point and a light source. The light source, for example, an LED, is disposed in the focal point of the optical housing. A lens surrounds at least a portion of the light source and encloses a cavity aligned with the light source. The top output surface of the lens is distal from the focal point of the optical housing. The optical housing is attached to an electrical board connected to the light source and an external housing at least partially encloses the optical housing, the light source and the electrical board. | 2009-09-24 |
20090237944 | LIGHT FIXTURES WITH ADJUSTABLE ILLUMINATION ANGLE - A ceiling light fixture having an adjustable illumination angle, comprising: a fixed mount; a flexible mount; and a soft pipe; wherein the fixed mount is adapted for connecting to a ceiling; the flexible mount is flexibly connected to the fixed mount via the soft pipe; the flexible mount is adapted to receive a light-emitting element; and the soft pipe exhibits plastic deformation behavior and is adapted to bend and stretch axially. The soft pipe is capable of bending and stretching axially and therefore the illumination angle can be freely adjusted. | 2009-09-24 |
20090237945 | Backlight Module with Integrated Base and Method of Manufacturing Thereof - A backlight module, a base used therein, and a manufacturing method thereof are provided. The backlight module includes a base and a slice-shaped circuit. The base has a back plate including a plate portion and a mezzanine portion. The mezzanine portion is parallelly offset from the plate portion, and the initial position of the mezzanine portion becomes an opening on the plate portion. Because the mezzanine portion is parallelly offset from the plate portion, a containing space is formed between an inner side of the mezzanine portion and the plane of the plate portion. A side of the mezzanine portion and a side of the plate portion corresponding to the opening together form a first slit. The slice-shaped circuit is inserted into the containing space through the first slit and stays between the plate portion and the mezzanine portion. | 2009-09-24 |
20090237946 | LIGHT FIXTURE COUPLING SYSTEM - A light fixture coupling system includes a plurality of lamp housings, a plurality of elongated wireways, and a mounting plate. The plurality of elongated wireways each includes a proximal end and a distal end, each of the distal ends coupled with a corresponding lamp housing. The mounting plate is positioned within each of the proximal ends, is used to couple each of the proximal ends together relative to one another, and is configured for being used to selectively move the proximal ends away from the mounting plate to align the proximal ends relative to one another. | 2009-09-24 |
20090237947 | LAMP POSITION ADJUSTMENT DEVICE AND LAMP MODULE HAVING THE SAME - A lamp position adjustment device includes a bottom frame, a lamp holder, and a lamp mount. The lamp holder is disposed on the bottom frame for supporting the lamp, and the lamp mount is disposed between the lamp holder and the bottom frame. The lamp mount includes a base portion, a first side portion and a second side portion that are respectively connected to two opposite sides of the base portion, a first positioning mechanism, and a second positioning mechanism. The first positioning mechanism is disposed on the base portion to enable the lamp mount to be slidably connected to the bottom frame, and the second positioning mechanism is disposed on the first side portion and the second side portion to enable the lamp mount to be slidably connected to the lamp holder. | 2009-09-24 |
20090237948 | Headlight support structure for a saddle-type vehicle - A headlight support structure for a saddle-type vehicle allows a headlight to be easily mounted easily on a handlebar of the vehicle. The headlight support structure includes a support member. The support member, in turn, includes: an attachment portion fixed to a mounting bracket disposed on a handlebar; a first holding portion covering the handlebar from an upward direction; and a second holding portion covering the handlebar from a forward direction. The headlight support member is supported on the handlebar by having the first and second holding portions supported on the handlebar with gaps interposed therebetween, while having the attachment portion fixed to the mounting bracket on the handlebar. The headlight is supported by first and right wall portions, extending respectively forwardly from right and left sides of a front portion of the support member. | 2009-09-24 |
20090237949 | Flashing stern light for boats - The flashing stern light for boats includes an elongated tubular base, a light source housing mounted on top of the base, a light source disposed inside the housing, an array of light emitting elements disposed along a length of the base, and wiring adapted to operative connect to a power source and/or control, wherein the array of light emitting elements flash sequentially in a pattern to thereby draw attention to the light source, warn and emphasize proximity and presence of the boat. The flashing lights enhances visibility of the boat at night and in reduced visibility conditions. | 2009-09-24 |
20090237950 | LOW GLARE LIGHTING FOR A TRANSIT VEHICLE - A low glare overhead lighting fixture for a transit vehicle comprises a lighting fixture base assembly for mounting one or more light sources (e.g., LEDs or fluorescent tubes), and a light permeable cover adapted to reduce glare. The light permeable cover may include a light guide embodied as a grid-like structure with holes or perforations for directing the light from the light source in a manner reducing light spread. The light guide may be disposed between a front and rear lens covers. The lighting fixture may also utilize a light permeable cover having an anti-glare surface element, such as a privacy filter screen or mesh which may be formed using microlouver technology. The lighting fixture base assembly may have separate compartments, each lined with a highly reflective coating, housing one or more deeply set LEDs. | 2009-09-24 |
20090237951 | Automotive Illumination-System Device and Light-Conductor System for an Automotive Illumination-System Device - The invention relates to a light-conductor structure ( | 2009-09-24 |
20090237952 | Semiconductor-based lighting system and lighting system components for automotive use - A modular semiconductor light source assembly includes a semiconductor light source, such as a light emitting diode, which is mounted on a substrate which supplies electricity to the light source and which assists in removing waste heat therefrom. Substantially all of the light emitted by the LED is transferred to a lens by a light pipe, the cross section of the light pipe increasing from the light source to the lens and the lens having a general D-shape such that the light pattern formed by the lens is constrained in a first direction orthogonal to a second direction. The assembly can be combined with other similar assemblies or other light sources in a light fixture to produce a desired overall beam pattern such as a automobile headlamp low beam or high beam pattern. | 2009-09-24 |
20090237953 | VEHICLE LIGHTING DEVICE - A vehicle lighting device is provided to maintain a viewability of light even when seen from a diagonal direction having a predetermined angle to an irradiation direction of the lighting device. The vehicle lighting device includes a board, which includes an array of a plurality of light sources. The vehicle lighting device also includes wall portions that bulge in an irradiation direction of the light sources from edge surfaces of the board. The wall portions also form a polygon surrounding the board. At least one of the wall portions includes a reflective surface on a side facing the light sources. | 2009-09-24 |
20090237954 | LIGHT PIPE ASSEMBLY - A light pipe assembly includes a lamp assembly and a light pipe. The lamp assembly has a housing that holds a light source configured to emit light. The light pipe is elongated between an attachment end and an opposing distal end. The attachment end is received in the housing of the lamp assembly. The light pipe receives light emitted by the light source. Additionally, the light pipe includes surface elements that are configured to permit the light to emanate from the light pipe between the attachment and distal ends. The surface elements are arranged in a pattern that provides a predetermined distribution of light emanating from the light pipe. | 2009-09-24 |
20090237955 | OPTICAL DEVICE AND IMAGE EXPOSURE APPARATUS - A window of a CAN package is sealed by a circular transparent plate member and a cylindrical transparent member. The diameter of the cylindrical transparent member is equal to the diameter of the window, and the thickness thereof is 1 mm. The distance from a semiconductor laser LD to a light output surface of the circular transparent member is approximately 1 mm, and the distance from the semiconductor laser LD to a light output surface of the cylindrical transparent member is approximately 2 mm. The output of the semiconductor laser LD is 800 mW, and the transmittance area of a laser beam at the light output surface of the transparent member is approximately 0.70 mm | 2009-09-24 |
20090237956 | LIGHT EMITTING DIODE ASSEMBLY - An LED assembly ( | 2009-09-24 |
20090237957 | ILLUMINATION DEVICE, METHOD OF ASSEMBLING ILLUMINATION DEVICE, AND LIQUID CRYSTAL DISPLAY DEVICE - There is provided an illumination device equipped with a light guide plate, a light source unit having a plurality of point like light sources for supplying light to the light guide plate and a light source holding member for holding the point like light sources, the light source unit being disposed to oppose an edge face of the light guide plate, and a housing for holding the light guide plate and the light source unit. The light source unit is constituted so as to be inserted in and extracted from the housing by a slide mechanism that can be slid along the edge face of the light guide plate, and the light source unit is equipped with a spacer for assuring a gap between the edge face of the light guide plate and the light sources at a slide insertion side end of the light source unit with respect to the housing when the light source unit is slidingly inserted in the housing. | 2009-09-24 |
20090237958 | Low-clearance light-emitting diode lighting - A low-clearance light-emitting diode lighting includes a light guide panel having side surfaces and a front surface opposing a back surface, a plurality of light-emitting diodes positioned on at least two side surfaces of the light guide panel, a reflecting plate at the back surface of the light guide panel, reflectors having an inclined angle, and a metal frame for supporting the reflecting plate and the light guide panel, wherein each of the plurality of light-emitting diodes is positioned between one of the at least two side surfaces and one of the reflectors such that light from the plurality of light-emitting diodes is reflected toward the at least two side surfaces. | 2009-09-24 |
20090237959 | Digital Control of Power Converters - A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, a digital pulse generator, and a pre-driver to control the power converter. Another embodiment also includes a digital filter as part of the control loop that may be used to control the loop characteristics of the control circuit. Yet another embodiment replaces the differential circuit with a sigma-delta analog-to-digital modulator and a decimator. | 2009-09-24 |
20090237960 | SWITCH MODE POWER SUPPLY CONTROLLERS - This invention relates to SMPS controllers employing primary side sensing. We describe a system for identifying a knee point in a sensing waveform, at which the output voltage of the SMPS may be sampled accurately on the primary side. The system identifies the knee point by fitting a tangent to a portion of a power transformer voltage waveform, and samples the voltage waveform at the knee point to determine the SMPS output voltage. In preferred embodiments this technique is implemented using a decaying peak detector, providing a timing signal indicating detection of the knee point. Sample/hold and error amplifier circuits may be employed to achieve output voltage regulation. | 2009-09-24 |
20090237961 | INVERTER - The inverter comprises a diode bridge ( | 2009-09-24 |
20090237962 | MULTI LEVEL INVERTER - The present invention relates to a multilevel inverter comprising: a converter unit converting an inputted AC power source to a direct current (DC) power source; a film capacitor rectifying the DC power source converted by the converter unit; an inverter unit converting the rectified DC power source to a three-phase current in response to a pulse width modulation (PWM) control signal and outputting the current; a current detector detecting a current outputted from the inverter unit; a power cell main controller generating a voltage instruction and a voltage instruction using the detected current; and a PWM controller generating the pulse width modulation (PWM) control signal using the voltage instruction and frequency instruction. | 2009-09-24 |
20090237963 | UPS FREQUENCY CONVERTER AND LINE CONDITIONER - Systems and methods disclosed herein monitor and control input to a converter in one or more of a UPS, a frequency converter, or a line conditioner. Distortion due at least in part to ripple voltage can be removed from a control signal that controls input current to the converter. The systems and methods described herein afford a simple and effective way to reduce or eliminate one or more of subharmonic oscillation and total harmonic distortion from a converter input current during synchronous and asynchronous modes of operation. The converter may include one or more of a rectifier and an inverter. | 2009-09-24 |
20090237964 | METHOD FOR OPERATING A CONVERTER CIRCUIT AND APPARATUS FOR IMPLEMENTING THE METHOD - A method is disclosed for the operation of a converter circuit, wherein the converter circuit has a converter unit having a multiplicity of actuatable power semiconductor switches and an LCL filter which is connected to each phase connection of the converter unit, in which the actuatable power semiconductor switches are actuated by means of an actuation signal (S) formed from a hysteresis active power value (d | 2009-09-24 |
20090237965 | SEMICONDUCTOR DEVICE FOR SWITCHING POWER SUPPLY CONTROL, STARTUP CIRCUIT, AND STARTUP METHOD FOR SWITCHING POWER SUPPLY DEVICE - A semiconductor device for switching power supply control limits the startup current supplied from a high-voltage input terminal, and prevents heat generation and combustion in case of an anomaly. A high-voltage input terminal is connected to the main winding of a transformer, and is supplied with a startup voltage upon input of a power supply to the switching power supply device. A power supply terminal is connected to a capacitor, and outputs a startup current to charge the capacitor after input of the power supply input. A startup circuit is connected between the high-voltage input terminal and the power supply terminal, and charges the capacitor while increasing the startup current with magnitude proportional to the voltage value of the power supply terminal, and after startup, turns off the startup current and supplies the power supply voltage only from the auxiliary winding of the transformer. | 2009-09-24 |
20090237966 | DIGITAL CONTROL OF POWER CONVERTERS - A system and method for controlling a power converter is presented. An embodiment comprises an analog differential circuit connected to an analog-to-digital converter, and comparing the digital error signal to at least a first threshold value. If the digital error signal is less than the first threshold value, a pulse is generated to control the power converter. Another embodiment includes multiple thresholds that may be compared against the digital error signal. | 2009-09-24 |
20090237967 | Power factor correction circuit with buck and boost conversions - A power factor correction circuit with buck and boost conversions has a rectifying circuit, a buck circuit and a boost circuit. When an input AC voltage of the power factor correction circuit is a relative low voltage, the AC voltage is converted to low level voltage by the buck circuit and then converted to an intermediate voltage with a desired level by the boost circuit. When the input AC voltage is a relative high voltage, the boost circuit is turned off. The input AC voltage is rectified and bucked to the intermediate voltage with a desired level. | 2009-09-24 |
20090237968 | POWER INVERTER AND METHOD - An apparatus and method for converting an input signal to an output AC signal in which the input voltage signal is inverted and modulated to provide an intermediate AC signal having twice the desired output frequency. The intermediate signal is then full-wave rectified and then the polarity of the rectified signal is switched every second cycle to produce the output AC signal of a desired frequency and voltage. | 2009-09-24 |
20090237969 | Controller IC, DC-AC conversion apparatus, and parallel running system of DC-AC conversion apparatuses - A DC power source voltage is supplied to a center tap of a primary winding, and first and second semiconductor switches alternately turned on are disposed between each of both ends of the primary winding and a common potential point, and a current flowing through a load is fed back and PWM control of each of the semiconductor switches is performed. Also, snubber circuits are respectively connected between a ground and the center tap of the primary winding, and an abnormal high voltage at the time of switching is reduced. Also, a parallel running of plural inverters is simply performed by disposing PWM comparators corresponding to the first and second semiconductor switches. | 2009-09-24 |
20090237970 | PROCESS VARIATION COMPENSATED MULTI-CHIP MEMORY PACKAGE - A multi-chip package memory includes an interface chip generating at least one reference signal defined in relation to a reference process variation, and a stacked plurality of memory chips electrically connected to the interface chip via a vertical connection path and receiving the reference clock signal via the vertical connection path, wherein each one of the stacked plurality of memory chips is characterized by a process variation and actively compensates for said process variation in relation to the reference signal. | 2009-09-24 |
20090237971 | SEMICONDUCTOR MEMORY DEVICES WITH INTERFACE CHIPS HAVING MEMORY CHIPS STACKED THEREON - A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed. The interface chips may forward the command signal from one end of the sequence of the stacked memories on one of the substrates to the selected stacked memory, and forward a response signal from the selected stacked memory through the remaining stacked memories in the sequence on the substrate back to the controller or through the same sequence of stacked memories that was taken by the command signal. | 2009-09-24 |
20090237972 | MEMORY INCLUDING PERIPHERY CIRCUITRY TO SUPPORT A PORTION OR ALL OF THE MULTIPLE BANKS OF MEMORY CELLS - A memory including periphery circuitry configured to support multiple banks of memory cells. The periphery circuitry includes switches that are set to put the periphery circuitry into a first mode to support a portion of the multiple banks of memory cells and a second mode to support all of the multiple banks of memory cells. | 2009-09-24 |
20090237973 | Design method for read-only memory devices - A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data word are mapped by the decoder to the same address decode line. Each address decode line is electrically connected to a bit output line as determined by the data set. An initial design of the ROM uses N connecting devices to respectively electrically connect N of the address decode lines to a bit output line. If N exceeds X/2, then an optimization process is performed. The optimization process involves electrically disconnecting each address decode line that was connected to the bit output line, and electrically connecting each address decode line that was not connected to the bit output line. The output of the bit output line is then run through a logical inverter to provide the correct output data bit. | 2009-09-24 |
20090237974 | Programmable memory cell - A disclosed embodiment is a programmable memory cell comprising an elevated ground node having a voltage greater than a common ground node by an amount substantially equal to a voltage drop across a trigger point adjustment element. In one embodiment, the trigger point adjustment element can be a diode. The trigger voltage of the programmable memory cell is raised closer to a supply voltage when current passes through the trigger point adjustment element during a write operation. The programmable memory cell can comprise a pair of cross-coupled inverters, and first and second programmable antifuses that can be coupled to each inverter in the pair of cross-coupled inverters. Since the trigger voltage of the programmable memory cell is raised closer to the supply voltage, a programmed antifuse can easily reach below the trigger voltage and result in a successful write operation even when the supply voltage is a low voltage. | 2009-09-24 |
20090237975 | One-time programmable memory cell - A disclosed embodiment is a programmable memory cell having improved IV characteristics comprising a thick oxide spacer transistor interposed between a programmable thin oxide antifuse and a thick oxide access transistor. The spacer transistor separates a rupture site formed during programming the programmable antifuse from the access transistor, so as to result in the improved IV characteristics. The programmable antifuse is proximate to one side of the spacer transistor, while the access transistor is proximate to an opposite side of the spacer transistor. The source region of the access transistor is coupled to ground, and the drain region of the access transistor also serves as the source region of the spacer transistor. The access transistor is coupled to a row line, while the spacer transistor and the programmable antifuse are coupled to a column line. The rupture site is formed during programming by applying a programming voltage to the programmable antifuse. | 2009-09-24 |
20090237976 | N-ary Three-Dimensional Mask-Programmable Read-Only Memory - N-ary three-dimensional mask-programmable read-only memory (N-3DMPROM) stores multi-bit-per-cell. Its memory cells can have N states (N>2) and data are stored as N-ary codes. N-3DMPROM has a larger storage density than the prior-art binary 3D-MPROM. One advantage of N-3DROM over other N-ary memory (e.g. multi-level-cell flash) is that its array efficiency can be kept high. N-3DMPROM could be geometry-defined, junction-defined, or a combination thereof. | 2009-09-24 |
20090237977 | SENSING RESISTANCE VARIABLE MEMORY - The present disclosure includes devices and methods for operating resistance variable memory. One device embodiment includes an array of memory cells wherein a number of the cells are commonly coupled to a select line, the number cells including a number of data cells programmable within a number of target threshold resistance (R | 2009-09-24 |
20090237978 | Semiconductor device having resistance based memory array, method of reading, and systems associated therewith - In one embodiment, the semiconductor device includes a non-volatile memory cell array. Memory cells of the non-volatile memory cell array are resistance based, and each memory cell has a resistance that changes over time after data is written into the memory cell. A write address buffer is configured to store write addresses associated with data being written into the non-volatile memory cell array, and a read unit is configured to perform a read operation to read data from the non-volatile memory cell array. The read unit is configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array. | 2009-09-24 |
20090237979 | SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM - A semiconduct or memory device comprises a memory cell array including a plurality of memory cells arranged at intersections of word lines and bit lines; a read/write circuit operative to execute data read/write to the memory cell; and an operational circuit operative to compare certain length data read out by the read/write circuit from plural ones of the memory cells with certain length data to be written in the plural memory cells to make a decision, and create a flag representing the decision result. The read/write circuit inverts each bit in the certain length data to be written in the memory cells in accordance with the flag, and writes only rewrite-intended data of the certain length data and the flag. The read/write circuit reads the certain length data together with the flag corresponding thereto, and inverts each bit in the certain length data in accordance with the flag. | 2009-09-24 |
20090237980 | ELECTROMECHANICAL SWITCH AND METHOD OF FORMING THE SAME - A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized. | 2009-09-24 |
20090237981 | DYNAMIC MEMORY WORD LINE DRIVER SCHEME - A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The circuit eliminates the need for a double-boot-strapping circuit, and ensures that no voltages exceed that necessary to fully turn on a memory cell access transistor. Voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, a gate receiving word line selecting signals at first logic levels V | 2009-09-24 |
20090237982 | Magnetically De-Coupling Magnetic Tunnel Junctions and Bit/Word Lines for Reducing Bit Selection Errors in Spin-Momentum Transfer Switching - Techniques for shielding magnetic memory cells from magnetic fields are presented. In accordance with aspects of the invention, a magnetic storage element is formed with at least one conductive segment electrically coupled to the magnetic storage element. At least a portion of the conductive segment is surrounded with a magnetic liner. The magnetic liner is operative to divert at least a portion of a magnetic field created by a current passing through the conductive segment away from the magnetic storage element. | 2009-09-24 |
20090237983 | INTEGRATED CIRCUIT INCLUDING MEMORY ELEMENT DOPED WITH DIELECTRIC MATERIAL - An integrated circuit includes a first electrode, a second electrode, and a damascene structured memory element coupled to the first electrode and the second electrode. The memory element has a height and a width. The height is greater than or equal to the width. The memory element includes resistance changing material doped with dielectric material. | 2009-09-24 |
20090237984 | MEMORY CELL - Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using a first self-biased sensing circuit and the complementary state of the second memory cell using a second self-biased sensing circuit, and comparing in a differential manner an indication of the state of the first memory cell to a reference indication of the complementary state of the second memory cell to determine the value. | 2009-09-24 |
20090237985 | SEMICONDUCTOR DEVICE AND ITS FABRICATION METHOD - An electrically rewritable non-volatile memory device is configured by the EEPROM | 2009-09-24 |
20090237986 | NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT - A nonvolatile memory device using variable resistive element with reduced layout size and improved performance is provided. The nonvolatile memory device comprising: a main word line; multiple sub-word lines, wherein each of the sub-word line is connected to multiple nonvolatile memory cells; and a section word line driver which controls voltage level of the multiple sub-word lines, wherein the section word line driver includes multiple pull-down elements which are connected to each of the multiple sub-word lines and a common node and a selection element which is connected to the common node and the main word line. | 2009-09-24 |
20090237987 | Crossbar diode-switched magnetoresistive random access memory system - A magnetic memory or MRAM memory system comprising an M×N crossbar array of MRAM cells. Each memory cell stores binary data bits with switchable magnetoresistive tunnel junctions (MJT) where the electrical conductance changes as the magnetic moment of one electrode (the storage layer) in the MJT switches direction. The switching of the magnetic moment is assisted by a phase transition interlayer that transitions from antiferromagnetic to ferromagnetic at a well defined, above ambient temperature. | 2009-09-24 |
20090237988 | MAGNETIC MEMORY DEVICE - A magnetic memory device includes a plurality of word lines, a plurality of bit lines arranged to intersect with the word lines, an MRAM cell array including a plurality of magnetic random access memory (MRAM) cells arranged at intersection portions between the word lines and the bit lines, a read current source which supplies a read current to the MRAM cells in a read mode, a sense amplifier which detects terminal voltages of the MRAM cells generated by the read current to generate a detection output signal, a latch circuit which latches the detection output signal to output read data, and a data write circuit which supplies a write current to the MRAM cells depending on write data in a write mode to perform writing and which supplies the write current to the MRAM cells depending on the read data in the read mode to perform rewriting. | 2009-09-24 |
20090237989 | MAGNETIC MEMORY DEVICE - A width and a thickness of a bit line are represented as W | 2009-09-24 |
20090237990 | SONOS DEVICE WITH INSULATING STORAGE LAYER AND P-N JUNCTION ISOLATION - The present invention provides a semiconductor device and a method for manufacturing thereof. The semiconductor device includes bit lines disposed in a semiconductor substrate, a first ONO disposed between the bit lines on the semiconductor substrate, and a second ONO film disposed on each of the bit lines. The film thickness of a first silicon nitride film in the first ONO film is larger than the film thickness of a second silicon nitride film in the second ONO film. | 2009-09-24 |
20090237991 | System for Operating a Memory Device - A system for operating a memory device comprises a memory array having a number of memory cells and a set of dynamic reference cells coupled to the memory cells in word lines. Each of the dynamic reference provides the associated memory cells with a dynamic reference value for determining a status of at least one of the associated memory cells. The dynamic reference value is capable of reflecting a variation in a threshold value of at least one of the associated memory cells. | 2009-09-24 |
20090237992 | SEMICONDUCTOR MEMORY DEVICE HAVING STACKED GATE INCLUDING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell, a bit line, a source line, a detection circuit, and a sense amplifier. The memory cell holds or more levels of data. The bit line is electrically connected to a drain of the memory cell. The source line is electrically connected to a source of the memory cell. The detection circuit detects a current flowing through the source line during a read operation and a verify operation on the data. The sense amplifier reads the data by sensing a current flowing through the bit line during the read operation and the verify operation. Whether or not the sense amplifier reads the same data plural times is determined according to a current amount detected by the detection circuit. | 2009-09-24 |
20090237993 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD - The nonvolatile semiconductor memory device related to the present invention includes a plurality of memory cells, a read/program circuit which supplies a program voltage and a program verification voltage to the plurality of memory cells and desired data is programmed, supplies a first program verification voltage to the plurality of memory cells and then supplies a second program verification voltage to the plurality of memory cells when programming the data, and a read/program control circuit which determines memory cells which reach a first data program state and memory cells which do not reach the first data program state when supplying the first program verification voltage, and determines memory cells which reach a second data program state and memory cells which do not reach the second data program state when supplying the second program verification voltage, and supplies a program control voltage which changes the program operation state for each memory cell. | 2009-09-24 |
20090237994 | Iterative Memory Cell Charging Based on Reference Cell Value - Systems and methods, including computer software for writing to a memory device include applying charge to each of multiple memory cells for storage of a selected data value in each memory cell. The memory cells include a first reference memory cell, and each data value is selected from a group of possible data values. Each possible data value has a corresponding target voltage level, and the first reference memory cell has a corresponding predetermined first reference target voltage level. The voltage level in the first reference memory cell is detected. A determination is made whether the voltage level in the first reference memory cell is less than the first reference target voltage level. Additional charge is applied to the memory cells upon the determination that the voltage level in the first reference memory cell is less than the first reference target voltage. | 2009-09-24 |
20090237995 | Scaleable memory Systems Using Third Dimension Memory - A non-volatile scalable memory circuit is described, including a bus formed on a substrate that includes active circuitry, metallization layers, and a plurality of high density third dimension memory arrays formed over the substrate. Each memory circuit can include an embedded controller for controlling data access to the memory arrays and optionally a control node that allows data access to be controlled by an external memory controller or by the embedded controller. The memory circuits can be chained together to increase memory capacity. The memory arrays can be two-terminal cross-point arrays that may be stacked upon one another. | 2009-09-24 |
20090237996 | MEMORY STRUCTURE HAVING VOLATILE AND NON-VOLATILE MEMORY PORTIONS - A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells. | 2009-09-24 |
20090237997 | RANDOM ACCESS MEMORY WITH CMOS-COMPATIBLE NONVOLATILE STORAGE ELEMENT - Embodiments provide systems, methods, and apparatuses with a plurality of row lines and column lines arranged in a matrix, and at least one memory cell having an access transistor and a CMOS-compatible non-volatile storage element coupled to the access transistor in series. The CMOS-compatible non-volatile storage element includes a node and is configured to hold a charge corresponding to a n-bit binary value where n is an integer greater than 1. The access transistor has a word line gate coupled to a row line, a first node coupled to a column line, a second node coupled to a storage node, with the storage node connected to said node of the CMOS-compatible non-volatile storage element. Access circuitry coupled to the memory cell is configured to activate the memory cell and sense a resulting current corresponding to the n-bit binary value. | 2009-09-24 |
20090237998 | Adaptive Algorithm in Cache Operation with Dynamic Data Latch Requirements - A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed. The memory subsequently can perform the second operation during the first operation when a sufficient number of latches become available; and if, in response to determining whether there are a sufficient number of the corresponding set of data latches to perform the second operation it is determined that there are a sufficient number, performing the second operation during the first operation. | 2009-09-24 |
20090237999 | Different Combinations of Wordline Order and Look-Ahead Read to Improve Non-Volatile Memory Performance - For a non-volatile memory storing three or more bits per cell, pages of data are written in an order where more than one, but less than all of the logical pages that a physical page along a wordline can store are written concurrently. More than one, but less than all of the logical pages that a physical page along a wordline can store are then written concurrently on an adjacent wordline. The process then comes back to the first wordline and writes at least one more logical page. A process is also described where one or more logical pages are written into a physical page along a wordline, after which one or more logical pages are written into a physical page along an adjacent wordline. A read operation is then performed on the first wordline and the resultant read is corrected based on the result of programming the adjacent wordline. This corrected read is then used in writing at least one more logical page in a second programming operation on the first wordline. | 2009-09-24 |
20090238000 | SYSTEMS AND DEVICES INCLUDING MULTI-GATE TRANSISTORS AND METHODS OF USING, MAKING, AND OPERATING THE SAME - Disclosed are methods, systems and devices, including a device having a digit line and a plurality of transistors each having one terminal connected to the digit line and another terminal disposed on alternating sides of the digit line. In some embodiments, each transistor among the plurality of transistors comprises a fin. | 2009-09-24 |
20090238001 | Interface for NAND-Type Flash Memory - A NAND-type flash memory device is described. In some embodiments, the memory device includes NAND-type flash memory cells, and a synchronous NAND interface. The synchronous NAND interface includes a standard NAND flash interface pin arrangement and a clock (CLK) pin. The synchronous NAND interface is configured to interface with a NOR-compatible memory interface. | 2009-09-24 |
20090238002 | NAND TYPE NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF - A NAND type non-volatile memory having a plurality of bit lines and a dummy bit line is provided. The intersections of each of the bit lines with a first select gate line, a plurality of word lines, and a second select gate line are corresponding to a memory cell row. The intersections of the dummy bit line with the first select gate line, the word lines, and the second select gate line are corresponding to a dummy memory cell row. A source line is disposed on the substrate at one side of the memory cell rows, wherein the dummy memory cell row and the dummy bit line are served as a current path for connecting the source line. | 2009-09-24 |
20090238003 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage. | 2009-09-24 |
20090238004 | Method of operating sonos memory device - A silicon-oxide-nitride-oxide-silicon (SONOS) memory device includes a memory type transistor including a gate with a SONOS structure on a semiconductor substrate. The gate is formed by sequentially stacking a tunneling oxide layer, a memory node structure including a trap site having nano-sized trap elements in which charges passing through the tunneling oxide layer are trapped, and a gate electrode. The nano-sized trap elements may be a crystal layer composed of nanocrystals that are separated from one another to trap the charges. The memory node structure may include additional memory node layers which are isolated from the nano-sized trap elements. | 2009-09-24 |
20090238005 | MULTI-PLANE TYPE FLASH MEMORY AND METHODS OF CONTROLLING PROGRAM AND READ OPERATIONS THEREOF - A multi-plane type flash memory device comprises a plurality of planes each including a plurality of memory cell blocks, page buffers each latching an input data bit to be output to its corresponding plane or latching an output data bit to be received from the corresponding plane, cache buffers each storing an input or output data bits in response to one of cache input control signals and each transferring the stored data bit to the page buffer or an external device in response to one of cache output control signals, and a control logic circuit generating the cache input and output control signals in response to command and chip enable signals containing plural bits. The program and read operations for the plural planes are conducted simultaneously in response to the chip enable signal containing the plural bits, which increases an operation speed and data throughput processed therein. | 2009-09-24 |
20090238006 | ADJUSTING PROGRAMMING OR ERASE VOLTAGE PULSES IN RESPONSE TO THE NUMBER OF PROGRAMMING OR ERASE FAILURES - Memory devices and methods of operating memory devices are provided. In one such embodiment a programming voltage pulse or an erase voltage pulse is applied to memory cells of a memory device. A number of the memory cells that failed to program or erase is determined and is compared to a certain number that can be different than a number of memory cells to be programmed or erased. The programming voltage pulse or the erase voltage pulse is adjusted in response to the comparison of the number of memory cells that failed to program or erase to the certain number. The adjusted programming voltage pulse or the adjusted erase voltage pulse is applied to the memory cells that failed to program or erase. | 2009-09-24 |
20090238007 | METHOD OF SUPPLYING AN OPERATING VOLTAGE OF A FLASH MEMORY DEVICE - A method of supplying an operating voltage of a flash memory device includes supplying an operating voltage to a word line selected according to an input address, and changing a pass voltage according to a change of the operating voltage level. The pass voltage is supplied to unselected word lines other than the selected word line. | 2009-09-24 |
20090238008 | Non-Volatile Memory Cell With BTBT Programming - A Non-Volatile Memory (NVM) cell and programming method in which the cell can denote at least two logic levels (e.g., 0 and 1) and includes a read-transistor with a floating gate and a Band-To-Band-Tunneling device (BTBT device) sharing the floating gate with the read-transistor. The BTBT device is configured as an injection device for injecting a first charge onto the floating gate when the BTBT device is biased so that it is in accumulation, to set at least one of the logic levels. | 2009-09-24 |
20090238009 | SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 2009-09-24 |
20090238010 | SYSTEMS AND DEVICES INCLUDING MULTI-TRANSISTOR CELLS AND METHODS OF USING, MAKING, AND OPERATING THE SAME - Disclosed are methods, systems and devices, including devices having a plurality of data cells. In some embodiments, each data cell includes a first transistor, a second transistor, and a data element. The first transistor may have a column gate and a channel, and the second transistor may include a row gate that crosses over the column gate, under the column gate, or both. The second transistor may also include another channel, a source disposed near a distal end of a first leg, and a drain disposed near a distal end of a second leg. The column gate may extend between the first leg and the second leg. The channel of the second transistor may be connected to the channel of the first transistor, and the data element may be connected to the source or the drain. | 2009-09-24 |
20090238011 | VCC CONTROL INSIDE DATA REGISTER OF MEMORY DEVICE - A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a voltage supplied to a second inverter inside the data register. The memory device may include a switch to allow coupling to the current-limiting circuitry for programming of the memory device. | 2009-09-24 |
20090238012 | CONTROLLING SLEW RATE PERFORMANCE ACROSS DIFFERENT OUTPUT DRIVER IMPEDANCES - Embodiments are provided including one directed to an output driver system, having an adjustable pre-driver configured to maintain a generally constant slew rate of an output driver across a plurality of output driver impedances. Other embodiments provide a method of operating a memory device, including determining an output driver strength of an output driver and configuring the pre-driver based on the determined output driver strength. | 2009-09-24 |
20090238013 | SEMICONDUCTOR DEVICE - A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR | 2009-09-24 |
20090238014 | LOW POWER SYNCHRONOUS MEMORY COMMAND ADDRESS SCHEME - A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array. | 2009-09-24 |
20090238015 | Appartus and method for controlling refresh with current dispersion effect in semiconductor device - A refresh control apparatus is provided which is capable of dispersing a peak current at an all-bank refresh mode and reducing the characteristic difference between the banks. The refresh control apparatus includes an internal refresh counter for outputting row address signals to select word lines when a refresh command is inputted from an external circuit, a row decoder for outputting row decoding signals to select all banks in response bank active signals and the row address signals, an enable signal control unit for sequentially outputting at a time interval sense amplifier enable signals in response to the bank active signals and the refresh command, and a sense amplifier for sequentially refreshing all of the banks at a time interval in response to the sense amplifier enable signals. | 2009-09-24 |
20090238016 | CIRCUITS TO DELAY SIGNALS FROM A MEMORY DEVICE - Various embodiments include method and apparatus for receiving a clock signal, determining a number of delay elements based on a relationship between the clock signal and a delayed feedback signal generated based on the clock signal, calculating an amount of time corresponding to the number of delay elements, and delaying a control signal by the amount of time to generate an additional clock signal, the control signal having a frequency higher than a frequency of the clock signal. Other embodiments are described. | 2009-09-24 |
20090238017 | DIGITAL DLL CIRCUIT - A digital delay locked loop circuit generates a delay value to delay the timing of taking in read-data by a memory interface when data is read from a memory. The digital delay locked loop circuit includes a selector that selects either one of a clock signal and a data strobe signal as a signal to output; a delay line that induces delay on the signal output from the selector when the signal passes through the delay line; and a phase-comparing/delay-value determining unit that compares a phase of the clock signal and a phase of the signal output from the delay line, and that determines a delay value that defines an amount of delay to be induced on the data strobe signal when passing through the delay line. | 2009-09-24 |
20090238018 | Integrated circuit including Built-In Self Test circuit to test memory and memory test method - An integrated circuit includes multiple memory circuits including memory cell arrays different in size, a BIST circuit which has a cell sequential transition test processor and which outputs a test cell address, a transition direction specification signal and an active signal. The integrated circuit has adjustment circuits which are provided respectively for the memory circuits and which replace the test cell address with the test cell address in a memory cell array area, or which convert the active signal into a signal indicating non-execution when the test cell address outputted from the BIST circuit corresponds to a cell in a virtual cell array being in an area outside the memory cell array. | 2009-09-24 |
20090238019 | Bit line precharge circuit having precharge elements outside sense amplifier - A bit line precharge circuit capable of improving bit line precharge operation includes a first precharge element for precharging a first bit line in response to a first precharge signal, a precharge unit for precharging second and third bit lines in response to a second precharge signal, and a second precharge element for precharging a fourth bit line in response to a third precharge signal. | 2009-09-24 |
20090238020 | INTEGRATED CIRCUIT INCLUDING MEMORY REFRESHED BASED ON TEMPERATURE - An integrated circuit includes an array of memory cells and a first circuit. The array includes word lines. Each word line is coupled to a plurality of memory cells. The first circuit is configured to refresh memory cells along a first number of word lines in response to a refresh command. The first number of word lines is based on a sensed temperature. | 2009-09-24 |
20090238021 | Semiconductor memory device and operation method therefor - Disclosed herein is a semiconductor memory device, including: a memory array section wherein a memory array which requires a refresh operation is formed; an interface section configured to carry out an interfacing process between an external apparatus and the memory array section; and a refresh control block for controlling the refresh operation; the interface section configured to include a plurality of interface modules individually corresponding to a plurality of memory types and selectively applied to the interfacing process between the external apparatus and the memory array section; the refresh control block having a function of issuing a refresh command within a refresh cycle and another function of preventing, if, upon issuance of the refresh command, an access command and the refresh command to the memory array are estimated to collide with each other, the collision. | 2009-09-24 |
20090238022 | SEMICONDUCTOR DEVICE AND CONTROLLING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a setting circuit which sets a first setting value; a control circuit which receives a predetermined control signal and the first setting value so as to output a second setting value; and an output circuit which outputs a predetermined level in response to the first setting value or the second setting value, wherein the second setting value is changed from the first setting value based on the predetermined control signal. | 2009-09-24 |