38th week of 2010 patent applcation highlights part 59 |
Patent application number | Title | Published |
20100241764 | METHOD AND APPARATUS FOR SYNCHRONIZING DATA - A method for synchronizing data between a client and a server is disclosed. The method includes: receiving a synchronization instruction and data items to be synchronized; and performing synchronization for the data items according to the synchronization instruction. A sending apparatus and a receiving apparatus for implementing the method are also provided. The embodiments of the present invention reduce retransmission of the data that needs no update or reduce futile data transmission drastically, save traffic of data transmission, save network resources, and improve the data synchronization efficiency. | 2010-09-23 |
20100241765 | DISK ARRAY APPARATUS - A disk array apparatus using an SAS can transfer data without lowering a transfer efficiency of data even if rates of a plurality of physical links connected to a controller and storage device are different. A plurality of HDDs are connected to a controller through an expander. Data are transferred from the controller to the expander and then to HDD. In this connection, the controller and the expander transfers a set of transfer data in a plurality of the HDD-side physical links. The controller-side physical link integrates the transfer data, and multiplexes them to transfer. A plurality of HDDs-side physical links separates the transfer data to transfer in parallel. | 2010-09-23 |
20100241766 | Min-Repro Framework for Database Systems - The min-repro finding technique described herein is designed to ease and speed-up the task of finding a min-repro, a minimum configuration that reproduces a problem in database-related products. Specifically, in one embodiment the technique simplifies transformations in order to find one or more min-repros. One embodiment provides a high-level script language to automate some sub-tasks and to guide the search for a simpler the configuration that reproduces the problem. Yet another embodiment provides record-and-replay functionality, and provides an intuitive representation of results and the search space. These tools can save hours of time for both customers and testers to isolate the problem and can result in faster fixes and large cost savings to organizations. | 2010-09-23 |
20100241767 | Migrating Domains from One Physical Data Processing System to Another - A system and method for migrating domains from one physical data processing system to another are provided. With the system and method, domains may be assigned direct access to physical I/O devices but in the case of migration, the I/O devices may be converted to virtual I/O devices without service interruption. At this point, the domain may be migrated without limitation. Upon completion of the migration process, the domain may be converted back to using direct physical access, if available in the new data processing system to which the domain is migrated. Alternatively, the virtualized access to the I/O devices may continue to be used until the domain is migrated back to the original data processing system. Once migration back to the original data processing system is completed, the access may be converted back to direct access with the original physical I/O devices. | 2010-09-23 |
20100241768 | METHOD FOR CONTROLLING ICON DISPLAY CORRESPONDING TO A USB MASS STORAGE, ASSOCIATED PERSONAL COMPUTER, AND STORAGE MEDIUM STORING AN ASSOCIATED USB MASS STORAGE DRIVER - A method for controlling icon display corresponding to a Universal Serial Bus (USB) Mass Storage is provided. The USB Mass Storage is electrically connected to a USB port of a personal computer. The method includes: when it is detected that there is nothing inserted into any memory card slot of the USB Mass Storage, preventing the USB Mass Storage from triggering a specific icon to be displayed, wherein the specific icon is selectively utilized for indicating that at least one USB device is electrically connected to the personal computer; and when it is detected that a memory card is inserted into any of at least one memory card slot of the USB Mass Storage, allowing the specific icon to be displayed. An associated personal computer and a storage medium storing an associated USB Mass Storage driver for controlling icon display corresponding to the USB Mass Storage are further provided. | 2010-09-23 |
20100241769 | INTERFACE DEVICE AND METHOD FOR COMMAND PROCESSING - Embodiments of the present invention provide an interface device and method for command processing for commands requiring data flow in both directions on a Fiber Channel or other data transport protocol exchange. The commands can include proprietary commands, SCSI linked commands or other commands known in the art. According to one embodiment, and interface device can assign a command a data flow direction indicator. When a reply to the command is received, the interface device can determine if the reply is expected or unexpected based on the data flow direction specified by the data flow direction indicator. If the reply is unexpected, the interface device can determine whether to process the reply. According to one embodiment, the data flow direction indicator can be the exchange identification. | 2010-09-23 |
20100241770 | METHOD AND APPARATUS FOR EFFICIENT SYNCHRONIZATION REQUEST RESPONSE - A data writing apparatus includes a tape drive, a buffer and non-volatile memory. When a synchronization request is received from a device sending data to be written to a tape, the apparatus is operable to copy data corresponding to the synchronization request from the buffer to the non-volatile memory. The data may be stored in the non-volatile memory until at least the time when the data which it is a copy of is written to the tape from the buffer. | 2010-09-23 |
20100241771 | PERIPHERAL CIRCUIT WITH HOST LOAD ADJUSTING FUNCTION - A peripheral circuit with a host load adjusting function which is capable of readily carrying out control so that the amounts of data processed by the peripheral circuit and a host CPU are balanced by limiting interrupts made by the peripheral circuit, usage of a memory bus bandwidth, and a processing throughput of data. A typical embodiment of the present invention has an adjustment limitation setting unit setting a minimum value of an interval of interrupt requests generated by the peripheral circuit with the host load adjusting function, and a cycle counter counting generation timing of the interrupt requests, and compares a value of the cycle counter with the interval set in the adjustment limitation setting unit, thereby suppressing the interrupt requests generated at an interval shorter than the set interval. | 2010-09-23 |
20100241772 | THIN CLIENT SERVER SYSTEM AND METHOD OF MANAGING A DRIVER OF A USB DEVICE - Provided is a more secure thin client server system by suppressing increase of the number of sessions established between a thin client and a server when the server controls a USB device connected to a USB bus of the thin client. When a thin client OS detects that a USB device (D) which is one of a plurality of predetermined USB devices is connected, a USB general-purpose device driver that supports all of the plurality of predetermined USB devices is loaded, and a type of the USB device (D) is notified from the thin client to the server via a session used when the screen information or the like is transmitted between the thin client and the server. The server loads a device driver of the USB device (D), assuming that the USB device (D) is connected to a USB virtual bus driver working as a virtual USB bus. | 2010-09-23 |
20100241773 | REAL-TIME INDUSTRIAL ETHERNET ETHERCAT COMMUNICATION CONTROL - A real-time industrial Ethernet EtherCAT system including a communication master and a plurality of slave nodes, wherein one slave node acts as a logic control master and the further slave nodes act as logic control slaves, and wherein a communication flow is as follows: the communication master sends a data fetching frame, when the data fetching frame passes through the logic control master, the logic control master inputs control data for the logic control slaves into the data fetching frame, when the data fetching frame passes through the logic control slaves, each logic control slave inputs status data into the data fetching frame, after return of the data fetching frame to the communication master, the communication master sends a data sending frame with output data, said output data being reorganized according to the control relationship between the logic control master and the logic control slaves by the communication master, when the data sending frame passes through the logic control master, the logic control master gets the status data of the logic control slaves from the data sending frame, and when the data sending frame passes through the logic control slaves, each logic control slave gets command data from data sending frame. | 2010-09-23 |
20100241774 | SCALABLE READER-WRITER LOCK - A reader-writer lock is provided that scales to accommodate multiple readers without contention. The lock comprises a hierarchical C-SNZI (Conditioned Scalable Non-Zero Indicator) structure that scales with the number readers seeking simultaneous acquisition of the lock. All readers that have joined the C-SNZI structure share concurrent acquisition, and additional readers may continue to join until the structure is disabled. The lock may be disabled by a writer, at which time subsequent readers will wait (e.g., in a wait queue) until the lock is again available. The C-SNZI structure may be implemented in a lockword or in reader entries within a wait queue. If implemented in reader entries of a wait queue, the lockword may be omitted, and new readers arriving at the queue may be able join an existing reader entry even if the reader entry is not at the tail of the queue. | 2010-09-23 |
20100241775 | METHOD AND APPARATUS FOR ARBITRATION ON A FULL-DUPLEX BUS USING DUAL PHASES - A method and apparatus for arbitrating on a high performance serial bus is disclosed. The invention provides for a plurality of arbitration phases and an arbitration advancing means. | 2010-09-23 |
20100241776 | DEVICE AND METHOD FOR MANIPULATING COMMUNICATION MESSAGES - A device for manipulating an operating state of a deterministic communication system is provided, which communication system includes a physical data bus, a plurality of nodes connected thereto, and an arrangement for transmitting messages in message frames at fixedly predefined communication cycles. The device is situated in the data bus between at least one node, from whose point of view the operating state of the communication system is manipulated, and the other nodes of the communication system. To make any desired manipulation of the operating state of the communication system possible, the manipulation device includes an arrangement for short-circuiting the data bus ( | 2010-09-23 |
20100241777 | Power efficient interrupt detection - Interrupt request detection circuitry is disclosed for detecting and outputting interrupt requests to a processor. The interrupt request detection circuitry comprises: an interrupt signal input for receiving an interrupt signal; an input for receiving a signal from the processor indicating whether the processor is currently processing an interrupt; a detection circuit for detecting an interrupt request and outputting an interrupt request signal to a data processing apparatus; disabling logic for disabling at least a portion of the detection circuitry; wherein in response to detecting the processor is currently processing an interrupt; the detection circuit is configured to detect a change in value of the interrupt signal caused by assertion of the interrupt signal indicating an interrupt request and to output an interrupt request signal to output circuitry in response to detecting the interrupt signal assertion; and in response to detecting the processor is not currently processing an interrupt; the disabling logic is configured to disable at least a portion of the detection circuit; and the detection circuit with the at least a portion disabled, is configured to output the interrupt signal as the interrupt request signal to the output circuitry. | 2010-09-23 |
20100241778 | INTERRUPT CONTROL APPARATUS AND IMAGE FORMING APPARATUS - An interrupt control apparatus includes: an interrupt request supply unit that supplies interrupt request information; a processing unit that performs interrupt processing based on the interrupt request information supplied by the interrupt request supply unit; and a time measuring unit that is used to measure an elapse of a predefined time period from a time point when the interrupt request supply unit starts to supply the interrupt request information, wherein: even if new interrupt cause information is stored during the time when the time measuring unit is measuring the elapse of the predefined time period, the interrupt request supply unit does not supply interrupt request information based on the new interrupt cause information to the processing unit; and after the elapsed time measured by the time measuring unit reaches the predefined time period, the interrupt request supply unit supplies the interrupt request information to the processing unit. | 2010-09-23 |
20100241779 | ALLEVIATING BLOCKING CASES IN A SAS SWITCH - A first SAS expander including at least two phys is operably coupled to a first and a second SAS wide port. A second SAS expander including at least two phys is operably coupled to the first and the second SAS wide port. The first and the second SAS wide port each include at least two lanes, one of each at least two lanes designateable as a connection request lane. The connection request lane of each SAS wide port is operably coupled to a different SAS expander. | 2010-09-23 |
20100241780 | Spin-bus for information transfer in quantum computing - A spin bus quantum computing architecture includes a spin bus formed of multiple strongly coupled and always on qubits that define a string of spin qubits. A plurality of information bearing qubits are disposed adjacent a qubit of the spin bus. Electrodes are formed to the information bearing qubits and the spin bus qubits to allow control of the establishment and breaking of coupling between qubits to allow control of the establishment and breaking of coupling between each information bearing qubit and the spin bus qubit adjacent to it. The spin bus architecture allows rapid and reliable long-range coupling of qubits. | 2010-09-23 |
20100241781 | Bus Enumeration in a System with Multiple Buses - Enumerating an expanded bus system in a system. The expanded bus system may include a first bus, a bridge coupled to the first bus, and a second bus coupled to the bridge, where the second bus includes one or more downstream bus ports. One or more of the downstream bus ports may initially be masked. An initial bus enumeration may be performed during system boot, which may not include enumerating the masked bus ports. After the initial bus enumeration, the masked bus ports may be unmasked. An operating system may re-enumerate the bus system, which may include enumerating the no-longer-masked bus ports. | 2010-09-23 |
20100241782 | MEMORY ACCESS CONTROLLER, SYSTEMS, AND METHODS FOR OPTIMIZING MEMORY ACCESS TIMES - A configurable memory access controller and related systems and methods. In embodiments described herein, the configurable memory controller is adapted to provide a separate memory access configuration for each of a plurality of memory banks in a given memory system. The memory access configuration provided for each memory bank can either be to leave open or close at least one memory page in each memory bank. In this manner, a memory access configuration can be provided for each memory bank on an individualized basis to optimize memory access times based on the type of data activity in each memory bank. In embodiments described herein, the memory controller can also be configured to allow for dynamic configuration of one or more memory banks. Dynamic configuration involves changing or overriding the memory access configuration for a particular memory bank to optimize memory access times. | 2010-09-23 |
20100241783 | MEMORY NODE FOR USE WITHIN A DATA STORAGE SYSTEM HAVING A PLURALITY OF INTERCONNECTED MEMORY NODES - A memory node for use within a data storage system having a plurality of interconnected memory nodes is provided. The memory node comprises three data input interfaces, three data output interfaces, a memory module for storing data, and a controller coupled to the three data output interfaces, the three data input interfaces, and the memory module. The controller is configured to receive data via one of the three input interfaces, the data having a predetermined destination, read a first portion of the data to determine if the memory node is the predetermined destination, store a second portion of the data on the memory module, if the memory node is the predetermined destination, and transmit the received data via at least one of the three data output interfaces, if the memory node is not the predetermined destination. | 2010-09-23 |
20100241784 | System and method for storing data in a virtualized high speed memory system - A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict. | 2010-09-23 |
20100241785 | MANAGEMENT OF HOST PHYSICAL MEMORY ALLOCATION TO VIRTUAL MACHINES WITH A BALLOON APPLICATION - Methods and systems for managing distribution of host physical memory (HPM) among virtual machines (VMs) executing on a host via a hypervisor are presented, where each VM has guest system software including an operating system. A method includes an operation for reserving, by a balloon application executing in a first VM, a guest virtual memory (GVM) location in the first VM. The GVM location is mapped to a guest physical memory (GPM) location, which is mapped to a host physical memory (HPM) location. The balloon application is responsive to the hypervisor for reserving memory. Further, the method includes operations for writing a value to the reserved GVM location and for remapping a plurality of GPM locations containing the value to a single HPM location. The remapping is performed by a content-based page sharing component of the hypervisor. Additionally, the method reclaims the HPM location when the HPM location is freed due to the remapping, and assigns the reclaimed HPM location to a different VM or to a pool of available HPM locations. | 2010-09-23 |
20100241786 | Apparatus and method for optimized NAND flash memory management for devices with limited resources - An apparatus and method for managing memory in low-end electronic devices is provided. The apparatus includes a memory management unit. The memory management unit configured to allocate a portion of random access memory and a portion of flash memory as swap areas. The memory management unit performs swapping operations by swapping pages of content between the random access memory swap area and one or more blocks of the flash memory swap area. Thereafter, a page of content can be loaded from the flash memory swap area. The memory management unit also allocates a portion of flash memory as a garbage collection area. The memory management unit transfers dirty pages from the flash swap area to the garbage collection unit to free up flash memory swap area blocks. | 2010-09-23 |
20100241787 | SENSOR PROTECTION USING A NON-VOLATILE MEMORY CELL - A method and apparatus for protecting an electrical device using a non-volatile memory cell, such as an STRAM or RRAM memory cell. In some embodiments, a memory element is connected in parallel with a sensor element, where the memory element is configured to be repetitively reprogrammable between a high resistance state and a low resistance state. The memory element is programmed to the low resistance state when the sensor element is in a non-operational state and reprogrammed to the high resistance state when the sensor element is in an operational state. | 2010-09-23 |
20100241788 | FLASH MEMORY WRITING MTHEOD AND STROAGE SYSTEM AND CONTROLLER USING THE SAME - A flash memory writing method for writing data into a flash memory storage system is provided. In the present method, a big data usage number and a small data usage number are counted for each logical unit in the flash memory storage system, so as to respectively represent the numbers of writing a big data and a small data into each the logical unit. When a host system writes new data into a logical unit in the flash memory storage system, the new data is written through different writing processes according to the big data usage number and the small data usage number of the logical unit. Thereby, the data writing efficiency is improved and the lifespan of the flash memory storage system is prolonged. | 2010-09-23 |
20100241789 | DATA STORAGE METHOD FOR FLASH MEMORY AND DATA STORAGE SYSTEM USING THE SAME - A data storage method for a flash memory storage device is provided. The method includes disposing a pattern identification unit in the flash memory storage device and disposing a pattern analysis unit in a host connected to the flash memory storage device. The method further includes analyzing a usage pattern of each flash memory storage address in the flash memory storage device by using the pattern analysis unit, receiving information from the pattern analysis unit through the pattern identification unit to identify the usage pattern of each flash memory storage address, and storing data into each flash memory storage address through a corresponding process according to the usage pattern of the flash memory storage address. Thereby, data can be stored according to the usage pattern of each flash memory storage address, and accordingly the speed of storing data into the flash memory storage device can be effectively increased. | 2010-09-23 |
20100241790 | METHOD OF STORING DATA INTO FLASH MEMORY IN A DBMS-INDEPENDENT MANNER USING THE PAGE-DIFFERENTIAL - The present invention proposes an effective and efficient method of storing data called page-differential logging for flash-based storage systems. The primary characteristics of the invention are: (1) it writes only the page-differential that is defined as the difference between an original page in flash memory and an up-to-date page in memory; (2) it computes and writes the page-differential only when an updated page needs to be reflected into flash memory. When an updated page needs to be reflected into flash memory, the present invention stores the page into a base page and a differential page in flash memory. When a page is recreated from flash memory, it reads the base page and the differential page, and then, creates the page by merging the base page with its page-differential in the differential page. This invention significantly improves I/O performance of flash-based storage systems compared with existing page-based and log-based methods. | 2010-09-23 |
20100241791 | CONTROLLER WHICH CONTROLS OPERATION OF NONVOLATILE SEMICONDUCTOR MEMORY AND SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE SEMICONDUCTOR MEMORY AND CONTROLLER THEREFORE - A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder. | 2010-09-23 |
20100241792 | STORAGE DEVICE AND METHOD OF MANAGING A BUFFER MEMORY OF THE STORAGE DEVICE - A storage device including a processor to transmit N pages of data from one or more pages in a buffer memory where N is a natural number. The storage device also includes a flash memory to program in parallel the N pages of data to N flash chips. The N pages may be transmitted via one or more channels. | 2010-09-23 |
20100241793 | STORAGE SYSTEM AND METHOD FOR CONTROLLING STORAGE SYSTEM - The present invention efficiently uses the storage capacity in a storage system that has flash memory as a storage medium. | 2010-09-23 |
20100241794 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one aspect of the present invention includes: a memory cell array provided to perform programming in page units; and a control circuit provided to control the programming. The control circuit includes: means that performs a first detection for memory cells in a part provided as a unit smaller than a page, concurrently with programming to memory cells to be written in a page; and means that subjects the memory cells in the page to a second detection that takes into consideration a failure relief due to a redundant region, when the number of memory cells of unwritten state in the part as detected by the first detection becomes equal to or less than a first constant, and that ends the program operation when the number of memory cells of unwritten state in the page becomes equal to or less than a second constant. | 2010-09-23 |
20100241795 | NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM - A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device. | 2010-09-23 |
20100241796 | MEMORY SYSTEM PROTECTED FROM ERRORS DUE TO READ DISTURBANCE AND READING METHOD THEREOF - A method of reading a memory system including a flash memory includes: reading data from a page in a first block of the flash memory, incrementing a counter each time data is read from the page to store a corresponding number of read-out cycles of the flash memory, and copying data from the first block of the flash memory to a second block of the flash memory when the counter exceeds a reference number of read-out cycles. The data from the first block includes data from the page. | 2010-09-23 |
20100241797 | STORAGE DEVICE AND STORING METHOD - To enable a capacity of an entire storage device to be kept by adding a flash drive or a flash module in the flash drive for a flash memory that has a failure, even if the storage device using the flash memory has a failure in its part such as a part of flash memory chip has a failure, for example, the flash memory chip has run out of its lifetime. In a storage device equipped with two or more memory device units with a plurality of semiconductor memory devices, each of which has a functional capacity unit smaller than a capacity of an entire semiconductor memory device and has a writing lifetime for each functional capacity unit, only a functional capacity unit whose writing lifetime is run out to be determined as unable to be written is substituted by a functional capacity unit in a memory device of the other memory device unit to keep a predetermined capacity of the entire device. | 2010-09-23 |
20100241798 | ROBUST INDEX STORAGE FOR NON-VOLATILE MEMORY - A non-volatile memory data address translation scheme is described that utilizes a hierarchal address translation system that is stored in the non-volatile memory itself. Embodiments of the present invention utilize a hierarchal address data and translation system wherein the address translation data entries are stored in one or more data structures/tables in the hierarchy, one or more of which can be updated in-place multiple times without having to overwrite data. This hierarchal address translation data structure and multiple update of data entries in the individual tables/data structures allow the hierarchal address translation data structure to be efficiently stored in a non-volatile memory array without markedly inducing write fatigue or adversely affecting the lifetime of the part. The hierarchal address translation of embodiments of the present invention also allow for an address translation layer that does not have to be resident in system RAM for operation. | 2010-09-23 |
20100241799 | MODULAR MASS STORAGE SYSGTEM AND METHOD THEREFOR - A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors. | 2010-09-23 |
20100241800 | SYSTEM AND METHOD FOR PROVIDING A VIRTUAL MEMORY ARCHITECTURE NARROWER AND DEEPER THAN A PHYSICAL MEMORY ARCHITECTURE - Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word. | 2010-09-23 |
20100241801 | METHOD FOR BACKING UP DATA OF A SERVER MACHINE - A method for backing up data of a server machine is provided. The server machine owns an operating system in which a kernel layer and an application layer are defined. When the application layer requests a backup agent at the kernel layer to back up data in the server machine to another server machine, the backup agent first requests the kernel layer to duplicate the data and put the data to a buffer at the kernel layer, and thereafter the backup agent requests the kernel layer to directly read the data from the buffer and transmit the data to the another server machine without being required to send the data back to the application layer. | 2010-09-23 |
20100241802 | STORAGE UNIT, DATA WRITE METHOD AND DATA WRITE PROGRAM - A storage unit includes a cache memory, a cache controller which accesses the cache memory, one or more disk units, a data receiving unit, a merge interpolation determination unit, a data readout unit, a write data generation unit and a data write unit. The data receiving unit receives, from the cache controller, unit readout data that includes update records updated by the cache controller and is unit of data read from the cache memory. The merge interpolation determination unit determines whether the received unit readout data is merge interpolated. The data readout unit reads, from the disk unit, data corresponding to the unit readout data when the unit readout data is determined to be merge interpolated. The write data generation unit generates data to be written to the disk unit by merge interpolating the unit readout data. The data write unit writes, to the disk unit, the generated data. | 2010-09-23 |
20100241803 | GLOBAL SPARE - A storage library is described including a first tape drive that is identified as a target tape drive to a host via a first address and a second tape drive that is masked from being identified by the host. The storage library further includes a controller that is linked with a switch system that shifts the first address to the second drive from the first drive such that after the shift, the second drive is identified as the target drive to the host and the first drive is masked from being identified by the host. | 2010-09-23 |
20100241804 | METHOD AND SYSTEM FOR FAST RETRIEVAL OF RANDOM UNIVERSALLY UNIQUE IDENTIFIERS THROUGH CACHING AND PARALLEL REGENERATION - In general, the invention relates to a system that includes a UUID cache and a UUID caching mechanism. The UUID caching mechanism is configured to, using a first thread, monitor the number of UUIDs stored in the UUID cache, determine that the number of UUIDs stored in the UUID cache is less than a first threshold, request a first set of UUIDs from a UUID generator, receive the first set of UUIDs from the UUID generator, and store the first set of UUIDs received from the UUID generator in the UUID cache. The UUID caching mechanism is further configured to provide a second set of UUIDs to a first application using a second thread, where at least one of the UUIDs in the second set of UUIDs is from the first set of UUIDs, and where the first thread and the second thread execute concurrently. | 2010-09-23 |
20100241805 | IMAGE FORMING APPARATUS, AND CONTROL METHOD AND PROGRAM THEREOF - An object attribute is determined with respect to an object and a determination is performed as to whether or not to execute image cache processing in response to the object attribute. By switching processing in accordance with this, execution of time-consuming image specifying processing is kept to a necessary minimum and performance reductions can be avoided. Furthermore, cache registration is avoided for images having low reusability, which achieves improvements in cache usage efficiency and improvements in cache search efficiency, thereby enabling performance to be improved. | 2010-09-23 |
20100241806 | DATA BACKUP METHOD AND INFORMATION PROCESSING APPARATUS - An information processing apparatus includes, a first storage unit, a second storage unit in which data stored in the first storage unit is backed up, and a memory controller that controls data backup operation. The memory controller divides a transfer source storage area into portions, and provides two transfer destination areas, each of the two transfer destination areas being divided into portions, backs up data in a direction from a beginning address of each divided area of the transfer source storage area to an end address thereof in one of the transfer destination areas provided for each divided area of the transfer source storage area, and backs up data in a direction from the end address of each divided area of the transfer source storage area to the beginning address thereof in the other transfer destination storage area. | 2010-09-23 |
20100241807 | VIRTUALIZED DATA STORAGE SYSTEM CACHE MANAGEMENT - Virtual storage arrays consolidate branch data storage at data centers connected via wide area networks. Virtual storage arrays appear to storage clients as local data storage; however, virtual storage arrays actually store data at the data center. The virtual storage arrays overcomes bandwidth and latency limitations of the wide area network by predicting and prefetching storage blocks, which are then cached at the branch location. Virtual storage arrays leverage an understanding of the semantics and structure of high-level data structures associated with storage blocks to predict which storage blocks are likely to be requested by a storage client in the near future. Virtual storage arrays determine the association between requested storage blocks and corresponding high-level data structure entities to predict additional high-level data structure entities that are likely to be accessed. From this, the virtual storage array identifies the additional storage blocks for prefetching. | 2010-09-23 |
20100241808 | CACHE-LINE AWARE COLLECTION FOR RUNTIME ENVIRONMENTS - Target data is allocated into caches of a shared-memory multiprocessor system during a runtime environment. The target data includes a plurality of data items that are allocated onto separate cache lines. Each data item is allocated on a separate cache line regardless of the size of the cache line of the system. The data items become members of a wrapper types when data items are value types. The runtime environment maintains a set of wrapper types of various sizes that are of typical cache line sizes. Garbage data is inserted into the cache line in cases where data items are reference types and data is stored on a managed heap. The allocation also configures garbage collectors in the runtime environment not to slide multiple data items onto the same cache line. Other examples are included where a developer can augment the runtime environment to be aware of cache line sizes. | 2010-09-23 |
20100241809 | PROCESSOR, SERVER SYSTEM, AND METHOD FOR ADDING A PROCESSOR - A processor according to an exemplary of the invention includes a first initialization unit which reads a first program for checking a reliability of the processor into a cache memory and executes the first program when the processor is started up, and a second initialization unit which reads a second program for checking a reliability of the cache memory into a predetermined memory area and executes the second program when the second initialization unit receives a notification indicating the completion of the establishment of a communication path between the predetermined memory area and the processor from another processor which exists in a partition in which the processor is added. | 2010-09-23 |
20100241810 | Method and System for Dynamic Distributed Data Caching - A method and system for dynamic distributed data caching is presented. The method includes providing a cache community ( | 2010-09-23 |
20100241811 | Multiprocessor Cache Prefetch With Off-Chip Bandwidth Allocation - Technologies are generally described for allocating available prefetch bandwidth among processor cores in a multiprocessor computing system. The prefetch bandwidth associated with an off-chip memory interface of the multiprocessor may be determined, partitioned, and allocated across multiple processor cores. | 2010-09-23 |
20100241812 | DATA PROCESSING SYSTEM WITH A PLURALITY OF PROCESSORS, CACHE CIRCUITS AND A SHARED MEMORY - Data from a shared memory ( | 2010-09-23 |
20100241813 | Data subscribe-and-publish mechanisms and methods for producer-consumer pre-fetch communications - A system supporting producer-consumer pre-fetch communications includes a first processor, wherein the first processor is a producer node, and a second processor, wherein the second processor is a consumer node. The system further includes a data subscribe mechanism for performing a data subscribe operation at the consumer node, wherein the data subscribe operation records that a memory address is subscribed at the consumer node, a data publish mechanism for performing a data publish operation at the producer nod; wherein the data publish operation sends data of the memory address from the producer node to the consumer node if the memory address is subscribed at the consumer node, and a communication network coupled to the producer node and the consumer node for enabling communicating between the producer node and the consumer node. | 2010-09-23 |
20100241814 | BANDWIDTH-EFFICIENT DIRECTORY-BASED COHERENCE PROTOCOL - Some embodiments of the present invention provide a system that processes a request for a cache line in a multiprocessor system that supports a directory-based cache-coherence scheme. During operation, the system receives the request for the cache line from a requesting node at a home node, wherein the home node maintains directory information for all or a subset of the address space which includes the cache line. Next, the system performs an action at the home node, which causes a valid copy of the cache line to be sent to the requesting node. The system then completes processing of the request at the home node without waiting for an acknowledgment indicating that the requesting node received the valid copy of the cache line. | 2010-09-23 |
20100241815 | Hybrid Storage Device - In one embodiment, a hybrid storage device including a persistent memory, a volatile memory, a processor, a memory loader module that enables the processor to load a first set of information from the persistent memory device to the volatile memory device, to organize the first set of information according to a predetermined format, and a storage drive interface controller that enables the processor to receive information access requests from a host computer, to provide a second set of information from the volatile memory device to the host computer, and to provide a metadata descriptive of the first set of information to the host computer is disclosed. A host computer is enabled to access the first set of information using metadata provided by the storage drive interface controller without having the first set of information in a local memory of the host computer. The time required to access the first set of information is reduced by having the first set of information in volatile memory in the hybrid storage device. Other embodiments include, a system having a host computer and a hybrid storage device and methods using a hybrid storage device in a host computer. | 2010-09-23 |
20100241816 | OPTIMIZED TRANSFER OF PACKETS IN A RESOURCE CONSTRAINED OPERATING ENVIRONMENT - An apparatus includes first and second components, a memory, and an allocator configured to allocate a portion of the memory to the first component, wherein the first component is configured to access the allocated portion of the memory and to send information to the second component to provide the second component with access to the allocated portion of the memory. | 2010-09-23 |
20100241817 | STORAGE APPARATUS AND METHOD THEREOF - A storage system includes a plurality of storage devices connected together, where the plurality of storage devices include a copy-source storage device having data to be copied and copy-target storage devices capable of receiving the copied data. The copy-source storage device includes a copy-source controller for checking parameters contained in a buffer newly setting command to determine a group of storage devices to be subjected to a newly setting of a buffer and a copy-target storage device in the group and transmitting the parameters to the specified copy-target storage device. The copy-target storage device includes a copy-target controller for performing a buffer newly setting process in the specified copy-target storage device on the basis of the parameters received from the copy-source storage device and notifying the copy-source storage device of a result of the buffer newly setting process. | 2010-09-23 |
20100241818 | Reducing Storage System Power Consumption in a Remote Copy Configuration - A storage system in a remote copy configuration includes a redirect mechanism. The redirect mechanism determines whether to redirect read operations to a remote storage system, which is part of the remote copy configuration, based on a power management policy and a redirect policy. The redirect mechanism takes into account response time data, input/output demand, power utilization data, and input/output classes and priorities to determine whether to redirect read access requests to the remote storage system. Redirection of read operations to the remote storage system results in reduced power consumption at the local system. | 2010-09-23 |
20100241819 | CONTROLLER AND MEMORY SYSTEM - A controller includes a storage for a translation table showing logical and physical addresses in a flash memory in correspondence with one another; another storage storing FAT information indicating the state of data stored in each of pages contained in each of blocks and FAT information identifiers each identifying a block to which pages each storing therein the data in the state indicated by the FAT information belong, while keeping them in correspondence with one another; yet another storage for a block management table showing block identifiers, use-state judging information indicating whether the corresponding block is used/unused, and the FAT information identifiers corresponding to all the blocks indicated as being used by the use-state judging information, while keeping them in correspondence with one another; and a controller controlling unit managing data stored in the flash memory by using the translation table, the FAT information, and the block management table. | 2010-09-23 |
20100241820 | RECLAIMING STORAGE ON A THIN-PROVISIONING STORAGE DEVICE - A method, medium and apparatus for managing storage in a thin-provisioning storage device. The method includes ceasing to use storage on thinly provisioned storage delivered by a thin-provisioning storage device and notifying the thin-provisioning storage device of the unused storage. The method may further include reclaiming the unused storage in response to the notification. Alternatively, the notification may include recognizing the storage being freed and communicating the recognition to the storage device. In another form, the invention is a method, medium and apparatus for managing storage in a thin-provisioning storage device. This method includes delivering thinly provisioned storage and receiving notification that part of the thinly provisioned storage is no longer in use. The method may further include reclaiming that part of the thinly provisioned storage in response to the notification. Between receiving and reclaiming, the method may wait for a time to pass. | 2010-09-23 |
20100241821 | Inter operating system memory hotswap to support memory growth a non-virtualized system - Methods, systems, apparatuses and program products are disclosed for managing memory multiple OSes within a single computer and the like. | 2010-09-23 |
20100241822 | METHOD AND APPARATUS FOR MANAGING TLB - An apparatus and method for managing a translation look-aside buffer (TLB). The TLB is shared by a plurality of jobs. The method including the steps of: obtaining at least one attribute of each job of the plurality of jobs; assigning a priority level to each job according to at least one attribute of each job; and managing the related TLB entries of each job according to the priority level of each job. The present invention also provides an apparatus for managing TLB corresponding to the above method. The method and apparatus according to the present invention provide an efficient use of the shared TLB. | 2010-09-23 |
20100241823 | DATA PROCESSING DEVICE AND METHOD - A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed. | 2010-09-23 |
20100241824 | PROCESSING ARRAY DATA ON SIMD MULTI-CORE PROCESSOR ARCHITECTURES - Techniques are disclosed for converting data into a format tailored for efficient multidimensional fast Fourier transforms (FFTS) on single instruction, multiple data (SIMD) multi-core processor architectures. The technique includes converting data from a multidimensional array stored in a conventional row-major order into SIMD format. Converted data in SIMD format consists of a sequence of blocks, where each block interleaves s rows such that SIMD vector processors may operate on s rows simultaneously. As a result, the converted data in SIMD format enables smaller-sized 1D FFTs to be optimized in SIMD multi-core processor architectures. | 2010-09-23 |
20100241825 | Opportunistic Transmission Of Software State Information Within A Link Based Computing System - A method is described that involves determining that software state information of program code is to be made visible to a monitoring system. The method also involves initiating the writing of the software state information into a register. The method also involves waiting for the software state information to be placed onto a link within a link based computing system. | 2010-09-23 |
20100241826 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD AND PROGRAM - A data processing apparatus can reduce an occupancy rate of a ring bus by suppressing occurrence of a stall packet, and can change a processing sequence. In the data processing apparatus, a buffer is provided in each communication unit connecting the ring bus and the associated processing unit. Transfer of data from the communication unit to the processing unit is controlled by an enable signal. Consequently, occurrence of a stall packet is suppressed. Accordingly, frequency of occurrence of a deadlock state is reduced by decreasing the occupancy rate of the ring bus. | 2010-09-23 |
20100241827 | High Level Programming Extensions For Distributed Data Parallel Processing - General-purpose distributed data-parallel computing using high-level computing languages is described. Data parallel portions of a sequential program that is written by a developer in a high-level language are automatically translated into a distributed execution plan. A set of extensions to a sequential high-level computing language are provided to support distributed parallel computations and to facilitate generation and optimization of distributed execution plans. The extensions are fully integrated with the programming language, thereby enabling developers to write sequential language programs using known constructs while providing the ability to invoke the extensions to enable better generation and optimization of the execution plan for a distributed computing environment. | 2010-09-23 |
20100241828 | General Distributed Reduction For Data Parallel Computing - General-purpose distributed data-parallel computing using high-level computing languages is described. Data parallel portions of a sequential program written in a high-level language are automatically translated into a distributed execution plan. Map and reduction computations are automatically added to the plan. Patterns in the sequential program can be automatically identified to trigger map and reduction processing. Direct invocation of map and reduction processing is also provided. One or more portions of the reduce computation are pushed to the map stage and dynamic aggregation is inserted when possible. The system automatically identifies opportunities for partial reductions and aggregation, but also provides a set of extensions in a high-level computing language for the generation and optimization of the distributed execution plan. The extensions include annotations to declare functions suitable for these optimizations. | 2010-09-23 |
20100241829 | HARDWARE SWITCH AND DISTRIBUTED PROCESSING SYSTEM - A hardware switch to which a plurality of processing elements are connected, wherein for sending side processing elements and receiving side processing elements different from the sending side processing elements selected from among the plurality of processing elements, the hardware switch interconnects one output selected from outputs that the sending side processing elements have and one input selected from inputs that the receiving side processing elements have, thereby selectively switching paths between the plurality of processing elements, and at least one of the number of outputs of the sending side processing element connected to the hardware switch and the number of inputs of the receiving side processing elements connected to the hardware switch is more than one. | 2010-09-23 |
20100241830 | Transfer Triggered Microcontroller with Orthogonal Instruction Set - A microcontroller includes a program memory, data memory, central processing unit, at least one register module, a memory management unit, and a transport network. Instructions are executed in one clock cycle via an instruction word. The instruction word indicates the source module from which data is to be retrieved and the destination module to which data is to be stored. The address/data capability of an instruction word may be extended via a prefix module. If an operation is performed on the data, the source module or the destination module may perform the operation during the same clock cycle in which the data is transferred. | 2010-09-23 |
20100241831 | DATA PACKET PROCESSING METHOD FOR A MULTI CORE PROCESSOR - A method for processing a data packet in a network server system comprising at least one central processor unit (CPU) having a plurality of cores; and a network interface for forming a connection to a network between the network and a designated CPU core, such that for all data packets received from the network an interrupt is created in the designated CPU core for received data packet processing. Each data packet received from the network is associated with an application connection established in a CPU core selected based on processor load and an interrupt thread is created on the CPU core associated with the application connection for processing the data packet. Each data packet being sent to the network is associated with an application connected established either in the CPU core in which the application is executing or an alternative CPU core selected based on processor load. Where the application connection is established in an alternative CPU core, an interrupt thread is created on the CPU core associated with the connection for processing the data packet. | 2010-09-23 |
20100241832 | Instruction fetching following changes in program flow - This application is concerned with a device and method for fetching instructions from a data store for processing by a data processor. The device comprises: a register for storing an address of an instruction to be processed by said data processor; a fetch unit responsive to an address input to said fetch unit to fetch an instruction stored at said address; an adder for adding a predetermined amount to said address stored in said register prior to sending said address to said fetch unit, said predetermined amount determining a position in a program flow said fetched instruction has with respect to said instruction addressed in said register; said adder being responsive to detection of a change in program flow to reset said predetermined amount to an initial value, and to increase said predetermined amount for subsequent fetches by an amount equal to the separation between addresses such that consecutive addresses are fetched up to a maximum predetermined amount. | 2010-09-23 |
20100241833 | INFORMATION PROCESSING APPARATUS - Disclosed is an information processing apparatus in which various kinds of information are processed in either the real time processing mode or the non-real time processing mode. The apparatus includes an operation display section to accept an inputted instruction, an image processing section to apply a processing to image information and a processor provided with a plurality of same cores. The real-time processing unnecessary process that is related to the operation display section, is fixed onto one of the plurality of same cores so that the one of the plurality of same cores is in charge of controlling the real-time processing unnecessary process, while, the real-time processing necessary process that is related to the image processing section, is fixed onto another one of the plurality of same cores so that the other one of the plurality of same cores is in charge of controlling the real-time processing necessary process. | 2010-09-23 |
20100241834 | METHOD OF ENCODING USING INSTRUCTION FIELD OVERLOADING - The method selects registers by a register instruction field having x bits. A first group of registers has up to 2 | 2010-09-23 |
20100241835 | PROCESSOR WITH AUTOMATIC SCHEDULING OF OPERATIONS - A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A notation is made when an operand for an instruction is generated by another instruction. When operands for an instruction are available, that instruction is a “ready” instruction. A ready instruction is selected in each cycle and executed. To allow data to be transmitted between terminals, each terminal is provided with a receive station, such that data generated in one terminal may be transmitted to another terminal for use as an operand in that terminal. In one embodiment, one terminal is an arithmetic terminal, executing arithmetic operations such as addition, multiplication and division. The processor has a second terminal, which contains functional logic to execute all other instructions in the instruction set. The invention is useful for arithmetic intensive applications, such as graphic processors. | 2010-09-23 |
20100241836 | REMOTE CONFIGURATION OF COMPUTING PLATFORMS - An embodiment of the invention relates to a computing platform ( | 2010-09-23 |
20100241837 | COMPUTER WITH BOOTABLE RESTORATION - A bootable restoration computer includes: at least one mass storage device; at least two mass storage device partitions in the at least one mass storage device, including first and second partitions; a partition image restoration program; at least one partition image; at least one human interface device; a primary operating system with graphical user interface; a secondary operating system; and, a boot loader responsive to the human interface device that provides for selecting between the primary secondary operating systems. The primary operating system resides on the first partition and is configured so that its standard locations for storing user-created files are folders rooted on at least one of any partition other than the first partition. The at least one partition image is an image of the first partition, and resides on at least one of any partition other than the first partition. If no opportunity is taken to select the secondary operating system in a predefined time, the computer loads the primary operating system. If the opportunity is taken, the partition image restoration program restores the partition image to the first partition. | 2010-09-23 |
20100241838 | METHOD AND SYSTEM FOR FIRMWARE UPDATES - A method for updating computing device firmware may comprise: (a) receiving a transmission of firmware update data; (b) writing the firmware update data to a firmware update data partition; and (c) writing the firmware update data to an active firmware partition. | 2010-09-23 |
20100241839 | Loading operating systems using memory segmentation and ACPI based context switch - Methods, systems, apparatuses and program products are disclosed for managing multiple OSes within a single computer and the like. | 2010-09-23 |
20100241840 | SYSTEM AND METHOD FOR RESOURCE ASSIGNMENT - A resource assignment system includes a driver on an option ROM mounted on a PCI (Peripheral Components Interconnect) device, arranged on a memory by a BIOS (Basic Input/Output System), and configured to perform hardware resources assignment under a Pre-Boot environment; and an OS driver arranged on the memory by the BIOS, and configured to perform the hardware resource assignment under an OS environment. The BIOS includes a resource management table which shows a range of an I/O space to be assigned to a bridge device in a layer higher than that of the PCI device which requests the I/O space; and an ACPI table which is used to notify a hardware configuration and data to use an extended I/O space to the OS. The resource management table includes a Pre-Boot table in which assignment of a first granularity to a Legacy-I/O space for a Pre-Boot environment is defined; and an OS table in which assignment of a second granularity to the extended I/O space for an OS environment is defined. | 2010-09-23 |
20100241841 | System and Method for Securing Executable Code - A system and method for the secure storage of executable code and the secure movement of such code from memory to a processor. The method includes the storage of an encrypted version of the code. The code is then decrypted and decompressed as necessary, before re-encryption in storage. The re-encrypted executable code is then written to external memory. As a cache line of executable code is required, a fetch is performed but intercepted. In the interception, the cache line is decrypted. The plain text cache line is then stored in an instruction cache associated with a processor. | 2010-09-23 |
20100241842 | Method for Command Line Interface Restore Points with Support for an Atomic Sets of Commands - The present invention introduces methods for controlling and configuring systems using a new command line interface (CLI) command. The CLI command allows a user to set a save point or a restore point of the configuration (e.g., setsavepoint). After the CLI command is executed, the user can continue issuing configuration commands. In addition, if at some point the user wants to go back to the restore point, the user can issue an additional command which generates a CLI script containing all of the commands that need to be executed in order to modify the configuration such that it goes back to its state at the point at which the restore point was set. | 2010-09-23 |
20100241843 | SERVER SYSTEM, SECURITY IMPROVING METHOD OF SERVER AND COMPUTER PROGRAM OF THE SAME - A server system is provided in which it is possible to avoid an improper operation or malicious operation on, for example, a power switch of a server. In such a system, both a management server and multiple servers are connected to a network. Each multiple server includes: an authentication key storing portion which stores an authentication key; and a management module which compares between data inputted by operating the operation switches and the authentication key stored in the authentication key storing portion, wherein the management module sets the operation switches available if the input data and the authentication key are the same. The management module includes a function of writing the authentication key received from the management server into the authentication key storing portion. The management server includes a virtualized environment software which transmits the authentication key to each of the multiple servers via the network. | 2010-09-23 |
20100241844 | METHOD, SYSTEM AND APPARATUS FOR PROVIDING STATEFUL INFORMATION REDACTION | 2010-09-23 |
20100241845 | METHOD AND SYSTEM FOR THE CONFIDENTIAL RECORDING, MANAGEMENT AND DISTRIBUTION OF MEETINGS BY MEANS OF MULTIPLE ELECTRONIC DEVICES WITH REMOTE STORAGE - A specific method is provided for recording, management and confidential distribution of meetings by means of multiple electronic devices, fitted with at least one microphone, mainly a mobile phone, an electronic agenda, or laptop. The method includes recording the meeting, sending this recorded data to the remote server, audio track synchronization, selecting optimum track sections to produce an optimum final track, store this ciphered, coded track in the database, and, finally, publish this track in a confidential manner. | 2010-09-23 |
20100241846 | SYSTEM AND METHOD FOR ESTABLISHING A VIRTUAL PRIVATE NETWORK - A system and method for establishing a virtual private network (VPN) between a client and a private data communication network. An encrypted data communication session, such as a—Secure Sockets Layer (SSL) data communication session, is established between a gateway and the client over a public data communication network. The gateway then sends a programming component to the client for automatic installation and execution thereon. The programming component operates to intercept communications from client applications destined for resources on the private data communication network and to send the intercepted communications to the gateway via the encrypted data communication session instead of to the resources on the private data communication network. | 2010-09-23 |
20100241847 | ENCRYPTED EMAIL BASED UPON TRUSTED OVERLAYS - Sending and receiving encrypted emails. At a web browser, user input is received requesting a compose email page user interface for a web-based email system. The compose email page user interface is requested from a server for the web-based mail system. Web page code is received from the server for the compose email page user interface. The web page code for the compose email page user interface is parsed to determine screen locations of one or more user input interface elements. The compose email page user interface is rendered in the browser. One or more browser-based interface elements implemented integral to the browser are overlaid onto the compose email page user interface. User input is received in the browser user interface elements. The user input received is encrypted. The encrypted user input is transferred into one or more elements of the compose email page user interface. | 2010-09-23 |
20100241848 | SYSTEM AND METHOD FOR SECURELY COMMUNICATING WITH ELECTRONIC METERS - An infrastructure for securely communicating with electronic meters is described, which enables secure communication between a utility and a meter located at a customer, over a communication link or connection such as via a network. This enables messages to be sent from the utility to the meter and vice versa in a secure manner. The network provides a communication medium for communicating via the C12.22 protocol for secure metering. A cryptographic backend is used to cryptographically process messages to be sent to the meter and to similarly cryptographically process messages sent from the meter. By providing appropriate cryptographic measures such as key management, confidentiality and authentication, the meter can only interpret and process messages from a legitimate utility and the utility can ensure that the messages it receives are from a legitimate meter and contain legitimate information. | 2010-09-23 |
20100241849 | INTEROPERABLE SYSTEMS AND METHODS FOR PEER-TO-PEER SERVICE ORCHESTRATION - Systems and methods are described for performing policy-managed, peer-to-peer service orchestration in a manner that supports the formation of self-organizing service networks that enable rich media experiences. In one embodiment, services are distributed across peer-to-peer communicating nodes, and each node provides message routing and orchestration using a message pump and workflow collator. Distributed policy management of service interfaces helps to provide trust and security, supporting commercial exchange of value. Peer-to-peer messaging and workflow collation allow services to be dynamically created from a heterogeneous set of primitive services. The shared resources are services of many different types, using different service interface bindings beyond those typically supported in a web service deployments built on UDDI, SOAP, and WSDL. In a preferred embodiment, a media services framework is provided that enables nodes to find one another, interact, exchange value, and cooperate across tiers of networks from WANs to PANs. | 2010-09-23 |
20100241850 | HANDHELD MULTIPLE ROLE ELECTRONIC AUTHENTICATOR AND ITS SERVICE SYSTEM - The present invention provides a handheld electronic authenticator and its service system that provide multiple dynamic authentication codes for authenticating with multiple service providers. The authenticator provides multiple dynamic authentication codes (e.g., including electronic signatures) for the multiple service providers, using an algorithm, secret key and dynamic variables chosen and maintained by the service provider. | 2010-09-23 |
20100241851 | SYSTEM AND METHOD FOR VALIDATING CERTIFICATE ISSUANCE NOTIFICATION MESSAGES - To validate a received certificate issuance notification message, a device may verify that the certificate issuance notification message conforms to expected norms or authenticate a signature associate with the certificate issuance notification message. Upon validating, the device may then transmit a uniform resource locator, extracted from the certificate issuance notification message, to a network entity configured for processing certificate issuance. | 2010-09-23 |
20100241852 | Methods for Producing Products with Certificates and Keys - The embodiments described herein provide methods for producing products with certificates and keys. In one embodiment, a requesting entity transmits a request for a plurality of certificates and corresponding keys to a certifying entity that generates the certificates and corresponding keys. The request preferably includes information for use by the certifying entity to verify an identity of the requesting entity rather than information to verify unique product identifiers of the respective products. The requesting entity then receives the plurality of certificates and corresponding keys from the certifying entity, preferably in a plurality of organized sets instead of in a single series of certificates. The requesting entity then stores the certificates and corresponding keys in respective products. Each stored certificate is thereafter useable for both identification and authentication of the respective product in which it is stored. | 2010-09-23 |
20100241853 | SYSTEM AND METHOD FOR GENERATING A PLAINTEXT / CYPHERTEXT DATABASE FOR USE IN DEVICE AUTHENTICATION - Plaintext/cyphertext pairs are generated for use in authenticating a device. The device performs a secure authentication algorithm on a secure authentication image file and a received plaintext challenge, and outputs a cyphertext response. If the cyphertext response matches a pre-stored cyphertext string associated with the plaintext challenge, then the device is authenticated. A master processor manages the generation of the plaintext/cyphertext pairs. Plaintext challenges are generated in the master processor using a binary counter and an n-bit key. Each plaintext challenge is transmitted to a first processor and a second processor. The first processor executes the secure authentication algorithm on each plaintext challenge and outputs a cyphertext response associated with each plaintext challenge. The second processor executes the secure authentication algorithm on each plaintext challenge and outputs a second cyphertext response associated with each plaintext challenge. The master processor receives the first and second cyphertext responses for each plaintext challenge. If the first cyphertext response matches the second cyphertext response, then the master processor stores each plaintext challenge and the associated cyphertext response as a vector pair in a database. | 2010-09-23 |
20100241854 | Method and apparatus for low-power ap-assisted fast wireless roaming using optimized neighbor graphs - An embodiment of the present invention provides a method, comprising using optimized neighbor graphs for low-power access point assisted fast wireless roaming by a wireless station (STA) operating in a wireless network. | 2010-09-23 |
20100241855 | Systems and Methods for Secure Execution of Code Using a Hardware Protection Module - Systems and methods for securely executing digital rights management software comprising content code are described. One method comprises receiving encrypted multimedia content and content code from a storage medium by a host processor, wherein the content code provides restricted content distribution by examining an environment in which a player application resides. Based on functions defined within the content code, the host processor partitions the content code into portions. Based on whether the functions corresponding to the portions are related to computations involving confidential data, commands and parameters related to the portions of the content code are generated and forwarded to a secure processor for decrypting the encrypted multimedia content. | 2010-09-23 |
20100241856 | COMMUNICATION DEVICES AND METHODS - A communication device, method and network are provided. The communication method comprises generating a first registration packet including first bio data, sending the first registration packet to a network, generating a content packet having second bio data and content data and sending the content packet to the network. The other communication method comprises receiving a first registration packet including first bio data, storing the first bio data together with a device identification, receiving a content packet including second bio data, extracting the second bio data from the content packet, comparing the first bio data with the second bio data and authorizing communication when the first bio data matches the second bio data. | 2010-09-23 |
20100241857 | AUTHENTICATION METHOD, AUTHENTICATION SYSTEM, IN-VEHICLE DEVICE, AND AUTHENTICATION APPARATUS - An authentication system is configured such that: an in-vehicle device generates an authentication key, and displays on a display unit, a two-dimensional code including the generated authentication key and a URL indicating a predetermined WEB page on a network; and a portable terminal device acquires the authentication key and the URL from the two-dimensional code by reading the two-dimensional code via an imaging unit, downloads a communication program for communicating with the in-vehicle device from the WEB page indicated by the URL, and transmits the authentication key to the in-vehicle device by causing the downloaded communication program to operate. | 2010-09-23 |
20100241858 | Downloadable Conditional Access System, Secure Micro, and Transport Processor, and Security Authentication Method Using the Same - A downloadable conditional access system (DCAS), a secure micro (SM), and a transport processor (TP), and a security authentication method using the same are provided. The DCAS provides a safe security environment through a security protocol which enables mutual authentication and secure channel establishment between the SM and the TP. | 2010-09-23 |
20100241859 | Mode of information transmission and complex protection - The mode is intended for application in simplex and duplex channels of arbitrary including low, quality with implementation of tasks for complex protection of information. | 2010-09-23 |
20100241860 | KEY-UPDATING METHOD, ENCRYPTION PROCESSING METHOD, KEY-INSULATED CRYPTOSYSTEM AND TERMINAL DEVICE - In a key-insulated cryptosystem according to the present invention, a plurality of external devices are associated with a number of updates of a terminal secret key which has already been updated, and a different piece of secret information is stored in each of the external devices. In addition, a key-updating method in the key-insulated cryptosystem according to the present invention includes steps of: selecting one of the external devices depending on the number of updates of the terminal secret key; and causing the selected external device to generate key-updating information used for updating the terminal secret key based on the number of updates and the stored secret information. | 2010-09-23 |
20100241861 | DHCP CLIENT SERVER SYSTEM, DHCP CLIENT DEVICE AND DHCP SERVER DEVICE - A conventional DHCP authentication method could not cope with a one-phase two-messages DHCP sequence involved in a Rapid-Commit option. Further, in the conventional DHCP authentication method, it is possible to replay attack at lease renewal timing and, when information used in a retransmission method between a client and a server becomes the loss of synchronization, the conventional DHCP authentication method cannot detect the loss of synchronization and has such a problem that unnecessary traffics are continuously produced. A DHCP client device includes a means that stores a user ID, a secret key, and retransmission detection method (RDM) information. A DHCP server device includes a database that is available for the retrieval of a secret key and RMD information based on a user ID as a key or an access mechanism to an external DB with the same function as that of the database. | 2010-09-23 |
20100241862 | MULTIDIMENSIONAL IDENTIFICATION, AUTHENTICATION, AUTHORIZATION AND KEY DISTRIBUTION SYSTEM FOR PATIENT MONITORING - A method, wireless system and a wireless device are described. The method, system and device provide multidimensional identification, authentication, authorization and key distribution providing secure communications at a deepest common security domain. | 2010-09-23 |
20100241863 | DEVICE FOR REPRODUCING DIGITAL CONTENT, SECURE ELECTRONIC ENTITY, SYSTEM COMPRISING SAID ELEMENTS AND METHOD FOR REPRODUCING DIGITAL CONTENT - The invention concerns a method for reproducing digital content including the following steps: receiving (E | 2010-09-23 |