38th week of 2010 patent applcation highlights part 20 |
Patent application number | Title | Published |
20100237861 | Method for mapping of the radio frequency field amplitude in a magnetic resonance imaging system using adiabatic excitation pulses - A method for determining the spatial distribution of the magnitude of the radio frequency transmission field B1 in a magnetic resonance imaging apparatus, wherein the method comprises performing an MRI experiment in which a B1-sensitive complex image (SI) of a sample is obtained, wherein the phase distribution within the B1-sensitive complex image (SI) depends on the spatial distribution of the magnitude of the field B1. For establishing the dependency of the phase distribution within the B1-sensitive complex image (SI) on the spatial distribution of the field B1, one or more adiabatic RF pulses are applied. The method provides a simple procedure for mapping the B1 field of a magnetic resonance imaging apparatus with an improved accuracy and a wider measurement range. | 2010-09-23 |
20100237862 | Mitigating Off-Resonance Angle In Steady-State Coherent Imaging - Systems, methods, and other embodiments associated with mitigating off-resonance angle in steady-state coherent magnetic resonance imaging (MRI) are described. One example method includes accessing a B0 map and a coil sensitivity profile associated with an MRI apparatus configured to produce a steady-state coherent MRI sequence to image an object. The MRI apparatus is configured with a multi-channel transmission array having individually controllable transmission channels. The method includes computing transmission control parameters for individual transmission channels as a function of the B0 map and the coil sensitivity profile. The transmission control parameters are configured to facilitate controlling the transmission array to create a spatially varying phase profile using a single dimensional radio frequency (RF) pulse. | 2010-09-23 |
20100237863 | METHOD AND DEVICE FOR CONTROLLING ACQUISITION OF MAGNETIC RESONANCE DATA IN A MAGNETIC RESONANCE APPARATUS - In a method and a device to control the workflow of an MR measurement in a magnetic resonance system, a predetermined volume segment is subdivided into parallel slices with a predetermined slice interval and measured with a continuous table feed. Apart from a start phase and an end phase of the MR measurement, multiple slices of the examination subject are excited and read out in every repetition of the underlying basic sequence, and these multiple slices are located in an active volume inside the magnetic resonance system. The number of slices excited and read out per repetition of the underlying basic sequence is selected automatically depending in particular on the parameters determining an image contrast and an image resolution, and thus cannot be freely set by a user of the magnetic resonance system. | 2010-09-23 |
20100237864 | MAGNETIC RESONANCE METHOD AND APPARATUS TO GENERATE AN IMAGE USING A PARALLEL ACQUISITION TECHNIQUE - In a magnetic resonance method and apparatus to generate images by a parallel acquisition technique an excitation pulse is radiated into an examination subject, and a first echo train is generated after the excitation pulse, wherein the first echo train densely scans a segment of k-space to be scanned for an acquisition of coil calibration data. Coil calibration data are acquired by means of the first echo train. The acquired coil calibration data are stored in a coil calibration data set. A second echo train is generated after the same excitation pulse, wherein the second echo train undersamples a segment of k-space to be scanned for an acquisition of image data. Image data are acquired by means of the second echo train. The acquired image data are stored in an incomplete image data set. An image data set is generated by substituting data missing in the incomplete image data set due to the undersampling by means of a selected PAT reconstruction technique using the coil calibration data. | 2010-09-23 |
20100237865 | MAGNETIC RESONANCE METHOD AND APPARATUS TO GENERATE AN IMAGE USING A PARALLEL ACQUISITION TECHNIQUE - In a magnetic resonance a method and apparatus to generate images by a parallel acquisition technique, a first echo train is generated after a first excitation pulse, wherein the first echo train sufficiently densely scans a segment of k-space to be scanned for an acquisition of coil calibration data. Coil calibration data are acquired by means of the first echo train after the first excitation pulse. The acquired coil calibration data are stored in a coil calibration data set. A second echo train is generated after a second excitation pulse, wherein the second echo train undersamples a segment of k-space to be scanned for an acquisition of image data. Image data are acquired by means of the second echo train after the second excitation pulse. The acquired image data are stored in an incomplete image data set. An image data set is generated by substituting data missing in the incomplete image data set due to the undersampling by means of a selected PAT reconstruction technique using the coil calibration data. The first echo train and the second echo train are generated by an identical sequence technique such that each echo train has a series of echoes, with a time interval of the echoes of a series of the first echo train being shorter than a time interval of the echoes of a series of the second echo train. | 2010-09-23 |
20100237866 | MAGNETIC RESONANCE CONTRAST USING FICTITIOUS FIELD RELAXATION - A system includes a signal generator and a processor. The signal generator is configured to couple with a magnetic resonance transmitter coil. The processor is configured to execute instructions to control the signal generator. The instructions include forming a sequence of waveforms. The sequence is configured to generate spin relaxation in a fictitious field in a third rotating frame of reference based on at least one magnetic field component that arises based on an effective field in a second rotating frame of reference. The third rotating frame of reference is of a higher order than the second rotating frame of reference and the second rotating frame of reference is of a higher order than the first rotating frame of reference. | 2010-09-23 |
20100237867 | Arrangements and Method for Shimming a Magnetic Field - A shim arrangement for increasing the homogeneity of a magnetic field within a homogeneous field region, comprising: shim channels extending within a volume between a magnetic field generator and the homogeneous field region; at least one piece of shim material located within each shim channel; an arrangement for moving each shim piece along the corresponding shim channel; and retaining means for retaining each shim piece in position. Shimming is performed by moving shim pieces within the shim channels, with the magnet at field. No shim pieces are added to, or removed from, the shim channels during the shimming step. | 2010-09-23 |
20100237868 | APPARATUS FOR LOW AC LOSS THERMAL SHIELDING AND METHOD OF MAKING SAME - A apparatus for low AC loss thermal shielding includes a plurality of thermally conducting fibers positioned along a desired direction of heat conduction. The fibers are electrically insulated from each other. The fibers are bonded together with a matrix, and a thermal link connects the bonded fibers to a cryogenic cold head. | 2010-09-23 |
20100237869 | Controlling Multi-Channel Transmitter Effects on Specific Absorption Rate - Systems, methods, and other embodiments associated with controlling the specific absorption rate (SAR) in a patient associated with a conductor are described. The conductor may be, for example, a wire associated with a pacemaker, a wire associated with a neurostimulator, an orthopaedic device, and so on. One example method includes calibrating a multi-channel transmitter associated with a magnetic resonance imaging (MRI) apparatus imaging the patient. The example method also includes controlling the MRI apparatus to transmit radio frequency (RF) energy to image the patient in a manner where the RF energy will only influence the SAR near the conductor in the patient less than a desired threshold amount. | 2010-09-23 |
20100237870 | Geophysical Prospecting Using Electric And Magnetic Components Of Natural Electromagnetic Fields - A geophysical survey system comprising: a first sensor system towed by an aircraft, having at least one airborne sensor for measuring electric components of a low frequency natural electromagnetic field in a survey area; a second sensor system for positioning at a fixed position on the ground during a survey, having at least two ground based induction coil sensors for measuring magnetic components of a low frequency natural electromagnetic field in or near the survey area, the ground based sensors each being oriented to sense the magnetic components in different directions; and a processing system for calculating a set of first vector values over time in dependence on the electric components measured through the first sensor system and calculating a set of second vector values over time in dependence on the magnetic components measured through the second sensor system and comparing one or more characteristics of the first vector values and the second vector values to identify geophysical information about the survey area. | 2010-09-23 |
20100237871 | Pipe Survey Method Using UWB Signal - A method of surveying the condition of an underground enclosure including the steps of (a) positioning at least one transmitter/receiver unit (including an antenna) within an underground, substantially nonconductive enclosure, such that a substantial air gap exists between the antenna and the inner wall of the enclosure; (b) transmitting an ultra wideband (UWB) signal toward at least a portion of the inner wall; and (c) processing the return signal in order to identify the interface between the soil and a region of conductivity different from the soil. | 2010-09-23 |
20100237872 | APPARATUS AND METHOD FOR SENSING LEAKAGE CURRENT OF BATTERY - An apparatus for sensing a leakage current of a battery comprises a floating capacitor charged with voltage detected from a cathode or anode terminal of a battery, a cathode terminal selection switching unit for selecting a voltage detection path for the cathode terminal and charging the floating capacitor with a detection voltage of the cathode terminal, an anode terminal selection switching unit for selecting a voltage detection path for the anode terminal and charging the floating capacitor with a detection voltage of the anode terminal, a DC voltage applying unit for applying DC voltage through the voltage detection path for the anode terminal, a voltage measuring unit for measuring the charged detection voltage of the cathode or anode terminal, and a leakage current determining unit for determining the occurrence of leakage current based on the measured detection voltages of the cathode and anode terminals. | 2010-09-23 |
20100237873 | CIRCUIT ARRANGEMENT HAVING A BATTERY CASCADE - In an electrical device, in which the load is supplied by a battery cascade, the voltages of the batteries of the battery cascade must be measured with high precision in order to start charge equalization and prevent undervoltages or overvoltages, wherein if possible favorable components should be used simultaneously. This problem is solved in that a circuit arrangement having a battery cascade is proposed, comprising a first battery (A | 2010-09-23 |
20100237874 | IONIZATION VACUUM GAUGE - An ionization vacuum gauge includes a cathode electrode, a gate electrode, and an ion collector. The cathode electrode includes a base and a field emission film disposed thereon. The gate electrode is disposed adjacent to the cathode electrode with a distance therebetween. The ion collector is disposed adjacent to the gate electrode with a distance therebetween. The field emission film of the cathode electrode includes carbon nanotubes, a low-melting-point glass, and conductive particles. | 2010-09-23 |
20100237875 | Unified brake and light tester - A portable diagnostic device for checking electrical signalling systems of for example tractors and their trailers. The device has several receptacles for connection to a corresponding receptacle or pin connector of a trailer. One electrical circuit includes switches for energizing individual signalling or other circuits of the trailer individually, and indicating lamps and/or horns for annunciating circuit operability. Another electrical circuit includes switches for energizing individual signalling or illumination circuits individually, and indicating lamps and/or horns for annunciating circuit operability. The device, which is contained on a wheeled stand, has its own power supply and circuit overcurrent protective devices, and is thus independent. | 2010-09-23 |
20100237876 | Method of Self Monitoring and Self Repair for a Semiconductor IC - A method for self repair of a semiconductor IC is presented. An IC state is set to test/repair mode upon powering up the IC. Fuse data is loaded from an e-fuse module. Defects or faults are detected by employing a built in self test (BIST) module. The IC self repairs using redundant circuitry by employing a built in self repair (BISR) module to repair each fault using redundant circuitry. The fault locations and repair locations are stored in the e-fuse module. The semiconductor IC state is changed to mission mode. | 2010-09-23 |
20100237877 | SYSTEM OPEN-CIRCUIT TESTING METHOD - A system open testing method is provided. Firstly, a system to be tested having at least an ESD protection unit, a signal input pad, a first voltage level end, and a second voltage level end is provided, wherein the first voltage level end and the second voltage level end are utilized for accessing electric power, the ESD protection unit has one end coupled to the signal input pad and the other end coupled to the first voltage level end. Afterward, a diode is connected to the signal input pad, and the conducting direction of the diode is opposite to that of the interior diode in the ESD circuit. Thereafter, a testing signal is send through the diode to the system. | 2010-09-23 |
20100237878 | LEAK CURRENT CALCULATION APPARATUS AND METHOD FOR CALCULATING LEAK CURRENT - A leak current calculation apparatus includes an acquiring section for acquiring partial circuit information, and a grouping section for forming a plurality of groups each comprising a part of the partial circuits connected with each other and for generating group information. The apparatus includes a leak difference value calculating section for calculating a leak difference value, which is a difference between a provisional maximum value acquired by adding up the maximum values of the leak current values of all the partial circuits and a sum of maximum values of the leak current values contained in the group information of the groups, and a maximum leak current calculating section for calculating the maximum leak current value of the integrated circuit by adjusting the provisional maximum value with the leak difference value. | 2010-09-23 |
20100237879 | METHOD AND APPARATUS FOR IMPROVING YIELD RATIO OF TESTING - A method and apparatus for improving yield ratio of testing are disclosed. The method includes the following steps. First of all, devices are tested and electromagnetic interference is measured. Next, the test results are examined for whether the devices pass the test or not. Then, electromagnetic interference data are examined for whether the electromagnetic interference data are over a predetermined standard if the devices fail the test. The above-mentioned steps are performed again if the electromagnetic interference data are over a predetermined standard. The test is terminated if the devices still fail the test and the values of electromagnetic interference are still over a predetermined standard. | 2010-09-23 |
20100237880 | Capacitive Sensors for Nano-Positioning and Methods of Using The Same - Symmetrical differential capacitive sensors are disclosed. Methods of making and using symmetrical differential capacitive sensors are also disclosed. | 2010-09-23 |
20100237881 | CALIBRATION METHOD FOR INERTIAL DRIVE ACTUATOR, AND INERTIAL DRIVE ACTUATOR DEVICE - A calibration method for inertial drive actuator of driving a target moving body among a plurality of moving bodies to move by inertia between a first movement limit position and a second movement limit position in relation to an oscillating plate that is moved to reciprocate by a moving member, and detecting positions of the moving bodies based on electrostatic capacitances includes detecting electrostatic capacitances of opposing parts of a moving body side electrode provided in a target moving body and an oscillating plate electrode provided in the oscillating plate is detected at the first movement limit position and the second movement limit position, respectively; and calculating a ratio of a difference between the electrostatic capacitances at the first movement limit position and the second movement limit position to a movement limit distance that is a distance between the first movement limit position and the second movement limit position. At least one of the first movement limit position and the second movement limit position is a position where the target moving body abuts against a non-target moving body. | 2010-09-23 |
20100237882 | SWITCHING CONFIGURATION FOR DETERMINING THE CAPACITANCE OF A CAPACITIVE SENSOR ELEMENT - A circuit arrangement for determining a capacitance of a capacitive sensor element (C | 2010-09-23 |
20100237883 | ELECTRICAL DETECTION AND QUANTIFICATION OF CESIUM DERIVATIVES - The invention relates to an apparatus and to a process for the detection and/or quantification of cesium ions Cs | 2010-09-23 |
20100237884 | INTEGRATED SWITCHLESS PROGRAMMABLE ATTENUATOR AND LOW NOISE AMPLIFIER - An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. | 2010-09-23 |
20100237885 | LABEL-FREE SENSOR - A label-free sensor is disclosed. The label-free sensor comprises a substrate, a first electrode formed on the substrate, a second electrode formed on the substrate and spaced away from the first electrode, and a semiconductor layer formed on the substrate and is in contact with the first electrode and the second electrode, wherein the semiconductor layer has a plurality of probe groups, which are bonded to the semiconductor layer by functionalization, for sensing a coupling-specific substance, which has bonding specificity with the probe groups. The semiconductor layer of the label-free sensor of the present invention is bonded with probe groups, and the detection of detected object is performed in instant, quick, rapid, and sensitive manner by measuring variation in electric current, thereby avoiding the use of the fluorescent reading equipment for reading fluorescent signals. | 2010-09-23 |
20100237886 | PROBE CARD - A probe card is provided. The probe card can serialize, analogise and divide a digital signal by a parallel-to-serial converter, a parallel-to-serial converter, and a power divided unit respectively. The probe card can increase signal channels, and is not restricted by signal channels of a tester to test more DUTs simultaneously. Moreover, the probe card has fine impedance matching and channels separating to raise testing efficiency and reduce signal loss. | 2010-09-23 |
20100237887 | MICROELECTRONIC CONTACTOR ASSEMBLY, STRUCTURES THEREOF, AND METHODS OF CONSTRUCTING SAME - A plurality of inserts are anchored in holes or recesses in a probe head. Shafts are coupled to the inserts, and adjustable multi-part fasteners are attached to the shafts and to a stiffener. The multi-part fasteners are operated to move the shafts and couple the probe head, the stiffener, and other components of a microelectronic contactor assembly. In some embodiments, the inserts may be anchored in the probe head using an adhesive. In some embodiments, the probe head may comprise more than one major substrate, and the inserts may be anchored in either of the substrates. | 2010-09-23 |
20100237888 | PROBE HEAD FOR A MICROELECTRONIC CONTACTOR ASSEMBLY, AND METHODS OF MAKING SAME - Microelectronic contactors on a probe contactor substrate, or adhesive elements on a probe contactor or space transformer substrate, are protected by a sacrificial material as 1) the microelectronic contactors or adhesive elements are planarized, or 2) a surface of the substrate on which the microelectronic contactors or adhesive elements are formed is planarized. The adhesive elements are used to bond the probe contactor substrate to the space transformer substrate. | 2010-09-23 |
20100237889 | PROBE HEAD FOR A MICROELECTRONIC CONTACTOR ASSEMBLY, THE PROBE HEAD HAVING SMT ELECTRONIC COMPONENTS THEREON - A probe head for a microelectronic contactor assembly includes a space transformer substrate and a probe contactor substrate. Surface mount technology (SMT) electronic components are positioned close to conductive elements on the probe contactor substrate by placing the SMT electronic components in cavities in the probe contactor substrate, which cavities may be through-hole or non-through-hole cavities. In some cases, the SMT electronic components may be placed on pedestal substrates. SMT electronic components may also be positioned between the probe contactor and space transformer substrates. | 2010-09-23 |
20100237890 | SYSTEM THAT MEASURES CHARACTERISTICS OF OUTPUT SIGNAL - A system including a first circuit and a second circuit. The first circuit includes analog components configured to receive an input signal and provide an output signal based on the input signal. The second circuit is configured to measure characteristics of the output signal to test the first circuit. At least one of the output signal and another output signal is fed back to provide the input signal and generate an oscillation in the output signal. | 2010-09-23 |
20100237891 | Method, apparatus and system of parallel IC test - A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones. | 2010-09-23 |
20100237892 | FLEXIBLE SUBSTRATE, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC DEVICE - A flexible substrate includes a substrate body; a plurality of lines that are arranged on the substrate body; a plurality of connection terminals that are arranged on an end portion of the substrate body and electrically connected to the respective lines; an integrated circuit that is arranged on the substrate body and electrically connected to at least one of the lines; and an inspection electrode that is arranged on the substrate body and electrically connected to the integrated circuit and capable of outputting a signal processed in the integrated circuit. | 2010-09-23 |
20100237893 | SEMICONDUCTOR TEST APPARATUS AND TEST METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor test apparatus comprising: a contact-resistance calculating unit that calculates contact resistance of a measuring jig using power supply current and internal voltage obtained when power supply voltage is applied; a regression-expression calculating unit that calculates a stationary time power supply current characteristic expression using the power supply current and the internal voltage obtained when the power supply voltage is applied; and a measurement-voltage calculating unit that calculates power supply voltage for a test using operating time power supply current information, which is a corresponding relation between operating time power supply current obtained when a plurality of types of power supply voltages are applied and the types of power supply voltages, the contact resistance, and the stationary time power supply current characteristic expression. | 2010-09-23 |
20100237894 | METHOD TO DETERMINE NEEDLE MARK AND PROGRAM THEREFOR - Disclosed is a method to determine a needle mark, which can more accurately determine whether marks formed on electrode pads of devices are probe needle marks, thereby significantly reducing misdetermination of the marks as the probe needle marks. The method includes giving scores, which are used to determine the quality of marks as probe needle marks, to marks formed on a plurality of electrode pads of a plurality of devices, and selecting, based on the scores, an object device including an object electrode pad with an indefinite mark formed thereon, and selecting four comparison devices preceding the object device and nine time-successive comparison devices following the object device at successive times along the test direction, and determining if the indefinite mark of the object device is good or bad as a probe needle mark, by comparing a value of the score given to the indefinite mark of the object device plus scores given to marks formed on the comparison devices' comparison electrode pads corresponding to the object electrode pad, with a reference value. | 2010-09-23 |
20100237895 | System and method for characterizing solar cell conversion performance and detecting defects in a solar cell - A system and method for characterizing the solar cell conversion performance and detecting a defect in a solar cell includes applying an optical test signal to the solar cell using the multiple-scanning method, measuring the solar cell photocurrent in response to the solar cell illumination by the multiple-scanning method, and detecting a defect and finding its location based on the characteristic mapping of solar cell photocurrent, which is obtained by the multiple-scanning method through the divisional control of light transmittance by the LVP (light valve panel). The defect may be a solar cell subsection which has abnormally low photocurrent below a critical value and can be caused by a short between the emitter and the base of solar cell. The LVP may be realized in any one of a variety of ways. For example, the LVP may be a flat-panel display such as AMLCD (Active-Matrix Liquid Crystal Display) and AMOLED (Active-Matrix Organic Light Emitting Diode). | 2010-09-23 |
20100237896 | LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - A liquid crystal display panel includes a first substrate, a second substrate, and a liquid crystal layer formed between the first substrate and the second substrate. A pixel area is formed on the first substrate, and a driver is formed on the substrate and electrically connected with the pixel area. A plurality of lines are electrically connected with the driver, and a plurality of pads are electrically connected with the plurality of lines. The plurality of pads are formed in a straight line and are not electrically connected with each other except for the electric connection with the plurality of lines. | 2010-09-23 |
20100237897 | OVERCURRENT DETECTING CIRCUIT AND POWER SUPPLY DEVICE - An overcurrent detecting circuit includes a comparison transistor, a constant current source circuit, and a comparison circuit. The comparison transistor includes a gate and a drain respectively connected to a gate and a drain of a main transistor provided in a power circuit. The comparison transistor is used for comparison with the main transistor when a voltage higher than a power supply voltage is applied to the gate of the main transistor and the gate of the comparison transistor during the operation of the power circuit. The constant current source circuit generates a constant current and supplies the constant current to the comparison transistor. The comparison circuit compares a source voltage of the comparison transistor with a source voltage of the main transistor and outputs a voltage indicating the comparison result. | 2010-09-23 |
20100237898 | OVERCURRENT DETECTING CIRCUIT AND POWER SUPPLY DEVICE - An overcurrent detecting circuit includes a comparison transistor, a constant current source circuit, a subtraction circuit, and a comparison circuit. The comparison transistor is used for comparison with a main transistor provided in the power circuit. The constant current source circuit supplies a constant current to the comparison transistor. The subtraction circuit subtracts a voltage corresponding to a power supply voltage from a voltage between a drain and a source of the comparison transistor and outputs a voltage indicating the subtraction result. The comparison circuit compares the voltage output from the subtraction circuit with a voltage corresponding to a source voltage of the main transistor and outputs a voltage indicating the comparison result. | 2010-09-23 |
20100237899 | Method and Apparatus for Ballistic Single Flux Quantum Logic - In one embodiment, the disclosure relates to a single flux quantum (SFQ) signal transmission line powered by an AC power source. The AC power source supplies power to a transformer having a primary winding and a secondary winding. The primary winding receives the AC signal and the secondary winding communicates the signal to the SFQ transmission line. The transmission line can optionally include an input filter circuit for receiving the incoming SFQ pulse. The filter circuit can have a resistor and an inductor connected in parallel. In an alternative arrangement, the filter circuit can comprise of an inductor. A first Josephson junction can be connected to the filter circuit and to the secondary winding. The Josephson junction triggers in response to the incoming SFQ pulse and regenerates a pulse signal in response to a power discharge from the secondary winding. | 2010-09-23 |
20100237900 | Semiconductor integrated circuit including a power controllable region - Provided is a semiconductor integrated circuit capable of testing power control operation in the semiconductor integrated circuit including a power controllable region. Power control switches have switch series each constituted by a plurality of switch cells. A power controllable region includes output nodes in the switch series. The output nodes output power control signals that have passed through final stages of the respective switch series of the power control switches to the outside of the power controllable region. A chip on which the semiconductor integrated circuit is mounted has output terminals that output outputs of the output nodes to the outside of the chip. In the case of inserting a scan path test, observation flip-flops that load the outputs of the output nodes to data terminals, and load scan data to scan-in terminals are disposed in correspondence with the respective output nodes. Those observation flip-flops are connected to constitute a scan path chain. | 2010-09-23 |
20100237901 | SEMICONDUCTOR APPARATUS AND DATA OUTPUT METHOD OF THE SAME - A semiconductor apparatus includes a driving control unit configured to receive an enable signal and a data signal. The driving control unit generates a pull-up source signal and a pull-down source signal. The driving control unit is configured to delay the generation timing of the pull-up source signal or the pull-down source signal. The semiconductor apparatus also includes a driver configured to generate a driving data signal by driving the pull-up source signal and the pull-down source signal from the driving control unit. A POD impedance control unit is connected to the output terminal of the driver and has a variable resistance value. | 2010-09-23 |
20100237902 | SEMICONDUCTOR DEVICE CAPABLE OF TESTING A TRANSMISSION LINE FOR AN IMPEDANCE CALIBRATION CODE - A semiconductor device includes a plurality of pads, where an external reference resistor is connected to a first one of the pads, an impedance calibrating unit configured to generate an impedance calibration code corresponding to an impedance of the reference resistor and output the impedance calibration code to a code transmitting line during a normal operating mode, and an impedance matching unit configured to perform an impedance matching operation in response to the impedance calibration code during the normal operating mode. The impedance calibrating unit is configured to output a test code to the code transmitting line in response to a test signal during a test operating mode. The impedance matching unit is configured to serialize the test code to output the serialized test code to each of the other pads in response to the test signal during the test operating mode. | 2010-09-23 |
20100237903 | Configurable On-Die Termination - Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted. | 2010-09-23 |
20100237904 | High Performance Output Drivers and Anti-Reflection Circuits - Long existing performance, noise, and power consumption problems of known output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. On-die termination-circuit-branches provide effective anti-reflection functions for multiple chips connected to the same transmission line(s). | 2010-09-23 |
20100237905 | INPUT CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - An input circuit for receiving an input signal supplied to an input terminal includes a capacitor having one end connected to the input terminal and a capacitor driving circuit for converting the input signal into a signal having positive logic that is the same as logic of the input signal and supplying the converted signal to the other end of the capacitor so as to drive the capacitor. | 2010-09-23 |
20100237906 | RECEIVING CIRCUIT - A receiving circuit includes an impedance compensating circuit, a first input terminal and a second input terminal coupled to a first signal line and a second signal line, a first signal and a second signal corresponding to differential signals being transmitted at the first input terminal and the second input terminal, respectively, a signal input circuit, coupled to the first input terminal and the second input terminal, which receives the first signal and the second signal are input, and a differential-signal detector that detects whether or not the differential signals are supplied to the first input terminal and the second input terminal. | 2010-09-23 |
20100237907 | COMPARATOR WITH OFFSET COMPENSATION, IN PARTICULAR FOR ANALOG DIGITAL CONVERTERS - A comparator formed by first and second stages. The second stage is formed by a pair of output transistors connected between a power-supply line and respective output nodes; a pair of bias transistors, connected between a respective output node and a current source; a pair of memory elements, connected between the control terminals of the output transistors and opposite output nodes; and switches coupled between the control terminals of the respective output transistors and the respective output nodes. In an initial autozeroing step, the first stage stores its offset so as to generate an offset-free current signal. In a subsequent tracking step, the second stage receives the current signal and the memory elements store control voltages of the respective output transistors. In a subsequent evaluating step, the first stage is disconnected from the second stage and the memory elements receive the current signal and switch the first and the second output node depending on the current signal. In subsequent comparisons, the tracking and evaluating steps follow one another without performing the autozeroing step. | 2010-09-23 |
20100237908 | LOW CURRENT COMPARATOR WITH PROGRAMMABLE HYSTERESIS - A low current comparator with programmable hysteresis is disclosed that uses a ratio of latch intrinsic (internal) latch capacitance and capacitance of a sample capacitor to adjust hysteresis. In some implementations, the comparator includes a switch capacitor sampling stage coupled to a dynamic latch output stage. Depending on an output state ( | 2010-09-23 |
20100237909 | PHYSICAL QUANTITY DETECTION CIRCUIT AND PHYSICAL QUANTITY SENSOR DEVICE - A physical quantity detection circuit ( | 2010-09-23 |
20100237910 | High-Speed, Low-Power Driver System - A reduced power driver is described. This reduced power driver comprises: an input current driver for transmitting a current signal that is a fraction of a DC current signal; a first resistor coupled at one end to a first voltage supply; a first current driver coupled to the input current driver and a first switch control; a second switch coupled a first current driver output, another end of the first resistor, and the output control; a dynamic booster coupled between the first voltage supply and the output control; and wherein the reduced power driver is operative for selectively adding an overshoot current to the output control so that power consumption is reduced, while synchronizing the DC current signal with the overshoot current. | 2010-09-23 |
20100237911 | Drive Circuit For A Power Switch Component - A drive circuit for a power switch component. | 2010-09-23 |
20100237912 | RESET SIGNAL GENERATING CIRCUIT - A reset signal generating circuit for a processor includes a charging circuit, a discharging circuit, and a triggering circuit. The charging circuit receives timing pulse signals from the processor to supply charging current according to the timing pulse signals when the processor operates normally, and stops supplying the charging current when the processor is at fault. The discharging circuit buffers the charging current supplied by the charging circuit when the processor operates normally, and discharges a low voltage to the triggering circuit when the processor is at fault. The triggering circuit outputs a trigger signal to the processor when the triggering circuit detects the low voltage to reset the processor. | 2010-09-23 |
20100237913 | ELECTRONIC DEVICE - An electronic device includes a first reset signal generator arranged to output a first reset signal when a power supply voltage becomes lower than or equal to a first threshold, a second reset signal generator arranged to output a second reset signal when the power supply voltage becomes lower than or equal to a second threshold lower than the first threshold, a return reset signal generator arranged to output a return reset signal based on a termination of the output of the first reset signal, a first resetting device arranged to be reset based on the first reset signal, a second resetting device arranged to be reset based on the second reset signal and the return reset signal, and a pre-processor arranged in the second resetting device to start a preliminary process of resetting based on the first reset signal. | 2010-09-23 |
20100237914 | CLOCK DISTRIBUTION DEVICE AND CLOCK DISTRIBUTION METHOD - A clock distribution device to an exemplary aspect of the invention includes: a first clock output unit outputting a first clock synchronized to a reference clock; a second clock output unit outputting a second clock synchronized to the reference clock; a first clock distribution unit including a first branch point, branching the first clock at the first branch point and outputting a third clock; a second clock distribution unit including a second branch point, branching the second clock at the second branch point and outputting a fourth clock; and a phase difference detecting unit detecting a first phase difference between a phase of the third clock and a phase of the fourth clock, and the second clock output unit controls a second phase difference between a phase of the first clock and a phase of the second clock so that the first phase difference is reduced. | 2010-09-23 |
20100237915 | METHOD AND APPARATUS FOR DIGITAL VCDL STARTUP - Methods and apparatus are provided for improved startup of a voltage controlled delay loop that has an injection clock and a return clock. A control signal is determined for a plurality of delay elements in a voltage controlled delay loop by obtaining a histogram count of a number of occurrences of at least one predefined logic value for a plurality of delay settings of the voltage controlled delay loop; determining a histogram count that approximately corresponds to an alignment of at least one edge in the injection and return clocks; and determining the control signal based on the determined histogram count that approximately corresponds to the alignment. The voltage controlled delay loop can be started using the deter wined control signal. The histogram count can be obtained for a plurality of PVT combinations and the control signal can then be determined for each PVT combination. | 2010-09-23 |
20100237916 | DELAY LOCKED LOOP WITH FREQUENCY CONTROL - Some embodiments include a delay line configured to apply a delay to an input signal to provide an output signal; an input circuit configured to provide the input signal based on a first signal, such that the cycle time of the input signal is different from a cycle time of the first signal; an output circuit configured to provide a second signal based on the output signal, the second signal having a cycle time different from a cycle time of the output signal; and a controller configured to adjust the delay to control a timing relationship between the first signal and the second signal. Other embodiments are described and claimed. | 2010-09-23 |
20100237917 | Duty detection circuit, clock generation circuit including the duty detection circuit, and semiconductor device - To provide a duty detection circuit including: a plurality of duty detectors that detect a duty ratio of internal clocks; a controller that controls the plurality of duty detectors so that the plurality of duty detectors operates in different phases from one another; and an output selecting unit that selects one of duty detection signals from the plurality of duty detectors. According to the present invention, since the duty detectors operate in the different phases from one another, the output selecting unit can output a duty detection signal with a higher frequency than a generation frequency with which each duty detector generates the duty detection signal. Accordingly, when the duty detection circuit according to the present invention is used to adjust a clock of the DLL circuit, a control period of the DLL circuit can be reduced. | 2010-09-23 |
20100237918 | Frequency measuring circuit and semiconductor device having the same - A frequency measuring circuit and a semiconductor device having the frequency measuring circuit include a divided and shifted clock signal generator, a delayed clock signal generator and a phase detecting unit. The divided and shifted clock signal generator divides a frequency of a clock signal input from an exterior to output a frequency-divided clock signal, and delays the frequency-divided clock signal by a time proportional to a period of the clock signal to output a shifted clock signal. The delayed clock signal generator delays the frequency-divided clock signal by a fixed time to generate a plurality of delayed clock signals. The phase detecting unit receives the plurality of delayed clock signals and the shifted clock signal and detects a phase difference between each of the plurality of delayed clock signals and the shifted clock signal to output a plurality of phase detecting signals that represent information related to a frequency of the clock signal | 2010-09-23 |
20100237919 | METHOD AND SYSTEM FOR A SIGNAL DRIVER USING CAPACITIVE FEEDBACK - Edge-rate control circuits and methods are implemented using a variety of arrangements and methods. Using one such method, an output signal of a bus is controlled by decoupling a feedback capacitor ( | 2010-09-23 |
20100237920 | PEAK MAGNETIC FLUX REGULATION METHOD, APPARATUS, AND SYSTEM USING SAME - The present invention discloses a peak magnetic flux regulation method for a power conversion via magnetic flux transformation through an inductive component, comprising the steps of: generating an adaptive reference voltage according to voltage comparison of a current sensing voltage and an expected peak voltage; and generating a PWM signal according to voltage comparison of said current sensing voltage and said adaptive reference voltage. Furthermore, the present invention also provides a peak magnetic flux regulation apparatus for a power conversion, and a system using the peak magnetic flux regulation apparatus for a power conversion. | 2010-09-23 |
20100237921 | Current-controlled CMOS logic family - Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C | 2010-09-23 |
20100237922 | CLOCK GENERATING CIRCUIT AND CLOCK GENERATING METHOD THEREOF - A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; and a multi-phase clock generating unit to generate a plurality of multi-phase clocks, a phase difference between the adjacent multi-phase clocks being equal to a second phase difference between pulse signals of a pulse signal pair, based on a plurality of unit-phase clock generating units receiving the pulse signal pairs. | 2010-09-23 |
20100237923 | Method of placing delay units of pulse delay circuit on programmable logic device - A method of placing delay units of a pulse delay circuit on a programmable logic device having logic cells in each of cell strings has a step of arranging each delay unit in one logic cell of the device such that the delay units are placed in respective specific cell strings aligned in a row direction and a step of serially connecting the delay units with one another as a straight delay line such that the delay units placed in the specific cell strings in the connecting order are aligned in the row direction. In the device, an inter-string transmission delay time on a line between two logic cells of different cell strings differs from an intra-string transmission delay time on a line between two logic cells of one cell string. | 2010-09-23 |
20100237924 | DIGITAL FREQUENCY SYNTHESIZER DEVICE AND METHOD THEREOF - A first plurality of clock signals including a first clock signal and a second clock signal is received, the first and second clock signal out of phase with each other. A second plurality of clock signals comprising a third clock signal and a fourth clock signal is received, the third and fourth clock signals out of phase with each other. A plurality of enable signals are received. A fifth clock signal is determined based on the first plurality of clock signals and the plurality of enable signals. A sixth clock signal is determined based on the second plurality of clock signals and the plurality of enable signals. A seventh clock signal is determined based on the fifth clock signal and the sixth clock signal. | 2010-09-23 |
20100237925 | CLOCK DISTRIBUTION NETWORK - Some embodiments include apparatus and methods having a clock path with a combination of current-mode logic (CML) based and complementary metal-oxide semiconductor (CMOS) components. | 2010-09-23 |
20100237926 | VOLTAGE GENERATING CIRCUIT - A voltage generating circuit including first and second voltage sources, and a subtracting circuit. The subtraction circuit is configured as a differential amplifier including an op-amp and four resistors, with an inverting input terminal of the op-amp connected to the second voltage source via a first resistor, a second resistor connected between the inverting input terminal and an output terminal of the op-amp, a non-inverting input terminal of the op-amp connected to the first voltage source via a third resistor of the same size as the second resistor, the non-inverting input terminal of the op-amp connected to a reference potential terminal via a fourth resistor of the same size as the first resistor, the first voltage from the first voltage source and the second voltage from the second voltage source inputted to the subtracting circuit, and the subtracting circuit outputting a third voltage having a positive temperature coefficient. | 2010-09-23 |
20100237927 | Circuit Configuration for Protecting a Circuit Element Having Overcurrent and Overtemperature Detection - A circuit configuration having a detection unit designed to generate an output signal that is representative of a load current of a transistor switch, depending on an input signal that is representative of the load current of the transistor switch. The detection unit includes a temperature compensation unit that is designed to take into account the temperature of the transistor switch. The detection unit further includes a delay unit that is designed to delay the detection of the input signal until a prescribed switch-on time period, relative to a switch-on procedure of the transistor switch, has passed. The detection unit is designed in an application-specific integrated circuit. | 2010-09-23 |
20100237928 | SWITCHING CIRCUIT AND METHOD FOR TESTING THE SAME - There is provided a method for testing a switching circuit including a first FET connected between input/output terminals, a capacitor connected between one of the input/output terminals and the first FET, and a second FET that is connected in parallel with the capacitor and has a gate electrode connected to a ground terminal. The method includes, applying a potential that sets the second FET to a conducting state to the ground terminal, and testing a DC test for the first FET via the second FET. | 2010-09-23 |
20100237929 | VOLTAGE GENERATING CIRCUIT FOR ELECTROSTATIC MEMS ACTUATOR - A plurality of capacitors each of which has a first and a second electrode. A plurality of first switches is connected between the first electrodes of the plurality of capacitors and a first power supply. A plurality of second switches is connected between the second electrodes of the plurality of capacitors and a second power supply. A plurality of resistances each of which is connected between the first electrode of one of the plurality of capacitors and the second electrode of another capacitor and which connect the plurality of capacitors in series, a voltage for driving an actuator being output from the last stage of the plurality of capacitors connected in series. | 2010-09-23 |
20100237930 | INTERNAL VOLTAGE GENERATING APPARATUS AND METHOD FOR CONTROLLING THE SAME - The internal voltage generating apparatus includes a first charge pumping circuit, an external voltage level detector, and a second charge pumping circuit. The first charge pumping circuit outputs an internal voltage and selectively performs first charge pumping for the internal voltage depending on a result detecting a level of the internal voltage feed-backed. The external voltage level detector detects a level of an external voltage and outputs the result detecting the level of the internal voltage and outputs a result detecting the level of the external voltage as a detection signal. The second charge pumping circuit performs second charge pumping for the internal voltage together with the first charge pumping against a case in which the level of the external voltage is lower than a predetermined level by the detection signal of the external voltage level detector. | 2010-09-23 |
20100237931 | INTERNAL POWER SUPPLY VOLTAGE GENERATION CIRCUIT - An internal power supply voltage generation circuit | 2010-09-23 |
20100237932 | Intermediate potential generation circuit - Provided is an intermediate potential generation circuit with a lower power supply potential. The intermediate potential generation circuit includes: a current mirror circuit including a first transistor and a second transistor each having a source input with a power supply potential; a current source circuit including a third transistor having a drain connected to a drain of the first transistor; a grounded source amplifier circuit including a fourth transistor having a gate input with the intermediate potential, and a drain connected to a drain of the second transistor; a parallel connection circuit including a fifth transistor connected in parallel with the first transistor, and a sixth transistor connected in parallel with the second transistor; and a source follower circuit including a seventh transistor and an eighth transistor having gates that are connected in common to each other, and connected with the drains of the second transistor and the sixth transistor. | 2010-09-23 |
20100237933 | CURRENT SUPPLY CIRCUIT - A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being respectively connected to the main terminals of the first to Nth transistors, a pulse width of a signal provided to a control terminal of the respective first to Nth switching transistors being set to be constant regardless of a pulse frequency of the signal. | 2010-09-23 |
20100237934 | METHOD FOR REDUCING LOW FREQUENCY NOISE OF TRANSISTOR - A method for reducing low frequency noise of a transistor operable at cryogenic temperatures includes a first step in which the transistor is illuminated with a light in a state that the transistor is activated and flowed current by supplying a power at a predetermined temperature, and a second step in which the transistor is operated at the predetermined temperature after the illumination of the light. | 2010-09-23 |
20100237935 | LOGARITHMIC DETECTORS - Disclosed is a logarithmic detector comprising: an amplifier element; means for setting a frequency of operation of the detector; and a controller, wherein an input signal to the amplifier element is arranged to cause an oscillation in the amplifier element, and the controller is operable to sense a pre-determined threshold, indicative of oscillation and, in response to sensing said threshold, to interrupt the oscillation of the amplifier such that the frequency of said interruption is proportional to the logarithm of the power of the input signal. | 2010-09-23 |
20100237936 | AMPLIFIER CIRCUIT AND MAGNETIC SENSOR - An amplifier circuit, includes: a first amplifier; a second amplifier; a first capacitor connected to the first amplifier; a second capacitor having one terminal connected to the first amplifier, another terminal connected to the second input terminal; and a first switch circuit switching a connection of the output terminal, the another terminal of the first capacitor, the first input terminal and the second input terminal, and switching supplying a reference potential supply, the first switch circuit including: a first state connecting the first input terminal to the second input terminal, connecting the output terminal to the another terminal of the first capacitor, and supplying the second input terminal with the reference potential, a second state connecting the first input terminal to the another terminal of the first capacitor and providing the output terminal and the second input terminal in an open state. | 2010-09-23 |
20100237937 | POWER AMPLIFYING DEVICE AND POWER AMPLIFYING METHOD - A power amplifying device includes an amplifier that amplifies a signal which is input in accordance with a voltage signal which is supplied to the amplifier, a voltage control section that controls the voltage signal in accordance with a transmission signal, a distortion compensating section that executes a distortion compensating process on the transmission signal by giving a value indicative of a reverse characteristic of the amplifier to the transmission signal in advance and inputs an output signal obtained by executing the distortion compensating process into the amplifier, an amplitude detecting section that detects an amplitude of the transmission signal, and a timing adjusting section that adjusts timings of the output signal and the voltage signal so that a value relating to the distortion compensating process meets a given condition when a detected value of the amplitude of the transmission signal is less than a given value. | 2010-09-23 |
20100237938 | HIGH EFFICIENCY LINEAR POWER AMPLIFIERS WITH LOAD COMPENSATION - The present invention addresses the problem to extend the dynamic power range where the amplifier operates linearly for a full input amplitude swing with improved efficiency. According to the present invention, the above presented problem is solved by changing the delivered power to the load by changing the value of the load and still keeping the amplifier in its linear condition. The invention enables the amplifier to maintain high efficiency over a wider power range. | 2010-09-23 |
20100237939 | ADAPTIVE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER LOAD COMPENSATION - A buffer varies the size of its output stage in response to a varying capacitive load. The capacitive load may vary in a predictable or a random manner. The buffer includes an operational amplifier having an output stage of multiple transistors, selectively connected in parallel. During operation, data regarding the size of the capacitive load is obtained and used to determine the size of the output stage. In general, as the capacitive load increases, the number of transistors connected in parallel at the output stage also increases. | 2010-09-23 |
20100237940 | Output Stage with Adaptive Bias Control - An input stage receives a differential input signal at first and second input nodes and provides a differential output current at first and second output nodes. The differential output current includes a component taken from the input nodes through first and second impedances, and an additional component generated in response to a sample of the voltage of the differential input signal. A transconductance cell having cross-coupled inputs may generate the additional component of the output current. | 2010-09-23 |
20100237941 | WIDEBAND RF AMPLIFIERS - A device for amplifying signals over a wide frequency range features stacked amplifying modules connected between a DC voltage source and an electrical ground. The stacking configuration reuses the DC current produced the voltage source, and thus reduces the amount of operational DC current permitting the use of lower voltage, higher frequency devices to be used. The amplifying modules are fed signals which are different versions of an input signal, and the output signals are AC coupled using capacitors to balance out gain imbalances and asymmetries between the amplifying modules. | 2010-09-23 |
20100237942 | COMMON-GATE COMMON-SOURCE AMPLIFIER - Techniques for integrating a common-source and common-gate amplifier topology in a single amplifier design. In one aspect, an input voltage is provided to both a common-source amplifier and a common-gate amplifier. The output voltages of the common-source amplifier and the common-gate amplifier are provided to a difference block for generating a single-ended voltage proportional to the difference between the output voltages. When applied to the design of, e.g., low-noise amplifiers (LNA's), the disclosed techniques may offer improved noise performance over the prior art. | 2010-09-23 |
20100237943 | Auto gain controllers, and communication terminals having the same - An auto gain controller is provided. The auto gain controller includes a variable gain amplification unit configured to receive differential input signals, adjust an amplification gain based on an auto gain control voltage and output differential output signals. The auto gain controller also includes a peak detector configured to detect at least one peak value among the amplified differential output signals, a comparator configured to compare the at least one detected peak value with a reference voltage and generate a comparison signal, and a voltage adjusting circuit configured to adjust the auto gain control voltage and the reference voltage based on the comparison signal. | 2010-09-23 |
20100237944 | Amplifier System With Digital Adaptive Power Boost - An amplifier system with digital adaptive power boost includes a charge pump for providing a power supply to an amplifier. The charge pump may switch between a fixed input DC voltage and a boosted value for a certain period of time in response to an increase in an input signal to the amplifier. The charge pump may use a switching transistor which is switched on only when the input signal to the amplifier exceeds a threshold. The amplifier system may be used for envelope tracking, especially for envelope tracking of low duty cycle signals, e.g., xDSL or vDSL. | 2010-09-23 |
20100237945 | CASCODE AMPLIFIER WITH PROTECTION CIRCUITRY - A cascode amplifier with protection circuitry is described. In one exemplary design, the amplifier includes multiple branches coupled in parallel, with at least one branch being switchable between “on” and “off” states. Each switchable branch includes a gain transistor coupled to a cascode transistor. The gain transistor amplifies an input signal and provides an amplified signal in the on state and does not amplify the input signal in the off state. The cascode transistor buffers the amplified signal and provides an output signal in the on state. The output signal swing may be split between the gain transistor and the cascode transistor in both the on and off states with the protection circuitry. Each transistor may then observe a fraction of the voltage swing. The voltage splitting in the off state may be achieved by floating the gain transistor and shorting the gate and source of the cascode transistor. | 2010-09-23 |
20100237946 | Low Noise Amplifier Circuit with Noise Cancellation and Increased Gain - A low noise amplifier circuit including a front end voltage sensing and matching amplification circuit, a gain circuit and a combining circuit is disclosed. The front end voltage sensing and matching amplification circuit includes an input and two outputs and provides a matched signal at each output. The gain circuit includes two inputs, each input being respectively coupled to at least one of the two outputs of the front end voltage sensing and matching amplification circuit. The gain circuit further includes two outputs and an output signal is provided at each output of the gain circuit. The combining circuit combines the two output signals of the gain circuit. The combining circuit includes two inputs, each input is respectively coupled to at least one of the two outputs of the gain circuit. The combining circuit further includes an output providing a combined signal. | 2010-09-23 |
20100237947 | AMPLIFIER SUPPORTING MULTIPLE GAIN MODES - Techniques for designing a low-noise amplifier (LNA) for operation over a wide range of input power levels. In an exemplary embodiment, a first gain path is provided in parallel with a second gain path. The first gain path includes a differential cascode amplifier with inductor source degeneration. The second gain path includes a differential cascode amplifier without inductor source degeneration. The cascode transistors of the gain paths may be selectively biased to enable or disable the first and/or second gain path. By selectively biasing the cascode transistors and input transistors, various combinations of the first and second gain paths may be selected to provide an optimized gain configuration for any input power level. | 2010-09-23 |
20100237948 | SYSTEM AND METHOD FOR DYNAMIC DRAIN VOLTAGE ADJUSTMENT TO CONTROL LINEARITY, OUTPUT POWER, AND EFFICIENCY IN RF POWER AMPLIFIERS - A system and method for dynamic adjustment of drain or collector voltage of a power amplifier (PA), including a PA having a voltage input, a temperature sensor measuring ambient temperature of the PA, and an adaptive PA control processor that dynamically changes the input voltage based on the ambient temperature, achieving a desired peak power when the system is subjected to high temperatures. In a further embodiment, a power sensor measures output power of the PA, and the control processor dynamically changes the voltage based on output power when the system serves a large cell in a mobile communication infrastructure employing high power. In a further embodiment, a multistage PA and method include amplifier stages having drain or collector voltage inputs, wherein a voltage applied to the inputs are set so as to be proportional to the peak power requirements of each stage, enhancing overall efficiency. | 2010-09-23 |
20100237949 | METHOD AND SYSTEM FOR ENHANCING EFFICIENCY BY MODULATING POWER AMPLIFIER GAIN - Aspects of a method and system for enhancing efficiency by modulating power amplifier (PA) gain are presented. Aspects of the system may comprise a PA gain modulator that enables modification of an amplitude of a digital baseband signal. A baseband processor may enable computation of a first gain value based on the modification. The baseband processor may enable computation of a second gain value based on the first gain value. A PA may enable generation of an RF output signal based on the modified digital baseband signal and the second gain value. | 2010-09-23 |
20100237950 | TRANSCONDUCTANCE BIAS CIRCUIT, AMPLIFIER AND METHOD - Methods, circuits and apparatus for biasing an amplifier to maintain consistent operational characteristics over variations in fabrication processes and operational temperature conditions are disclosed. A bias is determined by first comparing output voltages of replica circuits of the amplifier during an offset canceling phase. The output voltages are differently driven by an offset induced by a first reference current and the offset is canceled in response to the first comparing step. The output voltages are secondly compared during a calibration phase and a calibration bias current is adjusted in response to the second comparing step. The amplifier bias is determined based on the calibration bias current. The process is periodically repeated in response to operational variations. | 2010-09-23 |
20100237951 | FREQUENCY CALIBRATION OF RADIO FREQUENCY OSCILLATORS - A wireless communication device incorporating a set of comparators and logic interrupt into the local oscillator generation circuit block is described. In one design, the local oscillator circuit block includes a RF VCO with coarse and fine frequency tuning. The RF VCO fine frequency tuning signal is monitored continuously to determine if the control voltage is within specified limits. If the RF VCO fine frequency tuning voltage is too low or too high for the RF VCO to meet system requirements or lock on the current desired frequency, an interrupt signal is asserted. In response to the interrupt signal, a wireless communications processor or a hardware state machine initiates coarse frequency calibration of the RF VCO at the desired frequency. After coarse frequency calibration has completed, the RF VCO fine frequency tuning voltage is within specified limits and is continuously monitored. | 2010-09-23 |
20100237952 | CURRENT CONTROLLED OSCILLATOR WITH REGULATED SYMMETRIC LOADS - An integrated circuit incorporating a bias circuit for a current-controlled oscillator (ICO) with improved power supply rejection ratio (PSRR) is described. The bias circuit for the ICO includes two error amplifiers. The first error amplifier regulates the bias voltage, V | 2010-09-23 |
20100237953 | DIGITAL PHASE DETECTOR, AND DIGITAL PHASE LOCKED LOOP INCLUDING THE SAME - A digital phase detector includes a quantization unit that quantizes a frequency of a reference signal to generate reference delay information and reference integer phase information, and quantizes a frequency of an oscillation signal to generate oscillation delay information and oscillation integer phase information. A first conversion unit converts the frequency of the reference signal into reference frequency information based upon the reference delay information and the reference integer phase information. A second conversion unit converts the frequency of the oscillation signal into oscillation frequency information based upon the oscillation delay information and the oscillation integer phase information. A calculation unit converts the reference frequency information and the oscillation frequency information into first and second phase information, respectively, and outputs a digital phase difference between the first phase information and the second phase information. | 2010-09-23 |
20100237954 | SYSTEMS AND METHODS FOR SELF TESTING A VOLTAGE CONTROLLED OSCILLATOR - A method for self testing a multiband voltage controlled oscillator (VCO) is described. A first frequency band in a VCO is selected. An N value is selected for a frequency divider that produces a tuning voltage for the VCO that is between a low tuning voltage limit and a high tuning voltage limit for the VCO. The N value is adjusted in one direction until the tuning voltage reaches one of the tuning voltage limits. This N value at the tuning voltage is a first limit value. The frequency bands are switched from the first frequency band to a second frequency band that is adjacent to the first frequency band. | 2010-09-23 |
20100237955 | PROCESS, VOLTAGE, TEMPERATURE COMPENSATED OSCILLATOR - A voltage reference connects to a voltage-to-current converter to generate a reference current dependent on the reference voltage. Outputs of a toggle-type flip flop connect to switching transistors controlling the reference current charging capacitors. The toggling of the flip-flop is controlled by comparing the capacitor voltages to the reference voltage, such that the toggle frequency is proportional to the time charging the capacitors. Optionally, temperature compensation data, representing a magnitude and direction rotation of the frequency versus temperature characteristic is stored and, based on a sensed temperature, retrieved to modify the reference current. | 2010-09-23 |
20100237956 | BIAS GENERATION CIRCUIT AND VOLTAGE CONTROLLED OSCILLATOR - This invention includes a bias origination section configured to originate an original bias voltage; a comparison section configured to compare the original bias voltage and a comparison voltage, and output a comparison result; a resistive divider section composed by a resistance circuit including a variable resistor section having a resistor and a switch, and configured to generate the comparison voltage; a bias decision control section configured to determine bias decision data for controlling a resistance value of the variable resistor section so as to bring the comparison voltage close to the original bias voltage, based on a comparison result of the comparison section; and a storage section configured to hold the bias decision data and also output the comparison voltage as a bias voltage by controlling a resistance value of the variable resistor section based on the held bias decision data, thereby generating a low-noise bias with a small area. | 2010-09-23 |
20100237957 | DIFFERENTIAL OSCILLATION APPARATUS AND MODULATOR - It is an object of the present invention to shorten a time required until phases of output signals being output from two output terminals are inverted respectively from a start time of an oscillation in a differential oscillation apparatus. In a differential oscillation apparatus according to the present invention which includes a differential oscillator portion | 2010-09-23 |
20100237958 | FEED-BACK AND FEED-FORWARD SYSTEMS AND METHODS TO REDUCE OSCILLATOR PHASE-NOISE - Systems, methods, and apparatus are described that provide for low phase-noise, spectrally-pure, and low-jitter signals from electrical oscillators. An aspect of the present disclosure includes utilization of an open-loop feed-forward phase-noise cancellation scheme to cancel phase noise, or jitter, of an electrical oscillator. Phase noise can be measured and then subtracted, with the phase noise measurement and subtraction being performed at a speed faster than phase noise variations of the oscillator. Another aspect of the present disclosure includes use of a feedback scheme for phase noise reduction. A feedback scheme can be used alone or in conjunction with a feed-forward scheme. Related phase-noise cancellation and/or reduction methods are described. Notch filter and RF amplifier circuits are also described. | 2010-09-23 |
20100237959 | LAMB-WAVE RESONATOR AND OSCILLATOR - A Lamb-wave resonator includes: a piezoelectric substrate; an IDT electrode disposed on one principal surface of the piezoelectric substrate, having bus bar electrodes each connecting one ends of a plurality of electrode finger elements, the other ends of the plurality of electrode finger elements being interdigitated with each other to form an apposition area; and a pair of reflectors disposed on the one principal surface of the piezoelectric substrate, and respectively arranged on both sides of the IDT electrode in a propagation direction of a Lamb wave, wherein denoting a thickness of the piezoelectric substrate in the apposition area of the electrode finger elements as ti, a thickness of the piezoelectric substrate in areas between respective ends of the apposition area in a direction perpendicular to the propagation direction of the Lamb wave and the bus bar electrodes as tg, and a wavelength of the Lamb wave as λ, the thickness ti exists in a range represented by 02010-09-23 | |
20100237960 | FREQUENCY-JITTERING APPARATUSES, FREQUENCY-JITTERING METHODS AND POWER MANAGEMENT DEVICES - A frequency-jittering apparatuses includes an oscillator and a frequency control circuit. The oscillator generates a signal. When the magnitude of the signal exceeds a magnitude of a reference signal, the oscillator operates substantially in a first state; and when the magnitude of the signal is lower than the magnitude of the reference signal, the oscillator operates substantially in a second state different from the first one. The frequency control circuit varies the reference signal to change the frequency of the signal output from the oscillator. | 2010-09-23 |