38th week of 2012 patent applcation highlights part 62 |
Patent application number | Title | Published |
20120239842 | HIGH PERFORMANCE EXTENSION DEVICE - An extension device for connecting one or more peripheral devices to a computer, comprising a first bus for connecting to the computer; a second bus for connecting to the computer; a hub coupled to the first bus for connecting the computer to one or more peripheral devices; a controller for connecting the computer to a high-bandwidth device, the controller being switchably coupled to the hub and the second bus; and a switch for switching the controller, from being coupled to the hub, to being coupled to the second bus, when a connection to the computer is detected on the second bus. | 2012-09-20 |
20120239843 | SERIAL ATTACHED SCSI EXPANDER MANAGEMENT AND ALARM REPORTING USING SNMP - Disclosed is a Serial Attached SCSI (SAS) expander. The SAS expander is configured with an Ethernet interface and at least one SAS interface. The Ethernet interface is configured to communicate using TCP/IP protocol. The SAS expander is also configured to send an indicator of an alarm condition using Simple Network Management Protocol (SNMP). The indicator of the alarm condition is sent via the Ethernet interface. Configuration functions and status reads or writes of values stored in the SAS expander, or devices coupled to it may also be exchanged using SNMP. | 2012-09-20 |
20120239844 | DATA STORAGE SYSTEM FOR MANAGING SERIAL INTERFACE CONFIGURATION BASED ON DETECTED ACTIVITY - According to one aspect, a data storage system is disclosed. In one embodiment, the data storage system includes a storage backplane having a plurality of drive slots configured to operatively connect to a corresponding plurality of mass storage devices, a first serial interface operative to communicatively connect one or more sets of the plurality of drive slots to a host bus adapter (HBA), according to a first drive slot assignment, a second serial interface operative to communicatively connect one or more sets of the plurality of drive slots to the HBA, according to a second drive slot assignment, and a backplane controller operatively connected to the first serial interface and the second serial interface, operative to detect the activity status on the first serial interface and the activity status on the second serial interface and, if a change in the activity status is detected for at least one of the first serial interface and the second serial interface, modify the first drive slot assignment and the second drive slot assignment. | 2012-09-20 |
20120239845 | BACKPLANE CONTROLLER FOR MANAGING SERIAL INTERFACE CONFIGURATION BASED ON DETECTED ACTIVITY - According to one aspect, a backplane controller of a storage backplane is disclosed, the storage backplane having a plurality of drive slots configured to operatively connect to a corresponding plurality of mass storage devices. In one embodiment, the backplane controller is operative to perform functions that include detecting activity status on a first serial interface that is configured to operatively connect one or more sets of a plurality of drive slots on the storage backplane to a host bus adapter (HBA), according to a first drive slot assignment. The backplane controller is further operative to detect an activity status on a second serial interface that is configured to operatively connect one or more sets of a plurality of drive slots on the storage backplane to the HBA, according to a second drive slot assignment. The backplane controller is also operative to, if a change in the activity status is detected for at least one of the first serial interface and the second serial interface, modify the first drive slot assignment and the second drive slot assignment. | 2012-09-20 |
20120239846 | MULTI-RATE, MULTI-PORT, GIGABIT SERDES TRANSCEIVER - A multi-port SERDES transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port SERDES transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. | 2012-09-20 |
20120239847 | MULTI-CORE MICROPROCESSOR INTERNAL BYPASS BUS - Microprocessors with multi-core dies that include bypass buses are provided. Each microprocessor comprises a plurality of physical pins for coupling the microprocessor to a processor bus coupled to a chipset. The multi-core die has at least two complementary sets of one or more processing cores, each providing a bus interface coupling respective core inputs and outputs to corresponding processor bus lines. A bypass bus on the die enables cores of the complementary sets to bypass the processor bus and communicate directly with each other. The bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus. Moreover, the microprocessor is operable to detect whether the chipset or a complementary core is driving the processor bus, and if the latter, to select the higher quality bypass bus signals over the corresponding processor bus signals. | 2012-09-20 |
20120239848 | MITIGATION OF EMBEDDED CONTROLLER STARVATION IN REAL-TIME SHARED SPI FLASH ARCHITECTURE - An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met. | 2012-09-20 |
20120239849 | SYSTEM AND METHOD FOR PERFORMING RAID I/O OPERATIONS IN PCIE-BASED STORAGE RESOURCES - Systems and methods for performing RAID I/O operations in PCIe-based storage resources are disclosed. In accordance with embodiments of the present disclosure, a method for performing a read operation may be provided. The method may include overlaying memory address space of storage resources of a source logical unit for the read operation onto a destination address. The method may also include determining whether the source logical unit is a RAIDO array. The method may additionally include generating a source address in a receive buffer for each storage resource of the source logical unit if the source logical unit is a RAIDO array. The method may further include storing data received from each storage address of the logical unit at the generated source address of the receive buffer associated with such storage resource. | 2012-09-20 |
20120239850 | METHOD FOR CREATING VIRTUAL MACHINE, A VIRTUAL MACHINE MONITOR, AND A VIRTUAL MACHINE SYSTEM - A method for creating virtual machine, a virtual machine monitor and a virtual machine system are provided in the embodiments of this application. The method comprises: mapping guest frame number (GFN) corresponding to a pseudo-physical memory of a virtual machine to a shared zero page, the shared zero page being a page having content of all zeros in physical memory; when the GFN is written by the virtual machine and if a page exception occurs, allocating a physical memory page to relieve the mapping relation between the guest frame number (GFN) and the shared zero page, and establishing a mapping relation between the guest frame number (GFN) and a machine frame number (MFN) of the physical memory page. The method can reduce the amount of memory used in virtual machine startup, improve virtual machine density, and support the concurrent startup of a memory overcommitted number of virtual machine. | 2012-09-20 |
20120239851 | PRIORITIZED ERASURE OF DATA BLOCKS IN A FLASH STORAGE DEVICE - Methods and systems for the prioritized erasure of data blocks in a flash storage device are provided. A data block in the flash storage device is selected for erasure based upon the number of valid data segments therein, thereby minimizing the number of data segments that are carried over to another data block before erasing the selected data block. The overhead of write operations in the flash storage device is therefore greatly reduced, and the overall performance thereof greatly increased. A method for managing memory operations in a flash storage device having a plurality of data blocks comprises the steps of selecting one of the plurality of data blocks for erasure based upon a number of valid data segments therein, and erasing the selected one of the plurality of data blocks. | 2012-09-20 |
20120239852 | HIGH SPEED INPUT/OUTPUT PERFORMANCE IN SOLID STATE DEVICES - A method of transferring data in a flash storage device comprising a random access memory and a plurality of channels of a flash array is provided. The method comprises receiving a plurality of data segments from a host system, storing the plurality of data segments in the random access memory, allocating the plurality of data segments among the plurality of channels of the flash array, and writing the allocated data segments from the random access memory to the respective channels of the flash array. | 2012-09-20 |
20120239853 | SOLID STATE DEVICE WITH ALLOCATED FLASH CACHE - A flash storage device, and methods for a flash storage device, having improved write performance are provided. Data is received from a host system, the data comprising a data segment, the data segment is temporarily stored in a data buffer of the random access memory, the data segment is assigned to a logical block address, and the data segment is written to an allocated cache portion of the flash memory. Subsequently, the data segment is written from the allocated cache portion of the flash memory to a main storage portion of the flash memory. | 2012-09-20 |
20120239854 | FLASH STORAGE DEVICE WITH READ CACHE - A flash storage device includes a first memory, a flash memory comprising a plurality of physical blocks, each of the plurality of physical blocks comprising a plurality of physical pages, and a controller. The controller is configured to store, in the first memory, copies of data read from the flash memory, map a logical address in a read request received from a host system to a virtual unit address and a virtual page address, and check a virtual unit cache tag table stored in the first memory based on the virtual unit address. If a hit is found in the virtual unit cache tag table, a virtual page cache tag sub-table stored in the first memory is checked based on the virtual page address, wherein the virtual page cache tag sub-table is associated with the virtual unit address. If a hit is found in the virtual page cache tag sub-table, data stored in the first memory mapped to the hit in the virtual page cache tag sub-table is read in response to the read request received from the host system. | 2012-09-20 |
20120239855 | SOLID-STATE STORAGE DEVICE WITH MULTI-LEVEL ADDRESSING - A solid-state storage device with multi-level addressing is provided. The solid-state storage device includes a plurality of flash memory devices, a volatile memory, and a controller. The controller is configured to store data received from a host in the plurality of flash memory devices in response to a write command and to read the data stored in the plurality of flash memory devices in response to a read command. The controller is further configured to maintain a multi-level address table that maps logical addresses received from the host identifying the data stored in the plurality of flash memory devices to physical addresses in the plurality of flash memory devices containing the data. A first level of the multi-level address table is maintained by the controller in the volatile memory and second and third levels of the multi-level address table are maintained by the controller in the plurality of flash memory devices. | 2012-09-20 |
20120239856 | HYBRID SYSTEM ARCHITECTURE FOR RANDOM ACCESS MEMORY - Embodiments of the present invention provide a hybrid system architecture random access memory (RAM) such as Phase-Change RAM (PRAM), Magnetoresistive RAM (MRAM) and/or Ferroelectric RAM (FRAM). Specifically, embodiments of this invention provide a hybrid RAID controller coupled to a system control board. Coupled to the hybrid RAID controller are a DDR RAID controller, a RAM RAID controller, and a HDD/Flash RAID controller. A DDR RAID control block is coupled to the DDR RAID controller and includes (among other things) a set of DDR memory disks. Further, a RAM control block is coupled to the RAM RAID controller and includes a set of RAM SSDs. Still yet, a HDD RAID control block is coupled to the HDD/Flash RAID controller and includes a set of HDD/Flash SSD Units. | 2012-09-20 |
20120239857 | SYSTEM AND METHOD TO EFFICIENTLY SCHEDULE AND/OR COMMIT WRITE DATA TO FLASH BASED SSDs ATTACHED TO AN ARRAY CONTROLLER - An apparatus comprising a controller and an array. The controller may be configured to generate control signals in response to one or more input requests. The array may comprise a plurality of solid state devices. The solid state devices may be configured to (i) read and/or write data in response to the control signals received from the controller and (ii) distribute writes across the plurality of solid state devices such that each of said solid state devices has a similar number of writes. | 2012-09-20 |
20120239858 | APPARATUS AND METHOD FOR DETERMINING AN OPERATING CONDITION OF A MEMORY CELL BASED ON CYCLE INFORMATION - Disclosed is an apparatus and method for determining a parameter for programming a non-volatile memory circuit. On receiving write or erase operation a parameter is determined as a function of a circuit characteristic associated with a memory block. An adjusted condition, for example, read or write time, or the standard deviation of voltage thresholds in a distribution of cells, is then determined as a function of the parameter, and a command provided to the memory circuit to use the parameter in the next write or erase operation performed on the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit. | 2012-09-20 |
20120239859 | APPLICATION PROFILING IN A DATA STORAGE ARRAY - Method and apparatus for application profiling in a multi-device data storage array. In accordance with various embodiments, a storage array is formed of independent data storage devices that form a fast pool and a slow pool of said devices, such as solid-state drives (SSDs) and hard disc drives (HDDs). A controller is adapted to migrate a distributed data set stored across a first plurality of the devices in the slow pool to a second plurality of said devices in the fast pool. The controller carries out the migration responsive to a hint that a selected application is about to be executed that utilizes the distributed data set, and responsive to a return on investment (ROI) determination that an estimated cost of said migration will be outweighed by an overall improved data transfer capacity of the storage array over a predetermined minimum payback period of time. | 2012-09-20 |
20120239860 | APPARATUS, SYSTEM, AND METHOD FOR PERSISTENT DATA MANAGEMENT ON A NON-VOLATILE STORAGE MEDIA - Data is stored on a non-volatile storage media in a sequential, log-based format. The formatted data defines an ordered sequence of storage operations performed on the non-volatile storage media. A virtual storage layer maintains volatile metadata, which may include a forward index associating logical identifiers with respective physical storage units on the non-volatile storage media. The volatile metadata may be reconstructed from the ordered sequence of storage operations. Persistent notes may be used to maintain consistency between the volatile metadata and the contents of the non-volatile storage media. Persistent notes may identify data that does not need to be retained on the non-volatile storage media and/or is no longer valid. | 2012-09-20 |
20120239861 | NONVOLATILE MEMORY DEVICES WITH PAGE FLAGS, METHODS OF OPERATION AND MEMORY SYSTEMS INCLUDING SAME - A method programming multi-bit data to multi-level non-volatile memory cells (MLC) includes; programming a first page of data to the MLC, programming a first page flag to an initial first flag state in response in the programming of the first page, programming a second page of data to the MLC, in response to programming the second page, determining whether the first page has been programmed and if the first page has been programmed, programming the first page flag to a final first flag state different from the initial first flag state in response to programming of the second page, and if the first page has not been programmed, inhibiting programming of the first page flag during programming of the second page. | 2012-09-20 |
20120239862 | MEMORY CONTROLLER CONTROLLING A NONVOLATILE MEMORY - Described is a memory controller interfacing with a host and a nonvolatile memory. The memory controller may include a buffer unit configured to store an input address table and a first hot address table; and a processing unit configured to judge whether an address from the host coincides with one of addresses stored in the input address table and to store the address from the host in the first hot address table according to the judgment. | 2012-09-20 |
20120239863 | NONVOLATILE MEMORY SYSTEMS WITH EMBEDDED FAST READ AND WRITE MEMORIES - A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system. | 2012-09-20 |
20120239864 | CACHING SCHEME SYNERGY FOR EXTENT MIGRATION BETWEEN TIERS OF A STORAGE SYSTEM - A method according to one embodiment includes determining to move an extent from a source-tier in a storage system to a destination-tier in the storage system; determining whether any track from the set of tracks is presently being written to; designating to a write-stack associated with the source-tier each track that is presently being written to and designating to a read-stack associated with the source-tier remaining tracks from the set of tracks; removing oldest tracks from the read-stack and the write-stack until the read-stack and the write-stack have been depleted of tracks; when a parameter of the extent exceeds a migration threshold: populating a destination-tier cache with the tracks as they are removed from the read-stack and the write-stack using a predetermined read-to-write ratio and removing tracks from a source-tier cache that were removed from the read-stack and the write-stack; and migrating the extent from the source-tier to the destination-tier. | 2012-09-20 |
20120239865 | STORAGE DEVICE - A storage device realizing an improvement in rewrite endurance of a nonvolatile memory and an improvement in data transfer rate of write and read operations is provided including a nonvolatile memory; a volatile memory for storing file management information of the nonvolatile memory; a controller for controlling the nonvolatile memory and the volatile memory; and a power supply maintaining unit for supplying power to the nonvolatile memory, the volatile memory, or the controller upon power shutdown. The controller reads the file management information in the nonvolatile memory upon power-on and writes the same in the volatile memory, and read and write operations are performed based on the file management information in the volatile memory, and the file management information in the volatile memory is written in the nonvolatile memory upon power shutdown. | 2012-09-20 |
20120239866 | NON-VOLATILE MEMORY WITH ERROR CORRECTION FOR PAGE COPY OPERATION AND METHOD THEREOF - The disclosure is a NAND flash memory with the function of error checking and correction during a page copy operation. The NAND flash memory is able to prohibit transcription of erroneous bits to a duplicate page from a source page. Embodiments of the inventive flash memory include a correction circuit for correcting bit errors of source data stored in a page buffer, a circuit configured to provide the source data to the correction circuit and to provide correction data to the page buffer, and a copy circuit configured to copy the source data to the page buffer, and to store the correction data in the other page from the page buffer. | 2012-09-20 |
20120239867 | Flash Sector Seeding to Reduce Program Times - A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location,of the data byte in an address translation table so the data byte may be accessed. | 2012-09-20 |
20120239868 | Flash Memory Device and Control Method - The present invention is directed to a method for increasing the operational lifetime of a flash memory device, wherein, the method comprises varying the operating parameters of the flash memory device over the lifetime of the flash memory device. The advantage of providing a method which varies the operating parameters of a flash memory device is that the operational lifetime of the flash memory device will be increased. Relatively low voltages and relatively short voltage periods may be used initially to write to, read from and erase the flash cells in the flash memory device. As time passes, the flash cells in the flash memory device will begin to degrade and it will be necessary to increase the voltage and the period of the voltage applied to the flash memory device in order to ensure that the correct write, read and/or erase commands are carried out. The invention is also directed towards a flash memory device. | 2012-09-20 |
20120239869 | RANDOM WRITE OPTIMIZATION TECHNIQUES FOR FLASH DISKS - Disclosed is a method for managing logical block write requests for a flash drive. The method includes receiving a logical block write request from a file system; assigning a category to the logical block; and generating at least three writes from the logical block write request, a first write writes the logical block to an Erasure Unit (EU) according to the category assigned to each logical block, a second write inserts a Block Mapping Table (BMT) update entry to a BMT update log, and a third write commits the BMT update entry to an on-disk BMT, wherein the first and second writes are performed synchronously and the third write is performed asynchronously and in a batched fashion. | 2012-09-20 |
20120239870 | FIFO APPARATUS FOR THE BOUNDARY OF CLOCK TREES AND METHOD THEREOF - A FIFO apparatus uses a first clock signal in a first clock domain to receive an input signal and uses a second clock signal in a second clock domain to output an output signal. An example apparatus includes: at least three write registers belonging to the first clock domain for receiving the input signal. Each of the write registers has a first output. A first controller belonging to the first clock domain enables the registers, in accordance with an order, to generate an initial signal. A multiplexer receives the first outputs. A second controller belonging to the second clock domain, receives the initial signal through an asynchronous interface and controls the multiplexer to output the first outputs in accordance with the order to be the output signal, wherein the second clock domain is a clock tree generated based on the first clock domain. | 2012-09-20 |
20120239871 | VIRTUAL ADDRESS PAGER AND METHOD FOR USE WITH A BULK ERASE MEMORY - A virtual address pager and method for use with a bulk erase memory is disclosed. The virtual address pager includes a page protection controller configured with a heap manager interface configured to receive only bulk erase memory-backed page requests for a plurality of memory pages. A RAM object cache controller is configured to store and bulk write data for a portion of the bulk erase memory. The page protection controller may have an operating system interface configured to generate a page memory access permission for each of the plurality of memory pages. The page protection controller may be configured to receive a virtual memory allocation request and generate the page memory access permission based on the virtual memory allocation request. | 2012-09-20 |
20120239872 | PRE-FETCHING DATA INTO A MEMORY - Systems and methods for pre-fetching of data in a memory are provided. By pre-fetching stored data from a slower memory into a faster memory, the amount of time required for data retrieval and/or processing may be reduced. First, data is received and pre-scanned to generate a sample fingerprint. Fingerprints stored in a faster memory that are similar to the sample fingerprint are identified. Data stored in the slower memory associated with the identified stored fingerprints is copied into the faster memory. The copied data may be compared to the received data. Various embodiments may be included in a network memory architecture to allow for faster data matching and instruction generation in a central appliance. | 2012-09-20 |
20120239873 | Memory access system and method for optimizing SDRAM bandwidth - A memory access system for optimizing SDRAM bandwidth includes a memory command processor, and an SDRAM interface and protocol controller. The memory command processor is connected to a memory bus arbiter and data switch circuit for receiving memory access commands outputted by the memory bus arbiter and data switch circuit and converting the memory access commands into reordered SDRAM commands. The SDRAM interface and protocol controller is connected to the memory command processor for receiving and executing the reordered SDRAM commands based on protocol and timing of SDRAM. The memory command processor decodes the memory access commands into general SDRAM commands or alternative SDRAM commands. The memory access commands decoded into alternative SDRAM commands are generated by a specific bus master. | 2012-09-20 |
20120239874 | METHOD AND SYSTEM FOR RESOLVING INTEROPERABILITY OF MULTIPLE TYPES OF DUAL IN-LINE MEMORY MODULES - Systems and methods are described for resolving certain interoperability issues among multiple types of memory modules in the same memory subsystem. The system provides a single data load DIMM for constructing a high density and high speed memory subsystem that supports the standard JEDEC RDIMM interface while presenting a single load to the memory controller. At least one memory module includes one or more DRAM, a bi-directional data buffer and an interface bridge with a conflict resolution block. The interface bridge translates the CAS latency (CL) programming value that a memory controller sends to program the DRAMs, modifies the latency value, and is used for resolving command conflicts between the DRAMs and the memory controller to insure proper operation of the memory subsystem. | 2012-09-20 |
20120239875 | APPARATUS AND METHOD FOR HETEROGENEOUS CHIP MULTIPROCESSORS VIA RESOURCE ALLOCATION AND RESTRICTION - A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed. | 2012-09-20 |
20120239876 | MAPPING LOCATIONS OF LOGICAL VOLUME RECORDS ON A PHYSICAL STACKED VOLUME - In one embodiment, a method for accessing host data records stored in a VTS system includes receiving a mount request to access at least one host data record, determining a SLBID corresponding to the requested host data records, determining a PBID that corresponds to the SLBID, accessing a physical block on a sequential access storage medium corresponding to the PBID, and outputting at least the physical block corresponding to the PBID without outputting an entire logical volume that the physical block is stored to. According to another embodiment, a VTS system includes random access storage, sequential access storage, support for at least one virtual volume, a storage manager having logic for determining a PBID that corresponds to a SLBID, and logic for copying a portion of a logical volume from the sequential access storage to the random access storage without copying the entire logical volume. Other embodiments are disclosed also. | 2012-09-20 |
20120239877 | LOCATING HOST DATA RECORDS ON A PHYSICAL STACKED VOLUME - According to one embodiment, a method for accessing host data records stored on a VTS system includes receiving a mount request to access at least one host data record on a VTS system, determining a number of host compressed data records per physical block on a sequential access storage medium, determining a PBID that corresponds to the requested at least one host data record, accessing a physical block on the sequential access storage medium corresponding to the PBID, and outputting the physical block without outputting an entire logical volume that the physical block is stored to. In another embodiment, a VTS system includes random access storage, sequential access storage, support for at least one virtual volume, a storage manager having logic for determining a PBID that corresponds to a SLBID, and logic for performing the above described method. Other methods are also described. | 2012-09-20 |
20120239878 | METHODS FOR MANAGING A CACHE IN A MULTI-NODE VIRTUAL TAPE CONTROLLER - According to one embodiment, a method for managing cache space in a virtual tape controller includes receiving data from at least one host using the virtual tape controller; storing data received from the at least one host to a cache using the virtual tape controller; sending a first alert to the at least one host when a cache free space size is less than a first threshold and entering into a warning state using the virtual tape controller; sending a second alert to the at least one host when the cache free space size is less than a second threshold and entering into a critical state using the virtual tape controller; and allowing previously mounted virtual drives to continue normal writing activity when in the critical state. | 2012-09-20 |
20120239879 | STORAGE SYSTEM FOR MANAGING A LOG OF ACCESS - Provided is a storage system including: a first interface connected to a host computer; a second interface connected to a manager terminal; a control unit connected to the first interface and the second interface and equipping a processor and a memory; and one or more disk drives in which data that is requested to read by the host computer is stored, in which the control unit detects an access from the host computer to the first interface and an access from the manager terminal to the second interface, and generates log data of operations according to the accesses. Accordingly, log data concerning every action and every operation of the storage system is maintained and stored. | 2012-09-20 |
20120239880 | METHOD AND SYSTEM TO LOCATE A STORAGE DEVICE - A request is received from a client machine via a web interface for content presented on a web page. A globally unique identifier (GUID) that is associated with the user is accessed and a number is generated based on the GUID. The generated number is utilized as an index to locate the storage device from the number of storage devices. Here, the storage device stores a user profile associated with the user. The user profile is read from the located storage device and the web page is personalized based on this user profile. The personalized web page is then communicated to the client machine. Other techniques for locating a storage device are also described. | 2012-09-20 |
20120239881 | INFORMATION DISPLAY DEVICE, METHOD OF DISPLAYING INFORMATION, AND COMPUTER PROGRAM - The position relating to a content can be displayed on map information using a portable storage medium. With respect to a content the visual information of which is to be displayed on a display unit ( | 2012-09-20 |
20120239882 | CONTROL APPARATUS AND METHOD, AND STORAGE APPARATUS - In a storage apparatus, in the case where a data block to be written to a storage medium is a zero data block containing only zero data, a zero data information memory stores zero data identification information indicating that the data block is a zero data block. A control apparatus receives a data block from an access requesting apparatus in association with a write request issued by the access requesting apparatus for writing the data block a specified number of times to a predetermined storage area of the storage medium, and when determining that the data block is a zero data block containing only zero data, sets zero data identification information in the zero data information memory, and when completing the setting of the zero data identification information, sends the access requesting apparatus a completion notice of the writing to the storage medium. | 2012-09-20 |
20120239883 | RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR - A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure. | 2012-09-20 |
20120239884 | MEMORY CONTROL DEVICE, MEMORY DEVICE, MEMORY CONTROL METHOD, AND PROGRAM - There is provided a memory control device including a device driver that executes writing or reading of data to/from a main storage unit and temporary writing or reading of data to/from a cache unit including a plurality of cache blocks, and a control unit that issues an instruction for writing or reading of data of a file system to/from the main storage unit or the cache unit to the device driver. The control unit may notify priority information about a priority for data storage into a logical block to which the cache block is associated to the device driver. | 2012-09-20 |
20120239885 | MEMORY HUB WITH INTERNAL CACHE AND/OR MEMORY ACCESS PREDICTION - A computer system includes a memory hub for coupling a processor to a plurality of synchronous dynamic random access memory (“SDRAM”) devices. The memory hub includes a processor interface coupled to the processor and a plurality of memory interfaces coupled to respective SDRAM devices. The processor interface is coupled to the memory interfaces by a switch. Each of the memory interfaces includes a memory controller, a cache memory, and a prediction unit. The cache memory stores data recently read from or written to the respective SDRAM device so that it can be subsequently read by processor with relatively little latency. The prediction unit prefetches data from an address from which a read access is likely based on a previously accessed address. | 2012-09-20 |
20120239886 | DELAYED UPDATING OF SHARED DATA - To provide delayed updating of shared data, a concept of dualistic sequence information is introduced. In the concept, if during local modification of data, a modification to the data is published by another user, a local deviation is created, and when the modification is published, it is associated with an unambiguous sequence reference and the local deviation. | 2012-09-20 |
20120239887 | METHOD AND APPARATUS FOR MEMORY CONTROL - A method is provided for issuing subcommands to a memory module using unassigned bits in a memory control protocol. A buffer component within the memory module receives the subcommands and modifies a state of the memory module accordingly. This allows, for example, selectively powering down individual ranks of the memory module (e.g., an LRDIMM memory module). Unassigned bits in a JEDEC-compliant ZQ calibration command set may be used for implementing such subcommands. | 2012-09-20 |
20120239888 | STORAGE APPARATUS AND CONTROLLING METHOD OF STORAGE APPARATUS - A storage apparatus including: a first controller that generates an access to a storage device; the first controller includes: a first relay unit configured to relay the access to the storage device; and an access control unit configured to be activated after activation of the first relay unit and to relay the access to the storage device via a second relay unit; and a second controller that includes the second relay unit and generates the access to the storage device, wherein when the first relay unit receives a connection request for an access path between the first relay unit and the storage device from the second controller, the first relay unit establishes the access path to the storage device irrespective of an activation state of the access control unit. | 2012-09-20 |
20120239889 | METHOD AND APPARATUS FOR WRITING DATA IN MEMORY SYSTEM - A method of writing data in a memory system comprises determining a characteristic of write data and generating characteristic information according to the determined characteristic, generating a write command corresponding to the write data, and sending the write command, the characteristic information, and the write data to the memory system. | 2012-09-20 |
20120239890 | MEMORY CELL OPERATION - The present disclosure includes memory devices and systems having memory cells, as well as methods for operating the memory cells. One or more methods for operating memory cells includes determining age information for a portion of the memory cells and communicating a command set for the portion of the memory cells, the command set including the age information. | 2012-09-20 |
20120239891 | DYNAMIC REUSE AND RECONFIGURATION OF LOGICAL DATA OBJECTS IN A VIRTUAL TAPE SYSTEM - A method in one embodiment for operating a virtual server supporting at least one Write Once Read Many (WORM) logical data object and at least one read-write logical object includes initializing a logical data object from a common pool of the logical data objects, the logical data object bound with a member of a media type group, the member of the media type group comprising a WORM logical data object and a read-write logical data object; and reusing one of the logical data objects as the member of the media type group without ejection and reinsertion by mounting the logical data object with a write from beginning of logical data object to bind at least one data attribute to the member of the media type group to replace any previous attribute and data associated with the logical data object. | 2012-09-20 |
20120239892 | COMPUTER SYSTEM AND PROCESS FOR TRANSFERRING MULTIPLE HIGH BANDWIDTH STREAMS OF DATA BETWEEN MULTIPLE STORAGE UNITS AND MULTIPLE APPLICATIONS IN A SCALABLE AND RELIABLE MANNER - Multiple applications request data from multiple storage units over a computer network. The data is divided into segments and each segment is distributed randomly on one of several storage units, independent of the storage units on which other segments of the media data are stored. At least one additional copy of each segment also is distributed randomly over the storage units, such that each segment is stored on at least two storage units. When an application requests a selected segment of data, the request is processed by the storage unit with the shortest queue of requests. Random fluctuations in the load applied by multiple applications on multiple storage units are balanced nearly equally over all storage units. These techniques result in a system which can transfer multiple, independent high-bandwidth streams of data in a scalable and reliable manner in both directions between multiple applications and multiple storage units. | 2012-09-20 |
20120239893 | METHODS FOR DYNAMIC CONSISTENCY GROUP FORMATION - A method for dynamic consistency group formation, in one embodiment, includes creating a snapshot of first data stored on a source storage system with respect to data content and data structure, copying the snapshot to a target storage system, detecting one or more write operations affecting data on the source storage system while copying the first data, detecting one or more collisions affecting the first data on the source storage system, wherein a collision occurs whenever the write operations affect the first data prior to the first data being written, setting a consistency group interval which represents an interval duration between successive snapshot create-and-copy events, and altering the consistency group interval to minimize collisions affecting data on at least one of the storage systems. Other methods for dynamic consistency group formation are also described. | 2012-09-20 |
20120239894 | BACKUP METHOD FOR PORTABLE DEVICE - An embodiment of the invention provides a backup method for a portable device. The method includes steps of: creating a first log file according to a first file that has to be stored in a backup device; connecting the portable device to the backup device; transmitting the first log file to the backup device; reading the first log file, by the backup device, and storing the first file to a storage device of the backup device; wherein the first log file is transmitted to the storage device via a buffer that is controlled by a controller of the backup device. | 2012-09-20 |
20120239895 | Memory Management Unit that Applies Rules Based on Privilege Identifier - A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the master, usually a CPU originating the request based on a Privilege Identifier that accompanies each memory access request. Deputy masters such as DMA controllers inherit the Privilege Identifier of the originating master. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request. | 2012-09-20 |
20120239896 | Optimized Shrinking of Virtual Disks - Various systems and methods shrinking a storage object. For example, one method can involve receiving a request to shrink the storage object. The storage object can comprise multiple storage locations. The method can also involve receiving a list that identifies a set of the storage locations. The list can be generated in response to the request to shrink the storage object. The method can also involve reading data from a set of storage locations in the storage object that are not identified in the received list and copying the read data from the first storage object to a second storage object. | 2012-09-20 |
20120239897 | STORAGE APPARATUS, METHOD FOR MOVING DATA, AND STORAGE SYSTEM - A storage apparatus includes a storage unit that stores received data, an investigation frame transmission unit that transmits investigation frames to a plurality of other storage apparatuses connected through a communication network, a performance information creation unit that creates performance information for the plurality of other storage apparatuses on the basis of reception results of response frames transmitted in response to the investigation frames, a destination determination unit that determines a destination storage apparatus from among the plurality of other storage apparatuses on the basis of the created performance information, and a movement process unit that executes a movement process in which the data is moved from the storage unit to the destination storage apparatus. | 2012-09-20 |
20120239898 | MEMORY SYSTEM WITH INDEPENDENTLY ADJUSTABLE CORE AND INTERFACE DATA RATES - An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value. | 2012-09-20 |
20120239899 | Leasing Fragmented Storage Between Processes - A mechanism is provided for leasing fragmented storage between processes. The mechanism comprises a fragmented memory manager associated with instances of virtual memory managers to provide a pool of memory that may lease from the owners of the memory and in turn sub-let the memory for use by other processes or owners. The mechanism allows programs to operate under normal conditions until fragmentation sets. A different memory manager leases those fragmented memory blocks from processes to create a virtually contiguous block of memory that it can sub-lease to processes in need of temporary expansion beyond the memory available for the processes under normal circumstances. | 2012-09-20 |
20120239900 | MEMORY CONTROLLER ADDRESS AND DATA PIN MULTIPLEXING - A system and a method for configuring a memory controller that communicates with a memory device muxes selected pins for the data transfer. The memory controller includes a set of pins where each pin of the set is associated with a data bit and an address bit. A programmable logic block is connected to the set of pins and uses a subset of the set of pins to enable data transfer between the memory device and the memory controller depending on the size of the memory device such that the pins not included in the subset are available for other applications. | 2012-09-20 |
20120239901 | DYNAMIC MEASUREMENT AND ADAPTATION OF A COPYING GARBAGE COLLECTOR - An illustrative embodiment of a computer-implemented process for dynamic measurement and adaptation of a parallel copying garbage collector initializes values and data structures, receives an evacuate set, determines whether a new copy block is required and responsive to a determination that a new copy block is required, calculates a size of the new copy block. The computer-implemented process further selects a survivor region from a list of survivor regions to form a selected survivor region, places a lock on the selected survivor region, identifies a number of threads enqueued on the selected survivor region, responsive to a determination that a contention value exceeds a predetermined value, increases a size of the list of survivor regions, evacuates blocks to the selected survivor region and responsive to a determination that more evacuate blocks do not exist, terminates. | 2012-09-20 |
20120239902 | AREA EFFICIENT COUNTERS ARRAY SYSTEM AND METHOD FOR UPDATING COUNTERS - A counters array system comprises a memory device having a plurality of addressable memory locations for storing counter-values; a plurality of delta-counter devices. Each delta-counter device is operable to hold a maximum delta-value corresponding to a maximum number of occurrences of an event during a time duration between two counter scans controlled by a scan control unit. Each delta-counter device has an input connected to receive a signal from an event source corresponding to an occurrence of the event, and an output connected to provide a delta-value representing an accumulated number of occurrences of the event to a delta-count update circuit. The delta-count update circuit is connected to the memory device and the counter scan control unit, and being arranged to receive the delta-value and an address of a corresponding counter-value, read the counter-value from the memory device, and provide an updated counter-value incremented by the delta-value to the memory device. | 2012-09-20 |
20120239903 | ADDRESS TRANSFORMING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - An address transforming circuit that can change a memory mapping when a system is booted includes a switch control signal generating circuit and an address transforming unit. The switch control signal generating circuit generates alternately enabled switch control signals synchronized with a reset signal. The address transforming unit transforms bits of a first address to generate a second address in response to the switch control signals. Accordingly, a semiconductor memory device including the address transforming circuit has a long lifetime and high reliability. | 2012-09-20 |
20120239904 | SEAMLESS INTERFACE FOR MULTI-THREADED CORE ACCELERATORS - A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator. | 2012-09-20 |
20120239905 | MULTI-CORE DISTRIBUTED PROCESSING FOR MACHINE VISION APPLICATIONS - Embodiments of an apparatus including a first processor core having a local agent running thereon, the agent comprising a local process and a proxy agent and a second processor core having a remote agent running thereon, the remote agent being an instance of the local agent. A shared memory wherein coupled to the first processor core and the second processor core, wherein the local agent and the remote agent communicate via the shared memory. Other embodiments are disclosed and claimed. | 2012-09-20 |
20120239906 | Launching A Secure Kernel In A Multiprocessor System - In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if the master processor is verified; and launching the trusted agent on a plurality of processors of the system if the trusted agent is validated. After execution of such a trusted agent, a secure kernel may then be launched, in certain embodiments. The system may be a multiprocessor server system having a partially or fully connected topology with arbitrary point-to-point interconnects, for example. | 2012-09-20 |
20120239907 | ACTIVE MEMORY COMMAND ENGINE AND METHOD - A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. | 2012-09-20 |
20120239908 | DUAL THREAD PROCESSOR - Pipeline processor architectures, processors, and methods are provided. A described processor includes thread allocation counters for corresponding processor threads. For example, a first counter is configured to store a first processor time allocation that controls first periods of processor time for a first processor thread, the first processor thread retaining control of the processor during each of the first periods of processor time. The processor causes data associated with the first processor thread to pass through the processor's pipeline during the first periods of processor time. A second counter is similarly configured. The processor can be configured to receive an input defining processor time to be allocated to one or more processor threads and to use the input to change one or more of the counters such that subsequent periods of processor times for the one or more processor threads are affected. | 2012-09-20 |
20120239909 | SYSTEMS AND METHODS FOR VOTING AMONG PARALLEL THREADS - One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread to post an individual vote within the context of the group of related threads and to receive the result of the vote. In this fashion, the vote instruction advantageously reduces overhead associated with inter-thread communication, thereby improving overall system performance. | 2012-09-20 |
20120239910 | CONDITIONAL EXTRACT INSTRUCTION FOR PROCESSING VECTORS - The described embodiments include a vector processor that executes a ConditionalExtract instruction. In the described embodiments, the processor receives an input scalar variable, an input vector, and a predicate vector, wherein each of the vectors has N elements. The processor then executes the ConditionalExtract instruction, which causes the processor to determine if at least one element in the predicate vector is active. If so, the processor copies a value from a last element in the input vector for which a corresponding element in the predicate vector is active into a scalar result variable. Otherwise, of no elements of the predicate vector are active, the processor copies a value from the input scalar variable into the scalar result variable. | 2012-09-20 |
20120239911 | VALUE CHECK INSTRUCTION FOR PROCESSING VECTORS - The described embodiments include a processor that executes a ValueCheck instruction. In the described embodiments, the processor receives an input vector and a predicate vector, each including N elements. The processor then executes a ValueCheck instruction, which causes the processor to generate a result vector. When generating the result vector, for each element in a set of elements in the input vector for which a corresponding element of the predicate vector is active, the processor determines if at least one of the elements in the set of elements precedes the element in the input vector and contains a different value than the element in the input vector. If so, the processor writes an identifier for a closest preceding active element that contains the different value into a corresponding element of a result vector. Otherwise, the processor writes a zero in the corresponding element of the result vector. | 2012-09-20 |
20120239912 | INSTRUCTION PROCESSING METHOD, INSTRUCTION PROCESSING APPARATUS, AND INSTRUCTION PROCESSING PROGRAM - An instruction processing method includes generating a translated code block for an instruction, among instructions included in a target program to be executed and for which a number of executions through sequential interpretation is greater than or equal to a threshold, and storing the generated translated code block in a first storage unit and removing part or all of the translated code block from the first storage unit at a given timing, wherein the generating reduces the threshold with respect to the number of executions over a given period of time after the part or all of the translated code block is removed. | 2012-09-20 |
20120239913 | DIAGNOSING CODE USING SINGLE STEP EXECUTION - A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception. | 2012-09-20 |
20120239914 | MULTITHREADED PARALLEL EXECUTION DEVICE, BROADCAST STREAM PLAYBACK DEVICE, BROADCAST STREAM STORAGE DEVICE, STORED STREAM PLAYBACK DEVICE, STORED STREAM RE-ENCODING DEVICE, INTEGRATED CIRCUIT, MULTITHREADED PARALLEL EXECUTION METHOD, AND MULTITHREADED COMPILER - When a temporary data storage unit | 2012-09-20 |
20120239915 | Interrupt Handling - Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a first instruction execution thread and (ii) a second instruction thread for execution by an execution block of the multi-thread processing environment; providing a first interrupt signal via a first interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the first instruction execution thread; and providing a second interrupt signal via a second interrupt signal line within the multi-thread processing environment to interrupt fetching and issuing of instructions of the second instruction execution thread. The first interrupt signal line and the second interrupt signal line are physically separate and distinct signal lines that are directly electrically coupled to one another. | 2012-09-20 |
20120239916 | WI-FI ROUTER WITH INTEGRATED TOUCH-SCREEN AND ENHANCED SECURITY FEATURES - A Wi-Fi router with an integrated configuration touch-screen, and method to use this integrated touch screen to provide enhanced security features. The Wi-Fi router, which has a wired or optical network interface, may be factory pre-configured with hard to anticipate passwords and encryption codes, thus making even its default Wi-Fi settings difficult to attack. Besides displaying interactive menus on the touch-screen, the router may also generate touch sensitive dynamic alphanumeric virtual keypads to enable administrators to interact with the device without the need of extra computers or software. Inexperienced administrators secure in the knowledge that they may access and change even difficult to remember security settings at any time through the built-in touch-screen controller and simplified user interface, are encouraged to set up secure Wi-Fi systems. The device may optionally include security software that, upon touch of a button, can provide new randomized or otherwise obfuscated router settings. | 2012-09-20 |
20120239917 | Secure Boot With Minimum Number of Re-Boots - Systems, methods and products are described that provide secure boot with a minimum number of re-boots. One aspect provides a method including receiving an indication to boot from a power off state at a computing device; responsive to authenticating a user at one or more input devices, releasing a value derived from authenticating the user at the one or more input devices; responsive to releasing the value, unlocking one or more encrypted drives with a previously established alternate credential; and thereafter proceeding to boot from the power off state. By not having to call the non-BIOS software each boot, this minimizes the number of reboots for each boot cycle. | 2012-09-20 |
20120239918 | EXPEDITED COMPUTER BOOT SYSTEM AND METHOD - The present invention discloses an expedited computer boot system and method. The expedited computer boot system includes: ROM, RAM, and a module for selecting a boot mode. The module for selecting a boot mode at least includes: a detecting unit and a fast boot unit. The fast boot unit reads configuration settings stored in the RAM and loads into operating system based on the configuration settings if the detecting unit detects no device changed. Otherwise, the fast boot unit reads ROM and Power-On Self Test (POST) is executed if any device is changed. Therefore, the computer system can quickly boot and the time for booting computer is shortened. | 2012-09-20 |
20120239919 | COMPUTER FACILITATING BIOS SETTING - A computer includes a mother board, a standby power source, a BIOS display, and a BIOS user input. The mother board includes a storage unit. The storage unit stores BIOS software and BIOS settings of the computer. The standby power source is configured for providing a standby voltage when the computer is powered but not started up. The controller is configured for reading the BIOS software and the BIOS settings from the storage unit, driving the BIOS display to display a BIOS UI based upon the BIOS software and the BIOS setting, and editing the BIOS settings based upon inputs from the BIOS input unit upon the condition that the controller, the BIOS display, and the BIOS input unit receive the standby voltage. | 2012-09-20 |
20120239920 | APPROACHES FOR UPDATING BIOS - Approaches for updating a Basic Input/Output System (BIOS) program used in a computer system. The computer system includes a central processing unit (CPU) and a non-volatile memory. The non-volatile memory is used to store the BIOS program, and the BIOS program includes a booting area and a program area for storing a first BIOS image file. The update method includes: duplicating a second BIOS image file from an external storage device of the computer system to a designated area of an internal non-volatile storage device of the computer system; changing a flag from a first status to a second status after the duplication is completed; checking the status of the first BIOS image file when the computer system is booted; and booting the computer system by the first BIOS image file or the second BIOS image file according to the status of the first BIOS image file. | 2012-09-20 |
20120239921 | Data Storewidth Accelerator - Data storage controllers and data storage devices employing lossless or lossy data compression and decompression to provide accelerated data storage and retrieval bandwidth. In one embodiment of the invention, a composite disk controller provides data storage and retrieval acceleration using multiple caches for data pipelining and increased throughput. In another embodiment of the invention, the disk controller with acceleration is embedded in the storage device and utilized for data storage and retrieval acceleration. | 2012-09-20 |
20120239922 | PREPARING AND PRESERVING A SYSTEM CONFIGURATION DURING A HOT UPGRADE - A planned system configuration is stored to a volatile memory coupled to a processor executing a first operating system kernel. The planned system configuration is tagged. A boot of a second operating system kernel is initiated while preserving in the volatile memory contents stored therein, and following the boot of the second operating system kernel, a set of parameters referencing the tagged planned system configuration is retrieved from the volatile memory. The planned system configuration is then used, based on the retrieved set of parameters. | 2012-09-20 |
20120239923 | Wireless Activation Of IP Devices - A method of activating a wireless IP device by providing access to an installer to a customer's personal router or modem/router combination and providing access to the installer to a wireless Access Point which is supplied by the installer where the Access Point has a first slot for a default SSID2 password for a first wireless IP device and a second slot for an SSID1 password for a second wireless IP device. Connecting a first wireless IP device while in its initial or default state to the first slot where the first device and the wireless Access Point have a common default SSID2 code and factory preprogrammed public key and where, as soon as the device is powered up, the IP device immediately begins communicating through the wireless access point and the customer's router or modem/router to the internet, checking into a control server. | 2012-09-20 |
20120239924 | SYSTEM AND METHOD FOR SEQUENTIALLY PROCESSING A BIOMETRIC SAMPLE - This invention provides for progressive processing of biometric samples to facilitate user verification. A security token performs initial processing. Due to storage and processing limitations, false rejections may occur. To overcome this, the biometric sample is routed to a stateless server with greater processing power and data enhancement capabilities. The stateless server processes and returns an enhanced biometric sample to the security token for another attempt at verification. In another embodiment, the security token may have a second failure when verifying the enhanced biometric sample. It can then send the enhanced or raw biometric sample to a stateful server. The stateful server processes the biometric sample and performs a one to many search of a biometric database having a master set of enrolled authorized user biometric templates. The security token uses signals from the stateful server to grant or deny access. In both embodiments, heuristics remain with the security token. | 2012-09-20 |
20120239925 | SECURE MESSAGING - A method for secure communication of a message. The method includes providing a message including a plurality of message packets, providing a nodal network including a plurality of nodes, where nodal operations are capable of execution on the message packets at the nodes, gaining, by a first node of the network, a first message packet, processing the first message packet by the first node, relinquishing the first message packet as processed by the first node, gaining, by any other node of the network, at least one other message packet, processing the other message packet by the other node, relinquishing the other message packet as processed by the other node, receiving, by a message destination node of the network, a first message packet, receiving, by the message destination node, at least a second message packet, and processing the first message packet and the second message packet to provide a reproduced message. | 2012-09-20 |
20120239926 | OBFUSCATED AUTHENTICATION SYSTEMS, DEVICES, AND METHODS - Embodiments of the present invention are directed toward authentication systems, devices, and methods. Obfuscated executable instructions may encode an authentication procedure and protect an authentication key. The obfuscated executable instructions may require communication with a remote certifying authority for operation. In this manner, security may be controlled by the certifying authority without regard to the security of the electronic device running the obfuscated executable instructions. | 2012-09-20 |
20120239927 | SYSTEM AND METHOD FOR SEARCHING AND RETRIEVING CERTIFICATES - A system and method for searching and retrieving certificates, which may be used in the processing of encoded messages. In one broad aspect, a method is provided in which a certificate search request is received, a search of one or more certificate servers for certificates satisfying the request is performed, located certificates are retrieved and processed at a first computing device to determine data that uniquely identifies each located certificate, and search result data comprising the determined data is communicated to a second device (e.g. a mobile device) for use in determining whether each located certificate is already stored on the second device. | 2012-09-20 |
20120239928 | Online Security Systems and Methods - Described are a system and method for securing an online transaction. A request is output from an electronic device to a verification server to perform an online transaction. The verification server generates a challenge request. The challenge request is encrypted with a private key of a pair of cryptographic keys. The encrypted challenge request is decrypted with a public key of the pair of cryptographic keys. The decrypted challenge request and the challenge request generated by the verification server are compared. A verification result is generated in response to the comparison. | 2012-09-20 |
20120239929 | HYBRID NETWORKING MASTER PASSPHRASE - A method and apparatus for providing a passphrase-based security setup for a hybrid network including multiple network interfaces configured for communicating over one or more communication media are provided. The method includes receiving a passphrase from a user at a network interface of the multiple network interfaces. The received passphrase is then used for authenticating the device for one or more network interfaces. The authentication can be performed irrespective of a communication medium used by the network interfaces. | 2012-09-20 |
20120239930 | Keyed PV Signatures - A system and method enabling a recipient correspondent of a keyed PV signature to convert it to a signature with properties similar to a traditional signature (i.e., where the message is public and may be verified by anyone), removing the keyed aspect of the signature. The recipient correspondent may transfer the converted signature to a third party and provide the third party with a proof of knowledge such that the third party may be convinced that the originator of the signature signed the message. | 2012-09-20 |
20120239931 | INFORMATION PROCESSING APPARATUS, RECOVERY APPARATUS, AND DISK RECOVERY METHOD - An information processing apparatus includes: a disk to store data; a transmitting and receiving unit to exchange information with a recovery apparatus over a network; an authentication processor to, when receiving a first authentication key from the recovery apparatus, perform an authentication process based on the first authentication key and a second authentication key; and a writing controller to write an image file to the disk upon the authentication performed by the authentication processor and issue a completion message to the recovery apparatus on completion of the writing. | 2012-09-20 |
20120239932 | METHOD FOR VERIFICATION OF THE CORRECT RECORDING OF INFORMATION - Method for verifying that an item of information relating to an issuer has been registered correctly by a receiving entity while preserving the issuer's privacy, which method includes the following steps: a) the information relating to the issuer is coded in an issuing entity and said coding is sent to the receiving entity; b) the receiving entity generates a content test on the basis of the information coded in step a), and the content test is subsequently sent to the issuing entity; and c) the issuer verifies that the content test corresponds to the information which has been coded | 2012-09-20 |
20120239933 | Methods and Devices Having a Key Distributor Function for Improving the Speed and Quality of a Handover - Embodiments relate to a key distributer node (AS) for a network, which comprises:
| 2012-09-20 |
20120239934 | CREATION OF USER DIGITAL CERTIFICATE FOR PORTABLE CONSUMER PAYMENT DEVICE - A method for creating a digital certificate for a user issued by a reliant party, where the reliant party relies on an established cryptographic infrastructure by a registration or certificate authority is described. The registration authority, typically a large financial or credit institution, has already performed the initial overhead steps necessary for a digital authentication system using a chip card. These steps include minting and distributing the chip card, establishing that the key pair and card are given to the right person, and creating the certificate library. The reliant party leverages this cryptographic infrastructure to issue its own digital certificate and certificate chain to a user already having a chip card from the registration authority. Consequently, a user can have additional digital certificates issued to him and stored at a user-specific memory in a remote certificate library without having the chip card modified. | 2012-09-20 |
20120239935 | SYSTEM FOR ENABLING DIGITAL SIGNATURE AUDITING - A computer method, computer system, and article for enabling digital signature auditing. The method includes the steps of: receiving at least one signature request issued by at least one application, forwarding a first data corresponding to the received at least one signature request to at least one signing entity for subsequent signature of the first data, storing an updated system state that is computed using a function of: i) a reference system state and ii) a second data corresponding to the received at least one signature request, where the reference system state and the updated system state attest to the at least one signature request, and repeating the above steps, using the updated system state as a new reference system state, where the steps of the method are executed at a server of a computerized system. | 2012-09-20 |
20120239936 | CREDENTIAL TRANSFER - Methods and apparatus, including computer program products, are provided for credential transfer. In one aspect there is provided a method. The method may include receiving, at a first device, an authorization token; determining, at the first device, a delegation token, one or more credentials, and metadata; and providing, by the first device to a second device, the delegation token, the one or more credentials, and the metadata. Related apparatus, systems, methods, and articles are also described. | 2012-09-20 |
20120239937 | INFORMATION PROCESSING DEVICE, COMPUTER PROGRAM PRODUCT, AND ACCESS CONTROL SYSTEM - According to an embodiment, an information processing device includes a key set generating unit configured to generate a key set including at least a public key and a master key; a secret key generating unit configured to generate different secret keys for each server device accessing the information processing device by using the master key included in the key set; a secret key providing unit configured to provide each of the secret keys generated by the secret key generating unit to a corresponding server device; and a public key providing unit configured to provide the public key to a verification device to make the verification device verify signature information generated by using the secret key in each of the server devices. | 2012-09-20 |
20120239938 | LOCAL STORAGE OF INFORMATION PEDIGREES - This disclosure describes techniques for dynamically assembling and utilizing a pedigree of a resource. A pedigree of a resource is a set of statements that describe a provenance of the resource. As described herein, a document may include local pedigree fragments and optionally one or more pointers to remote pedigree fragments not locally stored in the document. A pedigree fragment, generally, is a data structure that specifies a direct relationship between a first resource, e.g., a primary resource, and a second resource from which an asserted fact of the first resource is derived. Because a pedigree fragment specifies such direct relationships, a set of pedigree fragments may be used to assemble the complete pedigree of resource. | 2012-09-20 |
20120239939 | Secure Resume for Encrypted Drives - Systems, methods and products are described that provide secure resume for encrypted drives. One aspect provides a method including: receiving an indication to resume from a suspended state at a computing device; responsive to authenticating a user at one or more input devices, accessing a value in a BIOS derived from authenticating the user at the one or more input devices; responsive to accessing the value, releasing a credential for unlocking one or more encrypted drives; and thereafter proceeding to resume from the suspend state. | 2012-09-20 |
20120239940 | IDENTIFICATION BY MEANS OF CHECKING A USER'S BIOMETRIC DATA - The invention relates to a database ( | 2012-09-20 |
20120239941 | PROGRAMMABLE CONTROLLER SYSTEM, TOOL DEVICE, TOOL PROGRAM, STORAGE MEDIUM, AND PROGRAMMABLE CONTROLLER - A programmable controller system, a tool device, a tool program, a storage medium, and a programmable controller capable of affording greater convenience in terms of preventing unauthorized use of user program running on the programmable controller. In the programmable controller system, the tool device sets up a first user program execution ID in a second non-volatile memory provided in the PLC and sets up a second user program execution ID in a project provided in the tool device. The PLC performs a matching operation to determine whether or not the first user program execution ID matches the second user program execution ID and blocks the execution of the user program if there is a mismatch. | 2012-09-20 |