38th week of 2012 patent applcation highlights part 15 |
Patent application number | Title | Published |
20120235134 | NOVEL IRIDIUM COMPLEX AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME - A novel iridium complex includes a ligand including a phenyl ring and a pyrazole ring. The phenyl group is bonded to a triazine ring to form a backbone of the novel iridium complex. An organic light-emitting device includes the novel iridium complex. | 2012-09-20 |
20120235135 | NOVEL IRIDIUM COMPLEX, ORGANIC LIGHT-EMITTING DEVICE, AND IMAGE DISPLAY APPARATUS - There is provided a novel iridium complex having a small half-width of an emission spectrum and an organic light-emitting device that contains the iridium complex. There is provided a novel iridium complex that has a phenyl ring and a pyrazole ring as ligands and that has a basic skeleton in which the phenyl ring is bonded to a triazine ring. | 2012-09-20 |
20120235136 | ORGANIC ELECTROLUMINESCENT DEVICE - Disclosed is an organic electroluminescent device (organic EL device) which is improved in luminous efficiency, sufficiently secures driving stability, and has a simple configuration. The organic EL device of this invention comprises a light-emitting layer between an anode and a cathode piled one upon another on a substrate wherein the light-emitting layer contains a phosphorescent dopant and a 1,9-substituted carbazole compound as a host material. An example of the 1,9-substituted carbazole compound is represented by the following general formula (1). In formula (1), Ar is an aromatic hydrocarbon group or aromatic heterocyclic group; L is an aromatic hydrocarbon group or aromatic heterocyclic group; each of R | 2012-09-20 |
20120235137 | OXIDE SEMICONDUCTOR FILM, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used. In a transistor using an oxide semiconductor film for an active layer, a microvoid is provided in a source region and a drain region adjacent to a channel region. By providing a microvoid in the source region and the drain region formed in an oxide semiconductor film, hydrogen contained in the channel region of an oxide semiconductor film can be captured in the microvoid. | 2012-09-20 |
20120235138 | MASK LEVEL REDUCTION FOR MOFET - A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode. | 2012-09-20 |
20120235139 | Suspending Liquid or Solution for Organic Optoelectronic Device, Making Method thereof, and Applications - A suspension or solution for an organic optoelectronic device is disclosed. The composition of the suspension or solution includes at least one kind of micro/nano transition metal oxide and a solvent. The composition of the suspension or solution can selectively include at least one kind of transition metal oxide ions or a precursor of transition metal oxide. Moreover, the method of making and applications of the suspension or solution are also disclosed. | 2012-09-20 |
20120235140 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In an embodiment, an insulating film is formed over a flat surface; a mask is formed over the insulating film; a slimming process is performed on the mask; an etching process is performed on the insulating film using the mask; a conductive film covering the insulating film is formed; a polishing process is performed on the conductive film and the insulating film, so that the conductive film and the insulating film have equal thicknesses; the conductive film is etched, so that a source electrode and a drain electrode which are thinner than the conductive film are formed; an oxide semiconductor film is formed in contact with the insulating film, the source electrode, and the drain electrode; a gate insulating film covering the oxide semiconductor film is formed; and a gate electrode is formed in a region which is over the gate insulating film and overlaps with the insulating film. | 2012-09-20 |
20120235141 | SEMICONDUCTOR MEMORY SYSTEM - According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed. | 2012-09-20 |
20120235142 | SEMICONDUCTOR LIGHT EMITTING DIODE CHIP, METHOD OF MANUFACTURING THEREOF AND METHOD FOR QUALITY CONTROL THEREOF - There are provided a semiconductor light emitting diode chip, a method of manufacturing thereof, and a method for quality control using the same. The semiconductor light emitting diode chip includes a substrate; a light emitting diode in one area of the substrate and at least one fuse signature circuit formed in the other area of substrate so as to be electrically insulated from the light emitting diode. The fuse signature circuit includes a circuit unit having unique electrical characteristic value corresponding to wafer based process information and a plurality of electrode pads connected to the circuit unit. The semiconductor light emitting diode chip may include chip information marking representing information. | 2012-09-20 |
20120235143 | VERTICAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR - A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter. | 2012-09-20 |
20120235144 | ORGANIC LIGHT EMITTING DIODE DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting diode device includes a substrate, a thin film transistor on the substrate, a first pixel electrode electrically connected to the thin film transistor, a pixel defining layer on the first pixel electrode and partitioning a light emitting region, a second pixel electrode contacting the first pixel electrode at the light emitting region, a light emitting layer contacting the second pixel electrode at the light emitting region, and a common electrode on the light emitting layer; and a method of manufacturing the same is provided. | 2012-09-20 |
20120235145 | Printed Material Constrained By Well Structures And Devices Including Same - A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g., an operative transistor. | 2012-09-20 |
20120235146 | Organic Light-Emitting Display Device and Method of Manufacturing the Same - An organic light-emitting display device comprises: a lower substrate; an upper substrate facing the lower substrate; and a spacer formed in a sealed space between the lower substrate and the upper substrate and dividing the space into two or more sections; wherein air holes are formed in the spacer and allow air to flow between the sections of the space. | 2012-09-20 |
20120235147 | ORGANIC LIGHT-EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display device includes an organic light-emitting device, a thin film transistor (TFT) electrically connected to the organic light-emitting device, and a capacitor electrically connected to the organic light-emitting device, the capacitor including a first electrode layer and a second electrode layer opposite to each other, and a first insulating layer interposed as a single layer between the first electrode layer and the second electrode layer. | 2012-09-20 |
20120235148 | PHOTO-CROSSLINKABLE MATERIAL FOR ORGANIC THIN FILM TRANSISTOR INSULATING LAYER - A problem of the present invention is to provide an organic thin film transistor insulating layer material which is capable of forming a cross-linked structure without conducting a treatment at higher temperature, and which enables an organic thin film transistor to have a small absolute value of threshold voltage (Vth) when it is used for the formation of a gate insulating layer. The means for solving the problem is an organic thin film transistor insulating layer material including a macromolecular compound that has a repeating unit having a group containing a fluorine atom and a repeating unit having a photodimerization-reactive group. | 2012-09-20 |
20120235149 | ACTIVE MATRIX SUBSTRATE, PRODUCTION METHOD, AND DISPLAY DEVICE - Disclosed is an active matrix substrate ( | 2012-09-20 |
20120235150 | SEMICONDUCTOR DEVICE - A semiconductor device in which improvement of a property of holding stored data can be achieved. Further, power consumption of a semiconductor device is reduced. A transistor in which a wide-gap semiconductor material capable of sufficiently reducing the off-state current of a transistor (e.g., an oxide semiconductor material) in a channel formation region is used and which has a trench structure, i.e., a trench for a gate electrode and a trench for element isolation, is provided. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor enables data to be held for a long time. Further, since the transistor has the trench for a gate electrode, the occurrence of a short-channel effect can be suppressed by appropriately setting the depth of the trench even when the distance between the source electrode and the drain electrode is decreased. | 2012-09-20 |
20120235151 | HORIZONTAL POLYSILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR - A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter. | 2012-09-20 |
20120235152 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment includes: a polycrystalline semiconductor layer formed on an insulating film, the polycrystalline semiconductor layer including a first region and second and third regions each having a greater width than the first region, one of the second and third regions being connected to the first region; a gate insulating film formed at least on side faces of the first region of the polycrystalline semiconductor layer; a gate electrode formed on the gate insulating film; and gate sidewalls made of an insulating material, the gate sidewalls being formed on side faces of the gate electrode on sides of the second and third regions. Content of an impurity per unit volume in the first region is larger than content of the impurity per unit volume in the second and third regions. | 2012-09-20 |
20120235153 | Semiconductor Device and Method of Manufacturing the Same - In a semiconductor device, gate signal lines are spaced apart from each other above a crystalline semiconductor film. Therefore a first protective circuit is not electrically connected when contact holes are opened in an interlayer insulating film. The static electricity generated during dry etching for opening the contact holes moves from the gate signal line, damages a gate insulating film, passes the crystalline semiconductor film, and again damages the gate insulating film before it reaches the gate signal line. As the static electricity generated during the dry etching damages the first protective circuit, the energy of the static electricity is reduced until it loses the capacity of damaging a driving circuit TFT. The driving circuit TFT is thus prevented from suffering electrostatic discharge damage. | 2012-09-20 |
20120235154 | Semiconductor Device - To realize a semiconductor device including a capacitor element capable of obtaining a sufficient capacitor without reducing an opening ratio, in which a pixel electrode is flattened in order to control a defect in orientation of liquid crystal. A semiconductor device of the present invention includes a light-shielding film formed on the thin film transistor, a capacitor insulating film formed on the light-shielding film, a conductive layer formed on the capacitor insulating film, and a pixel electrode that is formed so as to be electrically connected to the conductive layer, in which a storage capacitor element comprises the light-shielding film, the capacitor insulating film, and the conductive layer, whereby an area of a region serving as the capacitor element can be increased. | 2012-09-20 |
20120235155 | DISPLAY DEVICE - The present invention is intended to suppress power consumption of an EL display. In accordance with the brightness of an image to be displayed in a pixel portion, the contrast of the image is determined whether to be inverted or not, and the number of bits of the digital video signal to be input into the pixel portion is reduced, and the magnitude of a current to flow through the EL element is allowed to be maintained at a constant level even when a temperature of an EL layer changes by providing the EL display with another EL element to be used for monitoring a temperature. | 2012-09-20 |
20120235156 | NITRIDE SEMICONDUCTOR DEVICE - According to one embodiment, a nitride semiconductor device includes a semiconductor layer, a source electrode, a drain electrode, a first and a second gate electrode. The semiconductor layer includes a nitride semiconductor. The source electrode provided on a major surface of the layer forms ohmic contact with the layer. The drain electrode provided on the major surface forms ohmic contact with the layer and is separated from the source electrode. The first gate electrode is provided on the major surface between the source and drain electrodes. The second gate electrode is provided on the major surface between the source and first gate electrodes. When a potential difference between the source and first gate electrodes is 0 volts, a portion of the layer under the first gate electrode is conductive. The first gate electrode is configured to switch a constant current according to a voltage applied to the second gate electrode. | 2012-09-20 |
20120235157 | LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - An LED includes a substrate, a first n-type GaN layer, a connecting layer, a second n-type GaN layer, a light emitting layer, and a p-type GaN layer formed on the substrate in sequence, the connecting layer being etchable by alkaline solution, a bottom surface of the second n-type GaN layer facing towards the connecting layer having a roughened exposed portion, the GaN on the bottom surface of the second n-type GaN layer having an N-face polarity, a blind hole extending through the p-type GaN layer, the light emitting layer and the second n-type GaN layer to expose the connecting layer, and an annular rough portion formed on the bottom surface of the second n-type GaN layer and surrounding each blind hole. | 2012-09-20 |
20120235158 | LIGHT EMITTING DEVICE HAVING A PLURALITY OF NON-POLAR LIGHT EMITTING CELLS AND A METHOD OF FABRICATING THE SAME - The present invention relates to a light emitting device having a plurality of non-polar light emitting cells and a method of fabricating the same. Nitride semiconductor layers are disposed on a Gallium Nitride substrate having an upper surface. The upper surface is a non-polar or semi-polar crystal and forms an intersection angle with respect to a c-plane. The nitride semiconductor layers may be patterned to form light emitting cells separated from one another. When patterning the light emitting cells, the substrate may be partially removed in separation regions between the light emitting cells to form recess regions. The recess regions are filled with an insulating layer, and the substrate is at least partially removed by using the insulating layer. | 2012-09-20 |
20120235159 | Group III Nitride Field Effect Transistors (FETS) Capable of Withstanding High Temperature Reverse Bias Test Conditions - Group III Nitride based field effect transistor (FETs) are provided having a power degradation of less than about 3.0 dB when operated at a drain-to-source voltage (V | 2012-09-20 |
20120235160 | Normally-Off Semiconductor Devices - Normally-off semiconductor devices are provided. A Group III-nitride buffer layer is provided. A Group III-nitride barrier layer is provided on the Group III-nitride buffer layer. A non-conducting spacer layer is provided on the Group III-nitride barrier layer. The Group III-nitride barrier layer and the spacer layer are etched to form a trench. The trench extends through the barrier layer and exposes a portion of the buffer layer. A dielectric layer is formed on the spacer layer and in the trench and a gate electrode is formed on the dielectric layer. Related methods of forming semiconductor devices are also provided herein. | 2012-09-20 |
20120235161 | GROUP III NITRIDE TEMPLATES AND RELATED HETEROSTRUCTURES, DEVICES, AND METHODS FOR MAKING THEM - A templated substrate includes a base layer, and a template layer is disposed on the base layer and having a composition including a single-crystal Group III nitride. The template layer includes a continuous sublayer on the base layer and a nanocolumnar sublayer on the first sublayer, wherein the nanocolumnar sublayer includes a plurality of nano-scale columns. | 2012-09-20 |
20120235162 | POWER CONVERTER - This power converter includes a power-conversion semiconductor element, an electrode conductor having a substantially flat upper end surface, and a sealant. The sealant allows the substantially flat upper end surface of the electrode conductor to be exposed at an upper surface of the sealant, and provides electrical connection with an external device at the upper end surface of the exposed electrode conductor. | 2012-09-20 |
20120235163 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR PRODUCING SEMICONDUCTOR SUBSTRATE - A semiconductor substrate includes: single crystal silicon; a mask material formed on a surface of the single crystal silicon and having an opening; a silicon carbide film formed on a portion exposed in the opening of the single crystal silicon; and a single crystal silicon carbide film formed so as to cover the silicon carbide film and the mask material. The mask material has a viscosity of 10 | 2012-09-20 |
20120235164 | TRANSISTOR WITH A-FACE CONDUCTIVE CHANNEL AND TRENCH PROTECTING WELL REGION - A transistor structure optimizes current along the A-face of a silicon carbide body to form an AMOSFET that minimizes the JFET effect in the drift region during forward conduction in the on-state. The AMOSFET further shows high voltage blocking ability due to the addition of a highly doped well region that protects the gate corner region in a trench-gated device. The AMOSFET uses the A-face conduction along a trench sidewall in addition to a buried channel layer extending across portions of the semiconductor mesas defining the trench. A doped well extends from at least one of the mesas to a depth within the current spreading layer that is greater than the depth of the trench. A current spreading layer extends between the semiconductor mesas beneath the bottom of the trench to reduce junction resistance in the on-state. A buffer layer between the trench and the deep well further provides protection from field crowding at the trench corner. | 2012-09-20 |
20120235165 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a substrate made of silicon carbide and having a main surface having an off angle of not less than −° and not more than +5° relative to a (0-33-8) plane in a <01-10> direction; a p type layer made of silicon carbide and formed on the main surface of the substrate by means of epitaxial growth; and an oxide film formed in contact with a surface of the p type layer. A maximum value of nitrogen atom concentration is 1×10 | 2012-09-20 |
20120235166 | LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, LIGHTING DEVICE, AND ELECTRONIC DEVICE - An object is to provide a light-emitting element which exhibits light emission with high luminance and can be driven at low voltage. Another object is to provide a light-emitting device or an electronic device with reduced power consumption. Between an anode and a cathode, n (n is a natural number of two or more) EL layers are provided, where between a first EL layer and a second EL layer, a first layer containing any of an alkali metal, an alkaline earth metal, a rare earth metal, an alkali metal compound, an alkaline earth metal compound, and a rare earth metal compound, a second layer containing a material having a high electron-transporting property in contact with the first layer, and a region containing a material having a high hole-transporting property and an acceptor material in contact with the second layer are provided in this order from the anode side. | 2012-09-20 |
20120235167 | SOLID STATE OPTOELECTRONIC DEVICE WITH PREFORMED METAL SUPPORT SUBSTRATE - A wafer-level process for manufacturing solid state lighting (“SSL”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. The preformed metal substrate can be bonded to the light emitting structure via a metal-metal bond, such as a copper-copper bond, or with an inter-metallic compound bond. | 2012-09-20 |
20120235168 | SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device includes a stacked structure body, first and second electrodes. The stacked structure body includes first and second semiconductor layers and a light emitting layer provided between the second and first semiconductor layers, and has first and second major surfaces. The first electrode has a first contact part coming into contact with the first semiconductor layer. The second electrode has a part coming into contact with the second semiconductor layer. A surface of the first semiconductor layer on a side of the first major surface has a first part having a part overlapping a contact surface with the first semiconductor layer and a second part having a part overlapping the second semiconductor layer. The second part has irregularity. A pitch of the irregularity is longer than a peak wavelength of emission light. The first part has smaller irregularity than the second part. | 2012-09-20 |
20120235169 | SEMICONDUCTOR LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD - A semiconductor light-emitting device and a method for manufacturing the same can include a wavelength converting layer encapsulating at least one semiconductor light-emitting chip to emit various colored lights including white light. The semiconductor light-emitting device can include a base board with the chip mounted thereon, a frame located on the base board, a transparent plate located on the wavelength converting layer, a reflective material layer disposed between the frame and both side surfaces of the wavelength converting layer and the transparent plate, and a light-absorbing layer located on the reflective material layer. The semiconductor light-emitting device can be configured to improve light-emitting efficiency and a contrast between a light-emitting and non-light-emitting surfaces by using the transparent material and light-absorbing layer. A wavelength-converted light that is emitted can have a high light-emitting efficiency and a high contrast between a light-emitting and non-light-emitting surface from a small light-emitting surface. | 2012-09-20 |
20120235170 | Display Apparatus and Method of Fabricating the Same - A display apparatus comprises a first substrate, a second substrate separated from the first substrate and facing the first substrate, and a first sealing portion interposed between the first substrate and the second substrate, wherein the first substrate comprises a first region overlapped by the second substrate and a second region not overlapped by the second substrate, and the first sealing portion is situated on a boundary between the first region and the second region and comprises one or more injection holes. | 2012-09-20 |
20120235171 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes a substrate having a plurality of organic light emitting elements thereon and a thin film encapsulation layer on the substrate. The thin film encapsulation layer covers the organic light emitting elements, and the thin film encapsulation layer includes a first porous inorganic layer and a second inorganic layer on the first porous inorganic layer. | 2012-09-20 |
20120235172 | THREE DIMENSIONAL LIGHT EMITTING DIODE SYSTEMS, AND COMPOSITIONS AND METHODS RELATING THERETO - A flexible layered structure is disclosed having a flexible top conductive layer, a flexible bottom heat sink layer and a flexible dielectric middle layer. The combination has a longitudinal axis and a plurality of defined positions spaced along the longitudinal axis. The defined positions can be used for aligning a circuit and/or for the placement of LED lights. The flexible layered structure can be easily bent to form a LED substrate for shining light in more than one direction while efficiently removing heat arising from the LEDs. | 2012-09-20 |
20120235173 | THREE DIMENSIONAL LIGHT EMITTING DIODE SYSTEMS, AND COMPOSITIONS AND METHODS RELATING THERETO - A flexible layered structure is disclosed having a flexible top conductive layer, a flexible bottom heat sink layer and a flexible dielectric middle layer. The combination has a longitudinal axis and a plurality of defined positions spaced along the longitudinal axis. The defined positions can be used for aligning a circuit and/or for the placement of LED lights. The flexible layered structure can be easily bent to form a LED substrate for shining light in more than one direction while efficiently removing heat arising from the LEDs. | 2012-09-20 |
20120235174 | LIQUID CRYSTAL PANEL AND PIXEL STRUCTURE THEREOF - There is provided a pixel structure of a liquid crystal panel including a transparent substrate, and a gate line, a data line, a switching transistor, a first electrode, a second electrode and a shield layer formed on the transparent substrate. The gate line is substantially perpendicular to the data line. The switching transistor is located adjacent to a crossing point of the gate line and the data line, and is configured to input a display voltage of the data line to the second electrode according to the control of the gate line. The first electrode and the second electrode are arranged in such a way that the display voltage forms a transverse electric field between the first electrode and the second electrode. The shield layer overlaps at least a part of the gate and is electrically isolated from the first electrode and the second electrode. | 2012-09-20 |
20120235175 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus that improves image quality characteristics, the organic light-emitting display apparatus including: a substrate; a first electrode formed on the substrate; a pixel-defining layer (PDL) formed on the first electrode to expose a set or predetermined region of the first electrode; an intermediate layer formed in the exposed predetermined region of the first electrode and including an organic emission layer; and a second electrode having a light-scattering face facing the substrate or facing oppositely away from the substrate, the second electrode being disposed on the intermediate layer. | 2012-09-20 |
20120235176 | Optoelectronic Module Comprising at Least One First Semiconductor Body Having a Radiation Outlet Side and an Insulation Layer and Method for the Production Thereof - An optoelectronic module is provided which comprises a first semiconductor body ( | 2012-09-20 |
20120235177 | SEMICONDUCTOR LIGHT EMITTING DEVICE WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE - According to one embodiment, a semiconductor light emitting device wafer includes a plurality of semiconductor light emitting devices, the plurality of semiconductor light emitting devices being collectively formed, and includes a light emitting unit and a wavelength conversion unit. The light emitting unit has a first major surface and a second major surface on a side opposite to the first major surface. The wavelength conversion unit is provided on the first major surface side. The wavelength conversion unit contains a fluorescer. A thickness of the wavelength conversion unit changes based on a distribution in a surface of the wafer of at least one selected from a wavelength and an intensity of light emitted from the light emitting unit of the plurality of semiconductor light emitting devices. | 2012-09-20 |
20120235178 | DISPLAY DEVICE AND ELECTRONIC APPARATUS - Disclosed herein is a display device including a plurality of pixels configured to have a first electrode, a light emitting layer, and a second electrode in that order over a substrate, wherein: the plurality of pixels include a first pixel having a first light emitting layer common to the pixels and a second pixel having the first light emitting layer and a second light emitting layer provided on each second pixel basis; and a surface of the first electrode in the first pixel is closer to the substrate than a surface of the first electrode in the second pixel. | 2012-09-20 |
20120235179 | Measuring Method, Inspection Method, Inspection Device, Semiconductor Device, Method of Manufacturing a Semiconductor Device, and Method of Manufacturing an Element Substrate - An inspection method which simplifies an inspection step by eliminating the need to set probes on wiring or probe terminals, and an inspection device for performing the inspection step. A voltage is applied to each of inspected circuits or circuit elements to operate the same. Signal processing is performed on an output from each inspected circuit or circuit element during operation to form a signal (operation information signal) including information on the operating condition of the circuit or the circuit element. The operation information signal is amplified and the amplitude of an alternating current voltage separately input is modulated with the amplified operation information signal. The voltage of the modulated alternating current is read in a non-contact manner to determine whether the corresponding circuit or circuit element is non-defective or defective. | 2012-09-20 |
20120235180 | Packaged Semiconductor Light Emitting Devices Having Multiple Optical Elements and Methods of Forming the Same - Methods of packaging a semiconductor light emitting device include providing a substrate having the semiconductor light emitting device on a front face thereof. A first optical element is formed from a first material on the front face proximate the semiconductor light emitting device but not covering the semiconductor light emitting device and a second optical element is formed from a second material, different from the first material, over the semiconductor light emitting device and the first optical element. Packaged semiconductor light emitting devices are also provided. | 2012-09-20 |
20120235181 | LIGHT-EMITTING DEVICE AND LAMP - A light-emitting device including: a base which is translucent; a semiconductor light-emitting element provided on the base; a sealing member for sealing the semiconductor light-emitting element and including a first wavelength conversion material for converting a wavelength of light emitted by the semiconductor light-emitting element to a predetermined wavelength; and a groove provided on a side of the semiconductor light-emitting element, recessed from a top surface of the base on which the semiconductor light-emitting element is provided or a back surface of the base which is a surface opposite to the top surface, and for holding a second wavelength conversion material for converting the wavelength of the light emitted by the semiconductor light-emitting element to the predetermined wavelength. | 2012-09-20 |
20120235182 | Light-Emitting Diode Module and Corresponding Manufacturing Method - A new manufacturing method is described by the present invention for a new LED module | 2012-09-20 |
20120235183 | LIGHT EMITTING DEVICE, ILLUMINATION APPARATUS AND DISPLAY APPARATUS - Disclosed herein is a light emitting device including: an organic layer sandwiched between a first electrode and a second electrode to serve as an organic layer including a light emitting layer for emitting monochromatic light at one location; a first light reflection boundary face provided on a side close to the first electrode to serve as a boundary face for reflecting light emitted from the light emitting layer so as to radiate the reflected light from a side close to the second electrode; and a second light reflection boundary face, a third light reflection boundary face and a fourth light reflection boundary face which are sequentially provided at positions separated away from each other in a direction from the first electrode to the second electrode on the side close to the second electrode. | 2012-09-20 |
20120235184 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a light emitting section and a wavelength conversion section. The light emitting section is configured to emit light. The wavelength conversion section is provided on one major surface side of the light emitting section. The wavelength conversion section contains a phosphor. The wavelength conversion section has a distribution of amount of the phosphor based on a distribution of wavelength of the light emitted from the light emitting section. | 2012-09-20 |
20120235185 | DISPLAY - Disclosed herein is a display including an acceptor substrate having thereon a red light-emitting element column, a green light-emitting element column, and a blue light-emitting element column that are arranged along a row direction and are each obtained by arranging rectangular organic light-emitting elements for generating light of one of red, green, and blue along a longitudinal direction of the organic light-emitting elements. | 2012-09-20 |
20120235186 | Color-Temperature-Tunable Device - A color-temperature-tunable device comprises a first light emitting diode (LED) chip group comprising at least one first blue LED chip that emits a first light having a first peak wavelength, a second LED chip group comprising at least one second blue LED chip that emits a second light having a second peak wavelength different from the first peak wavelength, and a wavelength converting layer above at least a portion of the first LED chip group and a portion of the second LED chip group. The first LED chip group and the second LED chip group are driven by a first driving current and a second driving current, respectively. | 2012-09-20 |
20120235187 | Light Source with Inner and Outer Bodies - A light-emitting device having an inner reflective body and an outer non-reflective body is disclosed. The inner reflective body defines a reflector configured to reflect light. In one embodiment, the outer non-reflective body encloses the inner reflective body to minimize reflectivity of the light-emitting device. When assembled into an infotainment display system, the outer non-reflective body may be configured to reduce reflection of ambient light and hence, increase contrast ratio of the display. Reliability performance of the light-emitting device may be improved by using interlocking aperture at the lead frame, interlock structure and interlock geometries defined by the inner reflective body and the outer non-reflective body. | 2012-09-20 |
20120235188 | Method and Apparatus for a Flat Top Light Source - A light-emitting device and method for manufacturing the device are disclosed. In one embodiment, the light-emitting device comprises a flat substrate and an encapsulation layer formed above the flat substrate. The top portion of the encapsulation layer is flat and the encapsulation layer is divided into a high density layer and a low density layer. The high density layer is formed from a wavelength-converting material precipitated on one side of the encapsulation layer. In the low density layer, the wavelength-converting material exists in particle form suspended within the encapsulation layer. | 2012-09-20 |
20120235189 | LIGHT-EMITTING DEVICE - This disclosure discloses a light-emitting device. The light-emitting device comprises: a substrate; an intermediate layer formed on the substrate; a transparent bonding layer; a first semiconductor window layer bonded to the semiconductor layer through the transparent bonding layer; and a light-emitting stack formed on the first semiconductor window layer. The intermediate layer has a refractive index between the refractive index of the substrate and the refractive index of the first semiconductor window layer. | 2012-09-20 |
20120235190 | ENCAPSULANT WITH INDEX MATCHED THIXOTROPIC AGENT - Emitter packages are disclosed having a thixotropic agent or material, with the encapsulant exhibiting significant reduction of thixotropic agent scattering. The packages exhibit a corresponding reduction or elimination of encapsulant clouding and increased package emission efficiency. This allows for the thixotropic agents to be included in the encapsulant to alter certain properties (e.g. mechanical or thermal) while not significantly altering the optical properties of the encapsulant. One embodiment of a light emitting diode (LED) package according to the present invention comprises an LED chip with an encapsulant over the LED chip. The encapsulant has an encapsulant refractive index and also has a thixotropic material with a refractive index that is substantially the same as the encapsulant refractive index. | 2012-09-20 |
20120235191 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND PHOTOCOUPLER - According to one embodiment, a semiconductor light emitting device includes a light emitting layer, a first layer, a second layer and a distributed Bragg reflector. The light emitting layer has a first and second surfaces and is capable of emitting emission light having a peak wavelength in a range of 740 nm or more and 830 nm or less. The first layer is provided on a side of the first surface and has a light extraction surface. The second layer is provided on a side of the second surface. The distributed Bragg reflector layer is provided on a side of the second layer. A third and fourth layers are alternately stacked. The distributed Bragg reflector layer is capable of reflecting the emission light toward the light extraction surface. The third and fourth layers each have a bandgap wavelength shorter than the peak wavelength. | 2012-09-20 |
20120235192 | LIGHT EMITTING DIODE PACKAGE - A light emitting diode package comprises a light emitting diode chip, a first luminescent conversion layer and a separate second luminescent conversion layer on the first luminescent conversion layer. The first luminescent conversion layer has a first luminescent conversion element surrounding the light emitting diode chip. The second luminescent conversion layer has a second luminescent conversion element located above the light emitting diode chip. An excitation efficiency of the first luminescent conversion element is higher than that of the second luminescent conversion element. | 2012-09-20 |
20120235193 | LED PACKAGE - An LED package comprises a substrate, a reflector, a light-absorbing layer, an encapsulation layer and an LED chip. The light-absorbing layer is located around the reflector and is able to absorb any light which penetrates through the reflector. Therefore, any vignetting or halation of light from the LED package is prevented. Moreover, the LED package can be constructed on a very small scale with no reduction in its color rendering properties. | 2012-09-20 |
20120235194 | LIGHT EMITTING DIODE PACKAGE - An LED package includes an insulated frame, a first metallic conductor and a second metallic conductor, a chip and an encapsulation. The insulated frame has a receiving groove defined therein. The two metallic conductors are both mounted on bottom of the insulated frame and separated from each other. The chip is placed in the receiving groove and electrically connected to the two metallic conductors. The encapsulation is located in the receiving groove. The first metallic conductor and the second metallic conductor each comprise a mounting portion exposed to the receiving groove and a reflecting portion extending from the mounting portion into the insulated frame. The first reflecting portion and the second reflecting portion cooperatively surround the receiving groove of the insulated frame. | 2012-09-20 |
20120235195 | LEDS WITH EFFICIENT ELECTRODE STRUCTURES - Aspects include electrodes that provide specified reflectivity attributes for light generated from an active region of a Light Emitting Diode (LED). LEDs that incorporate such electrode aspects. Other aspects include methods for forming such electrodes, LEDs including such electrodes, and structures including such LEDs. | 2012-09-20 |
20120235196 | LIGHT EMITTING DEVICE AND PROJECTOR - A light emitting device includes a first layer that generates light by injection current and forms a waveguide for the light, and an electrode that injects the current into the first layer, wherein the waveguide of the light has a first region, a second region, a third region, and a fourth region, the first region and the second region are connected at a first reflection part, the first region and the third region are connected at a second reflection part, the second region and the third region are tilted at the same angle and connected to an output surface, a distance between the fourth region and at least one of the first region, the second region, and the third region is a distance that produces evanescent coupling, and the fourth region forms a resonator. | 2012-09-20 |
20120235197 | ORGANIC EL DEVICE - An organic EL device includes a substrate, a first electrode layer arranged on the substrate, an organic EL layer arranged on the first electrode layer, an optical property adjusting layer arranged on the organic EL layer, and a second electrode layer arranged on the optical property adjusting layer. | 2012-09-20 |
20120235198 | LIGHT EMITTING DIODE PACKAGE STRUCTURE - The invention provides a light emitting diode package structure, including: a light emitting diode chip formed on a substrate; a composite coating layer formed on the light emitting diode chip, wherein the composite coating layer comprises a first coating layer and a second coating layer, and the composite coating layer has a reflectivity greater than 95% at the wavelength of 500-800 nm; a cup body formed on the substrate, wherein the cup body surrounds the light emitting diode chip; and an encapsulation housing covering the light emitting diode chip, wherein the encapsulation housing comprises a wavelength transformation material. | 2012-09-20 |
20120235199 | POWER SURFACE MOUNT LIGHT EMITTING DIE PACKAGE - A light emitting die package is provided which includes a metal substrate having a first surface and a first conductive lead on the first surface. The first conductive lead is insulated from the substrate by an insulating film. The first conductive lead forms a mounting pad for mounting a light emitting device. The package includes a metal lead electrically connected to the first conductive lead and extending away from the first surface. | 2012-09-20 |
20120235200 | LED DEVICE HAVING A DOME LENS - A light emitting device comprises an LED die, a dome lens encapsulating the LED die, the dome lens having a first outer curved surface, and a photopolymerizable composition disposed on the dome lens. The photopolymerizable composition forms a meniscus lens defined by a second outer curved surface and an inner curved surface, the inner curved surface being in contact with only a portion of the first outer curved surface. The dome lens and the meniscus lens in combination form an elongated dome lens. | 2012-09-20 |
20120235201 | SYSTEM AND METHOD FOR LED PACKAGING - System and method for LED packaging. The present invention is directed to optical devices. More specifically, embodiments of the presentation provide LED packaging having one or more reflector surfaces. In certain embodiments, the present invention provides LED packages that include thermal pad structures for dissipating heat generated by LED devices. In particular, thermal pad structures with large surface areas are used to allow heat to transfer. In certain embodiments, thick thermally conductive material is used to improve overall thermal conductivity of an LED package, thereby allowing heat generated by LED devices to dissipate quickly. Depending on the application, thermal pad structure, thick thermal conductive layer, and reflective surface may be individually adapted in LED packages or used in combinations. There are other embodiments as well. | 2012-09-20 |
20120235202 | Light Emitting Device and Method of Manufacturing a Light Emitting Device - A light emitting device comprising a heat sink, a dielectric layer arranged on the heat sink, a heat conductive layer arranged on the dielectric layer, an undercoating arranged on at least a part of the heat conductive layer, and a light emitting chip attached to the heat conductive layer by means of the undercoating. | 2012-09-20 |
20120235203 | METHOD FOR PRODUCING NANOPARTICLES - Some embodiments disclosed herein are related to methods of preparing a nanoparticle composition comprising: providing an aerosol comprising a plurality of droplets of a precursor solution comprising at least one nanoparticle precursor and an expansive component; passing the aerosol through a plasma; and collecting a nanoparticle composition product from the carrier gas which has exited the plasma. Some embodiments relate to nanoparticle compositions provided by this process. Some embodiments relate to light-emitting diodes or light emitting devices comprising these compositions. | 2012-09-20 |
20120235204 | SEMICONDUCTOR LIGHT EMITTING ELEMENT, LIGHT EMITTING DEVICE USING SEMICONDUCTOR LIGHT EMITTING ELEMENT, AND ELECTRONIC APPARATUS - Disclosed is a semiconductor light emitting element ( | 2012-09-20 |
20120235205 | LIGHT EMITTING CHIP AND METHOD FOR MANUFACTURING THE SAME - A light emitting chip includes a substrate, a buffer layer, a cap layer and a light emitting structure. The buffer layer is formed on the substrate and includes a carbon nano tube structure substantially parallel to the substrate. The carbon nano tube structure is comprised of nitride semiconductor. The cap layer grows from the buffer layer. The light emitting structure is formed on the cap layer. The light emitting structure sequentially includes a first cladding layer connected to the cap layer, a light emitting layer, and a second cladding layer. | 2012-09-20 |
20120235206 | LIGHTING DEVICE AND METHOD FOR CONTACTING A LIGHTING DEVICE - A lighting device may include a printed circuit board, wherein the printed circuit board has wiring on at least one of the front side and the back side thereof, the respective wiring is covered by at least one potting layer, the lighting device furthermore has at least one electrically conductive punched bushing and the punched bushing extends through a potting layer at least to the wiring and contacts the wiring. | 2012-09-20 |
20120235207 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An organic light emitting diode display includes: a substrate; a display area including an organic light emitting element on the substrate; an organic encapsulation layer covering the organic light emitting element and having a second boundary spaced from a first boundary of the display area by a first distance; and an inorganic encapsulation layer having a peripheral area contacting the substrate and covering the organic encapsulation layer. | 2012-09-20 |
20120235208 | Semiconductor Mismatch Reduction - A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches. | 2012-09-20 |
20120235209 | High Voltage Rectifier and Switching Circuits - According to one exemplary embodiment, a rectifier circuit includes a diode. A first depletion-mode transistor is connected to a cathode of the diode. Also, at least one second depletion-mode transistor is in parallel with the first depletion-mode transistor and is configured to supply a pre-determined current range to a cathode of the diode. A pinch off voltage of the at least one second depletion-mode transistor can be more negative than a pinch off voltage of the first depletion-mode transistor and the at least one second depletion-mode transistor can be configured to supply the pre-determined current range while the first depletion-mode transistor is OFF. Also, the pre-determined current range can be greater than a leakage current of the first depletion-mode transistor. | 2012-09-20 |
20120235210 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD AND TRANSISTOR CIRCUIT - A transistor circuit includes a first high electron mobility transistor and a second high electron mobility transistor having a negative threshold voltage, wherein a source of the second high electron mobility transistor is coupled to a gate of the first high electron mobility transistor, and a gate of the second high electron mobility transistor is coupled to a source of the first high electron mobility transistor. | 2012-09-20 |
20120235211 | Cross-Point Memory Structures - Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction. | 2012-09-20 |
20120235212 | BACKSIDE-ILLUMINATED (BSI) IMAGE SENSOR WITH REDUCED BLOOMING AND ELECTRICAL SHUTTER - Embodiments of a pixel including a photosensitive region formed in a surface of a substrate and an overflow drain formed in the surface of the substrate at a distance from the photosensitive area, an electrical bias of the overflow drain being variable and controllable. Embodiments of a pixel including a photosensitive region formed in a surface of a substrate, a source-follower transistor coupled to the photosensitive region, the source-follower transistor including a drain, and a doped bridge coupling the photosensitive region to the drain of the source-follower transistor. | 2012-09-20 |
20120235213 | SEMICONDUCTOR STRUCTURE WITH A STRESSED LAYER IN THE CHANNEL AND METHOD FOR FORMING THE SAME - The present invention provides a semiconductor structure with a stressed layer in the channel and method for forming the same. The semiconductor structure comprises a substrate; a gate stack, including a gate dielectric layer formed over the substrate, gate layer formed over the gate dielectric layer, a source region and a drain region formed in the substrate by both sides of the gate stack; one or more spacers formed on both sides of the gate stack; and an embedded stressed layer formed under the gate stack in the substrate. In the embodiments of the present invention, the carrier mobility can be effectively increased by the embedded stressed layer added in the channel under the gate stack, so that the driving current of transistors is improved. Moreover, the technological process for forming this embedded stressed layer in the present invention has a lower thermal budget, which therefore assists in maintaining a higher stress level in the channel region. Besides, apart from the advantage in the aspect of stress, the embedded stressed layer in the channel can further decrease the diffusion/invasion of B (boron) from the heavily doped source and drain regions. | 2012-09-20 |
20120235214 | LOCALLY 2 SIDED CHC DRAM ACCESS TRANSISTOR STRUCTURE - A method for forming a DRAM memory with a two-sided transistor includes: providing a silicon finFET structure having at least two fins, and a trench between the fins; forming high ohmic gates on either side of the fins; forming a hole between each pair of high ohmic gates to enable connection between the pair of high ohmic gates; forming a gate on one side of the trench and underneath one of the pair of high ohmic gate; forming a layer of oxide over the gate; and depositing tungsten in the trench to form a thick layer of metal at the bottom to form a word line. | 2012-09-20 |
20120235215 | PERFORMANCE ENHANCEMENT IN TRANSISTORS BY REDUCING THE RECESSING OF ACTIVE REGIONS AND REMOVING SPACERS - Sophisticated transistors for semiconductor devices may be formed on the basis of a superior process sequence in which an increased space between closely spaced gate electrode structures may be obtained in combination with a reduced material loss in the active regions. To this end, an offset spacer conventionally used for laterally profiling the drain and source extension regions is omitted and the spacer for the deep drain and source areas may be completely removed. | 2012-09-20 |
20120235216 | DAMASCENE METAL GATE AND SHIELD STRUCTURE, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Semiconductor structures with damascene metal gates and pixel sensor cell shields, methods of manufacture and design structures are provided. The method includes forming a dielectric layer over a dummy gate structure. The method further includes forming one or more recesses in the dielectric layer. The method further includes removing the dummy gate structure in the dielectric layer to form a trench. The method further includes forming metal in the trench and the one more recesses in the dielectric layer to form a damascene metal gate structure in the trench and one or more metal components in the one or more recesses. | 2012-09-20 |
20120235217 | Semiconductor Constructions - Some embodiments include methods in which a pair of spaced-apart adjacent features is formed over a substrate. The features have silicon dioxide surfaces. Silicon nitride is deposited between the features. A first region of the silicon nitride is protected with a mask while a second region is not. The second region is removed to form an opening between the features. Some embodiments include semiconductor constructions that contain a pair of spaced-apart adjacent features. The features are lines extending along a first direction, and are spaced from one another by a trench. Alternating plugs and intervening materials are within the trench, with the plugs and intervening materials alternating along the first direction. The intervening materials consist of silicon nitride, and the plugs have lateral peripheries that directly contact silicon dioxide of the features, and that directly contact silicon nitride of the intervening regions. | 2012-09-20 |
20120235218 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a device includes a semiconductor substrate, a first region including a first well which is formed in substrate, a second well which is formed in substrate and on first well, and a memory cell which is formed on second well, and a second region including a third well which is formed in substrate, and a first transistor which is formed on third well. The device includes a third region including a second transistor which is formed on semiconductor substrate, and a fourth region including a fourth well which is formed in semiconductor substrate, a fifth well which is formed in substrate and on fourth well, and a third transistor which is formed on fifth well. Bottoms of first well and fourth well are lower than a bottom of third well, and bottom of third well is lower than bottoms of second well and fifth well. | 2012-09-20 |
20120235219 | SEMICONDUCTOR MEMORY - In one embodiment, there is provided a semiconductor memory that includes: a semiconductor substrate having a channel region; a first tunnel insulating film on the channel region; a first fine particle layer on the first tunnel insulating film, the first fine particle layer including first conductive fine particles; a second tunnel insulating film on the first fine particle layer; a second fine particle layer on the second tunnel insulating film, the second fine particle layer including second conductive fine particles; a third tunnel insulating film on the second fine particle layer; a third fine particle layer on the third tunnel insulating film, the third fine particle layer including third conductive fine particles. A mean particle diameter of the second conductive fine particles is larger than that of the first conductive fine particles and that of the third conductive fine particles. | 2012-09-20 |
20120235220 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a substrate, a stacked body, a first insulating film, a charge storage film, a second insulating film and a channel body. The stacked body includes a plurality of electrode layers and insulating layers which are alternately stacked above the substrate. The first insulating film is provided on a side wall of a hole which is formed through the stacked body. The charge storage film is provided on an inner side of the first insulating film. The charge storage film includes a protrusion part which protrudes toward the electrode layer with facing the electrode layer and has a film thickness thicker than a film thickness of a part other than the protrusion part. The second insulating film is provided on an inner side of the charge storage film. The channel body is provided on an inner side of the second insulating film. | 2012-09-20 |
20120235221 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body. | 2012-09-20 |
20120235222 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A device isolation film has a first height in a first area and a second height higher than the first height in a second area. The first area includes a first end of a dummy memory transistor facing a memory string and a part of a device isolation film adjacent thereof. The second area includes a second end of the dummy memory transistor facing a select transistor and a part of the device isolation film adjacent thereof. | 2012-09-20 |
20120235223 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory including a first gate insulating film formed on a channel region of a semiconductor substrate, a first particle layer formed in the first gate insulating film, a charge storage part formed on the first gate insulating film, a second gate insulating film which is formed on the charge storage part, a second particle layer formed in the second gate insulating film, and a gate electrode formed on the second gate insulating film. The first particle layer includes first conductive particles that satisfy Coulomb blockade conditions. The second particle layer includes second conductive particles that satisfy Coulomb blockade conditions and differs from the first conductive particles in average particle diameter. | 2012-09-20 |
20120235224 | Circuit and Method for a Three Dimensional Non-Volatile Memory - An architecture, circuit and method for providing a very dense, producible, non volatile FLASH memory with SONOS cells. SONOS memory cells are formed using a uniformly doped channel region. A FinFET embodiment cell is disclosed. Because the novel SONOS cells do not rely on diffused regions, the cells may be formed into a three dimensional array of cells without diffusion problems. FLASH memory arrays are formed by forming layers of NAND Flash cells in the local interconnect layers of an integrated circuit, with the metal layers forming the global bit line conductors. The three dimensional non-volatile arrays formed of the SONOS cells rely on conventional semiconductor processing. P-channel and n-channel devices may be used to form the SONOS non-volatile cells. | 2012-09-20 |
20120235225 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process. | 2012-09-20 |
20120235226 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory of an aspect of the present invention includes a memory cell including, a charge storage layer on a gate insulating film, a multilayer insulator on the charge storage layer, and a control gate electrode on the multilayer insulator, the gate insulating film including a first tunnel film, a first high-dielectric-constant film on the first tunnel film and offering a greater dielectric constant than the first tunnel film, and a second tunnel film on the first high-dielectric-constant film and having the same configuration as that of the first tunnel film, the multilayer insulator including a first insulating film, a second high-dielectric-constant film on the first insulating film and offering a greater dielectric constant than the first insulating film, and a second insulating film on the second high-dielectric-constant film and having the same configuration as that of the first insulating film. | 2012-09-20 |
20120235227 | Power Semiconductor Device - A semiconductor device includes a vertical power semiconductor chip including a semiconductor layer. A first terminal is at a first side of the semiconductor layer and a second terminal is at a second side of the semiconductor layer opposite the first side along a first direction. A drift zone is within the semiconductor layer between the first terminal and the second terminal. The drift zone has, in a central part, a compressive stress of at least 100 MPa along a second direction perpendicular to the first direction. The central part extends from 40% to 60% of an overall extension of the drift zone along the first direction and into a depth of the semiconductor layer of at least 10 μm with respect to at least one of the first side and the second side of the semiconductor layer. | 2012-09-20 |
20120235228 | TRANSISTOR STRUCTURE AND METHOD FOR PREPARING THE SAME - A buried channel transistor structure includes a semiconductor substrate; a conductive block positioned in the semiconductor substrate; a gate dielectric layer positioned between the conductive block and the semiconductor substrate; and a bulge-shaped dielectric structure positioned on the conductive block and the gate dielectric layer. | 2012-09-20 |
20120235229 | INTER-POLY DIELECTRIC IN A SHIELDED GATE MOSFET DEVICE - In one general aspect, an apparatus can include a shield dielectric disposed within a trench aligned along an axis within an epitaxial layer of a semiconductor, and a shield electrode disposed within the shield dielectric and aligned along the axis. The apparatus can include a first inter-poly dielectric having a portion intersecting a plane orthogonal to the axis where the plane intersects the shield electrode, and a second inter-poly dielectric having a portion intersecting the plane and disposed between the first inter-poly dielectric and the shield electrode. The apparatus can also include a gate dielectric having a portion disposed on the first inter-poly dielectric. | 2012-09-20 |
20120235230 | MOSFET DEVICE WITH THICK TRENCH BOTTOM OXIDE - In one general aspect, an apparatus can include a first trench oxide disposed within a first trench of an epitaxial layer and having a trench bottom oxide disposed below a gate portion of the first trench oxide. The apparatus can include a second trench disposed lateral to the first trench. The trench bottom oxide portion of the first oxide can have a thickness greater than a distance within the epitaxial layer from the first trench to the second trench. | 2012-09-20 |
20120235231 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided. A second area is disposed between first and third areas. An epitaxial layer is on a substrate. A body layer is in the epitaxial layer in first and second areas. First and second gates are in the body layer and in a portion of the epitaxial layer. The first gate is in the substrate and partially in first and second areas. The second gate is in the substrate and partially in second and third areas. A first contact plug is in a portion of the body layer in the first area. A second contact plug is at least in the epitaxial layer in the third area and contacts the epitaxial layer and the second gate. The first contact plug is electrically connected to the second contact plug. A first doped region is in the body layer between the first contact plug and the first gate. | 2012-09-20 |
20120235232 | Short Channel Lateral MOSFET - A short channel Lateral MOSFET (LMOS) and method are disclosed with interpenetrating drain-body protrusions (IDBP) for reducing channel-on resistance while maintaining high punch-through voltage. The LMOS includes lower device bulk layer; upper source and upper drain region both located atop lower device bulk layer; both upper source and upper drain region are in contact with an intervening upper body region atop lower device bulk layer; both upper drain and upper body region are shaped to form a drain-body interface; the drain-body interface has an IDBP structure with a surface drain protrusion lying atop a buried body protrusion while revealing a top body surface area of the upper body region; gate oxide-gate electrode bi-layer disposed atop the upper body region forming an LMOS with a short channel length defined by the horizontal length of the top body surface area delineated between the upper source region and the upper drain region. | 2012-09-20 |
20120235233 | FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME - The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer. | 2012-09-20 |