38th week of 2014 patent applcation highlights part 98 |
Patent application number | Title | Published |
20140268966 | HIGH-VOLTAGE INVERTER - An inverter includes transformers having identical characteristics. Exciting windings of the transformers are connected in parallel so that the transformers are excited simultaneously. Output windings of the transformers are connected in series so that waveforms of output voltages of the output windings are time-synchronized. Each transformer includes a core having an identical shape and including an inner leg having an independent closed magnetic circuit. The excitation winding and the output winding are wrapped around the inner leg of the core in layers. The inner leg of the core has a gap whose size is steplessly adjustable in a state where the excitation current is applied to the excitation winding. The size of the gap is adjusted to regulate exciting inductances of the transformers to a same predetermined value. | 2014-09-18 |
20140268967 | ELECTROMAGNETIC INTERFERENCE (EMI) REDUCTION IN MULTI-LEVEL POWER CONVERTER - A multi-level power converter system includes a multi-level power converter configured to synthesize at least three direct current (DC) voltages into an alternating current (AC) output voltage, and includes a plurality of transistors. A controller generates pulse-width modulation (PWM) signals used to control a state of the plurality of transistors of the multi-level converter by comparing first and second carrier signals to a reference signals, wherein a period of the first and second carrier signals is randomly varied from a nominal period. | 2014-09-18 |
20140268968 | TRANSFORMER FOR AN INVERTER SYSTEM AND AN INVERTER SYSTEM COMPRISING THE TRANSFORMER - A transformer comprises a primary winding | 2014-09-18 |
20140268969 | POWER POLE INVERTER - An arm assembly is provided. The arm assembly includes a heat exchanger assembly, a plurality of electrical components thermally coupled to the heat exchanger assembly, and a number of electrical buses. Each electrical component is coupled to, and in electrical communication with, one electrical bus. A sealing compound is then applied to each electrical bus and to a limited number of the electrical components. | 2014-09-18 |
20140268970 | MATRIX CONVERTER AND METHOD FOR CONTROLLING MATRIX CONVERTER - A matrix converter according to an embodiment includes a power converter having a plurality of bidirectional switches, a controller, and a current detector. The controller controls the power converter. The correct detector detects a current flowing to an output side of the power converter. The controller extracts a high-frequency component contained in the current detected by the current detector, adjusts an output current reference on the basis of the high-frequency component, and controls the power converter on the basis of the adjusted output current reference. | 2014-09-18 |
20140268971 | TCAM WITH EFFICIENT RANGE SEARCH CAPABILITY - An embodiment of the invention includes a ternary content addressable memory (TCAM) that has input search data bits, TCAM words and range search input data bits. Each TCAM word is operable to store a match pattern and provide a match output. The match output indicates a match when the match pattern of the TCAM word matches the TCAM input search data bits. The range search input data bits are separated into groups. Each group has a bit width N where N is the number of range search input data bits. For the match pattern in each group, there is a Boolean function that uses the N range of search input data bits. (2 | 2014-09-18 |
20140268972 | TCAM WITH EFFICIENT MULTIPLE DIMENSION RANGE SEARCH CAPABILITY - An embodiment of the invention includes first and second Ternary Content Addressable Memories (TCAMs), a first vector, and TCAM match-merge unit. Each of the TCAMs includes a plurality of words, stores TCAM match entries and outputs a TCAM match signal for each word in the plurality of words. The first vector includes first TCAM group enable register bits. An enabling value on the first TCAM register bit indicates that the first TCAM match signal and the neighboring first TCAM match are in the same TCAM group. The TCAM match-merge unit receives the first TCAM match signal from each of the words and the first vector and outputs a first TCAM group match signal for each of the words. The TCAM match-merge unit outputs a match indication when any of the TCAM match signals indicate a match and outputs a mismatch when none of the TCAM match signals match. | 2014-09-18 |
20140268973 | 276-PIN BUFFERED MEMORY CARD WITH ENHANCED MEMORY SYSTEM INTERCONNECT - An embodiment is a memory card including a rectangular printed circuit card having a first side and a second side, a first length of between 151.35 and 161.5 millimeters, and first and second ends having a second length smaller than the first length. The memory card also includes a first plurality of pins on the first side extending along a first edge of the rectangular printed circuit card that extends along a length of the card, a second plurality of pins on the second side extending on the first edge of the rectangular printed circuit card, and a positioning key having its center positioned on the first edge of the rectangular printed circuit card and located between 94.0 and 95.5 millimeters from the first end of the rectangular printed circuit card. The memory card also includes a memory module, a hub device and pins for boundary scan signals. | 2014-09-18 |
20140268974 | APPARATUSES AND METHODS FOR IMPROVING RETENTION PERFORMANCE OF HIERARCHICAL DIGIT LINES - Apparatuses and methods for improving retention performance of hierarchical digit lines are disclosed herein. An example apparatus may include a first digit line portion and a second digit line portion. The apparatus may further include a first selector configured to selectively couple the first digit line portion to the second digit line portion based, at least in part, on a first control signal. The apparatus may further include a second selector configured to selectively couple the second digit line portion to a voltage based, at least in part, on a second control signal. | 2014-09-18 |
20140268975 | INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY STRESS SUPPRESSION AND METHOD OF MANUFACTURE THEREOF - An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line. | 2014-09-18 |
20140268976 | GROUND-REFERENCED SINGLE-ENDED MEMORY INTERCONNECT - A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package is configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface, where the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network. | 2014-09-18 |
20140268977 | ELECTRICAL LINES WITH COUPLING EFFECTS - A circuit includes a first line, a second line, a first sub-circuit, and a second sub-circuit. The first line has a first signal. The second line has a second signal. The first sub-circuit is configured to generate a first output signal. The second sub-circuit is configured to generate a second output signal. The first output signal and the second output signal have coupling effects if the first signal and the second signal have coupling effects based on the first line and the second line. The first output signal and the second output signal do not have coupling effects if the first signal and the second signal do not have coupling effects. | 2014-09-18 |
20140268978 | SEMICONDUCTOR MEMORY DEVICE HAVING ASYMMETRIC ACCESS TIME - A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays. | 2014-09-18 |
20140268979 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE - A semiconductor device includes a system-on-chip (SOC) and at least one wide input/output memory device. The SOC includes a plurality of SOC bump groups which provide input/output channels, respectively, independent from each other. The at least one wide input/output memory device is stacked on the system-on-chip to transmit/receive data to/from the system-on-chip through the SOC bump groups. The SOC bump groups are arranged and the at least one wide input/output memory device is configured such that one of the wide input/output memory devices can be mounted to the SOC as connected to all of the SOC bump groups, or such that two wide input/output memory devices can be mounted to the SOC with each of the wide input/out memory devices connected a respective half of the SOC bump groups. | 2014-09-18 |
20140268980 | MEMORY CHIP PACKAGE, MEMORY SYSTEM HAVING THE SAME AND DRIVING METHOD THEREOF - A memory chip package includes memory chips stacked, electrically connected one another, and configured to input and output an optical signal through an optical line formed by a via penetrating the memory chips. The memory chips input and output optical signals with different wavelengths, and each of the memory chips has an optical-electrical converter configured to convert an optical signal with a corresponding wavelength into an electrical signal and to convert an electrical signal into an optical signal with the corresponding wavelength. | 2014-09-18 |
20140268981 | RACETRACK MEMORY WITH ELECTRIC-FIELD ASSISTED DOMAIN WALL INJECTION FOR LOW-POWER WRITE OPERATION - Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire. | 2014-09-18 |
20140268982 | RACETRACK MEMORY WITH ELECTRIC-FIELD ASSISTED DOMAIN WALL INJECTION FOR LOW-POWER WRITE OPERATION - Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire. | 2014-09-18 |
20140268983 | OTPROM ARRAY WITH LEAKAGE CURRENT CANCELATION FOR ENHANCED EFUSE SENSING - Disclosed herein are memory cell arrays and methods for operating memory cell arrays. In one embodiment, a memory cell array includes a plurality of bitcells, a first bitline, a second bitline, a first wordline and a second wordline. The bitcells are arranged into rows and columns and each include a first transistor, a second transistor, and a fuse with a first end and a second end. The second transistor is selectively operable to couple the first end of the fuse to a ground. The first bitline is coupled to the first transistor of each of the bitcells of one column. The second bitline is coupled to the second end of the fuse of each of the bitcells of the column. The first transistor of each of the bitcells of the column is selectively operable to couple the first end of the fuse to the first bitline. | 2014-09-18 |
20140268984 | SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS - Provided is a semiconductor device that includes: a storage element including a first terminal, a second terminal, and a third terminal, and in which a resistance state between the second terminal and the third terminal is changed from a high resistance state to a low resistance state based on a stress current that flows between the first terminal and the second terminal; and a fuse connected to the first terminal, and configured to change from a conductive state to a non-conductive state based on the stress current. | 2014-09-18 |
20140268985 | READ ONLY MEMORY BITLINE LOAD-BALANCING - A Read Only Memory (ROM) bitline cell apparatus and programming method therefore. The programming methodology ensures a ROM structure having open state and/or breaks in the diffusion and/or dummy wordline rows to provide bitline load balancing. The ROM bitline cell apparatus and programming method exhibits improved load balancing for any combination of 1's or all 0's on the bitline. The programming methodology identifies groups of consecutive ‘1’s on the bitline and instead of connecting the ‘1’ devices between BL/BL or GND/GND, those ‘1’ devices can be connected between BL/OPEN, OPEN/BL, GND/OPEN, OPEN/GND or OPEN/OPEN. With little or no variation in bitline loading, timing can be optimized for that single case of bitline loading. | 2014-09-18 |
20140268986 | Read Only Memory Array Architecture and Methods of Operation - An encoded ROM array structure couples a first one of a first set of bitlines to a second one of a second set of bitlines through a transistor when the wordline connected to the gate terminal of that transistor is asserted. This encoded arrangement can be extended to any number of encoded bitlines, e.g., 2, 4, 8, 16, and so on. Each of the first plurality and second sets of bit lines are coupled to circuits for charging and discharging the bitlines. To read data from the first set of bit lines, the second set of bitlines is discharged, and vice versa. | 2014-09-18 |
20140268987 | Thermally-Assisted Mram with Ferromagnetic Layers with Temperature Dependent Magnetization - A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer. | 2014-09-18 |
20140268988 | RESISTIVE MEMORY CELL - The present invention discloses a resistive memory cell, including a unipolar type RRAM and a MOS transistor as a selection transistor serially connected to the unipolar type RRAM, wherein the MOS transistor is fabricated over a partial depletion SOI substrate and provides a large current for program and erase of the RRAM by using an intrinsic floating effect of the SOI substrate. The present invention utilizes a floating effect of a SOI device, in which under the same width/length ratio, a MOS transistor over a SOI substrate can provide larger source/drain current than a MOS transistor over a bulk silicon, so that the area occupied by the selection transistor is reduced, which is advantageous to the integration of the RRAM array. | 2014-09-18 |
20140268989 | RESISTIVE NON-VOLATILE MEMORY - A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes primary and secondary cell selectors. The primary selector selects the multi-bit cell while the secondary selector selects a bit within the multi-bit cell. A plurality of storage units can be commonly coupled to a primary selector, facilitating high density applications. | 2014-09-18 |
20140268990 | STACKABLE NON-VOLATILE MEMORY - A multi-bit NVM cell includes a storage unit having resistive elements, such as phase change resistive elements. The NVM cell may be configured as a single port or dual port multi-bit cell. The NVM cell includes a cell selector. The cell selector selects the multi-bit cell. When appropriate signals are applied to the NVM cell, the cell selector selects an appropriate resistive element of the storage unit. A plurality of storage units can be commonly coupled to the cell selector, facilitating high density applications. | 2014-09-18 |
20140268991 | CHALCOGENIDE MATERIAL AND METHODS FOR FORMING AND OPERATING DEVICES INCORPORATING THE SAME - Embodiments disclosed herein may relate to a memory cell comprising a chalcogenide material mixture having a chalcogenide composition and a metallic glass-forming composition. | 2014-09-18 |
20140268992 | Memory Cells, Memory Systems, and Memory Programming Methods - Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes. | 2014-09-18 |
20140268993 | Nonvolatile resistive memory element with an oxygen-gettering layer - A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (ΔfG°) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiO | 2014-09-18 |
20140268994 | Write-Time Based Memristive Physical Unclonable Function - A physical unclonable function (PUF) device consisting of a hybrid CMOS-memristor circuit that leverages variations in the required write-time of a memristor. Variations in the time required to write, or SET, a memristor from a high to low resistance state arise from variability in physical parameters such as the memristor thickness. When applying a SET voltage across the memristor for the nominal minimum SET time, variability leads to a situation where the memristor will actually SET to the low resistance state only 50% of the time. When the device does not SET it will remain in the high resistance state. Since the to resistance state of the memristor corresponds to reading either a logic 1 or logic 0 on the output of the circuit, the write-time based memristive PUF produces a digital signature directly corresponding to the fabrication process-induced physical variations of an integrated circuit. | 2014-09-18 |
20140268995 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device includes: a vertical electrode provided over a substrate; a variable resistance layer provided at least a sidewall of the vertical electrode; a plurality of horizontal electrodes extending from the sidewall of the vertical electrode and having the variable resistance layer interposed; a transition metal oxide layer provided (i) between the vertical electrode and the variable resistance layer or (ii) between the plurality of horizontal electrodes and the variable resistance layer; and a threshold voltage switching layer provided in the transition metal oxide layer and selectively between the vertical electrode and the any of the plurality of horizontal electrodes. | 2014-09-18 |
20140268996 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A variable resistance memory device and a driving method thereof are provided. The variable resistance memory device includes a base layer and a pillar-shaped gate electrode formed on the base layer and extending substantially perpendicular to a surface of the base layer. A current transfer layer is formed to surround the pillar-shaped gate electrode. A variable resistance layer formed in an outer portion of the current transfer layer. A blocking layer blocks a path of current flowing through the current transfer layer based on a voltage applied voltage to the pillar-shaped gate electrode, and diverts the current flowing through the current transfer layer to the variable resistance layer. | 2014-09-18 |
20140268997 | PROGRAMMING TWO-TERMINAL MEMORY CELLS WITH REDUCED PROGRAM CURRENT - Providing for programming a two-terminal memory cell array with low sneak path current is described herein. Groups of two-terminal memory cells can be arranged into blocks or sub-blocks, along sets of bitlines and local wordlines. Further, groups of local wordlines within a given sub-block can be electrically isolated from bitlines outside the sub-block. A programming signal can be applied to the two-terminal memory cells from an associated local wordline thereof. Sneak path currents can be mitigated or avoided with respect to bitlines outside a particular sub-block, or on non-selected wordlines of the sub-block. This can significantly reduce a magnitude of combined sneak path current within the sub-block in response to the programming operation. | 2014-09-18 |
20140268998 | RRAM WITH DUAL MODE OPERATION - A two-terminal memory cell comprises a dual mode of operation in a unipolar mode and bipolar mode for a programming or On-state and for an erase or Off-state of the cell. The two-terminal memory cell is field programmable and can be flexibly designed or integrated into existing architecture. The two-terminal memory comprises a first electrode layer and a second electrode layer with a switching layer disposed between that has an electrical insulator material. A semiconductor layer is disposed between the switching layer and at least one of the first electrode or the second electrode. The switching layer generates a conductive path that is configured to be in a program state and an erase state, based on a bipolar mode and a unipolar mode. | 2014-09-18 |
20140268999 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value. | 2014-09-18 |
20140269000 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes multiple memory cells that include a variable resistance element and a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured so that, during the set operation in which the variable resistance element is changed to the set state, a set voltage of a first polarity is applied to the select memory cell. The control circuit is configured so that, during the reset operation in which the variable resistance elements are changed to the reset state, and a cancel voltage of the first polarity is applied to an unselected memory cell to which voltage that is less than the reset voltage was applied. The voltage value and the voltage application time of the set voltage and the voltage value and the voltage application time of the cancel voltage have a set relationship. | 2014-09-18 |
20140269001 | AMORPHOUS SILICON RRAM WITH NON-LINEAR DEVICE AND OPERATION - A non-volatile memory device includes a resistive switching device having a first electrode, a second electrode, and a resistive switching element, wherein the resistive switching element comprises a silicon material disposed in an overlapping region between the first electrode and the second electrode, wherein the second electrode comprises at least a metal material physically and electrically in contact with the resistive switching material, wherein the resistive switching element is characterized by a resistance depending on an electric field in the resistive switching element, and a non-linear device coupled between the first electrode and the resistive switching element , wherein the non-linear device is configured to conduct electric current when a voltage greater than a first voltage is applied to the second electrode, wherein the resistive switching device is configured to change from a first state to a second state in response to the first voltage. | 2014-09-18 |
20140269002 | TWO-TERMINAL MEMORY WITH INTRINSIC RECTIFYING CHARACTERISTIC - Providing for two-terminal memory having an inherent rectifying characteristic(s) is described herein. By way of example, the two-terminal memory can be a resistive switching device having one or more “on” states and an “off” state, to facilitate storage of digital information. A conductive filament can be electrically isolated from an electrode of the two-terminal memory by a thin tunneling layer, which permits a tunneling current for voltages greater in magnitude than a positive rectifying voltage or a negative rectifying voltage. The two-terminal memory cell can therefore have high resistance to small voltages, mitigating leakage currents in an array of the two-terminal memory cells. In addition, the memory cell can be conductive above a rectifying voltage, enabling reading of the memory cell in response to a suitable read bias, and erasing of the memory cell in response to a suitable negative erase bias. | 2014-09-18 |
20140269003 | MEMORY CELL WITH VOLATILE AND NON-VOLATILE STORAGE - The invention concerns a non-volatile memory element comprising: first and second transistors ( | 2014-09-18 |
20140269004 | Method for Improving Data Retention of ReRAM Chips Operating at Low Operating Temperatures - Programming a resistive memory structure at a temperature well above the operating temperature can create a defect distribution with higher stability, leading to a potential improvement of the retention time. The programming temperature can be up to 100 C above the operating temperature. The memory chip can include embedded heaters in the chip package, allowing for heating the memory cells before the programming operations. | 2014-09-18 |
20140269005 | ELECTRONIC DEVICES HAVING SEMICONDUCTOR MEMORY UNITS AND METHOD FOR FABRICATING THE SAME - The disclosed technology provides an electronic device and a fabrication method thereof. An electronic device according to an implementation of the disclosed technology may include: a first interlayer insulating layer formed over a substrate; first and second contact plugs passing through the first interlayer insulating layer to contact the substrate and alternately arranged to cross each other; a variable resistance element formed over the first interlayer insulating layer and coupled to the first contact plug; a second interlayer insulating layer formed over an entire structure including the first interlayer insulating layer; a third contact plug passing through the second interlayer insulating layer so as to be coupled to the variable resistance element, and a fourth contact plug passing through the second interlayer insulating layer so as to be contacted to the second contact plug; and conductive lines coupled to the third contact plug and the fourth contact plug, respectively. | 2014-09-18 |
20140269006 | FAST READ SPEED MEMORY DEVICE - A memory device includes an array of resistive memory cells. Each resistive memory cell in the array includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node between a first terminal of the first resistive memory element and a first terminal of the second resistive memory element, and a transistor comprising a gate electrically coupled with the common node. | 2014-09-18 |
20140269007 | COMPLEMENTARY METAL OXIDE OR METAL NITRIDE HETEROJUNCTION MEMORY DEVICES WITH ASYMMETRIC HYSTERESIS PROPERTY - A resistive memory device is disclosed. The resistive memory device comprises one or more metal oxide layers. The resistive memory device displays a property of asymmetric hysteresis loop formation when positive and negative electrical biases are applied across the device. | 2014-09-18 |
20140269008 | NON-VOLATILE MEMORY USING BI-DIRECTIONAL RESISTIVE ELEMENTS - A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node . A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being written. During a subsequent restoration operation, the value as written in the first BRME and second BRME is written to the first storage node and the second storage node while a wordline connected to the memory cell is deasserted. | 2014-09-18 |
20140269009 | DRAM WITH PULSED SENSE AMP - Disclosed is a pulsed sense amplifier approach for resolving data on a bit line. | 2014-09-18 |
20140269010 | GROUND-REFERENCED SINGLE-ENDED MEMORY INTERCONNECT - A system is provided for transmitting signals. The system includes a ground-referenced single-ended signaling (GRS) driver circuit that is configured to pre-charge a first capacitor to store a first charge between a first output node and a first reference node based on a first input data signal during a first pre-charge phase and drive an output signal relative to a ground network based on the first charge during a first drive phase. A control circuit is configured to generate a first set of control signals based on the first input data signal and a first clock signal, where the first set of control signals causes the first GRS driver circuit to operate in either the first pre-charge phase or in the first drive phase. | 2014-09-18 |
20140269011 | MULTI-PHASE GROUND-REFERENCED SINGLE-ENDED SIGNALING - A system includes a control circuit and first, second, and third ground-referenced single-ended signaling (GRS) driver circuits that are each coupled to an output signal. The control circuit is configured to generate a first, second, and third set of control signals that are each based on a respective phase of a clock signal. Each GRS driver circuit is configured to pre-charge a capacitor to store a charge based on the respective set of control signals during at least one phase of the clock signal and drive the output signal relative to a ground network by discharging the charge during a respective phase of the clock signal. | 2014-09-18 |
20140269012 | GROUND-REFERENCED SINGLE-ENDED SYSTEM-ON-PACKAGE - A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip. | 2014-09-18 |
20140269013 | MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A memory device includes a first memory circuit including a silicon transistor, a selection circuit including a silicon transistor, and a second memory circuit including oxide semiconductor transistors and a storage capacitor, in which one terminal of the storage capacitor is connected to a portion where two oxide semiconductor transistors are connected in series, an output of the second memory circuit is connected to a second input terminal of the selection circuit, and an input of the second memory circuit is connected to a first input terminal of the selection circuit or an output terminal of the first memory circuit. | 2014-09-18 |
20140269014 | MEMORY DEVICE - A memory device with a novel structure that is suitable for a register file is provided. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit includes a first logic element and a second logic element each of which is configured to perform logic inversion, a selection circuit, a first switch, a second switch, and a third switch. The second memory circuit includes a first transistor in which a channel formation region is provided in an oxide semiconductor film, a second transistor, and a capacitor to which a potential is supplied through the first transistor. | 2014-09-18 |
20140269015 | USE OF HYDROCARBON NANORINGS FOR DATA STORAGE - Hydro-carbon nanorings may be used in storage. Sufficiently cooled, an externally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of electrons. Similarly, an internally hydrogen doped carbon nanoring may be used to create a radial dipole field to contain streams of positrons. When matched streams of positrons and electrons are sufficiently compressed they may form Cooper pairs with magnetic moments aligned to the movement of the stream. Matched adjacent Cooper pairs of electrons and positrons may contain information within their magnetic moments, and as such, may transmit and store information with little or no energy loss. Information may be similarly encoded in magnetic moments of spins of pairs of positrons and electrons, not in the form of Cooper pairs. | 2014-09-18 |
20140269016 | MULTIPORT MEMORY WITH MATCHING ADDRESS CONTROL - A multiport SRAM has an array of cells, a first port, and a second port. During a period of different row addresses for the ports, the first port uses first word lines and first bit lines. The second port uses second word lines and second bit lines. In response to the second port switching to the same address as the first port to make a row match, the second port and the first port use the first plurality of word lines, but the first port uses the first plurality of bit lines and the second port uses the second plurality of bit lines. If the row match is removed by the first port changing row addresses, a correlation swap is performed so that the first port performs accesses using the second word lines and bit lines and the second port performs accesses using the first word lines and bit lines. | 2014-09-18 |
20140269017 | PROCESS CORNER SENSOR FOR BIT-CELLS - An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells. | 2014-09-18 |
20140269018 | Write-Assisted Memory with Enhanced Speed - A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining non-accessed memory cells in the bit-line-multiplexed group of memory cells. | 2014-09-18 |
20140269019 | DUAL-PORT STATIC RANDOM ACCESS MEMORY (SRAM) - In one embodiment, a memory cell circuit for storing data includes a pair of cross-coupled inverters for storing states of the memory cell circuit. Access devices provide access to the pair of cross-coupled inverters. The memory cell circuit also includes a set of electrically inactive p-type metal oxide semiconductor (PMOS) devices that are coupled to the pair of cross-coupled inverters. The set of electrically inactive PMOS devices in combination with a portion (e.g., PMOS devices) of the pair of cross-coupled inverters enables a continuous p-type diffusion layer for the memory cell circuit. | 2014-09-18 |
20140269020 | SYSTEM AND METHOD TO REGULATE OPERATING VOLTAGE OF A MEMORY ARRAY - A method includes measuring a temperature of a sensor associated with a memory array. The method also includes calculating, at a voltage regulating device, an operating voltage based on the temperature and based on fabrication data associated with the memory array. The method further includes regulating, at the voltage regulating device, a voltage provided to the memory array based on the operating voltage. | 2014-09-18 |
20140269021 | TIMING LOGIC FOR MEMORY ARRAY - Among other things, techniques and systems are provided for devising a schedule for performing read/write operations on a memory cell. A control signal is provided to timing logic. Using one or more properties of the control signal, such as a voltage property, the timing logic is configured to adjust a time window during which at least one of a read operation or a write operation is performed within a cycle. In this way, the timing logic affects a dynamic switch between an early-read operation, a late-read operation, an early-write operation, a late-write operation, a read-then-write operation, and a write-then-read operation between cycles. In some embodiments, the memory cell for which the schedule is devised is an SRAM cell, such as a six-transistor SRAM cell. | 2014-09-18 |
20140269022 | THREE-DIMENSIONAL (3D) MEMORY CELL SEPARATION AMONG 3D INTEGRATED CIRCUIT (IC) TIERS, AND RELATED 3D INTEGRATED CIRCUITS (3DICS), 3DIC PROCESSOR CORES, AND METHODS - A three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) (3DIC) tiers is disclosed. Related 3DICs, 3DIC processor cores, and methods are also disclosed. In embodiments disclosed herein, memory read access ports of a memory block are separated from a memory cell in different tiers of a 3DIC. 3DICs achieve higher device packing density, lower interconnect delays, and lower costs. In this manner, different supply voltages can be provided for the read access ports and the memory cell to be able to lower supply voltage for the read access ports. Static noise margins and read/write noise margins in the memory cell may be provided as a result. Providing multiple power supply rails inside a non-separated memory block that increases area can also be avoided. | 2014-09-18 |
20140269023 | BIASING BULK OF A TRANSISTOR - A circuit comprises a first transistor of a first type, a second transistor of a second type, and a third transistor of the first type or the second type. The first transistor and the second transistor form an inverter. The third transistor is coupled with an output of the inverter. The circuit includes at least one of the following voltage sources: a first voltage source, a second voltage source, and a third voltage source. The first voltage source is coupled with a bulk of the first transistor, and is different from a first supply voltage source of the first transistor. T second voltage source is coupled with a bulk of the second transistor, and is different from a second supply voltage of the second transistor. The third voltage source is coupled with a bulk of the third transistor. | 2014-09-18 |
20140269024 | MEMORY DEVICE AND METHOD FOR WRITING THEREFOR - A method of writing a memory cell includes, during a write cycle, causing a voltage level at a power terminal of the memory cell to change from a supply voltage level toward a first voltage level. The voltage level at the power terminal of the memory cell is maintained at the first voltage level for a first predetermined duration. The voltage level at the power terminal of the memory cell is maintained at a second voltage level for a second predetermined duration, where the second voltage level is between the first voltage level and the supply voltage level. During the write cycle, the voltage level at the power terminal of the memory cell is caused to change from the first voltage level toward the supply voltage level. | 2014-09-18 |
20140269025 | MEMORY WITH REDUNDANT SENSE AMPLIFIER - Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state. | 2014-09-18 |
20140269026 | TRACKING CIRCUIT - A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal. | 2014-09-18 |
20140269027 | AMPLIFIER - A circuit comprises a first data line, a second data line, a charging circuit, a first circuit, a second circuit, a first switching circuit, and a second switching circuit. The charging circuit and the first circuit are each coupled with the first data and the second data line. The first switching circuit is coupled between the first data line and a first node of the second circuit. The second switching circuit is coupled between the second data line and a second node of the second circuit. The data on the first node or the second node represents data in a single-ended circuit. Data on both the first node and the second node represent data in a differential circuit. | 2014-09-18 |
20140269028 | Thermally-Assisted Mram with Ferromagnetic Layers with Temperature Dependent Magnetization - A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer. | 2014-09-18 |
20140269029 | SELECTIVE SELF-REFERENCE READ - This disclosure relates to selectively performing a read with increased accuracy, such as a self-reference read, from a memory. In one aspect, data is read from memory cells, such as magnetoresitive random access memory (MRAM) cells, of a memory array. In response to detecting a condition associated with reading from the memory cells, a self-reference read can be performed from at least one of the memory cells. For instance, the condition can indicate that data read from the memory cells is uncorrectable via decoding of error correction codes (ECC). Selectively performing self-reference reads can reduce power consumption and/or latency associated with reading from the memory compared to always performing self-reference reads. | 2014-09-18 |
20140269030 | METHOD AND APPARATUS FOR MRAM SENSE REFERENCE TRIMMING - A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current. | 2014-09-18 |
20140269031 | SYSTEM AND METHOD OF SENSING A MEMORY CELL - A method includes sensing a state of a data cell to generate a data voltage. The state of the data cell corresponds to a state of a programmable resistance based memory element of the data cell. The method further includes sensing a state of a reference cell to generate a reference voltage. The state of the data cell and the state of the reference cell are sensed via a common sensing path. The method further includes determining a logic value of the data cell based on the data voltage and the reference voltage. | 2014-09-18 |
20140269032 | ARCHITECTURE FOR MAGNETIC MEMORIES INCLUDING MAGNETIC TUNNELING JUNCTIONS USING SPIN-ORBIT INTERACTION BASED SWITCHING - A magnetic memory includes memory array tiles (MATs), intermediate circuitry, global bit lines and global circuitry. Each MAT includes bit lines, word lines, and magnetic storage cells having magnetic junction(s), selection device(s) and at least part of a spin-orbit interaction (SO) active layer adjacent to the magnetic junction(s). The SO active layer exerts a SO torque on the magnetic junction(s) due to a preconditioning current passing through the SO active layer. The magnetic junction(s) are programmable using write current(s) driven through the magnetic junction(s) and the preconditioning current. The bit and word lines correspond to the magnetic storage cells. The intermediate circuitry controls read and write operations within the MATs. Each global bit line corresponds to a portion of the MATs. The global circuitry selects and drives portions of the global bit lines for read operations and write operations. | 2014-09-18 |
20140269033 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes magnetoresistive effect elements each including a first magnetic layer, a tunnel barrier layer, and a second magnetic layer which are successively stacked, and a ferroelectric capacitor provided above the magnetoresistive effect elements via an insulating layer, and including a lower electrode, a ferroelectric film, and an upper electrode which are successively stacked. | 2014-09-18 |
20140269034 | INTEGRATED CAPACITOR BASED POWER DISTRIBUTION - An embodiment provides power (having low voltage, high current, and high current density) to ultra low voltage non-CMOS based devices using a distributed capacitor that is integrated onto the same chip as the non-CMOS devices. For example, an embodiment provides a spin logic gate adjacent dielectric material and first and second plates of a capacitor. The capacitor discharges low voltage/high current to the spin logic gate using a step down switched mode power supply that charges numerous capacitors during one clock cycle (using a switching element configured in a first orientation) and discharges power from the capacitors during the opposite clock cycle (using the switching element configured in a second orientation). The capacitors discharge the current out of plane and to the spin logic devices without having to traverse long power dissipating interconnect paths. Other embodiments are described herein. | 2014-09-18 |
20140269035 | CROSS POINT ARRAY MRAM HAVING SPIN HALL MTJ DEVICES - Cross point array magnetoresistive random access memory (MRAM) implementing spin hall magnetic tunnel junction (MTJ)-based devices and methods of operation of such arrays are described. For example, a bit cell for a non-volatile memory includes a magnetic tunnel junction (MTJ) stack disposed above a substrate and having a free magnetic layer disposed above a dielectric layer disposed above a fixed magnetic layer. The bit cell also includes a spin hall metal electrode disposed above the free magnetic layer of the MTJ stack. | 2014-09-18 |
20140269036 | MAGNETIC MEMORY DEVICES AND METHODS OF WRITING DATA TO THE SAME - Magnetic memory devices include a magnetoresistive cell including a free layer having a variable magnetization direction and a pinned layer having a fixed magnetization direction, a bit line on the magnetoresistive cell and including a spin Hall effect material layer exhibiting a spin Hall effect and contacting the free layer; and a lower electrode under the magnetoresistive cell. A voltage is applied between the bit line and the lower electrode so that current passes through the magnetoresistive cell. | 2014-09-18 |
20140269037 | MAGNETIC MEMORY ELEMENT AND NONVOLATILE MEMORY DEVICE - A magnetic memory element includes a first stacked unit and a second stacked unit. The first stacked unit includes a first ferromagnetic layer, a second ferromagnetic layer, and a first nonmagnetic layer. The second ferromagnetic layer is stacked with the first ferromagnetic layer. The second ferromagnetic layer has a first and second portion. The first and second portion has a changeable direction of magnetization. The second portion is stacked with the first portion in a stacking direction of the first ferromagnetic layer and the second ferromagnetic layer. A magnetic resonance frequency of the second portion is lower than a magnetic resonance frequency of the first portion. The first nonmagnetic layer is provided between the first ferromagnetic layer and the second ferromagnetic layer. The second stacked unit is stacked with the first stacked unit in the stacking direction. The second stacked unit includes a third ferromagnetic layer. | 2014-09-18 |
20140269038 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes at least one MTJ element, the MTJ element including: a magnetic multilayer structure including a first magnetic layer in which a direction of magnetization is fixed, a second magnetic layer in which a direction of magnetization is changeable, and a tunnel barrier layer located between the first and second magnetic layers; a first electrode provided on a first surface of the magnetic multilayer structure; a second electrode provided on a second surface of the magnetic multilayer structure; an insulating film provided on a side surface of the magnetic multilayer structure; and a control electrode provided on the side surface of the magnetic multilayer structure with the insulating film located therebetween, a voltage being applied to the control electrode in a read operation, which increases an energy barrier for changing the magnetization of the second magnetic layer. | 2014-09-18 |
20140269039 | ELECTRONIC DEVICE AND VARIABLE RESISTANCE ELEMENT - A variable resistance element includes: first and second magnetic layers having a lanthanide series element alloyed in a nickel-iron compound; and a tunnel barrier layer interposed between the first and second magnetic layers. | 2014-09-18 |
20140269040 | PULSE PROGRAMMING TECHNIQUES FOR VOLTAGE-CONTROLLED MAGNETORESISTIVE TUNNEL JUNCTION (MTJ) - A method of programming a voltage-controlled magnetoresistive tunnel junction (MTJ) includes applying a programming voltage pulse (Vp), reading the voltage-controlled MTJ, and determining if the voltage-controlled MTJ is programmed to a desired state and if not, changing the Vp and repeating the applying and reading steps until the voltage-controlled MTJ is programmed to the desired state. | 2014-09-18 |
20140269041 | EMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) BY MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A magnetic memory system includes a magnetic random access memory (MRAM) including a plurality of magnetic memory banks and operative to store data during a write operation initiated by a write command. The magnetic memory system further includes a first-in-first-out (FIFO) interface device coupled to the MRAM and including a plurality of FIFOs Each of the magnetic memory banks is coupled to a respective one of the plurality of FIFOs, the FIFO being operative to queue write commands on a per magnetic memory bank basis and further operative to issue the queued write commands at a time when the MRAM is not in use, wherein concurrent write operations are performed to at least two of the plurality of magnetic memory banks. | 2014-09-18 |
20140269042 | Self-referenced Magnetic Random Access Memory - The present disclosure concerns a magnetic random access memory cell containing a magnetic tunnel junction formed from an insulating layer comprised between a sense layer and a storage layer. The present disclosure also concerns a method for writing and reading the memory cell comprising, during a write operation, switching a magnetization direction of said storage layer to write data to said storage layer and, during a read operation, aligning magnetization direction of said sense layer in a first aligned direction and comparing said write data with said first aligned direction by measuring a first resistance value of said magnetic tunnel junction. The disclosed memory cell and method allow for performing the write and read operations with low power consumption and an increased speed. | 2014-09-18 |
20140269043 | PHASE CHANGE MEMORY MASK - Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic. | 2014-09-18 |
20140269044 | METHODS AND APPARATUSES FOR CONTROLLING MEMORY WRITE SEQUENCES - Subject matter disclosed herein relates to memory operations regarding changing an order of program bits to be programmed into a memory array. | 2014-09-18 |
20140269045 | CELL PROGRAMMING VERIFICATION - Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages. | 2014-09-18 |
20140269046 | APPARATUSES AND METHODS FOR USE IN SELECTING OR ISOLATING MEMORY CELLS - Methods and devices for selection and/or isolation of memory cells include use of a thyristor For example, a memory storage component may be selected for access, at least in part, by initiating application of a triggering potential to affect a gate of a thyristor that is coupled in series with a memory storage component. The gate of the thyristor connects to a memory cell word line and permits an efficient polarity scheme for selected and unselected memory array conductors to reduce leakage current relative to conventional selectors, such as bipolar junction transistors. | 2014-09-18 |
20140269047 | APPARATUS AND METHODS RELATING TO A MEMORY CELL HAVING A FLOATING BODY - An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto. | 2014-09-18 |
20140269048 | RETENTION DETECTION AND/OR CHANNEL TRACKING POLICY IN A FLASH MEMORY BASED STORAGE SYSTEM - A method for determining a retention time in a solid state device (SSD), comprising the steps of providing a plurality of write operations to a memory, determining a reference voltage for each of the write operations, determining a difference between (i) the reference voltage after each of the write operations and (ii) a target reference voltage and if the difference is above a predetermined value, generating a flag indicating an excessive retention has occurred. | 2014-09-18 |
20140269049 | Hybrid Chargepump And Regulation Means And Method For Flash Memory Device - A hybrid charge pump and control circuit for use in a memory device is disclosed. | 2014-09-18 |
20140269050 | DETERMINING READ VOLTAGES FOR READING MEMORY - A method of reading data at a data storage device that includes a non-volatile memory having a three-dimensional (3D) configuration includes identifying a first set of storage elements of a first word line of the non-volatile memory that satisfy a condition. The condition is based on one or more states of one or more storage elements. The method includes determining a first read voltage corresponding to the first set of storage elements of the first word line and determining a second read voltage corresponding to a second set of storage elements of the first word line that do not satisfy the condition. The method includes reading data from the first word line by applying the first read voltage to the first set of storage elements of the first word line and applying the second read voltage to the second set of storage elements of the first word line. | 2014-09-18 |
20140269051 | PROGRAMMING SCHEMES FOR 3-D NON-VOLATILE MEMORY - A method includes providing data for storage in a memory, which includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines, and a third dimension associated with sections. The data is stored in the memory cells in accordance with a programming order that alternates among the sections, including storing a first portion of the data in a first section, then storing a second portion of the data in a second section different from the first section, and then storing a third portion of the data in the first section. | 2014-09-18 |
20140269052 | SYSTEM AND METHOD OF DETERMINING READING VOLTAGES OF A DATA STORAGE DEVICE - A data storage device includes a memory and a controller. In a particular embodiment, a method is performed in the data storage device. The method is performed during a read threshold voltage update operation and includes determining a first read threshold voltage of a set of storage elements of a memory according to a first technique and determining a second read threshold voltage of the set of storage elements of the memory according to a second technique. The first read threshold voltage is different from the second read threshold voltage, and the first technique is different from the second technique. | 2014-09-18 |
20140269053 | NONVOLATILE MEMORY DATA RECOVERY AFTER POWER FAILURE - A method for data recovery after a power failure is disclosed. The method may include steps (A) to (D). Step (A) may determine that a last power-down of a solid-state drive was an unsafe power-down. Step (B) may search at least some of a plurality of pages of a nonvolatile memory of the solid-state drive to define an unsafe zone in response to the determining that the last power-down of the solid-state drive was the unsafe power-down. Step (C) may define a pad zone comprising one or more of the pages subsequent to the unsafe zone. Step (D) may resume operation of the solid-state drive by writing new data subsequent to the pad zone. | 2014-09-18 |
20140269054 | NON-VOLATILE MEMORY AND METHOD OF OPERATION THEREOF - A method of altering threshold voltage distribution of a non-volatile MLC memory before the memory is programmed according to a pre-designated coding table. The method includes grouping a plurality of cells which are pre-designated to have the same first bit voltage in a same main state and then grouping the cells in a selected main state into a same sub state if they have the same pre-designated second bit voltage. The method further has a step by elevating the first bit voltage of the cells with highest pre-designated second bit voltage to a voltage which is greater than the voltage of the pre-designated highest main state. | 2014-09-18 |
20140269055 | SEMICONDUCTOR MEMORY DEVICE - Each memory cell has a threshold voltage to distinguish a storage data item. A controller generates one of storage data items from one or more sets of reception data, stores the storage data item, randomizes data transmission for memory cells, instructs the cells to store the randomized data, uses read voltage candidates to read storage data from the cells, counts a distribution of voltages stored in the cells for each read voltage candidate, specifies a minimum read voltage candidate where a sum of the counting exceeds an expected number, and uses the specified candidate as a read voltage to distinguish a first storage data item corresponding to the expected number and an adjacent second storage data item. | 2014-09-18 |
20140269056 | SOLID STATE DRIVE ENCOUNTERING POWER FAILURE AND ASSOCIATED DATA STORAGE METHOD - A solid state drive and its associated data storage method are provided. The data storage method comprising steps of: receiving data-for-writing from a host, and transforming the data-for-writing to data-for-storage; comparing a supply voltage and a predetermined voltage; and when the supply voltage is lower than the predetermined voltage, proceeding a strong-page programming procedure for storing the data-for-storage to a blank area of a multi-level cell flash memory. | 2014-09-18 |
20140269057 | NON-VOLATILE MEMORY DEVICE AND PROGRAMMING METHOD - A method of programming a non-volatile memory device includes; defining a set of verification voltages, setting a maximum verification voltage among verification voltages that are less than or equal to a first target programming voltage to be a target verification voltage, calculating a number of extra pulses based on the target verification voltage and the first target programming voltage, verifying whether a threshold voltage of the memory cell is equal to or greater than the target verification voltage by applying an incremental step pulse program (ISPP) pulse to the memory cell and then applying at least one verification voltage in the set of verification voltages to the memory cell, and further applying the ISPP pulse to the memory cell a number of times equal to the number of extra pulses when the threshold voltage is verified to be equal to or greater than the target verification voltage. | 2014-09-18 |
20140269058 | Non-volatile Memory Program Algorithm Device And Method - A non-volatile memory device and method for programming cells using repeated pulses of program voltages, with interleaved read operations to determine the level of read current, until the desired programming state is achieved. Each successive program pulse has one or more program voltages increased by a step value relative to the previous pulse. For a single level cell type, each cell is individually removed from the programming pulses after reaching a first read current threshold, and the step value is increased for one or more kicker pulses thereafter. For a multi-level cell type, the step value drops after one of the cells reaches a first read current threshold, some cells are individually removed from the programming pulses after reaching a second read current threshold while others are individually removed from the programming pulses after reaching a third read current threshold. | 2014-09-18 |
20140269059 | SHIFTING CELL VOLTAGE BASED ON GROUPING OF SOLID-STATE, NON-VOLATILE MEMORY CELLS - Cells of a solid-state, non-volatile memory are assigned to one of a plurality of groups. Each group is defined by expected symbols stored in the cells in view of actual symbols read from the cells. Based on cell counts within the groups, it can be determined that a shift in a reference voltage will reduce a collective bit error rate of the cells. The shift can be applied to data access operations affecting the cells. | 2014-09-18 |
20140269060 | INTEGRATED CIRCUITS AND METHODS FOR OPERATING INTEGRATED CIRCUITS WITH NON-VOLATILE MEMORY - Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector. | 2014-09-18 |
20140269061 | High Speed Sensing For Advanced Nanometer Flash Memory Device - Improved sensing circuits and improved bit line layouts for advanced nanometer flash memory devices are disclosed. | 2014-09-18 |
20140269062 | Low Leakage, Low Threshold Voltage, Split-Gate Flash Cell Operation - A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance. | 2014-09-18 |
20140269063 | METHOD FOR DRIVING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The electrical charge of a bit line is discharged, the potential of the bit line is charged via a transistor for writing data, and the potential of the bit line which is changed by the charging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data. | 2014-09-18 |
20140269064 | SOURCE LINE FLOATING CIRCUITS, MEMORY DEVICES INCLUDING THE SAME AND METHODS OF READING DATA IN A MEMORY DEVICE - A source line floating circuit includes a plurality of floating units. The floating units directly receive decoded row address signals or voltages of word lines as floating control signals, respectively. The decoded row address signals are activated selectively in response to a row address signal. The floating units control electrical connections between source lines and a source voltage in response to the floating control signals in a read operation. Related devices and methods are also described. | 2014-09-18 |
20140269065 | NAND Flash Memory - Serial NAND flash memory may be provided with the characteristics of continuous read of the memory across page boundaries and from logically contiguous memory locations without wait intervals, while also being clock-compatible with the high performance serial flash NOR (“HPSF-NOR”) memory read commands so that the serial NAND flash memory may be used with controllers designed for HPSF-NOR memory. Serial NAND flash memory having these compatibilities is referred to herein as high-performance serial flash NAND (“SPSF-NAND”) memory. Since devices and systems which use HPSF-NOR memories and controllers often have extreme space limitations, HPSF-NAND may also be provided with the same physical attributes of low pin count and small package size of HPSF-NOR memory for further compatibility. HPSF-NAND memory is particularly suitable for code shadow applications, even while enjoying the low “cost per bit” and low per bit power consumption of a NAND memory array at higher densities. | 2014-09-18 |