38th week of 2014 patent applcation highlights part 54 |
Patent application number | Title | Published |
20140264561 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first fin-shaped silicon layer on a substrate and a second fin-shaped silicon layer on the substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. A silicide in upper portions of n-type and p-type diffusion layers in the upper portions of the first and second fin-shaped silicon layers. A metal gate line is connected to first and second metal gate electrodes and extends in a direction perpendicular to the first fin-shaped silicon layer and the second fin-shaped silicon layer. A first contact is in direct contact with the n-type diffusion layer in the upper portion of the first pillar-shaped silicon layer, and a second contact is in direct contact with the p-type diffusion layer in the upper portion of the second pillar-shaped silicon layer. | 2014-09-18 |
20140264562 | Field Effect Transistor Devices with Regrown P-Layers - A transistor device includes a drift layer having a first conductivity type, a body layer on the drift layer, the body layer having a second conductivity type opposite the first conductivity type, and a source region on the body layer, the source region having the first conductivity type. The device further includes a trench extending through the source region and the body layer and into the drift layer, a channel layer on the inner sidewall of the trench, the channel layer having the second conductivity type and having an inner sidewall opposite an inner sidewall of the trench, a gate insulator on the inner sidewall of the channel layer, and a gate contact on the gate insulator. | 2014-09-18 |
20140264563 | Field Effect Transistor Devices with Protective Regions - A transistor device includes a first conductivity type drift layer, a second conductivity type first region in the drift layer, a body layer having the second conductivity type on the drift layer including the first region, a source layer on the body layer, and a body contact region that extends through the source layer and the body layer and into the first region. The transistor device further includes a trench through the source layer and the body layer and extending into the drift layer adjacent the first region. The trench has an inner sidewall facing away from the first region. A gate insulator is on the inner sidewall of the trench, and a gate contact is on the gate insulator. | 2014-09-18 |
20140264564 | Field Effect Transistor Devices with Buried Well Protection Regions - A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator. | 2014-09-18 |
20140264565 | METHOD OF FORMING A TRANSISTOR AND STRUCTURE THEREFOR - In one embodiment, a semiconductor device is formed to include a gate structure extending into a semiconductor material that is underlying a first region of semiconductor material. The gate structure includes a conductor and also a gate insulator that has a first portion positioned between the gate conductor and a first portion of the semiconductor material that underlies the gate conductor. The first portion of the semiconductor material is configured to form a channel region of the transistor which underlies the gate conductor. The gate structure may also include a shield conductor overlying the gate conductor and having a shield insulator between the shield conductor and the gate conductor. The shield insulator may also have a second portion positioned between the shield conductor and a second portion of the gate insulator and a third portion overlying the shield conductor. | 2014-09-18 |
20140264566 | SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD AND OPERATING METHOD OF THE SAME - A memory device and a manufacturing method of the same are provided. The memory device includes a substrate, a memory material layer, a first dielectric layer, a first gate layer, a second gate layer, and a source/drain (S/D) region. The substrate has a trench, and the memory material layer is formed on a sidewall of the trench. The first gate layer, the second gate layer, and the first dielectric layer, which is formed between the first gate layer and the second gate layer, are filled in the trench. The source/drain region is formed in the substrate and adjacent to the memory material layer. The first gate layer is extended in a direction perpendicular to a direction in which the source/drain region is extended. | 2014-09-18 |
20140264567 | DIRECT-DRAIN TRENCH FET WITH SOURCE AND DRAIN ISOLATION - In a general aspect, an apparatus can include a semiconductor layer of a first conductivity type, the semiconductor layer having a top-side surface. The apparatus can also include a well region of a second conductivity type opposite the first conductivity type, the well region being disposed in an upper portion of the semiconductor layer. The apparatus can further include a gate trench disposed in the semiconductor layer, the gate trench extending through the well region, and a drain contact disposed, at least in part, on the top-side surface of the semiconductor layer, the drain contact being adjacent to the well region. The apparatus can still further include an isolation trench disposed between the drain contact and the gate trench in the semiconductor layer, the isolation trench extending through the well region. | 2014-09-18 |
20140264568 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor device, a trench is formed by removing an upper portion of a substrate. A gate insulation layer pattern is formed on an inner wall of the trench. A gate electrode is formed on the gate insulation layer pattern. The gate electrode fills a lower portion of the trench. A capping layer is formed on the gate electrode and the gate insulation layer pattern. The capping layer is partially oxidized to form a first capping layer pattern and a second capping layer pattern. The first capping layer pattern is not oxidized, and the second capping layer pattern is oxidized. A third capping layer pattern is formed on the second capping layer pattern, the third capping layer pattern filling an upper portion of the trench. | 2014-09-18 |
20140264569 | METHODS AND APPARATUS RELATED TO TERMINATION REGIONS OF A SEMICONDUCTOR DEVICE - In one general aspect, an apparatus can include a semiconductor region, and a trench defined within the semiconductor region. The trench can have a depth aligned along a vertical axis and have a length aligned along a longitudinal axis orthogonal to the vertical axis. The trench can have a first portion of the length included in a termination region of the semiconductor region and can have a second portion of the length included in an active region of the semiconductor region. | 2014-09-18 |
20140264570 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME - A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased. | 2014-09-18 |
20140264571 | SHIELDED GATE TRENCH MOSFET PACKAGE - A trench formed in a body layer and epitaxial layer of a substrate is lined with a dielectric layer. A shield electrode formed within a lower portion of the trench is insulated by the dielectric layer. A gate electrode formed in the trench above the shield electrode is insulated from the shield electrode by another dielectric layer. One or more source regions formed within the body layer is adjacent a sidewall of the trench. A source pad formed above the body layer is electrically connected to the source regions and insulated from the gate electrode and shield electrode. The source pad provides an external contact to the source region. A gate pad provides an external contact to the gate electrode. A shield electrode pad provides an external contact to the shield electrode. A resistive element is electrically connected between the shield electrode pad and a source lead. | 2014-09-18 |
20140264572 | METHODS OF FORMING SEMICONDUCTOR DEVICES USING HARD MASK LAYERS - A method of forming a semiconductor structure can include forming a photolithography mask on a silicon fin having a hard mask layer thereon extending in a first direction. A trench can be formed through the hard mask layer into the silicon fin using the photolithography mask, where the trench extends in a second direction to separate the silicon fin into first and second fin structures extending end-to-end in the first direction. A portion of the trench formed by the hard mask layer can be widened relative to a lower portion of the trench defined by the first and second fin structures. | 2014-09-18 |
20140264573 | METHOD FOR FORMING ACCUMULATION-MODE FIELD EFFECT TRANSISTOR WITH IMPROVED CURRENT CAPABILITY - An accumulation-mode field effect transistor including a plurality of gates. The accumulation-mode field effect transistor including a semiconductor region including a channel region adjacent to but insulated from each of the plurality of gates. | 2014-09-18 |
20140264574 | ELECTRONIC DEVICE INCLUDING VERTICAL CONDUCTIVE REGIONS AND A PROCESS OF FORMING THE SAME - An electronic device can include different vertical conductive structures that can be formed at different times. The vertical conductive structures can have the same or different shapes. In an embodiment, an insulating spacer can be used to help electrically insulate a particular vertical conductive structure from another part of the workpiece, and an insulating spacer may not be used to electrically isolate a different vertical conductive structure. The vertical conductive structures can be tailored for particular electrical considerations or to a process flow when formation of other electronic components may also be formed within either or both of the particular vertical conductive structures. | 2014-09-18 |
20140264575 | MECHANISMS FOR DOPING LIGHTLY-DOPED-DRAIN (LDD) REGIONS OF FINFET DEVICES - The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving dopants from highly doped source and drain regions by annealing for finFET devices are provided. The mechanisms overcome the limitation by shadowing effects of ion implantation for advanced finFET devices. The highly doped source and drain regions are formed by epitaxial growing one or more doped silicon-containing materials from recesses formed in the fins. The dopants are then driven into the LDD regions by advanced annealing process, which can achieve targeted dopant levels and profiles in the LDD regions. | 2014-09-18 |
20140264576 | INTEGRATION OF LOW RDSON LDMOS WITH HIGH SHEET RESISTANCE POLY RESISTOR - A method for forming a low Rds | 2014-09-18 |
20140264577 | Adjustable Transistor Device - A transistor device includes at least one first type transistor cell including a drift region, a source region, a body region arranged between the source region and the drift region, a drain region, a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric, and a field electrode adjacent the drift region and dielectrically insulated from the drift region by a field electrode dielectric. A gate terminal is coupled to the gate electrode, a source terminal is coupled to the source region, and a control terminal is configured to receive a control signal. A variable resistor is connected between the field electrode and the gate terminal or the source terminal. The variable resistor includes a variable resistance configured to be adjusted by the control signal received at the control terminal. | 2014-09-18 |
20140264578 | SWITCH CIRCUIT USING LDMOS DEVICE - The present invention relates to a switch circuit, and more particularly, to a switch circuit that uses an LDMOS (lateral diffusion metal oxide semiconductor) device inside an IC (Integrated Circuit). In the switch circuit that uses the LDMOS device according to an embodiment of the present invention, a gate-source voltage (V | 2014-09-18 |
20140264579 | Field Effect Transistor Devices with Buried Well Regions and Epitaxial Layers - A method of forming a transistor device includes providing a drift layer having a first conductivity type and an upper surface, forming first regions in the drift layer and adjacent the upper surface, the first regions having a second conductivity type that is opposite the first conductivity type and being spaced apart from one another, forming a body layer on the drift layer including the source regions, forming spaced apart source regions in the body layer above respective ones of the first regions, forming a vertical conduction region in the body layer between the source regions, the vertical conduction region having the first conductivity type and defining channel regions in the body layer between the vertical conduction region and respective ones of the source regions, forming a gate insulator on the body layer, and forming a gate contact on the gate insulator. | 2014-09-18 |
20140264580 | Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device - A semiconductor device comprises a transistor. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode being adjacent to the body region. The body region, the drift zone, the source region and the drain region are disposed in a first semiconductor layer having a first main surface. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The transistor further comprises a drift control region arranged adjacent to the drift zone, the drift control region being disposed over the first main surface. | 2014-09-18 |
20140264581 | LOW ON RESISTANCE SEMICONDUCTOR DEVICE - A semiconductor device is provided having a dual dielectric layer structure defined by a thin dielectric layer adjacent to a thick dielectric layer. More particularly, a high voltage metal oxide semiconductor transistor having a dual gate oxide layer structure comprising a thin gate oxide layer adjacent to a thick oxide/thin oxide layer may be provided. Such structures may be used in extended drain metal oxide semiconductor field effect transmitters, laterally diffused metal oxide field effect transistors, or any high voltage metal oxide semiconductor transistor. Methods of fabricating an extended drain metal oxide semiconductor transistor device are also provided. | 2014-09-18 |
20140264582 | 800 V SUPERJUNCTION DEVICE - A superjunction device includes a substrate having first and second main surfaces and a first doping concentration of a first dopant. A first semiconductor layer having a second doping concentration of the first dopant is formed on the substrate. A second semiconductor layer is formed on the first layer and has a main surface. At least one trench extends from the main surface at least partially into the first semiconductor layer. A first region having a third doping concentration of the first dopant extends at least partially between the main surface and the first layer. A second region having a fourth doping concentration of a second dopant is disposed between the first region and a trench sidewall and extends at least partially between the main surface and the first layer. A third region having a fifth doping concentration of the first dopant is disposed proximate the main surface. | 2014-09-18 |
20140264583 | HIGH-VOLTAGE SEMICONDUCTOR DEVICE - A withstand voltage region is formed to surround a logic circuit formation region. A high-voltage MOSFET for level shifting is formed in part of the withstand voltage region. A p | 2014-09-18 |
20140264584 | LATERAL DOUBLE-DIFFUSED HIGH VOLTAGE DEVICE - A method of forming a device is disclosed. The method includes providing a substrate with a device region. The method also includes forming a transistor in the device region. The transistor includes a gate having first and second sides along a gate direction. The transistor also includes a first doped region adjacent to a first side of the gate, a second doped region adjacent to a second side of the gate, and a channel under the gate. The transistor further includes a channel trench in the channel of the gate, wherein the channel trench is along a trench direction which is at an angle θ other than 90° with respect to the gate direction. | 2014-09-18 |
20140264585 | SEMICONDUCTOR DEVICE INCLUDING LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR - A semiconductor device and method of manufacturing the same are provided. A device can include an LDMOS region and a high side region on a semiconductor substrate. The device can further include an insulating region separating the LDMOS region from the high side region and the insulating region can include a plurality of second conductive type wells, a plurality of second conductive type buried layer patterns, or both. | 2014-09-18 |
20140264586 | BOOTSTRAP FET AND METHOD OF MANUFACTURING THE SAME - A laterally diffused metal oxide semiconductor (LDMOS) device, and a method of manufacturing the same are provided. The LDMOS device can include a drain region of a bootstrap field effect transistor (FET), a source region of the bootstrap FET, a drift region formed between the drain region and the source region, and a gate formed at one side of the source region and on the drift region. | 2014-09-18 |
20140264587 | LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR AND METHOD FOR FABRICATING THE SAME - A laterally-diffused metal oxide semiconductor (LDMOS) device and method of manufacturing the same are provided. The LDMOS device can include a drift region, a source region and a drain region spaced a predetermined interval apart from each other in the drift region, a field insulating layer formed in the drift region between the source region and the drain region, and a first P-TOP region formed under the field insulating layer. The LDMOS device can further include a gate polysilicon covering a portion of the field insulating layer, a gate electrode formed on the gate polysilicon, and a contact line penetrating the gate electrode, the gate polysilicon, and the field insulating layer. | 2014-09-18 |
20140264588 | Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with Step Oxide - The present disclosure relates to a method of ultra-high voltage UHV device formation which utilizes a composite step oxide as a gate oxide to achieve isolation of the gate and drain-side spacer from the drain region. The thickness of the step gate oxide improves device breakdown voltage, and allows for the drain to be self-aligned to the gate, thus reducing device drift region and improves device on state resistance. The composite isolation layer comprises two or more dielectric layers which are formed through a series of deposition and etch steps including thermal oxidation and chemical vapor deposition. The composite isolation layer may then be etched to form a self-align structure which utilizes the spacers as hard mask to achieve a reduced device pitch relative to some prior art methods. A thicker gate oxide under one or both spacers can improve yield and high temperature operating life of the UHV device. | 2014-09-18 |
20140264589 | SEMICONDUCTOR STRUCTURE PROFILE - One or more embodiments of techniques or systems for forming a semiconductor structure are provided herein. In some embodiments, a semiconductor structure includes a substrate, a first lightly doped drain (LDD), a second LDD, an interface layer (IL), a high-k stack, a gate region, a dummy poly region, a first hard mask (HM) region, a second HM region, and a seal spacer region. The HK stack has a HK stack width and the gate region has a gate region width that is less than or substantially equal to the HK stack width. Because of the increased width of the HK stack, some of the HK stack likely overlaps some of the first LDD or the second LDD. In this manner, a saturation current and a threshold voltage associated with the semiconductor structure are improved. The increased width of the HK stack also protects more of the IL during LDD implanting. | 2014-09-18 |
20140264590 | FinFET with Bottom SiGe Layer in Source/Drain - A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure between the source and the drain, a gate dielectric layer over the channel, and a gate over the gate dielectric layer. At least one of the source and the drain includes a bottom SiGe layer. | 2014-09-18 |
20140264591 | METHOD AND STRUCTURE FOR DIELECTRIC ISOLATION IN A FIN FIELD EFFECT TRANSISTOR - A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants. | 2014-09-18 |
20140264592 | Barrier Layer for FinFET Channels - Integrated circuit devices having FinFETs with channel regions low in crystal defects and current-blocking layers underneath the channels to improve electrostatic control. Optionally, an interface control layer formed of a high bandgap semiconductor is provided between the current-blocking layer and the channel. The disclosure also provides methods of forming integrated circuit devices having these structures. The methods include forming a FinFET fin including a channel by epitaxial growth, then oxidizing a portion of the fin to form a current-blocking layer. | 2014-09-18 |
20140264593 | Hybrid ETSOI Structure to Minimize Noise Coupling from TSV - In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided. | 2014-09-18 |
20140264594 | FORMATION OF BULK SiGe FIN WITH DIELECTRIC ISOLATION BY ANODIZATION - A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure. | 2014-09-18 |
20140264595 | FORMING STRAINED AND RELAXED SILICON AND SILICON GERMANIUM FINS ON THE SAME WAFER - Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon. | 2014-09-18 |
20140264596 | PARTIALLY ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTORS - A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates. | 2014-09-18 |
20140264597 | SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME - To fabricate a semiconductor device, a fin is formed to protrude from a substrate. The fin is extended in a first direction. A gate line is formed on the fin and the substrate. The gate line is extended in a second direction crossing the first direction. An amorphous material layer is conformally formed to cover the substrate, the fin, and the gate line. The amorphous material layer is partially removed, thereby forming a first remaining amorphous layer on side walls of the fin and a second remaining amorphous layer on side walls of the gate line. The first remaining amorphous layer and the second remaining amorphous layer are annealed and the first remaining amorphous material layer and the second remaining amorphous material layer are crystallized into a monocrystalline material layer and a polycrystalline material layer, respectively. The polycrystalline material layer is removed. | 2014-09-18 |
20140264598 | STRESS ENHANCED FINFET DEVICES - A non-planar semiconductor with enhanced strain includes a substrate and at least one semiconducting fin formed on a surface of the substrate. A gate stack is formed on a portion of the at least one semiconducting fin. A stress liner is formed over at least each of a plurality of sidewalls of the at least one semiconducting fin and the gate stack. The stress liner imparts stress to at least a source region, a drain region, and a channel region of the at least one semiconducting fin. The channel region is located in at least one semiconducting fin beneath the gate stack. | 2014-09-18 |
20140264599 | SEMICONDUCTOR DEVICE HAVING REDUCED LEAKAGE CURRENT AT BREAKDOWN AND METHOD OF FABRICATING THEREOF - A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n− (HVN−) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a drain n− well and a source n− well disposed in the HVN− doped well and HVPD well, respectively, is provided. A method of fabricating the semiconductor device is also provided. In certain embodiments, the method of fabricating the semiconductor device is characterized by implanting the HVN− ions at a first tilt angle and/or implanting the HVPD ions at a second tilt angle. | 2014-09-18 |
20140264600 | FORMATION OF BULK SiGe FIN WITH DIELECTRIC ISOLATION BY ANODIZATION - A method of fabricating a semiconductor device is provided that includes providing a material stack that includes a silicon layer, a doped semiconductor layer, and an undoped silicon germanium layer. At least one fin structure is formed from the material stack by etching through the undoped silicon germanium layer, the doped semiconductor layer, and etching a portion of the silicon-containing layer. An isolation region is formed in contact with at least one end of the at least one fin structure. An anodization process removes the doped semiconductor layer of the at least one fin structure to provide a void. A dielectric layer is deposited to fill the void that is present between the silicon layer and the doped semiconductor layer. Source and drain regions are then formed on a channel portion of the at least one fin structure. | 2014-09-18 |
20140264601 | STRAINED SILICON NFET AND SILICON GERMANIUM PFET ON SAME WAFER - Various embodiments form silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is obtained. The semiconductor wafer comprises a substrate, a dielectric layer, and a semiconductor layer including silicon germanium (SiGe). At least one SiGe fin is formed from at least a first SiGe region of the semiconductor layer in at least one PFET region of the semiconductor wafer. Strained silicon is epitaxially grown on at least a second SiGe region of the semiconductor layer. At least one strained silicon fin is formed from the strained silicon in at least one NFET region of the semiconductor wafer. | 2014-09-18 |
20140264602 | FORMING STRAINED AND RELAXED SILICON AND SILICON GERMANIUM FINS ON THE SAME WAFER - Various embodiments form strained and relaxed silicon and silicon germanium fins on a semiconductor wafer. In one embodiment a semiconductor wafer is formed. The semiconductor wafer comprises a substrate, a dielectric layer, and a strained silicon germanium (SiGe) layer. At least one region of the strained SiGe layer is transformed into a relaxed SiGe region. At least one strained SiGe fin is formed from a first strained SiGe region of the strained SiGe layer. At least one relaxed SiGe fin is formed from a first portion of the relaxed SiGe region. Relaxed silicon is epitaxially grown on a second strained SiGe region of the strained SiGe layer. Strained silicon is epitaxially grown on a second portion of the relaxed SiGe region. At least one relaxed silicon fin is formed from the relaxed silicon. At least one strained silicon fin is formed from the strained silicon. | 2014-09-18 |
20140264603 | PARTIALLY ISOLATED FIN-SHAPED FIELD EFFECT TRANSISTORS - A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates. | 2014-09-18 |
20140264604 | FinFET Having Source-Drain Sidewall Spacers with Reduced Heights - An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and the second portion on opposite sides of the semiconductor fin. The semiconductor fin has a first height. A gate stack is overlying a middle portion of the semiconductor fin. A fin spacer is on a sidewall of an end portion of the semiconductor fin. The fin spacer has a second height, wherein the first height is greater than about two times the second height. | 2014-09-18 |
20140264605 | Hybrid ETSOI Structure to Minimize Noise Coupling from TSV - In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI segments each of the ETSOI segments having a width of from about 3 nm to about 20 nm. A gate electrode is formed over a portion of the one or more ETSOI segments which serves as a channel region of a transistor, wherein portions of the one or more ETSOI segments extending out from under the gate electrode serve as source and drain regions of the transistor. At least one TSV is formed in the ETSOI wafer adjacent to the transistor. An electronic device is also provided. | 2014-09-18 |
20140264606 | PIXEL STRUCTURE - A pixel structure includes a flexible substrate, an active device, a conductive pattern, a first insulation layer, and a pixel electrode. The active device is disposed on the flexible substrate and includes a gate, a channel, a source, and a drain. The source and the drain are connected to the channel and are separated from each other. The channel and the gate are stacked in a thickness direction. The active device is disposed between the conductive pattern and the flexible substrate. The conductive pattern is electrically connected to the drain of the active device. The first insulation layer covers the conductive pattern and has first contact holes separated from one another, and the first contact holes expose the conductive pattern. The first insulation layer is disposed between the pixel electrode and the conductive pattern. The pixel electrode is electrically connected to the conductive pattern through the first contact holes. | 2014-09-18 |
20140264607 | III-V FINFETS ON SILICON SUBSTRATE - A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a non-silicon containing semiconductor material in the trenches using an aspect ratio trapping process to form fins. The one or more dielectric layers are etched to expose a portion of the fins. A barrier layer is epitaxially grown on the portion of the fins, and a gate stack is formed over the fins. A spacer is formed around the portion of the fins and the gate stack. Dopants are implanted into the portion of the fins. Source and drain regions are grown over the fins using a non-silicon containing semiconductor material. | 2014-09-18 |
20140264608 | DITCHES NEAR SEMICONDUCTOR FINS AND METHODS FOR FORMING THE SAME - A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor strip is between and contacting the isolation regions. A semiconductor fin overlaps, and is joined to, the semiconductor strip. A ditch extends from a top surface of the isolation regions into the isolation regions, wherein the ditch adjoins the semiconductor fin. | 2014-09-18 |
20140264609 | SEMICONDUCTOR DEVICE INCLUDING DUMMY ISOLATION GATE STRUCTURE AND METHOD OF FABRICATING THEREOF - A device having a first active transistor, a second active transistor, an isolation gate structure, and an active region underlying each of the first active transistor, the second active transistor, and the isolation gate structure is provided. The first and second active transistors each have a metal gate with a first type of conductivity (e.g., one of n-type and p-type). The isolation gate structure interposes the first and second active transistors. The isolation gate structure has a metal gate with a second type of conductivity (e.g., the other one of n-type and p-type). A method of fabricating devices such as this are also described. | 2014-09-18 |
20140264610 | METAL OXIDE SEMICONDUCTOR (MOS) ISOLATION SCHEMES WITH CONTINUOUS ACTIVE AREAS SEPARATED BY DUMMY GATES AND RELATED METHODS - Embodiments disclosed in the detailed description include metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates. A MOS device includes an active area formed from a material with a work function that is described as either an n-metal or a p-metal. Active components are formed on this active area using materials having a similar work function. Isolation is effectuated by positioning a dummy gate between the active components. The dummy gate is made from a material having an opposite work function relative to the material of the active area. For example, if the active area was a p-metal material, the dummy gate would be made from an n-metal, and vice versa. | 2014-09-18 |
20140264611 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component and a method for manufacturing the semiconductor component. In accordance with an embodiment, the semiconductor component includes a plurality of stacked semiconductor chips mounted to a support structure, wherein one semiconductor chip has a side with a plurality of electrical contacts electrically coupled to conductive tabs of the support structure. An electrical connector electrically connects an electrical contact formed from a side opposite the side with the plurality of electrical contacts to a corresponding conductive tab. Another semiconductor chip is mounted to the electrical connector and electrical contacts formed from this semiconductor chip are electrically connected to corresponding conductive tabs of the support structure. | 2014-09-18 |
20140264612 | GROWTH OF EPITAXIAL SEMICONDUCTOR REGIONS WITH CURVED TOP SURFACES - Embodiments include epitaxial source/drain regions having curved top surfaces and methods of forming the same. According to an exemplary embodiment, an epitaxial semiconductor region having a curved top surface may be formed by providing a region having a substantially planar bottom made of semiconductor material and sidewalls made of non-semiconductor material substantially perpendicular to the planar bottom, depositing a semiconductor layer having a crystalline portion on the flat bottom and amorphous portions on the sidewalls using a low pressure chemical vapor deposition process with a nitrogen carrier gas, and removing the amorphous portions from the sidewalls. To further increase the thickness of the epitaxial semiconductor region, the method may cycle between depositing a semiconductor layer having a crystalline portion on the flat bottom and amorphous portions on the sidewalls; and removing the amorphous portions on the sidewalls until the combined thickness of all the crystalline portions reaches a desired thickness. | 2014-09-18 |
20140264613 | INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ACTIVE AREA PROTECTION - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure. | 2014-09-18 |
20140264614 | Spacer Enabled Poly Gate - A spacer etching process produces ultra-narrow polysilicon and gate oxides for insulated gates used with insulated gate transistors. Narrow channels are formed using dielectric and spacer film deposition techniques. The spacer film is removed from the dielectric wherein narrow channels are formed therein. Insulating gate oxides are grown on portions of the semiconductor substrate exposed at the bottoms of these narrow channels. Then the narrow channels are filled with polysilicon. The dielectric is removed from the face of the semiconductor substrate, leaving only the very narrow gate oxides and the polysilicon. The very narrow gate oxides and the polysilicon are separated into insulated gates for the insulated gate transistors. | 2014-09-18 |
20140264615 | 3D MEMORY PROCESS AND STRUCTURES - A semiconductor device includes a substrate, a stack structure and a transistor. The substrate includes a first region and a second region. The stack structure is formed over the substrate in the first region. The transistor structure has a gate formed in the second region. A bottom portion of the gate structure is disposed at a height from the substrate that is less than a height between the substrate and a bottom portion of the stack structure. | 2014-09-18 |
20140264616 | Epitaxial Growth Between Gates - An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between two gate devices. The device further includes at least one dummy gate between two epitaxially grown active regions. Each active region is substantially uniform in length. | 2014-09-18 |
20140264617 | HK/MG PROCESS FLOWS FOR P-TYPE SEMICONDUCTOR DEVICES - The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel. | 2014-09-18 |
20140264618 | ISOLATION STRUCTURE - A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well. | 2014-09-18 |
20140264619 | GATE PAD AND GATE FEED BREAKDOWN VOLTAGE ENHANCEMENT - A semiconductor chip includes a semiconductor layer having first and second opposing main surfaces. A plurality of MOSFET cells are at least partially formed in the semiconductor layer. A gate pad region is at least partially formed in the semiconductor layer and includes a gate pad contact and a first plurality of trenches extending from the first main surface. The first plurality of trenches are spaced apart from one another in a direction parallel to the first main surface by about 45 micrometers to about 60 micrometers. At least one gate feed region is at least partially formed in the semiconductor layer and includes a gate feed contact and a second plurality of trenches extending from the first main surface. The second plurality of trenches are spaced apart from one another in the direction parallel to the first main surface by about 45 micrometers to about 60 micrometers. | 2014-09-18 |
20140264620 | STRIPE ORIENTATION FOR TRENCHES AND CONTACT WINDOWS - A semiconductor device includes a semiconductor layer having first and second main surfaces, with the first surface defining a plane containing first and second perpendicular axes. A first gate is disposed proximate the first main surface and extends parallel to the first axis. A dielectric layer is formed on the first main surface and separates the first gate from the first main surface. First and second trenches are formed in the semiconductor layer proximate the first gate and spaced apart in a direction parallel to the first axis. First and second pluralities of contact windows are formed in the dielectric layer to expose the first main surface and are respectively arranged in first and second rows extending between the first and second trenches in a direction parallel to the first axis. Adjacent contact windows in each first row are separated only by the dielectric layer. | 2014-09-18 |
20140264621 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME - A semiconductor structure and a manufacturing method for the same are provided. The method comprises following steps. A first gate structure is formed on a substrate in a first region. A protecting layer is formed covering the first gate structure. A second gate structure is formed on the substrate in second region exposed by the protecting layer and adjacent to the first region. | 2014-09-18 |
20140264622 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate of a first conductivity type, a mesh-type gate electrode including first portions extending in a first direction and second portions extending in a second direction crossing the first direction over the substrate. The mesh-type gate structure may have a plurality of openings, and source regions and drain regions of second conductivity type alternately arranged in the first direction and the second direction in the substrate at locations corresponding to the openings. | 2014-09-18 |
20140264623 | TRANSISTOR WITH DEEP NWELL IMPLANTED THROUGH THE GATE - A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate surface having a first gate stack thereon to form NLDD regions for forming n-source/drain extension regions for at least a portion of a plurality of n-channel MOS (NMOS) transistors on the IC. A p-type dopant is implanted at a second masking level that exposes an n-region in the substrate surface having a second gate stack thereon to form PLDD regions for at least a portion of a plurality of p-channel MOS (PMOS) transistors on the IC. A second n-type dopant is retrograde implanted including through the first gate stack to form a deep nwell (DNwell) for the portion of NMOS transistors. A depth of the DNwell is shallower below the first gate stack as compared to under the NLDD regions. | 2014-09-18 |
20140264624 | Metal Gate Structure and Method - A semiconductor structure comprises a metal gate structure formed in a substrate, wherein the metal gate structure comprises a first film formed of a first material and formed on a bottom and sidewalls of a gate trench, a second film formed of a second material and formed over the first film and a gate electrode formed over the second film. The semiconductor structure further comprises a resistor structure formed in the substrate, where the resistor structure comprises a third film formed of the first material and formed on a bottom and sidewalls of a resistor trench and a fourth film formed of the second material and formed over the third film. | 2014-09-18 |
20140264625 | Merged Active Devices on a Common Substrate - Merged active devices on a common substrate are presented. Methods for operating and fabricating such merged active devices are also presented. | 2014-09-18 |
20140264626 | METHOD FOR FORMING A GATE ELECTRODE OF A SEMICONDUCTOR DEVICE, GATE ELECTRODE STRUCTURE FOR A SEMICONDUCTOR DEVICE AND ACCORDING SEMICONDUCTOR DEVICE STRUCTURE - The present disclosure provides, in some aspects, a gate electrode structure for a semiconductor device. In some illustrative embodiments herein, the gate electrode structure includes a first high-k dielectric layer over a first active region of a semiconductor substrate and a second high-k dielectric layer on the first high-k dielectric layer. The first high-k dielectric layer has a metal species incorporated therein for adjusting the work function of the first high-k dielectric layer. | 2014-09-18 |
20140264627 | MULTI-GATE TRANSISTOR - Disclosed is a multi-gate transistor which includes a plurality of gates that is branched from one port, that is alternately formed to face each other, and in which currents flow in the adjacent gates in an opposite direction to each other; a source that is formed on one side or the other side of each of the plurality of gates; and a drain that is formed on the other side or the one side of each of the plurality of gates. | 2014-09-18 |
20140264628 | Multi-Gate and Complementary Varactors in FinFET Process - A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor. | 2014-09-18 |
20140264629 | LOCAL INTERCONNECT STRUCTURES FOR HIGH DENSITY - A local interconnect structure is provided that includes a gate-directed local interconnect coupled to an adjacent gate layer through a diffusion-directed local interconnect. | 2014-09-18 |
20140264630 | Integrated Structure - An integrated structure comprises a substrate with a first dielectric layer and a second dielectric cap layer disposed thereon in sequence, a metal gate transistor with a high-k gate dielectric layer on the substrate, a gate electrode embedded within the first dielectric layer and a source/drain within the substrate, a first metal contact penetrating the first dielectric layer and being in direct contact with the source/drain and a through-silicon via penetrating the second dielectric cap layer, the first dielectric layer and the substrate. | 2014-09-18 |
20140264631 | METHODS OF FORMING ALIGNMENT MARKS AND OVERLAY MARKS ON INTEGRATED CIRCUIT PRODUCTS EMPLOYING FINFET DEVICES AND THE RESULTING ALIGNMENT/OVERLAY MARK - One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate. | 2014-09-18 |
20140264632 | SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR HAVING A LAYER OF A STRESS-CREATING MATERIAL AND METHOD FOR THE FORMATION THEREOF - A semiconductor structure is provided including a transistor, the transistor including one or more elongated semiconductor regions, each of the one or more elongated semiconductor regions having a channel region, a gate electrode, wherein the gate electrode is provided at least at two opposite sides of each of the one or more elongated semiconductor regions, and a layer of a stress-creating material, the stress-creating material providing a variable stress, wherein the layer of stress-creating material is arranged to provide a stress at least in the channel region of each of the one or more elongated semiconductor regions, the stress provided in the channel region of each of the one or more elongated semiconductor regions being variable. | 2014-09-18 |
20140264633 | FINFET DEVICES HAVING A BODY CONTACT AND METHODS OF FORMING THE SAME - Fin field-effect transistor devices and methods of forming the fin field-effect transistor devices are provided herein. In an embodiment, a fin field-effect transistor device includes a semiconductor substrate that has a fin. A gate electrode structure overlies the fin. Source and drain halo and/or extension regions and epitaxially-grown source regions and drain regions are formed in the fin and are disposed adjacent to the gate electrode structure. A body contact is disposed on a contact surface of the fin, and the body contact is spaced separately from the halo and/or extension regions and the epitaxially-grown source regions and drain regions. | 2014-09-18 |
20140264634 | FINFET FOR RF AND ANALOG INTEGRATED CIRCUITS - Methods for making a FinFET having reduced device mismatch and low-frequency noise are disclosed for RF/analog IC designs. A semiconductor fin is formed having a height between 2 and 6 times its width, atomically smooth sidewalls, and rounded active corners to minimize device variability. The fin is operable as a channel between a source and a drain. A first layer of SiO | 2014-09-18 |
20140264635 | RF Switch on High Resistive Substrate - A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch. | 2014-09-18 |
20140264636 | ASYMMETRIC CYCLIC DEPOSITON AND ETCH PROCESS FOR EPITAXIAL FORMATION MECHANISMS OF SOURCE AND DRAIN REGIONS - The embodiments of mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) described uses Cl | 2014-09-18 |
20140264637 | STRIP-GROUND FIELD PLATE - Among other things, one or more semiconductor devices and techniques for forming such semiconductor devices are provided. The semiconductor device comprises a strip-ground field plate. The strip-ground field plate is connected to a source region of the semiconductor device and/or a ground plane. The strip-ground field plate provides a release path for a gate edge electric field. The release path directs an electrical field away from a gate region of the semiconductor device. In this way, breakdown voltage and gate charge are improved. | 2014-09-18 |
20140264638 | GATE STACK OF BORON SEMICONDUCTOR ALLOY, POLYSILICON AND HIGH-K GATE DIELECTRIC FOR LOW VOLTAGE APPLICATIONS - A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process. | 2014-09-18 |
20140264639 | GATE STACK OF BORON SEMICONDUCTOR ALLOY, POLYSILICON AND HIGH-K GATE DIELECTRIC FOR LOW VOLTAGE APPLICATIONS - A method of forming a gate structure for a semiconductor device that includes forming a non-stoichiometric high-k gate dielectric layer on a semiconductor substrate, wherein an oxide containing interfacial layer can be present between the non-stoichiometric high-k gate dielectric layer and the semiconductor substrate. At least one gate conductor layer may be formed on the non-stoichiometric high-k gate dielectric layer. The at least one gate conductor layer comprises a boron semiconductor alloy layer. An anneal process is applied, wherein during the anneal process the non-stoichiometric high-k gate dielectric layer removes oxide material from the oxide containing interfacial layer. The oxide containing interfacial layer is thinned by removing the oxide material during the anneal process. | 2014-09-18 |
20140264640 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer. | 2014-09-18 |
20140264641 | SEMICONDUCTOR DEVICE COMPRISING CONTACT STRUCTURES WITH PROTECTION LAYERS FORMED ON SIDEWALLS OF CONTACT ETCH STOP LAYERS - When forming semiconductor devices with contact plugs comprising protection layers formed on sidewalls of etch stop layers to reduce the risk of shorts, the protection layers may be formed by performing a sputter process to remove material from a contact region and redeposit the removed material on the sidewalls of the etch stop layers. | 2014-09-18 |
20140264642 | GAS SENSOR - A gas sensor comprises a set of one or more sensor cells (SC) and a substrate ( | 2014-09-18 |
20140264643 | METHODS OF FORMING BURIED ELECTROMECHANICAL STRUCTURES COUPLED WITH DEVICE SUBSTRATES AND STRUCTURES FORMED THEREBY - Methods of forming integrated MEMS structures are described. Those methods and structures may include forming at least one MEMS structure on a first substrate, forming a first bonding layer on a top surface of the first substrate, and then coupling the first bonding layer disposed on the first substrate to a second substrate, wherein the second substrate comprises a device layer. The bonding may comprise a layer transfer process, wherein an integrated MEMS device is formed. | 2014-09-18 |
20140264644 | MEMS Method and Structure - MEMS structures and methods utilizing a locker film are provided. In an embodiment a locker film is utilized to hold and support a moveable mass region during the release of the moveable mass region from a surrounding substrate. By providing additional support during the release of the moveable mass, the locker film can reduce the amount of undesired movement that can occur during the release of the moveable mass, and preventing undesired etching of the sidewalls of the moveable mass. | 2014-09-18 |
20140264645 | INTEGRATED STRUCTURE WITH BIDIRECTIONAL VERTICAL ACTUATION - A Micro-Electro-Mechanical Systems (MEMS) device includes a first substrate with a first surface and a second surface, the first substrate including a base layer, a moveable beam disposed on the base layer, at least one metal layer, and one or more standoffs disposed on the base layer such that one or more metal layers are situated on the top surface of the one or more standoffs. The MEMS device further includes a second substrate including one or more metal layers bonded to the one or more standoffs resulting in an electrical connection between at least a portion of the one or more metal layers of the second substrate and one or more of the at least one electrode on the bottom surface and the at least one electrode on the top surface. | 2014-09-18 |
20140264646 | Microelectromechanical system and method - A microelectromechanical system, including a first element and a second element, the first element having a first conductive surface facing a second conductive surface of the second element; wherein at least one of the first element and the second element is operable to constrainedly move nearer and farther from the other element; and at least one insulating separating member which is operable to mechanically maintain a separation between the first surface and the second surface, wherein a minimal distance between a first projection of a first contact area of the insulating separating member and a second projection of a second contact area of the insulating separating member is larger than a minimal separation maintained by the insulating separating member between the first element and the second element. | 2014-09-18 |
20140264647 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming a monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of: providing a semiconductor substrate; forming MEMS or NEMS materials on the substrate having conductive, structural, or dielectric layers; forming at least one opening(s) on the semiconductor substrate; positioning on the substrate at least one prefabricated MEMS, NEMS, or semiconductor chip(s), wherein the chip(s) comprise a side facing the substrate; applying at least one filler material(s) in the opening(s) on the semiconductor substrate; applying at least one metallization layer electrically connecting chip(s) to the MEMS or NEMS materials; and performing at least one micro or nano fabrication etching step to remove a portion of the MEMS or NEMS materials. | 2014-09-18 |
20140264648 | MEMS Integrated Pressure Sensor Devices and Methods of Forming Same - A method embodiment includes providing a micro-electromechanical (MEMS) wafer including a polysilicon layer having a first and a second portion. A carrier wafer is bonded to a first surface of the MEMS wafer. Bonding the carrier wafer creates a first cavity. A first surface of the first portion of the polysilicon layer is exposed to a pressure level of the first cavity. A cap wafer is bonded to a second surface of the MEMS wafer opposite the first surface of the MEMS wafer. The bonding the cap wafer creates a second cavity comprising the second portion of the polysilicon layer and a third cavity. A second surface of the first portion of the polysilicon layer is exposed to a pressure level of the third cavity. The first cavity or the third cavity is exposed to an ambient environment. | 2014-09-18 |
20140264649 | MICROMECHANICAL STRUCTURE AND CORRESPONDING PRODUCTION PROCESS - A micromechanical structure includes a substrate, a micromechanical functional structure, and a conductor track arrangement. The substrate has a top side, and the micromechanical functional structure is formed in the substrate on the top side. The conductor track arrangement is formed above the top side of the substrate, and the conductor track arrangement includes at least two insulation layers of non-conductive material and a conductor track layer of conductive material located between the at least two insulation layers. | 2014-09-18 |
20140264650 | Low Frequency Response Microphone Diaphragm Structures And Methods For Producing The Same - A microphone system includes a diaphragm suspended by springs and including a sealing layer that seals passageways which, if left open, would degrade the microphone's frequency response by allowing air to pass from one side of the diaphragm to the other when the diaphragm is responding to an incident acoustic signal. In some embodiments, the sealing layer may include an equalization aperture to allow pressure to equalize on both sides of the diaphragm. | 2014-09-18 |
20140264651 | Semiconductor Devices and Methods of Forming Thereof - In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a sacrificial layer over a first surface of a workpiece having the first surface and an opposite second surface. A membrane is formed over the sacrificial layer. A through hole is etched through the workpiece from the second surface to expose a surface of the sacrificial layer. At least a portion of the sacrificial layer is removed from the second surface to form a cavity under the membrane. The cavity is aligned with the membrane. | 2014-09-18 |
20140264652 | ACOUSTIC SENSOR WITH INTEGRATED PROGRAMMABLE ELECTRONIC INTERFACE - An integrated MEMS acoustic sensor has a MEMS transducer and a programmable electronic interface. The programmable electronic interface includes non-volatile memory and is coupled to the MEMS transducer. Using programmable electrical functions, the programmable electronic interface is operable to sense variations in the MEMS transducer caused by application of an acoustic pressure to the MEMS transducer. | 2014-09-18 |
20140264653 | MEMS Pressure Sensor and Microphone Devices Having Through-Vias and Methods of Forming Same - A method embodiment includes providing a MEMS wafer. A portion of the MEMS wafer is patterned to provide a first membrane for a microphone device and a second membrane for a pressure sensor device. A carrier wafer is bonded to the MEMS wafer. The carrier wafer is etched to expose the first membrane and a first surface of the second membrane to an ambient environment. A MEMS structure is formed in the MEMS wafer. A cap wafer is bonded to a side of the MEMS wafer opposing the carrier wafer to form a first sealed cavity including the MEMS structure and a second sealed cavity including a second surface of the second membrane for the pressure sensor device. The cap wafer comprises an interconnect structure. A through-via electrically connected to the interconnect structure is formed in the cap wafer. | 2014-09-18 |
20140264654 | MICROPHONE PACKAGE WITH INTEGRATED SUBSTRATE - MEMS microphone packages are described that include an ASIC integrated in the base substrate of the package housing. Methods of manufacturing the same and methods for separating individual microphone packages from wafer form assembly arrays are also described. | 2014-09-18 |
20140264655 | SURFACE ROUGHENING TO REDUCE ADHESION IN AN INTEGRATED MEMS DEVICE - In an integrated MEMS device, moving silicon parts with smooth surfaces can stick together if they come into contact. By roughening at least one smooth surface, the effective area of contact, and therefore surface adhesion energy, is reduced and hence the sticking force is reduced. The roughening of a surface can be provided by etching the smooth surfaces in gas, plasma, or liquid with locally non-uniform etch rate. Various etch chemistries and conditions lead to various surface roughness. | 2014-09-18 |
20140264656 | MEMS ACOUSTIC SENSOR WITH INTEGRATED BACK CAVITY - A MEMS device is disclosed. The MEMS device comprises a first plate with a first surface and a second surface; and an anchor attached to a first substrate. The MEMS device further includes a second plate with a third surface and a fourth surface attached to the first plate. A linkage connects the anchor to the first plate, wherein the first plate and second plate are displaced in the presence of an acoustic pressure differential between the first and second surfaces of the first plate. The first plate, second plate, linkage, and anchor are all contained in an enclosure formed by the first substrate and a second substrate, wherein one of the first and second substrates contains a through opening to expose the first surface of the first plate to the environment. | 2014-09-18 |
20140264657 | MONOLITHICALLY INTEGRATED MULTI-SENSOR DEVICE ON A SEMICONDUCTOR SUBSTRATE AND METHOD THEREFOR - An integrated circuit having an indirect sensor and a direct sensor formed on a common semiconductor substrate is disclosed. The direct sensor requires the parameter being measured to be directly applied to the direct sensor. Conversely, the indirect sensor can have the parameter being measured to be indirectly applied to the indirect sensor. The parameter being measured by the direct sensor is different than the parameter being measured by the indirect sensor. In other words, the direct sensor and indirect sensor are of different types. An example of a direct sensor is a pressure sensor. The pressure being measured by the pressure sensor must be applied to the pressure sensor. An example of an indirect sensor is an accelerometer. The rate of change of velocity does not have to be applied directly to the accelerometer. In one embodiment, the direct and indirect sensors are formed using photolithographic techniques. | 2014-09-18 |
20140264658 | CELL PHONE HAVING A MONOLITHICALLY INTEGRATED MULTI-SENSOR DEVICE ON A SEMICONDUCTOR SUBSTRATE AND METHOD THEREFOR - A cell phone is provided having multiple sensors configured to detect and measure different parameters of interest. The cell phone includes at least one monolithic integrated multi-sensor (MIMS) device. The MIMS device comprises at least two sensors of different types formed on a common semiconductor substrate. For example, the MIMS device can comprise an indirect sensor and a direct sensor. The cell phone couples a first parameter to be measured directly to the direct sensor. Conversely, the cell phone can couple a second parameter to be measured to the indirect sensor indirectly. Other sensors can be added to the cell phone by stacking a sensor to the MIMS device or to another substrate coupled to the MIMS device. This supports integrating multiple sensors such as a microphone, an accelerometer, and a temperature sensor to reduce cost, complexity, simplify assembly, while increasing performance. | 2014-09-18 |
20140264659 | TRANSPORTATION DEVICE HAVING A MONOLITHICALLY INTEGRATED MULTI-SENSOR DEVICE ON A SEMICONDUCTOR SUBSTRATE AND METHOD THEREFOR - A transportation device is provided having multiple sensors configured to detect and measure different parameters of interest. The transportation device includes at least one monolithic integrated multi-sensor (MIMS) device. The MIMS device comprises at least two sensors of different types formed on a common semiconductor substrate. For example, the MIMS device can comprise an indirect sensor and a direct sensor. The transportation device couples a first parameter to be measured directly to the direct sensor. Conversely, the transportation device can couple a second parameter to be measured to the indirect sensor indirectly. Other sensors can be added to the transportation device by stacking a sensor to the MIMS device or to another substrate coupled to the MIMS device. This supports integrating multiple sensors such as a microphone, an accelerometer, and a temperature sensor to reduce cost, complexity, simplify assembly, while increasing performance. | 2014-09-18 |
20140264660 | COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ULTRASONIC TRANSDUCERS AND METHODS FOR FORMING THE SAME - Complementary metal oxide semiconductor (CMOS) ultrasonic transducers (CUTs) and methods for forming CUTs are described. The CUTs may include monolithically integrated ultrasonic transducers and integrated circuits for operating in connection with the transducers. The CUTs may be used in ultrasound devices such as ultrasound imaging devices and/or high intensity focused ultrasound (HIFU) devices. | 2014-09-18 |