38th week of 2014 patent applcation highlights part 51 |
Patent application number | Title | Published |
20140264261 | LIGHT EMITTING DEVICE ON METAL FOAM SUBSTRATE - A light emitting device having an electrically conductive metal foam or porous metal substrate, one or more light emitting nanowires in contact with the substrate, and a metal or conductive oxide contact layer in contact with each nanowire junction opposite of the substrate. More specifically, a light emitting device having an electrically conductive metal foam substrate, one or more light emitting nanowires in contact with the substrate, a quantum well on the nanowire(s), a p-type shell on the quantum well, a metal or conductive oxide contact layer in contact with the shell, and an energy down-converting material. Also disclosed is the related method of making a light emitting device. | 2014-09-18 |
20140264262 | Concentric Forster Resonance Energy Transfer Relay for the Parallel Detection of Two Bio/Physicochemical Process - Described herein is a Förster (or fluorescence) resonance energy transfer (FRET) configuration with three energy transfer pathways between three luminescent components, where two of the energy transfer steps occur in sequence as a relay, and the first step of the relay is in competition with a third energy transfer process (energy transfer from the donor to the intermediary is in competition with energy transfer from the donor directly to the terminal acceptor). | 2014-09-18 |
20140264263 | PSEUDOMORPHIC ELECTRONIC AND OPTOELECTRONIC DEVICES HAVING PLANAR CONTACTS - In various embodiments, light-emitting devices incorporate smooth contact layers and polarization doping (i.e., underlying layers substantially free of dopant impurities) and exhibit high photon extraction efficiencies. | 2014-09-18 |
20140264264 | LIGHT EMITTING DIODE - A light emitting diode (LED) and a method for manufacturing the same is disclosed. The disclosed LED comprises a first substrate, an epitaxy layer, and a plurality of bumps. The first substrate is doped with YAG: Ce and is for converting a first light with a first range of wavelength to a second light with a second range of wavelength. The epitaxy layer is disposed on the first substrate and is for emitting the first light. The plurality of bumps are disposed on the epitaxy layer. With the first substrate doped with YAG: Ce, the disclosed LED does not need additional phosphor to convert the first light with the first range of wavelength to the second light with the second range of wavelength. | 2014-09-18 |
20140264265 | SEMICONDUCTOR STRUCTURES HAVING ACTIVE REGIONS COMPRISING INGAN, METHODS OF FORMING SUCH SEMICONDUCTOR STRUCTURES, AND LIGHT EMITTING DEVICES FORMED FROM SUCH SEMICONDUCTOR STRUCTURES - Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising In | 2014-09-18 |
20140264266 | PACKAGING STRUCTURE OF LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - The present disclosure relates to a light emitting diode packaging structure and the method of manufacturing the same. The light emitting diode packaging structure comprises: an insulating substrate with through holes formed on each side of the upper surface thereof, the through hole being filling with conductive metal; a n-type layer formed on the insulating substrate with a hole, which is filled with conductive metal; an active layer provided on the n-type layer; a p-type layer formed on the active layer; an insulating layer configured on one side of the n-type layer, the active layer and the p-type layer and to cover part of the upper surface of the p-type layer; a p-type electrode configured to cover the insulating layer and part of the upper surface of the p-type layer; a n-type electrode provided on a side of the upper surface of the n-type layer and configured to connect with the conductive metal in the through hole in the insulating substrate; a first back electrode provided at one side of back surface of the insulating substrate, the first back electrode connecting with the p-type electrode through the conductive metal in the through hole in the insulating substrate; a second back electrode provided at the other side of back surface of the insulating substrate, the second back electrode connecting with the n-type electrode through the conductive metal in the through hole in the insulating substrate; an optical element packaged on the base substrate, thereby finishing a device. | 2014-09-18 |
20140264267 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A high luminance semiconductor light emitting device including a metallic reflecting layer formed using a non-transparent semiconductor substrate is provided. The device includes a GaAs substrate; a metal layer disposed on the GaAs substrate; and a light emitting diode structure. The light emitting diode structure includes a patterned metal contact layer and a patterned insulating layer disposed on the metal layer, a p type cladding layer disposed on the patterned metal contact layer and the patterned insulating layer, a multi-quantum well layer disposed on the p type cladding layer, an n type cladding layer disposed on the multi-quantum well layer, and a window layer disposed on the n type cladding layer. The GaAs substrate and the light emitting diode structure are bonded by using the metal layer. | 2014-09-18 |
20140264268 | METHOD AND APPARATUS FOR FABRICATING PHOSPHOR-COATED LED DIES - The present disclosure involves lighting apparatus. The lighting apparatus includes a first doped semiconductor layer. A light-emitting layer is disposed over the first doped semiconductor layer. A second doped semiconductor layer is disposed over the light-emitting layer. The second doped semiconductor layer has a different type of conductivity than the first doped semiconductor layer. A photo-conversion layer is disposed over the second doped semiconductor layer and over side surfaces of the first and second doped semiconductor layers and the light-emitting layer. The photo-conversion layer has an angular profile. | 2014-09-18 |
20140264269 | TUNABLE LIGHT EMITTING DIODE USING GRAPHENE CONJUGATED METAL OXIDE SEMICONDUCTOR-GRAPHENE CORE-SHELL QUANTUM DOTS AND ITS FABRICATION PROCESS THEREOF - Disclosed is a method of preparing metal oxide semiconductor-graphene core-shell quantum dots by chemically linking graphenes with superior electrical properties to a metal oxide semiconductor, and a method of fabricating a light emitting diode by using the same. The light emitting diode according to the present invention has the advantages that it shows excellent power conversion efficiency, the cost for materials and equipments required for its fabrication can be reduced, its fabricating process is simple, and it is possible to mass-produce and enlarge the size of display based on a quantum dot light emitting diode. Further, the present invention relates to core-shell quantum dots that can be used in fabricating a light emitting diode with a different wavelength by using various multi-component metal oxide semiconductors and a fabricating method thereof. | 2014-09-18 |
20140264270 | BROADBAND IMAGE SENSOR AND MANUFACTURING THEREOF - This invention relates to multiband detector and multiband image sensing devices, and their manufacturing technologies. The innovative detector (or image sensing) provides significant broadband capability covering the wavelengths from within ultra-violet (UV) to long-Infrared, and it is achieved in a single element. More particularly, this invention is related to the multiband or dual band detectors, which can not only detect the broad spectrum wavelengths ranges from within as low as UV to the wavelengths as high as 25 μm, but also band selection capability. This invention is also related to the multiband detector arrays or image sensing device for multicolor imaging, sensing, and advanced communication. | 2014-09-18 |
20140264271 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device includes a memory layer, made of a silicon-based ferroelectric memory material. The silicon-based ferroelectric memory material includes a mesoporous silica film with nanopores and atomic polar structures on inner walls of the nanopores. The atomic polar structures are formed by asymmetrically bonding metal ions to silicon-oxygen atoms on the inner walls, and the silicon-based ferroelectric memory material includes semiconductor quantum dots, metal quantum dots and metal-semiconductor alloy quantum dots. | 2014-09-18 |
20140264272 | Semiconductor Diodes Fabricated by Aspect Ratio Trapping with Coalesced Films - A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials. | 2014-09-18 |
20140264273 | SUPERLATTICE CRENELATED GATE FIELD EFFECT TRANSISTOR - The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches. | 2014-09-18 |
20140264274 | SEMICONDUCTOR DEVICE - To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap. | 2014-09-18 |
20140264275 | PHOTODETECTORS BASED ON DOUBLE LAYER HETEROSTRUCTURES - A photodetector is provided with a thin film double layer heterostructure. The photodetector is comprised of: a substrate; a channel layer of a transistor deposited onto a top surface of the substrate; a source layer of the transistor deposited on the top surface of the substrate; a drain layer of the transistor deposited on the top surface of the substrate, the source layer and the drain layer disposed on opposing sides of the channel layer; a barrier layer deposited onto the channel layer; and a light absorbing layer deposited on the barrier layer. The light absorbing layer is configured to absorb light and, in response to light incident on the light absorbing layer, electrical conductance of the channel layer is changed through hot carrier tunneling from the light absorbing layer to the channel layer. | 2014-09-18 |
20140264276 | NON-REPLACEMENT GATE NANOMESH FIELD EFFECT TRANSISTOR WITH PAD REGIONS - A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region. | 2014-09-18 |
20140264277 | Intra-Band Tunnel FET - The present disclosure relates to an intra-band tunnel FET, which has a symmetric FET that is able to provide for a high drive current. In some embodiments, the disclosed intra-band tunnel FET has a source region having a first doping type and a drain region having the first doping type. The source region and the drain region are separated by a channel region. A gate region may generate an electric field that varies the position of a valence band and/or a conduction band in the channel region. By controlling the position of the valence band and/or the conduction band of the channel region, quantum mechanical tunneling of charge carries between the conduction band in the source region and in the drain region or between the valence band in the source region and in the drain region can be controlled. | 2014-09-18 |
20140264278 | Strained InGaAs Quantum Wells for Complementary Transistors - An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials. | 2014-09-18 |
20140264279 | FACETED SEMICONDUCTOR NANOWIRE - Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical. A gate electrode can be formed over the semiconductor nanowire such that the faceted surfaces can be employed as channel surfaces. The epitaxially deposited portions of the faceted semiconductor nanowire can apply stress to the channels. Further, an additional semiconductor material may be added to form an outer shell of the faceted semiconductor nanowire prior to forming a gate electrode thereupon. The faceted surfaces of the semiconductor nanowire provide well-defined charge carrier transport properties, which can be advantageously employed to provide a semiconductor device with well-controlled device characteristics. | 2014-09-18 |
20140264280 | NANOWIRE TRANSISTOR WITH UNDERLAYER ETCH STOPS - A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented. | 2014-09-18 |
20140264281 | Channel-Last Methods for Making FETS - Semiconductor devices and methods of making thereof are disclosed. A field effect transistor (FET) is provided comprising a substrate, a first layer disposed above the substrate, the first layer being operable as a gate electrode, a second layer disposed above the first layer, the second layer comprising a dielectric material, a third layer disposed above the second layer, the third layer comprising a semiconductor, and a fourth layer comprising one or more conductive materials and operable as source and drain electrodes disposed above the third layer. In some embodiments, the dielectric material comprises a high-κ dielectric. In some embodiments, the source and drain electrodes comprise one or more metals. The source and drain electrodes are each in ohmic contact with an area of the top surface of the third layer, and substantially all of the current through the transistor flows through the ohmic contacts. | 2014-09-18 |
20140264282 | HETEROGENEOUS LAYERED STRUCTURE, METHOD OF PREPARING THE HETEROGENEOUS LAYERED STRUCTURE, AND ELECTRONIC DEVICE INCLUDING THE HETEROGENEOUS LAYERED STRUCTURE - A method of manufacturing a heterogeneous layered structure includes growing a hexagonal boron nitride sheet directly on a metal substrate in a chamber, increasing a temperature of the chamber to about 300° C. to about 1500° C., and forming a graphene sheet on the hexagonal boron nitride sheet by supplying a carbon source into the chamber while thermally treating the hexagonal boron nitride sheet at the increased temperature. | 2014-09-18 |
20140264283 | FREQUENCY ARRANGEMENT FOR SURFACE CODE ON A SUPERCONDUCTING LATTICE - A device lattice arrangement including a plurality of devices, a plurality of physical connections for the plurality of devices, wherein each of the plurality of devices are coupled to at least two of the plurality of physical connections, a plurality of identity labels associated with individual devices of the plurality of devices and an arrangement of identity labels such that pairs of devices of the plurality of devices connected by some number of the plurality of connections have different identity labels. | 2014-09-18 |
20140264284 | FREQUENCY SEPARATION BETWEEN QUBIT AND CHIP MODE TO REDUCE PURCELL LOSS - A system, method, and chip to control Purcell loss are described. The chip includes qubits formed on a first surface of a substrate. The method includes determining frequencies of the qubits, and controlling a separation between the frequencies of the qubits and chip mode frequencies of the chip. | 2014-09-18 |
20140264285 | MULTIPLE-QUBIT WAVE-ACTIVATED CONTROLLED GATE - A device includes a housing, at least two qubits disposed in the housing and a resonator disposed in the housing and coupled to the at least two qubits, wherein the at least two qubits are maintained at a fixed frequency and are statically coupled to one another via the resonator, wherein energy levels |03> and |12> are closely aligned, wherein a tuned microwave signal applied to the qubit activates a two-qubit phase interaction. | 2014-09-18 |
20140264286 | SUSPENDED SUPERCONDUCTING QUBITS - A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer. | 2014-09-18 |
20140264287 | REMOVAL OF SPURIOUS MICROWAVE MODES VIA FLIP-CHIP CROSSOVER - A coplanar waveguide device includes a coplanar waveguide structure disposed on a substrate, at least one qubit coupled to the coplanar waveguide structure and an add-on chip having a metallized trench, and disposed over the substrate. | 2014-09-18 |
20140264288 | METHOD AND SYSTEM THAT IMPLEMENT A V-GATE QUANTUM CIRCUIT - The current application is directed to methods and quantum circuits that prepare qubits in specified non-stabilizer quantum states that can, in turn, be used for a variety of different purposes, including in a quantum-circuit implementation of an arbitrary single-qubit unitary quantum gate that imparts a specified, arbitrary rotation to the state-vector representation of the state of an input qubit. In certain implementations, the methods and systems consume multiple magic-state qubits in order to carry out probabilistic rotation operators to prepare qubits with state vectors having specified rotation angles with respect to a rotation axis. These qubits are used as resources input to various quantum circuits, including the quantum-circuit implementation of an arbitrary single-qubit unitary quantum gate, including a V gate. | 2014-09-18 |
20140264289 | Structure and Method for Vertical Tunneling Field Effect Transistor with Leveled Source and Drain - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa. | 2014-09-18 |
20140264290 | OLED DISPLAY ARCHITECTURE - A display includes one or more organic light emitting device panels. Each organic light emitting device panel has an array of single-color subpixel areas of different colors extending over an active area thereof arranged in a predetermined pattern by color. At least one of the subpixel areas in the predetermined pattern that would otherwise be designated as a subpixel area through which blue light is emitted based on a position thereof in the predetermined pattern being predetermined to be non-emissive. A volume of the organic light emitting device panel associated with the at least one predetermined non-emissive subpixel area is non-emissive and includes a via or a functional electronic component therein. | 2014-09-18 |
20140264291 | Light Emitting Device with Spherical Back Mirror - A method is provided for fabricating an organic light emitting device (OLED) with a spherical back mirror. The method forms a spherical curvature in the substrate and deposits a metal film overlying the spherical curvature, forming a spherical back mirror. A transparent isolation layer is formed overlying the spherical back mirror having a planar top surface. A transparent first electrode layer is formed overlying the isolation layer, and a transparent second electrode layer is formed overlying the first electrode layer. A stack is interposed between the first and second electrode layers. The stack is made up of an electron transport layer adjacent the cathode, a light-emitting (electron injection) layer adjacent to the electron transport layer, a hole transport layer adjacent to the light-emitting layer, and a hole injection layer adjacent to the hole transport layer. The order of the stack layering is dependent which electrode is the anode. | 2014-09-18 |
20140264292 | HOST COMPOUNDS FOR PHOSPHORESCENT OLEDS AND DEVICES THEREOF - A compound according to a formula I, devices incorporating the same, and formulations including the same are described. The compound according to the formula I can have the structure | 2014-09-18 |
20140264293 | COATED ARTICLE AND/OR DEVICE WITH OPTICAL OUT-COUPLING LAYER STACK (OCLS) INCLUDING VACUUM DEPOSITED INDEX MATCH LAYER OVER SCATTERING MATRIX, AND/OR ASSOCIATED METHODS - Certain example embodiments relate to light emitting diode (e.g., OLED and/or PLED) inclusive devices, and/or methods of making the same. Certain example embodiments incorporate an optical out-coupling layer stack (OCLS) structure that includes a vacuum deposited index matching layer (imL) provided over an organo-metallic scattering matrix layer. The imL may be a silicon-inclusive layer and may include, for example, vacuum deposited SiOxNy. The OCLS including scattering micro-particles, the imL, and the anode may be designed such that the device extraction efficiency is significantly improved, e.g., by efficiently coupling the light generated in the organic layers of the devices and extracted through the glass substrate. In certain example embodiments, the refractive index of the ITO, SiOxNy index matching layer, OCLS scattering layer and the glass substrate may be provided in decreasing order. | 2014-09-18 |
20140264294 | Three-dimensional Printing Surface Treatments - Systems and methods for applying a surface treatment to a product may implement operations including, but not limited to: depositing at least one first conductive element on at least one surface of the product; depositing at least one of one or more microcapsules or one or more organic light-emitting diodes (OLEDs) to at least partially electrically couple with the at least one first conductive element; and depositing at least one second conductive element to at least partially electrically couple with the at least one of one or more microcapsules or one or more OLEDs. | 2014-09-18 |
20140264295 | ORGANIC LIGHT EMITTING DIODE DISPLAY - An OLED display having a first pixel, a second pixel, and a third pixel which neighbor each other, includes: a plurality of first electrodes provided respectively corresponding to the first pixel, the second pixel, and the third pixel and being separated from each other; a hole injection layer provided on the plurality of first electrodes; a main emission layer including a first emission layer disposed on the hole injection layer corresponding to the first pixel, a second emission layer disposed on the hole injection layer corresponding to the second pixel, and a third emission layer disposed on the hole injection layer corresponding to the third pixel; a p-type hole transport layer disposed between the second emission layer and the hole injection layer and p-type doped; and a second electrode disposed on the main emission layer. | 2014-09-18 |
20140264296 | BARRIER FILM PERFORMANCE WITH N2O DILUTION PROCESS FOR THIN FILM ENCAPSULATION - A method and apparatus for depositing an inorganic layer onto a substrate is described. The inorganic layer may be part of an encapsulating film utilized in various display applications. The encapsulating film includes one or more inorganic layers as barrier layers to improve water-barrier performance. An oxygen containing gas, such as nitrous oxide, is introduced during the deposition of the inorganic layer. As a result, the inorganic layer is lower in stress and may obtain a water vapor transmission rate (WVTR) of less than 100 mg/m | 2014-09-18 |
20140264297 | THIN FILM ENCAPSULATION-THIN ULTRA HIGH BARRIER LAYER FOR OLED APPLICATION - A method and apparatus for depositing a multilayer barrier structure is disclosed herein. In one embodiment, a thin barrier layer formed over an organic semiconductor includes a non-conformal organic layer, an inorganic layer formed over the non-conformal organic layer, a metallic layer formed over the inorganic layer and a second organic layer formed over the metallic layer. In another embodiment, a method of depositing a barrier layer includes forming an organic semiconductor device over the exposed surface of a substrate, depositing an inorganic layer using CVD, depositing a metallic layer comprising one or more metal oxide or metal nitride layers over the inorganic layer by ALD, each of the metal oxide or metal nitride layers comprising a metal, wherein the metal is selected from the group consisting of aluminum, hafnium, titanium, zirconium, silicon or combinations thereof and depositing an organic layer over the metallic layer. | 2014-09-18 |
20140264298 | IMAGE SENSOR AND METHOD OF FORMING THE SAME - An image sensor is provided. The image sensor includes an interlayered dielectric structure having a first recess region, in which an organic photoelectric layer is provided, and a second recess region, in which a color filter is provided. The second recess region may be provided under the first recess region. | 2014-09-18 |
20140264299 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND MANUFACTURING METHOD THEREOF - A method of manufacturing an organic light emitting diode (OLED) display includes forming a thin film transistor on a substrate; forming a first electrode electrically connected with the thin film transistor; forming a hole auxiliary layer on the first electrode; depositing an organic material on the hole auxiliary layer using a mask having an opening corresponding to the first electrode; forming an organic emission layer by partially eliminating the organic material through dry-etching, the dry-etching being performed to eliminate the organic material deposited outside of a boundary of the first electrode; forming an electron auxiliary layer on the organic emission layer; and forming a second electrode on the electron auxiliary layer. | 2014-09-18 |
20140264300 | ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE AND METHOD OF MANUFACTURING ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE - The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer. | 2014-09-18 |
20140264301 | ORGANIC ELECTROLUMINESCENT ELEMENT, AND LIGHT EMITTING DEVICE, DISPLAY DEVICE AND LIGHTING DEVICE EACH USING ORGANIC ELECTROLUMINESCENT ELEMENT - An organic electroluminescent element including a substrate, a pair of electrodes including an anode and a cathode, disposed on the substrate, and at least one organic layer including a light emitting layer, disposed between the electrodes, in which at least one kind of compound represented by the following general formula (I) is contained in any layer of the at least one organic layer. The organic electroluminescent element has good luminous efficiency, driving voltage, and driving durability, and has low dependence of such performance on a deposition rate: | 2014-09-18 |
20140264302 | ADHESIVE AND METHOD OF ENCAPSULATING ORGANIC ELECTRONIC DEVICE USING THE SAME - An adhesive, and an encapsulated product and method of encapsulating an organic electronic device (OED) using the same are provided. The adhesive film serves to encapsulate the OED and includes a curable resin and a moisture absorbent, and the adhesive includes a first region coming in contact with the OED upon encapsulation of the OED and a second region not coming in contact with the OED. Also, the moisture absorbent is present at contents of 0 to 20% and 80 to 100% in the first and second regions, respectively, based on the total weight of the moisture absorbent in the adhesive. | 2014-09-18 |
20140264303 | LUMINESCENT DISPLAY DEVICE - A luminescent display device includes a substrate and first and second thin-film transistors above the substrate. The first thin-film transistor includes a semiconductor layer, a gate insulating film, a gate electrode, a source electrode and a drain. The second thin-film transistor includes a semiconductor layer, a gate insulating film, a gate electrode, and a drain electrode. The device also includes an interlayer insulating film on the gate electrode of the first thin-film transistor and the gate electrode of the second thin-film transistor, a first capacitor electrode on the interlayer insulating film, and a luminescent element such that the first capacitor electrode and the gate electrode of the first thin-film transistor constitute a first capacitor, and the first capacitor electrode is not connected to the source electrode and the drain electrode of the first thin-film transistor. | 2014-09-18 |
20140264304 | Light Emitting Element, Light Emitting Device, and Electronic Device - It is an object of the present invention to provide a light emitting element that realizes a high contrast. It is another object of the present invention to provide a light emitting device that realizes a high contrast by using the light emitting element with an excellent contrast. The light emitting element has a layer containing a light emitting substance interposed between a first electrode and a second electrode, and the layer containing the light emitting substance includes a light emitting layer, a layer containing a first organic compound, and a layer containing a second organic compound. The first electrode has a light-transmitting property, and the layer containing the first organic compound and the layer containing the second organic compound are interposed between the second electrode and the light emitting layer. Furthermore, color of the first organic compound and color of the second organic compound are complementary. | 2014-09-18 |
20140264305 | EL DISPLAY DEVICE - A EL display device has EL display panel including the a display area where a pixel is arranged in matrix, and a wiring pattern formed in a circumferential portion of the display area and supplying voltage to a pixel. The EL display panel includes a flexible substrate having an electrode connected to a source signal line or a gate signal line arranged thereon. The flexible substrate includes an anode reinforcement wiring and a cathode reinforcement wiring which are electrically parallel to the wiring pattern. | 2014-09-18 |
20140264306 | DISPLAY MODULE - An organic display device includes a pixel driving circuit having a thin film transistor connected to a current supply line and a capacitor. A first insulation layer, with a first electrode thereon, covers a source electrode of the transistor. The first electrode is connected to the transistor through a contact hole in the insulation layer. A second insulation layer including an aperture is formed on the first insulation layer and electrode layers. An organic light emitting layer, with a second electrode thereon is formed in the aperture and connected to the first electrode. The second insulation layer includes an inner wall at the aperture, said inner wall having a surface of a convex plane on an edge of the recessed part of the first electrode. The convex plane is located between the organic light emitting layer and the edge of the first electrode, and the second electrode is formed over plurality of pixels. | 2014-09-18 |
20140264307 | PROCESS FOR FORMING AN ELECTROACTIVE LAYER - There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes: providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of −25 to 80° C. and under a vacuum in the range of 10 | 2014-09-18 |
20140264308 | ORGANIC LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DEVICE WITH THE ORGANIC LIGHT-EMITTING ELEMENT - The present invention provides a white organic light-emitting element high in the emission efficiency. In particular, the invention provides a white organic light-emitting element that has an emission spectrum having peaks in the respective wavelength regions of red color, green color and blue color and is high in the emission efficiency. It is preferable to use an electron transport material between a first emission region and a second emission region and more preferable to use a hole block material. | 2014-09-18 |
20140264309 | DISPLAY PANEL AND SYSTEM FOR DISPLAYING IMAGES UTILIZING THE SAME - An embodiment of the invention provides a display panel, which includes a substrate having a pixel region and a peripheral region, a conducting layer overlying the substrate in the peripheral region, a first insulating layer overlying the conducting layer in the peripheral region, wherein a ratio between an area of the first insulating layer and an area of the conducting layer in the peripheral region is between about 0.27 and 0.99, a lower electrode layer overlying the first insulating layer, a second insulating layer overlying the lower electrode layer, and an upper electrode layer overlying the second insulating layer. | 2014-09-18 |
20140264310 | LIGHTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - The lighting device includes a first resin layer having a first refractive index and a second resin layer having a second refractive index lower than the first refractive index and higher than the refractive index of the air, which are over a light-emitting element layer, a plurality of granules provided at the interface between the first resin layer and the second resin layer and each having the second refractive index or a plurality of projections each having an apex provided inside the first resin layer and a flat surface in contact with the interface between the first resin layer and the second resin layer and having the second refractive index, an uneven structure provided at the interface with the air, and a resin substrate having the second refractive index. | 2014-09-18 |
20140264311 | LIGHT-EMITTING COMPONENT AND METHOD FOR PRODUCING A LIGHT-EMITTING COMPONENT - A light-emitting component may include: an electrically active region, including a first electrode, a second electrode, an organic functional layer structure between the first electrode and the second electrode, a cover arranged above the electrically active region, and a layer structure arranged between the cover and the electrically active region. The component may have at least one layer having a refractive index which is less than the refractive index of the cover. | 2014-09-18 |
20140264312 | NOVEL ORGANIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE - The present invention relates to a novel stable benzo[h]hexaphene compound and an organic light-emitting device including the compound. The present invention provides a benzo[h]hexaphene shown in Claim | 2014-09-18 |
20140264313 | Organic Electronic Component with Dopant, Use of a Dopant and Method for the Production of the Dopant - An organic electronic component includes an organic functional layer having a p-dopant. The p-dopant includes a copper complex having at least one ligand containing an aryloxy group and an iminium group. Additionally specified are the use of a copper complex as a p-dopant and a process for producing a p-dopant. | 2014-09-18 |
20140264314 | METHOD FOR MANUFACTURING ORGANIC SEMICONDUCTOR ELEMENT, SEMICONDUCTOR ELEMENT, AND ELECTRONIC APPARATUS - An organic single crystal thin film includes an organic single crystal formed on a substrate across a boundary between a first region of the substrate and a second region of the substrate that is adjacent to the first region. The first region has a different shape or size than the second region. | 2014-09-18 |
20140264315 | ORGANIC ELECTROLUMINESCENCE DISPLAY PANEL AND ORGANIC ELECTROLUMINESCENCE DISPLAY APPARATUS - An organic electroluminescence (EL) display panel includes a cathode electrode formed above a bank and formed opposite to a plurality of anode electrodes, and a charge functional layer commonly formed for each of the organic light-emitting layers across a plurality of aperture areas formed in the bank. An end portion of the cathode electrode and an end portion of the charge functional layer are provided above the bank located adjacent to a boundary between a display region and a peripheral region of a display region. | 2014-09-18 |
20140264316 | Organic Light-Emitting Device - An organic light-emitting device includes a substrate, on which a transparent electrode and a further electrode are applied. An organic light-emitting layer is arranged between the electrodes. At least one optical scattering layer is arranged on a side of the transparent electrode facing away from the organic light-emitting layer. | 2014-09-18 |
20140264317 | ORGANIC ELECTROLUMINESCENCE ELEMENT AND PLANAR LIGHT-EMITTING BODY - Provided is an organic EL element having both excellent light extraction efficiency and excellent weather resistance. The organic EL element ( | 2014-09-18 |
20140264318 | NOVEL ORGANIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME - The present invention provides a novel stable benzo[a]naphtho[2,1-c]tetracene compound and an organic light-emitting device including the compound. | 2014-09-18 |
20140264319 | LOW TEMPERATURE, THIN FILM CRYSTALLIZATION METHOD AND PRODUCTS PREPARED THEREFROM - An organic material with a porous interpenetrating network and an amount of inorganic material at least partially distributed within the porosity of the organic material is disclosed. A method of producing the organic-inorganic thin films and devices therefrom comprises seeding with nanoparticles and depositing an amorphous material on the nanoparticles. | 2014-09-18 |
20140264320 | Compositional Graded IGZO Thin Film Transistor - A gradient in the composition of at least one of the elements of a metal-based semiconductor layer is introduced as a function of depth through the layer. The gradient(s) influence the current density response of the device at different gate voltages. In some embodiments, the composition of an element (e.g. Ga) is greater at the interface between the metal-based semiconductor layer and the source/drain layers. The shape of the gradient profile is one of linear, stepped, parabolic, exponential, and the like. | 2014-09-18 |
20140264321 | Method of Fabricating IGZO by Sputtering in Oxidizing Gas - In some embodiments, oxidants such as ozone (O | 2014-09-18 |
20140264322 | CHEMICAL SENSOR WITH PROTRUDED SENSOR SURFACE - In one implementation, a chemical sensor is described. The chemical sensor includes a chemically-sensitive field effect transistor including a floating gate conductor having an upper surface. A conductive element protrudes from the upper surface of the floating gate conductor into an opening. A dielectric material defines a reaction region. The reaction region overlies and extends below an upper surface of the conductive element. | 2014-09-18 |
20140264323 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - When an oxide semiconductor film is microfabricated, with the use of a hard mask, unevenness of a side surface of the oxide semiconductor film can be suppressed. Specifically, a semiconductor device comprises an oxide semiconductor film over an insulating surface; a first hard mask and a second hard mask over the oxide semiconductor film; a source electrode over the oxide semiconductor film and the first hard mask; a drain electrode over the oxide semiconductor film and the second hard mask; a gate insulating film over the source electrode and the drain electrode; and a gate electrode overlapping with the gate insulating film and the oxide semiconductor film, and the first and second hard masks have conductivity. | 2014-09-18 |
20140264324 | SEMICONDUCTOR DEVICE - The semiconductor device includes an oxide semiconductor layer including a plurality of channel formation regions arranged in the channel width direction and parallel to each other and a gate electrode layer covering a side surface and a top surface of each channel formation region with a gate insulating layer placed between the gate electrode layer and the channel formation regions. With this structure, an electric field is applied to each channel formation region from the side surface direction and the top surface direction. This makes it possible to favorably control the threshold voltage of the transistor and improve the S value thereof. Moreover, with the plurality of channel formation regions, the transistor can have increased effective channel width; thus, a decrease in on-state current can be prevented. | 2014-09-18 |
20140264325 | Double Sided Sl(GE)/Sapphire/lll-Nitride Hybrid Structure - One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer. | 2014-09-18 |
20140264326 | FIELD EFFECT TRANSISTOR - A FET disclosed herein comprises a substrate, a first semiconductor layer disposed over the substrate, a second semiconductor layer disposed over the first semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer has a two-dimensional electron gas. The E-mode FET further comprises a p+ III-V semiconductor layer disposed over the second semiconductor layer and a depolarization layer disposed between the second semiconductor layer and the p+ III-V semiconductor layer. | 2014-09-18 |
20140264327 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon. | 2014-09-18 |
20140264328 | SEMICONDUCTOR ELEMENT - Provided is a semiconductor element including a p-type semiconductor layer that is used in combination with an n-type ZnO-based semiconductor layer, and that can be formed, even at relatively low temperature, to have a small thickness, high crystallinity, and surface smoothness. The semiconductor element is expected to achieve high performance when used for a large-screen display. Specifically, the semiconductor element includes: a glass substrate; a lower electrode; a ZnO active layer (n-type semiconductor layer) having a thickness of 2 um to 4 um; a p-type ZnNiO layer (first p-type semiconductor layer) made of a p-type semiconductor material of Zn | 2014-09-18 |
20140264329 | DISPLAY DEVICE - A protective circuit includes a non-linear element, which includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a second oxide semiconductor layer and a conductive layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved. | 2014-09-18 |
20140264330 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE - The present invention provides a thin film transistor array substrate and a liquid crystal display device including the thin film transistor array substrate that are preferably applicable to a liquid crystal display device including the three-layered electrode structure that enables high response speed and high transmittance, and can have a high aperture ratio. The thin film transistor array substrate of the present invention includes: a thin film transistor element, gate bus lines, and source bus lines, in which the thin film transistor array substrate includes electrodes, the electrodes include a first electrode and a second electrode, the first electrode includes a linear portion along the source bus lines, the first electrode includes a linear portion along the gate bus lines, at least one linear portion along the source bus lines is disposed transversely to the linear portion along the gate bus lines in a plan view of main face of the substrate and is connected to a drain electrode of the thin film transistor element at a position overlapping the gate bus lines, and the second electrode is a planar electrode. | 2014-09-18 |
20140264331 | DAISY CHAIN CONNECTION FOR TESTING CONTINUITY IN A SEMICONDUCTOR DIE - An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch. | 2014-09-18 |
20140264332 | SEMICONDUCTOR CHIP WITH POWER GATING THROUGH SILICON VIAS - A semiconductor chip includes a substrate having a frontside and a backside coupled to a ground. The chip includes a circuit in the substrate at the frontside. A through silicon via (TSV) having a front-end, a back-end, and a lateral surface is included. The back-end and lateral surface of the TSV are in the substrate, and the front-end of the TSV is substantially parallel to the frontside of the substrate. The chip also includes an antifuse material deposited between the back-end and lateral surface of the TSV and the substrate. The antifuse material insulates the TSV from the substrate. The chip includes a ground layer insulated from the substrate and coupled with the TSV and the circuit. The ground layer conducts a program voltage to the TSV to cause a portion of the antifuse material to migrate away from the TSV, thereby connecting the circuit to the ground. | 2014-09-18 |
20140264333 | METHOD AND APPARATUS FOR MONITORING SEMICONDUCTOR FABRICATION - A semiconductor chip for process monitoring of semiconductor fabrication, has a plurality of arrays with a plurality of diodes, each diode being formed in the chip, each diode being associated with a stack with at least one horizontal interconnect, the stack and the diode connected in series to form a diode stack combination, wherein the horizontal interconnect has a salicided polysilicon interconnect comprising complementary doped polysilicon sections to form a reverse biased diode. | 2014-09-18 |
20140264334 | LAYOUT FOR RETICLE AND WAFER SCANNING ELECTRON MICROSCOPE REGISTRATION OR OVERLAY MEASUREMENTS - A method and a resulting device are provided for forming stack overlay and registration monitoring structures for FEOL layers including implant layers and for forming BEOL SEM overlay and registration monitoring structures including BEOL interconnections, respectively. Embodiments include forming an active monitoring structure having first and second edges separated by a first distance in an active layer on a semiconductor substrate; forming a poly monitoring structure having first and second edges separated by a second distance in a poly layer; and forming one or more contact monitoring structures in a contact layer, collectively exposing at least the first and second edges of each of the active and poly monitoring structures; wherein the active, poly, and contact monitoring structures are formed in an area which includes no IC patterns in the active, the poly, and the contact layers, respectively. | 2014-09-18 |
20140264335 | PACKAGE SUBSTRATE AND METHOD FOR TESTING THE SAME - A package substrate is provided, including a board body having a wiring region and a testing region defined thereon, conductive pads embedded in the wiring region, and a plurality of testing pads disposed in the testing region and electrically connected to the conductive pads, wherein the top surface area of each of the testing pads is greater than the top surface area of each of the conductive pads in order to facilitate a precise alignment of a probe with a corresponding one of the testing pads and prevent the probe from being blocked by the board body when in electrically testing an embedded circuit. | 2014-09-18 |
20140264336 | PATTERN FOR ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICE MANUFACTURING AND PROCESS MONITORING - A pattern for use in the manufacture of semiconductor devices is provided which, according to an example embodiment, may comprise at least one second field region comprising a main array of dies, each having a height of Y | 2014-09-18 |
20140264337 | PACKAGING MECHANISMS FOR DIES WITH DIFFERENT SIZES OF CONNECTORS - Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost. | 2014-09-18 |
20140264338 | LINE STRUCTURE FOR REPAIR AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME - A line structure for repair may include a first line in a first direction, a second line parallel with the first line, the second line having side portions extending along a second direction from respective end portions and coupled to the first line, and a third line intersecting the first and second lines, wherein at least one portion of the second line is made of undoped poly-silicon. | 2014-09-18 |
20140264339 | HEAT SLUG HAVING THERMOELECTRIC ELEMENTS AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - In a heat slug and a semiconductor package including the same, the heat slug includes a thermal conductive body having an active face and a dissipating face opposite to the active face, a dielectric layer covering the active face of the body, at least one thermoelectric element arranged on the dielectric layer and a conductive pattern arranged on the dielectric layer and electrically connected to the thermoelectric element. The electrical characteristics of the thermoelectric element are interacted with heat generated from a heat source. | 2014-09-18 |
20140264340 | REVERSIBLE HYBRIDIZATION OF LARGE SURFACE AREA ARRAY ELECTRONICS - Various technologies pertaining to characterizing a component of a large surface area array electronic device, such as a focal plane array (FPA), are described. A first semiconductor chip is reversibly hybridized with a second semiconductor chip through use of a conductive layer. Responsive to being reversibly hybridized, at least one of the first semiconductor chip or the second semiconductor chip is characterized as being defective or suitable for deployment. Thereafter, the conductive layer is removed, and the first semiconductor chip is separated from the second semiconductor chip without damaging either of the first semiconductor chip or the second semiconductor chip. | 2014-09-18 |
20140264341 | BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE - Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer. | 2014-09-18 |
20140264342 | SEMICONDUCTOR DEVICE INCLUDING A RESISTOR AND METHOD FOR THE FORMATION THEREOF - A semiconductor structure includes a substrate and a resistor provided over the substrate. The resistor includes a first material layer, a second material layer, a first contact structure and a second contact structure. The first material layer includes at least one of a metal and a metal compound. The second material layer includes a semiconductor material. The second material layer is provided over the first material layer and includes a first sub-layer and a second sub-layer. The second sub-layer is provided over the first sub-layer. The first sub-layer and the second sub-layer are differently doped. Each of the first contact structure and the second contact structure provides an electrical connection to the second sub-layer of the second material layer. | 2014-09-18 |
20140264343 | DEVICE ARCHITECTURE AND METHOD FOR TEMPERATURE COMPENSATION OF VERTICAL FIELD EFFECT DEVICES - A field effect device is disclosed that provides a reduced variation in on-resistance as a function of junction temperature. The field effect device, having a source junction, gate junction and drain junction, includes a resistive thin film adjacent the drain junction wherein the resistive thin film comprises a material having a negative temperature coefficient of resistance. The material is selected from one or more materials from the group consisting of doped polysilicon, amorphous silicon, silicon-chromium and silicon-nickel, where the material properties, such as thickness and doping level, are chosen to create a desired resistance and temperature profile for the field effect device. Temperature variation of on-resistance for the disclosed field effect device is reduced from the temperature variation for a similar field effect device without the resistive thin film. | 2014-09-18 |
20140264344 | Wafers, Panels, Semiconductor Devices, and Glass Treatment Methods - Glass treatment methods, wafer, panels, and semiconductor devices are disclosed. In some embodiments, a method of treating a glass substrate includes forming a first film on the glass substrate, the first film having a first porosity. The method includes forming a second film on the first film, the second film comprising an electrically insulating material and having a second porosity. The first porosity is lower than the second porosity. | 2014-09-18 |
20140264345 | WAFER WARPAGE REDUCTION - The present disclosure relates a method to mitigate wafer warpage in advanced technology manufacturing processes due to crystallization of one or more amorphous layers with asymmetrical front-surface and back-surface layer thicknesses. After deposition of one or more layers of amorphous material on a front-surface and a back-surface of the wafer in a furnace tool, the front-surface layers are patterned which thins a front layer thickness. Downstream thermal processing performed at a temperature which exceeds a crystallization threshold of the amorphous material will result in asymmetric stress between the front and back surfaces due to the asymmetrical layer thicknesses. To mitigate this effect, the amount of warpage as a function of the difference in asymmetrical layer thickness may be determined such that a front-surface deposition tool may be utilized in conjunction with the furnace tool to reduce the difference in front-surface and back-surface layer thicknesses. Other methods are also disclosed. | 2014-09-18 |
20140264346 | INTEGRATED PHOTODIODE - In accordance with one implementation, a photodiode may be integrated by thin film processing within a slider. In accordance with another implementation, an apparatus can be configured to include a slider, a first layer of a metal disposed within the slider, a layer of amorphous silicon disposed adjacent the first layer of metal, a second layer of metal disposed adjacent the layer of amorphous silicon, and wherein the first layer of metal, the layer of amorphous silicon, and the second layer of metal are operable as a photodiode. | 2014-09-18 |
20140264347 | TRANSISTOR WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES BASED ON AN AMORPHIZATION PROCESS AND A HEAT TREATMENT - When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved. | 2014-09-18 |
20140264348 | Asymmetric Cyclic Desposition Etch Epitaxy - The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed. | 2014-09-18 |
20140264349 | LOW THERMAL BUDGET SCHEMES IN SEMICONDUCTOR DEVICE FABRICATION - In aspects of the present invention, a method of forming a semiconductor device is disclosed, wherein amorphous regions are formed at an early stage during fabrication and the amorphous regions are conserved during subsequent processing sequences, and an intermediate semiconductor device structure with amorphous regions are provided at an early stage during fabrication. Herein a gate structure is provided over a semiconductor substrate and amorphous regions are formed adjacent the gate structure. Source/drain extension regions or source/drain regions are formed in the amorphous regions. In some illustrative embodiments, fluorine may be implanted into the amorphous regions. After the source/drain extension regions and/or the source/drain regions are formed, a rapid thermal anneal process is performed. | 2014-09-18 |
20140264350 | CRYSTALLIZATION METHOD OF THIN FILM TRANSISTOR, THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD FOR THIN FILM TRANSISTOR ARRAY PANEL - Exemplary embodiments of the invention disclose a method of manufacturing a thin film transistor array panel having reduced overall processing time and providing a uniform crystallization. Exemplary embodiments of the invention also disclose a crystallization method of a thin film transistor, including forming on a substrate a semiconductor layer including a first pixel area, a second pixel area, and a third pixel area. The crystallization method includes crystallizing a portion of the semiconductor layer corresponding to a channel region of a thin film transistor using a micro lens array. | 2014-09-18 |
20140264351 | Peeling Method and Method of Manufacturing Semiconductor Device - There is provided a peeling method capable of preventing a damage to a layer to be peeled. Thus, not only a layer to be peeled having a small area but also a layer to be peeled having a large area can be peeled over the entire surface at a high yield. Processing for partially reducing contact property between a first material layer ( | 2014-09-18 |
20140264352 | MASK LAYER AND METHOD OF FORMATION - A semiconductor device includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The second semiconductor layer is formed over the first semiconductor layer and includes a recess in a vertical direction towards the first semiconductor layer. The third semiconductor layer is formed in the recess of the second semiconductor layer and includes a seam or void in the recess. | 2014-09-18 |
20140264353 | 3D MEMORY ARRAY INCLUDING CRYSTALLIZED CHANNELS - A method for manufacturing a memory device includes forming a plurality of active layers alternating with insulating layers on a substrate where the active layers include an active material, etching the active layers and insulating layers to define a plurality of stacks of active strips, and after the etching, causing crystal growth in the active strips. The substrate can have a single crystalline surface with a crystal structure orientation, and the crystal growth in the active material can form crystallized material having the crystal structure orientation of the substrate at least near side surfaces of the active strips. Causing crystal growth includes depositing a seeding layer over the plurality of stacks and the substrate, where the seeding layer is in contact with the side surfaces of the active strips, and in contact with the substrate. The method can include, after causing crystal growth, removing the seeding layer. | 2014-09-18 |
20140264354 | BUFFER LAYERS FOR METAL OXIDE SEMICONDUCTORS FOR TFT - The present invention generally relates to a thin film semiconductor device having a buffer layer formed between the semiconductor layer and one or more layers. In one embodiment, a thin film semiconductor device includes a semiconductor layer having a first work function and a first electron affinity level, a buffer layer having a second work function greater than the first work function and a second electron affinity level that is less than the first electron affinity level; and a gate dielectric layer having a third work function less than the second work function and a third electron affinity level that is greater than the second electron affinity level. | 2014-09-18 |
20140264355 | DISPLAY DEVICE, DISPLAY DEVICE DRIVING METHOD, AND ELECTRONIC APPARATUS - A display device includes a pixel array portion and a driving portion for driving the pixel array portion. The pixel array portion includes row scanning lines, column signal lines, and pixels arranged in a matrix form at intersections of the scanning lines and the signal lines. The driving portion includes a write scanner for supplying a control signal to each of the scanning lines by sequentially scanning the scanning lines in each field and a signal selector for supplying a video signal to each of the signal lines in synchronization with the sequential scanning. Each pixel includes a drive transistor for supplying driving current to the light-emitting element in accordance with the video signal stored in a storage capacitor. | 2014-09-18 |
20140264356 | DIMENSIONALLY-STABLE, DAMAGE-RESISTANT, GLASS SHEETS - Described herein are aluminoborosilicate glass compositions that are substantially alkali-free and exhibit desirable physical and chemical properties for use as substrates in flat panel display devices, such as, active matrix liquid crystal displays (AMLCDs). The glass compositions can be formed into glass sheets by, for example, the float process. When used as substrates, the glass sheets exhibit dimensional stability during processing and damage resistance during cutting. | 2014-09-18 |
20140264357 | DISPLAY PANEL - A display device includes a plurality of pixel units. Each of the pixel units at least includes three sub-pixels for displaying different colors. The three sub-pixels are electrically connected to three different gate lines, and at least two of the three sub-pixels are electrically connected to the same data line. | 2014-09-18 |
20140264358 | STRUCTURE AND METHOD FOR FORMING INTEGRAL NITRIDE LIGHT SENSORS ON SILICON SUBSTRATES - A semiconductor integrated circuit has one or more integral nitride-type sensors. In one embodiment, an integral nitride-type sensor and a coplanar supplemental circuit are formed from a common silicon substrate base. In another embodiment, an integral nitride-type sensor and a supplemental circuit are integrated in a vertical orientation. | 2014-09-18 |
20140264359 | Lightweight self-cooling light sources - A solid-state light source has light emitting diodes embedded in a thermally conductive translucent luminescent element. The thermally conductive translucent luminescent element has optically translucent thermal filler and at least one luminescent element in a matrix material. A leadframe is electrically connected to the light emitting diodes. The leadframe distributes heat from the light emitting diodes to the thermally conductive translucent luminescent element. The thermally conductive translucent luminescent element distributes heat from light emitting diodes and the thermally conductive translucent luminescent element. | 2014-09-18 |
20140264360 | TRANSISTOR WITH CHARGE ENHANCED FIELD PLATE STRUCTURE AND METHOD - Transistors and methods of fabricating are described herein. These transistors include a field plate ( | 2014-09-18 |