37th week of 2010 patent applcation highlights part 30 |
Patent application number | Title | Published |
20100232172 | OPTICAL DEVICE, IN PARTICULAR FOR A MOTOR VEHICLE, SUCH AS A LIGHTING OR SIGNALING DEVICE - An optical device, in particular for a motor vehicle, such as a lighting or signaling device, this device comprising at least one light guide which is designed to guide at least part of the light which is emitted by a source of light, the light guide comprising at least one output surface and at least one main reflection surface, which is designed to reflect towards the output surface light which is propagated in the guide, the light guide comprising a portion for coupling with the source of light, this coupling portion having a transverse axis (Y), wherein the coupling portion is arranged such that the light which is emitted from this coupling portion is propagated in the light guide, around the transverse axis, according to a total angular opening, measured around this transverse axis, which is strictly less than 360°, and in particular is less than 320° or 300°. | 2010-09-16 |
20100232173 | VEHICLE HEADLIGHT - The disclosed subject matter includes a projector headlight using a plurality of optical units for a low beam with a high visible/visual quality. Each of the optical units can include a plurality of LED devices and a projector lens. The projector lens can include a light-emitting surface including a reflex function and a reflex surface including a light incoming surface that is located on the opposite side of the light-emitting surface. The LED devices can be located adjacent the light incoming surface, and the optical units can be located so that angles between optical axes of adjacent optical units can become substantially a same angle. Thus, the projector headlight can form various favorable light distribution patterns by changing curvature factors of the light-emitting surface and the reflex surface of the projector lens in each of the optical units and by changing the angles between the optical axes of the adjacent optical units. | 2010-09-16 |
20100232174 | Front Grill - A vehicle front grill includes a grill main body and lamp housings that are integrally formed. A surface of the grill main body and surfaces of the lamp housings are coated with a single plating film, and light originating from the lamps accommodated in the lamp housings is reflected by the plating films of the lamp housings. | 2010-09-16 |
20100232175 | Freely plastically flexible light-emitting strip structure - A freely plastically flexible light-emitting strip structure, which is a hollow light guide strip body made of transparent material The light guide strip body is formed with at least one axial internal chamber. A plastically flexible strip body is implanted in the internal chamber. Recessed/raised sections are formed on a wall of the internal chamber for changing light path. When a light source projects light into the internal chamber, the recessed/raised sections deflect or reflect the projected light, whereby the light guide strip body can emit light outward. The plastically flexible strip body makes the light guide strip body plastically flexible and self-patternable. Accordingly, the configuration of the light guide strip body is freely adjustable in accordance with the requirements of use sites so as to enlarge application range and provide enhanced decorative or warning effect. | 2010-09-16 |
20100232176 | Illuminator method and device - A first toroidal ray guide defines an axis of revolution and has a toroidal entrance pupil adapted to image light incident on the entrance pupil at an angle to the axis of revolution between 40 and 140 degrees, and it also has a first imaging surface opposite the entrance pupil. A second toroidal ray guide also defines the same axis of revolution and has a second imaging surface adjacent to the first imaging surface. Various additions and further qualities of the ray guides, which form optical channels, are disclosed. In a method light emanating from a source at between 40-140 degrees from an optical axis is received at an entrance pupil of a ray guide arrangement that is circularly symmetric about the optical axis. Then the received light is redirected through the ray guide arrangement to an exit pupil in an average direction substantially parallel to the optical axis. | 2010-09-16 |
20100232177 | LIGHT EMITTING DEVICE PACKAGE AND METHOD OF FABRICATING THE SAME - A light emitting device package and a method of manufacturing the light emitting device package are provided. A base is first provided and a hole is formed on the base. After a light emitting portion is formed on the base, a mold die is placed on the light emitting portion and a molding material is injected through the hole. The mold die is removed to complete the package. | 2010-09-16 |
20100232178 | Light Guide Plate Assembly - Alight guide plate assembly for a backlight module is provided. The light guide plate assembly includes a plurality of light guide plates. Each light guide plate has a top face, at least one side face, and at least one connecting part. The connecting part is formed on the side face of the light guide plate. The connecting part has a connecting face, wherein the adjacent connecting faces are connected to each other. The top faces of the plurality of light guide plates are coplanar. A distance between the connecting face and the top face is ⅓ to 1/20 of the thickness of the light guide plate. | 2010-09-16 |
20100232179 | PRINTED CIRCUIT BOARD AND BACK LIGHT MODULE USING THE SAME - A back light module includes a printed circuit board and a plurality of surface mounting elements mounted on the printed circuit board. Each surface mounting element is an LED lighting element. The printed circuit board has a plurality of pads. Each of the pads includes a first bar and two second bars extending respectively from two ends of the first bar. The surface mounting element includes a plurality of pins. The pins are placed on two sides of the surface mounting element. The pins are soldered on the pads. | 2010-09-16 |
20100232180 | POWER SUPPLY UNIT, HARD DISK DRIVE AND METHOD OF SWITCHING THE POWER SUPPLY UNIT - Zero volt switching during a light load is performed in such a manner that through an ON/OFF control of switches provided for a full bridge circuit and the synchronous rectifier switches in a rectifier and smoothing circuit, a resonant peak voltage necessary for the zero voltage switching determined by the output current flowing to output terminals, a resonant inductor and a resonant capacitor capacitance is ensured so that an energy accumulated in the rectifier and smoothing circuit is returned to the full bridge circuit so as to act as equivalent as when the output current is increased and to increase the current flowing through the full bridge circuit. | 2010-09-16 |
20100232181 | TRANSFORMER AND SWITCHING POWER SUPPLY UNIT - The transformer includes: a magnetic core having two base-plates and four legs; a first conductive member as a first winding, having four through-holes through which the four legs pass, respectively; and one or more second conductive members as a second winding, each having four through-holes through which the four legs pass, respectively. The first and second windings are wound around the four legs. Closed magnetic paths are formed inside the magnetic core from the four legs to the two base-plates due to currents flowing through the first or the second winding. A couple of magnetic fluxes each generated inside each of a couple of legs arranged along one diagonal line are both directed in a first direction, while another couple of magnetic fluxes each generated inside each of another couple of legs arranged along another diagonal line are both directed in a second direction opposite to the first direction. | 2010-09-16 |
20100232182 | DUAL-SWITCHES FLYBACK POWER CONVERTER WITH SELF-EXCITED SUPPLY TO POWER THE HIGH-SIDE DRIVER - An exemplary embodiment of a flyback power converter includes a transformer for power transfer, a high-side transistor, a low-side transistor, two diodes, a control circuit, and a high-side drive circuit. The high-side transistor and the low-side transistor are coupled to switch the transformer. The two diodes are coupled to said transformer to circulate energy of leakage inductance of the transformer to an input power rail of the power converter. The control circuit generates a switching signal coupled to control the high-side transistor and the low-side transistor. The high-side drive circuit is coupled to receive the switching signal for driving the high-side transistor. The transformer has an auxiliary winding generating a floating power to provide power supply for said high-side drive circuit. | 2010-09-16 |
20100232183 | CONTROL CIRCUIT OF RESONANT POWER CONVERTER WITH ASYMMETRICAL PHASE SHIFT TO IMPROVE THE OPERATION - A control circuit of the resonant power converter according to the present invention comprises a frequency modulation circuit modulating a switching frequency of a switching signal in response to a feedback signal in a first operation range. A phase-shift circuit performs a phase-shift modulation to the switching signal in response to the feedback signal in a second operation range. A burst circuit performs a burst modulation to the switching signal in response to the feedback signal in a third operation range. The control circuit is operated in the first operation range when the feedback signal is higher than a first threshold. The control circuit is operated in the second operation range when the feedback signal is lower than the first threshold and higher than a second threshold. The control circuit is operated in the third operation range when the feedback signal is lower than the second threshold. | 2010-09-16 |
20100232184 | DC CONVERTER - A DC converter includes: a transformer (T | 2010-09-16 |
20100232185 | POWER SUPPLY MODULE - A power supply module includes an AC/DC converter, a voltage transforming circuit, a feedback circuit, and a detecting circuit. The AC/DC converter is used for converting the input AC voltage to a primary DC voltage. The voltage transforming circuit is used for transforming the primary DC voltage to the first DC voltage. The feedback circuit is used for sampling the first DC voltage to generate a feedback signal. The detecting circuit is used for detecting if the power supply module is powered on, and generating a first voltage when detecting that the power supply module is powered on. Wherein the voltage transforming circuit maintains the first DC voltage at a first predetermined value according to the feedback signal, the feedback circuit increases a magnitude of the feedback signal according to the first voltage. | 2010-09-16 |
20100232186 | SWITCHING POWER SUPPLY DEVICE - A switching power supply device includes a transformer, a switching unit which is connected with a primary winding of the transformer and configured to switch a current flowing to the primary winding, a start unit configured to start the switching unit, a voltage drop unit configured to lower output voltage from a secondary winding of the transform, and a current control unit configured to control an amount of a current flowing in the start unit when the switching unit is in an off state by lowering output voltage by the voltage drop unit. | 2010-09-16 |
20100232187 | OUTPUT VOLTAGE CONTROL CIRCUIT OF POWER CONVERTER FOR LIGHT-LOAD POWER SAVING - A control circuit of a power converter for light-load power saving according to the present invention comprises a first feedback circuit coupled to an output voltage of the power converter to receive a first feedback signal. A second feedback circuit is coupled to the output voltage to receive a second feedback signal. A control circuit generates a switching signal for switching a transformer of the power converter and regulating the output voltage of the power converter in response to the first feedback signal and the second feedback signal. The switching signal is generated in accordance with the first feedback signal when an output load is high. The switching signal is generated in accordance with the second feedback signal during a light-load condition. | 2010-09-16 |
20100232188 | POWER SUPPLY APPARATUS - In a power supply apparatus, a current limitation unit configured to detect a current flowing through a primary winding of a transformer to limit a current to a switching unit has a self-holding unit configured to self-hold a state where the current to the switching unit is limited. | 2010-09-16 |
20100232189 | METHOD FOR PORTIONING OUTPUT CURRENT OF A DC-DC CONVERTER - At least some aspects of the invention are directed to methods and apparatus for controlling an uninterruptible power supply and subsystems of a UPS. A first aspect of the invention is directed to a method of controlling a DC-DC converter having a predetermined maximum peak load current value. The DC-DC converter has first and second outputs to couple to a load with a capacitor coupled across the first and second outputs. The method includes in a first mode of operation, charging the capacitor to a predetermined output voltage value, and in a second mode of operation, providing output current having the maximum peak load current value to a load coupled to the output of the DC-DC converter, wherein a first portion of the output current is provided by the DC-DC converter and a second portion of the output current is provided by discharging the capacitor to a voltage value that is less than the predetermined output voltage value. | 2010-09-16 |
20100232190 | CONVERSION OF AC LINES TO HVDC LINES - An electric power transmission system includes at each end of a high voltage direct current transmission line including three conductors, a converter station for conversion of an alternating voltage into a direct voltage for transmitting direct current between the stations in all three conductors. Each station has a voltage source converter and an extra phase leg connected between the two pole conductors of the direct voltage side of the converter. A third of the conductors is connected to a midpoint between current valves of the extra phase leg. An arrangement is adapted to control the current valves of the extra phase leg to switch for connecting the third conductor either to the first pole conductor or the second pole conductor for utilizing the third conductor for conducting current between the stations. | 2010-09-16 |
20100232191 | POWER CONDITIONER AND SOLAR PHOTOVOLTAIC POWER GENERATION SYSTEM - A first circuit generates a first sequence of square wave voltages having a voltage level that changes to a positive side relative to a first reference potential, which is a potential on a negative-electrode side of a direct current power source, from a direct current voltage. A second circuit generates a second sequence of square wave voltages having a voltage level lower than the voltage level of the first sequence of square wave voltages on the positive side that changes to a negative side relative to a second reference potential. The second chopper circuit further generates a third sequence of square wave voltages having a voltage level that changes to the positive and negative side in turns in the manner of sinusoidal wave relative to the first reference potential by summing the first sequence of square wave voltages and the second sequence of square wave voltages. A third circuit outputs the third sequence of square wave voltages as a charge/discharge output. The third circuit further PWM-controls the charge/discharge output so that a difference of the third sequence of square wave voltages to a sinusoidal wave voltage is corrected and thereby generates a sinusoidal wave voltage that continuously changes to the positive and negative sides relative to the first reference potential from the third sequence of square wave voltages and the PWM-controlled output, and outputs the generated sinusoidal wave voltage to a load. | 2010-09-16 |
20100232192 | POWER CONVERSION APPARATUS, POWER CONDITIONER, AND POWER GENERATION SYSTEM - A first chopper circuit generates a first sequence of square wave voltages having a voltage level that changes to a positive side by chopping a direct current voltage at a system frequency. A second chopper circuit generates a second sequence of square wave voltages having a voltage level that changes to a negative side by chopping a direct current voltage at a frequency twice as high as the system frequency. The second chopper circuit further generates a third sequence of square wave voltages having a voltage level that changes to the positive and negative side in turns in the manner of sinusoidal wave by summing the first sequence of square wave voltages and the second sequence of square wave voltages. A third chopper circuit chops the third sequence of square wave voltages at a frequency determined by a timing that depends on if a voltage difference thereof to a sinusoidal wave voltage results in a positive value or a negative value and outputting the chopped third sequence of square wave voltages as a charge/discharge output. The third chopper circuit PWM-controls the charge/discharge output at a PWM frequency so that the difference is corrected to thereby generate a sinusoidal wave voltage that continuously changes to the positive and negative sides. | 2010-09-16 |
20100232193 | CAPACITIVE POWER SUPPLY - A capacitive power supply comprises an input section ( | 2010-09-16 |
20100232194 | Content Addressable Memory Having Bidirectional Lines That Support Passing Read/Write Data And Search Data - A CAM column structure includes an interface that drives search data to a plurality of CAM cells via a search line pair. The CAM cells are divided into sections, each section including: a set of CAM cells, a bit line pair coupled to the set of CAM cells, a sense amplifier coupled to the bit line pair, a tri-state read buffer configured to drive read data from the sense amplifier to the search line pair, and a pair of tri-state write buffers configured to drive write data from the search line pair to the bit line pair. In one embodiment, the pair of tri-state write buffers is replaced by a pair of switches that couple the search line pair to the sense amplifier. The search line pair may be segmented by tri-state buffers, which are controlled to drive the search, read and write data along the search line pair. | 2010-09-16 |
20100232195 | Content Addressable Memory (CAM) Array Capable Of Implementing Read Or Write Operations During Search Operations - A read operation and a search operation are performed during the same cycle within a CAM system including a CAM array by: (1) forcing a non-matching condition to exist in the row of the CAM array selected for the read operation, (2) comparing the read data value with the search data value outside of the CAM array to determine whether a match exists, and (3) prioritizing the results of the search operation performed within the CAM array and the results of the comparison performed outside of the CAM array to provide a final search result. | 2010-09-16 |
20100232196 | MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE PROVIDING ACTIVE TERMINATION CONTROL - A semiconductor memory device having a multi-chip package structure providing active termination control. The semiconductor memory device includes first and second memory chips sharing a data I/O bus. The first memory chip includes a first chip enable (CE) port determining whether the first memory chip is activated, and a second CE port monitoring whether the second memory chip is activated. An active termination unit is turned ON only when the first and second chips are deactivated. | 2010-09-16 |
20100232197 | DATA STORAGE DEVICE - A device to selectively activate memory chips includes a memory unit including n memory chips activated in response to n memory chip activation signals (n is a natural number), a controller to generate m control signals (m is a natural number), and a memory chip activation signal generator to combine m chip enable (CE) signals to generate the n memory chip activation signals. | 2010-09-16 |
20100232198 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a cell array including a plurality of first wirings, a plurality of second wirings intersecting the first wirings, and memory cells positioned at intersecting portions between the first wirings and the second wirings, each of the memory cells having a series circuit of a non-ohmic element and a variable resistance element; a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit from a low resistance state to a high resistance state, to the memory cells through the first wirings and the second wirings; and a bias voltage application circuit configured to apply a bias voltage, which suppresses a potential variation caused by the transition of the variable resistance element from the low resistance state to the high resistance state, to one end of the variable resistance element. | 2010-09-16 |
20100232199 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a memory cell array including memory cells, each of the memory cells having a variable resistance element; and a control circuit configured to apply a control voltage, which is necessary for the variable resistance element to transit a resistance state, to a selected memory cell. When applying the control voltage plural times, the control circuit operates to set a value of the control voltage applied in a first control voltage application operation to be substantially equal to a minimum value of distribution of the voltage values of all the memory cells in the memory cell array required to transit the resistance state of the variable resistance element from a high resistance state to a low resistance state. The control circuit operates to perform a plurality of control voltage application operations by increasing the value of the control voltage by a certain value. | 2010-09-16 |
20100232200 | VERTICAL SWITCH THREE-DIMENSIONAL MEMORY ARRAY - A memory device includes a substrate, and, disposed thereover, an array of vertical memory switches. In some embodiments, each switch has at least three terminals and a cross-sectional area less than 6F | 2010-09-16 |
20100232201 | STACKED SEMICONDUCTOR MEMORY DEVICE - A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes. | 2010-09-16 |
20100232202 | DUAL PORT MEMORY DEVICE - A multi-port memory device having a storage node, a precharge node, a first, second, third, and fourth transistor, and a control module. The first transistor includes a current electrode connected to the storage node, another current electrode connected to a first bit line, and a gate connected to a first wordline. The second transistor includes a current electrode connected to the storage node, another current electrode connected to a second bit line, and a gate connected to a second wordline. The third transistor includes a current electrode connected to the reference node, another current electrode connected to the first bit line, and a gate. The fourth transistor includes a current electrode connected to the precharge node, another current electrode connected to the second bit line, and a gate. The control module deactivates the fourth transistor in response to a dummy access of the first storage module at the second transistor. | 2010-09-16 |
20100232203 | ELECTRICAL ANTI-FUSE AND RELATED APPLICATIONS - A first terminal and a second terminal of a FinFET transistor are used as two terminals of an anti-fuse. To program the anti-fuse, a gate of the FinFET transistor is controlled, and a voltage having a predetermined amplitude and a predetermined duration is applied to the first terminal to cause the first terminal to be electrically shorted to the second terminal. | 2010-09-16 |
20100232204 | RESISTANCE VARIABLE ELEMENT, NONVOLATILE SWITCHING ELEMENT, AND RESISTANCE VARIABLE MEMORY APPARATUS - A resistance variable element comprises a first electrode ( | 2010-09-16 |
20100232205 | Programmable resistance memory - A memory includes an interface through which it provides access to memory cells, such as phase change memory cells. Such access permits circuitry located on a separate integrated circuit to provide access signals, including read and write signals suitable for binary or multi-level accesses. | 2010-09-16 |
20100232206 | NON-VOLATILE MEMORY READ/WRITE VERIFY - An apparatus and associated method for writing data to a non-volatile memory cell, such as a resistive random access memory (RRAM) cell. In some embodiments, a control circuitry is configured to write a logic state to a resistive sense element while simultaneously verifying the logic state of the resistive sense element. | 2010-09-16 |
20100232207 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF RESETTING THE SAME - A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage. | 2010-09-16 |
20100232208 | METHOD OF EXECUTING A FORMING OPERATION TO VARIABLE RESISTANCE ELEMENT - A method of executing a forming operation to a variable resistance element to render a resistance value of the variable resistance element capable of transition, the variable resistance element being included in a memory cell connected between a first wiring and a second wiring and changing the resistance value by electrical control, comprises applying a voltage required to execute the forming operation to the variable resistance element between the first and second wirings and changing the first wiring to a floating state. | 2010-09-16 |
20100232209 | CONTROL CIRCUIT FOR FORMING PROCESS ON NONVOLATILE VARIABLE RESISTIVE ELEMENT AND CONTROL METHOD FOR FORMING PROCESS - A nonvolatile semiconductor memory device can carry out a forming process simultaneously on the nonvolatile variable resistive elements of memory cells and make the forming time shorter. The nonvolatile semiconductor memory device has a forming detection circuit provided between the memory cell array and the second selection line (bit line) decoder. The forming detection circuit detects the completion of the forming process for memory cells by measuring the fluctuation in the potential of second selection lines or the current flowing through the second selection lines when applying a voltage pulse for a forming process through the second selection lines simultaneously to the memory cells on which a forming process is to be carried out connected to the same first selection line (word line), and prevents a voltage from being applied to the second selection lines connected to the memory cells where the completion of the forming process is detected. | 2010-09-16 |
20100232210 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes variable resistance elements arranged in a memory area and configured to store data according to a resistance variation, each of the variable resistance elements having a first terminal electrically connected to a first line and a second terminal electrically connected to a second line, and dummy elements arranged in the memory area, formed of the same material as the variable resistance element and electrically isolated. | 2010-09-16 |
20100232211 | MEMORY ARRAY WITH READ REFERENCE VOLTAGE CELLS - The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage. | 2010-09-16 |
20100232212 | SPLIT-GATE DRAM WITH LATERAL CONTROL-GATE MUGFET - A semiconductor structure of an array of dynamic random access memory cells. The structure includes: a first fin of a first split-gate fin-type field effect transistor (FinFET) device on a substrate; a second fin of a second split-gate fin-type field effect transistor (FinFET) device on the substrate; and a back-gate associated with the first fin and the second fin. The back-gate influences a threshold voltage of the first fin and a threshold voltage of the second fin. | 2010-09-16 |
20100232213 | CONTROL SIGNAL TRANSMITTING SYSTEM OF A SEMICONDUCTOR DEVICE - Exemplary embodiments relate to a control signal driving device of a semiconductor device, including: a bus line; a converter receiving a first periodic control signal having the period (frequency) of a clock signal, converting the first periodic control signal into a converted control signal that has twice the period (half the frequency) of the clock signal, and outputting the converted control signal to the bus line; and a restoring unit connected to the opposite end of the bus line and receiving the converted control signal and restoring the converted control signal back into the first periodic control signal. | 2010-09-16 |
20100232214 | STATIC MEMORY MEMORY POINT AND APPLICATION TO AN IMAGE SENSOR - The invention relates to a memory point of SRAM (static memory) type memory. The memory point conventionally comprises two inverters mounted head-to-tail between two nodes, and at least one access transistor able to be made conductive during a writing phase and linked between a first node and a line of data to be written, characterized in that it comprises an isolating transistor inserted in series between the output of a first inverter and the first node, the isolating transistor being controlled by an insulation signal at the start of a writing phase. The current consumption is reduced when the state of the memory point has to be inverted. | 2010-09-16 |
20100232215 | MRAM with coupling valve switching - The free layer in a magneto-resistive memory element is stabilized through being pinned by an antiferromagnetic layer. A control valve layer provides exchange coupling between this antiferromagnetic layer and the free layer. When writing data into the free layer, the control valve layer is heated above its curie point thereby temporarily uncoupling the free layer from said antiferromagnetic layer. Once the control valve cools, the free layer magnetization is once again pinned by the antiferromagnetic layer. | 2010-09-16 |
20100232216 | Phase-Change Memory Device - A phase-change memory device is capable of reducing current consumption and preventing performance deterioration caused due to line load by improving a process of selecting memory cells for a write/read operation. The phase-change memory device has a plurality of cell matrixes and includes word line decoding units that are each shared by a plurality of cell matrixes arranged in a row direction and are configured to activate one of global row signals according to a first row address, local row switch units that are provided to the respective cell matrixes and are configured to connect local current lines to corresponding word lines in response to the activated global row signal, bus connecting units that are provided to the respective cell matrixes and are configured to connect the local current lines to global current lines, and enabling units configured to activate one of the global current lines according to a second row address. | 2010-09-16 |
20100232217 | METHOD FOR EFFICIENTLY DRIVING A PHASE CHANGE MEMORY DEVICE - A method for efficiently driving a phase change memory device is presented that includes the operational procedures of writing, reading, comparing and changing. The phase change memory device has a resistor configured to sense a crystallization state changed by currents so as to store data corresponding to the crystallization state. The writing operation writes data having a first state in a corresponding unit cell of the phase change memory device. The reading operation reads a cell data stored in the unit cell. The comparing operation compares the data having the first state with the cell data read from the unit cell to verify whether or not the data is having the first state is the same as the cell data. The changing operation changes a write condition when the data having a first state is different from that of the cell data. | 2010-09-16 |
20100232218 | METHOD OF TESTING PRAM DEVICE - A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results. | 2010-09-16 |
20100232219 | Micromagnetic Elements, Logic Devices And Related Methods - Micromagnetic elements, logic devices and methods of fabricating and using them to store data and perform logic operations are disclosed. Micromagnetic elements for data storage, as well as those providing output from a logic device, are at least partially covered with an optical coating that facilitates determination of the magnetic state. The disclosed logic devices perform one or more of AND, OR, NAND and NOR operations. | 2010-09-16 |
20100232220 | ELECTRONIC DEVICES FORMED OF TWO OR MORE SUBSTRATES BONDED TOGETHER, ELECTRONIC SYSTEMS COMPRISING ELECTRONIC DEVICES AND METHODS OF MAKING ELECTRONIC DEVICES - Electronic devices comprise a first substrate and a second substrate. The first substrate comprises circuitry including a plurality of conductive traces at least substantially parallel to each other through at least a portion of the first substrate. A plurality of bond pads are positioned on a surface of the first substrate and comprise a width extending over at least two of the plurality of conductive traces. A plurality of vias extend from adjacent at least some of the conductive traces to the plurality of bond pads. The second substrate is bonded to the first substrate and comprises circuitry coupled to the plurality of bond pads on the first substrate with a plurality of conductive bumps. Memory devices and related methods of forming electronic devices and memory devices are also disclosed, as are electronic systems. | 2010-09-16 |
20100232221 | NONVOLATILE MEMORY DEVICE AND METHOD OF READING SAME - A method of reading a nonvolatile memory device comprises sensing data stored in memory cells adjacent to selected memory cells to identify adjacent aggressor cells, and performing separate precharge operations on bitlines connected to selected memory cells having adjacent aggressor cells and on bitlines connected to selected memory cells having adjacent non-aggressor cells. | 2010-09-16 |
20100232222 | MEMORY PAGE BOOSTING METHOD, DEVICE AND SYSTEM - A memory page boosting method, device and system for boosting unselected memory cells in a multi-level cell memory cell is described. The memory device includes a memory array of multi-level cell memory cells configured to store a first portion of logic states and a second portion of logic states. When programming the first portion of logic states, a first boosting process is applied to unselected memory cells and when programming the second portion of logic states, a second boosting process is applied to unselected memory cells. | 2010-09-16 |
20100232223 | Defective block handling method for a multiple data channel flash memory storege device - The block groups of a multiple data channel flash memory storage device are detected for defective blocks. The block group containing any defective blocks is divided into subgroups, each of which contains only defective blocks or only good blocks. The subgroups containing only good blocks are selected to establish a new block group having the same amount of blocks as that of the original block groups. | 2010-09-16 |
20100232224 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - A memory cell array has plural memory strings arranged therein, each of which including a plurality of electrically-rewritable memory transistors and selection transistors. Each memory string includes a body semiconductor layer including four or more columnar portions, and a joining portion formed to join the lower ends thereof. An electric charge storage layer is formed to surround a side surface of the columnar portions. A first conductive layer is formed to surround a side surface of the columnar portions as well as the electric charge storage layer. A plurality of second conductive layers are formed on side surfaces of the joining portion via an insulation film, and function as control electrodes of a plurality of back-gate transistors formed at a respective one of the joining portions. | 2010-09-16 |
20100232225 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has a sense amplifier. The sense amplifier includes a first lower interconnection; a second interlayer insulation film formed on the first interlayer insulation film and top of the first interconnection; a contact interconnection formed in a direction perpendicular to a substrate plane of the semiconductor substrate so as to pass through the second interlayer insulation film, and connected to the first lower interconnection; a first upper interconnection formed on the second interlayer insulation film and connected to the contact interconnection disposed under the first upper interconnection; a dummy contact interconnection formed in a direction perpendicular to the substrate plane of the semiconductor substrate in the second interlayer insulation film, and adjacent to the contact interconnection; and a second upper interconnection formed on the second interlayer insulation film so as to extend in the first direction, and connected to the dummy contact interconnection disposed under the second upper interconnection. | 2010-09-16 |
20100232226 | SOLID STATE STORAGE SYSTEM FOR UNIFORMLY USING MEMORY AREA AND METHOD CONTROLLING THE SAME - A solid state storage system includes a memory area having a plurality of pages and is capable of storing program information about each page. The memory area stores the number of pulse counts applied to each page. A main memory controller receives the program information from the memory area and determines whether to program pages according to the program information. The main memory controller determines whether the program information for a page is at a predetermined amount and if the corresponding page should be programmed again or not. | 2010-09-16 |
20100232227 | NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A non-volatile memory device including a memory cell array; a read/write circuit configured to drive bit lines of the memory cell array with a negative bit line voltage according to data to be programmed; a bit line setup-time measuring circuit configured to measure the bit line setup-time, which may be a function of the amount of data to be programmed, at each ISPP program loop; and a control logic configured to control the program voltage and/or the applied time of a program voltage applied to the selected wordline of the memory cell array based on the measured bit line setup-times measured at each ISPP program loop. | 2010-09-16 |
20100232228 | MEMORY DEVICE, MEMORY SYSTEM AND PROGRAMMING METHOD - A method of programming a memory device includes comparing a first verify voltage and a distribution voltage of at least one memory cell, and if a result of the comparison is a pass, adjusting the distribution voltage until the distribution voltage is higher than a second verify voltage while comparing the distribution voltage and the second verify voltage. | 2010-09-16 |
20100232229 | SEMICONDUCTOR MEMORY DEVICE INCLUDING STACKED GATE INCLUDING CHARGE ACCUMULATION LAYER AND CONTROL GATE - A semiconductor memory device includes a memory cell, a bit line, a source line, a source line driver, a sense amplifier, a counter, a detector, a controller. The sense amplifier reads the data by sensing current flowing through the bit line. The counter counts ON memory cells and/or OFF memory cells. The detector detects whether the voltage of the source line has exceeded a reference voltage. The controller controls the number of times of data sensing by the sense amplifier in accordance with the detection result in the detector, and controls a driving force of the source line driver in accordance with the count in the counter. | 2010-09-16 |
20100232230 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - When data is written to a memory cell transistor, a write controller controls in such a manner that a verification operation subsequent to a program operation is carried out while a program voltage is increased stepwise for each program operation. The write controller controls in such a manner that a verification operation subsequent to a program operation by which a threshold voltage of a memory cell transistor to be written has become equal to or higher than a verification level for the first time is carried out twice or more at the same verification level, verification operations of the second and subsequent times are carried out after a second program operation which is carried out with the memory cell transistor set in an unselected state. | 2010-09-16 |
20100232231 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. | 2010-09-16 |
20100232232 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array. | 2010-09-16 |
20100232233 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device in which a negative-threshold cell read operation is performed by biasing a source line and well line to a positive voltage includes a first drive circuit that sets at least unselected word line in a floating state at a negative-threshold cell read time. | 2010-09-16 |
20100232234 | MEMORY DEVICE HAVING IMPROVED PROGRAMMING OPERATION - Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation. | 2010-09-16 |
20100232235 | Memory Device Having Buried Boosting Plate and Methods of Operating the Same - Memory devices are disclosed, such as those that include a semiconductor-on-insulator (SOI) NAND memory array having a boosting plate. The boosting plate may be disposed in an insulator layer of the SOI substrate such that the boosting plate exerts a capacitive coupling effect on a p-well of the memory array. Such a boosting plate may be used to boost the p-well during program and erase operations of the memory array. During a read operation, the boosting plate may be grounded to minimize interaction with p-well. Systems including the memory array and methods of operating the memory array are also disclosed. | 2010-09-16 |
20100232236 | SRAM LEAKAGE REDUCTION CIRCUIT - A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of V | 2010-09-16 |
20100232237 | HIGH SPEED DRAM ARCHITECTURE WITH UNIFORM ACCESS LATENCY - A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time. | 2010-09-16 |
20100232238 | DUAL PORT MEMORY DEVICE, MEMORY DEVICE AND METHOD OF OPERATING THE DUAL PORT MEMORY DEVICE - A dual port memory device converts an address and a control signal, which are inputted via a first port and conform to a first type memory interface, into an address and a control signal which conform to a second type memory interface, to access a memory array. The dual port memory device accesses a memory array based on an address and a control signal which are inputted via a second port and conform to the second type memory interface. The dual port memory device accesses a memory array according to the first type memory interface or the second type memory interface in response to a selecting signal. Therefore, the dual port memory device can be coupled to a processor with a first interface (e.g., PSRAM or SRAM interface) and a processor with a second interface (e.g., SDRAM interface). | 2010-09-16 |
20100232239 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a row path activating unit configured to generate a line connection control signal according to a received address and active command. The semiconductor memory apparatus also includes a cell array circuit unit including an input/output line switch for connecting a first input/output line in a cell block and a second input/output line extending to the outside of the cell block. The cell array also including a bit line switch for connecting a bit line pair to each other. The input/output line switch and the bit line switch are further controlled by the line connection control signal from the row path activating unit. | 2010-09-16 |
20100232240 | Columnar replacement of defective memory cells - Circuits and methods to compensate for defective memory in BEOL third dimensional memory technology are described. An integrated circuit is configured to perform columnar replacement of defective BEOL multi-layered memory. For example, the integrated circuit can include a primary BEOL memory array having a plurality of BEOL memory cells being configured to change resistivity, a secondary BEOL memory array having another plurality of BEOL memory cells being configured to change resistivity, and a FEOL restoration module associated with the primary BEOL memory array and the secondary BEOL memory array, the FEOL restoration module being configured to locate a BEOL memory cell within the secondary BEOL memory array to replace a defective BEOL memory cell within the primary BEOL memory array. The FEOL portion can be fabricated on a substrate and the BEOL portion can be fabricated above and in contact with the FEOL portion to form the integrated circuit. | 2010-09-16 |
20100232241 | Redundancy architecture for an integrated circuit memory - An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group | 2010-09-16 |
20100232242 | Method for Constructing Shmoo Plots for SRAMS - A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point. | 2010-09-16 |
20100232243 | DIFFERENTIAL SENSE AMPLIFIER - The differential sense amplifier according to one aspect of the present invention includes a first differential amplification unit that detects a difference between the pair of complementary signals inputted from a first bit line and a second bit line, a second differential amplification unit that detects a difference between one of the complementary signals inputted from the first bit line and a first reference signal, and a third differential amplification unit that detects a difference between the other complementary signal inputted from the second bit line and a second reference signal. | 2010-09-16 |
20100232244 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: a memory cell array including a plurality of word lines, a plurality of bit line pairs containing a first bit line and a second bit line, and a plurality of memory cells; a plurality of replica bit lines formed in the same manner as the first and second bit lines; a write buffer circuit operative to drive the first or second bit line to the ground voltage; a replica write buffer circuit operative to drive the replica bit lines to the ground voltage; and a boot strap circuit operative to drive the first or second bit line currently driven to the ground voltage further to a negative potential at a timing when the potential on the replica bit lines reaches a certain value. | 2010-09-16 |
20100232245 | ELECTRONIC CIRCUIT THAT COMPRISES A MEMORY MATRIX AND METHOD OF READING FOR BITLINE NOISE COMPENSATION - Data is read from a memory matrix ( | 2010-09-16 |
20100232246 | REFRESH CONTROL CIRCUIT AND METHOD FOR SEMICONDUCTOR MEMORY APPARATUS - A refresh control circuit of a semiconductor memory apparatus includes: a variable oscillator configured to generate a room-temperature oscillation signal and a limit-temperature oscillation signal in response to a temperature state signal; a cycle selector configured to selectively output the room temperature oscillation signal and the limit-temperature oscillation signal as a variable oscillation signal in response to the temperature state signal; a refresh signal generator configured to generate a refresh signal in response to the variable oscillation signal and a fixed oscillation signal; and a temperature state detector configured to generate the temperature state signal by detecting current temperature in response to the room-temperature oscillation signal and the fixed oscillation signal. | 2010-09-16 |
20100232247 | DATA STORAGE APPARATUS AND CONTROL METHOD OF DATA STORAGE APPARATUS - In a data storage apparatus having data storage means, if it is judged that a condition of transitioning the data storage apparatus into a power saving state is established, it is controlled so that states of signals to be output by operation control means of controlling an operation of the data storage means to plural signal lines are fixed to a specific signal state, and supply of a reference voltage by reference voltage supply means to the plural signal lines is stopped. | 2010-09-16 |
20100232248 | Implementing eFuse Resistance Determination Before Initiating eFuse Blow - A method and an eFuse programming circuit for implementing resistance determination of an eFuse before initiating eFuse blow, and a design structure on which the subject circuit resides are provided. An eFuse on a chip is used to set current flow through a known resistor and measure the eFuse resistance. An applied voltage to program selected eFuses on the chip is selected responsive to an identified eFuse voltage value. | 2010-09-16 |
20100232249 | MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR - A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports. | 2010-09-16 |
20100232250 | Interface circuit and method for coupling between a memory device and processing circuitry - Interface circuitry is provided for coupling between a memory device and processing circuitry, the processing circuitry issuing a plurality of access signals relating to accesses to be performed in the memory device. The interface circuitry comprises write address latch circuitry for storing a write address signal, and write address decoder circuitry that is responsive to a set first enable signal to decode the write address signal provided from the write address latch circuitry. Further, read address latch circuitry is provided for storing a read address signal issued by the processing circuitry, and read address decoder circuitry is responsive to a set second enable signal for decoding the read address signal provided from the read address latch circuitry. Decoder select latch circuitry is responsive to an access type indication signal from the processing circuitry to generate the first and second enable signals in dependence on that access type indication signal. In the event of metastability occurring in the decoder select latch circuitry, the decoder select latch circuitry is arranged not to set at least the second enable signal, thereby disabling at least the read address decoder circuitry in the presence of such metastability. Such an approach prevents metastable signals being used in the arbitration of data accesses in a manner which could corrupt the state of the memory device. | 2010-09-16 |
20100232251 | METHOD AND SYSTEM FOR CODING AND READ OUT OF INFORMATION IN A MICROSCOPIC CLUSTER COMPRISING COUPLED FUNCTIONAL ISLANDS - A method and a system for coding and reading out information in a microscopic cluster formed with coupled functional islands includes: generating the cluster by forming a regular microscopic pattern for locating the functional islands; making use of a physical or chemical property of each individual island and making use of the coupling between the functional islands; assigning different information to different energy levels of the cluster; effecting a change of the physical or chemical property of at least one functional island in order to change the energy level of the cluster to the energy level equivalent to the information content to be coded; and reading out the information. These measures allow forming a cluster having distinct energy levels, each being assigned to a distinct information content. These systems pave the way for future devices based on clusters of coupled islands and, armed with the complete knowledge of the energy states, the door is opened for use of these finite multistate clustered structures in future spintronic devices, for example for data storage, memory applications or to perform logic operations. | 2010-09-16 |
20100232252 | CONCRETE MIXING SYSTEM - A mixing tool is provided for mixing, in a mixing container, plural materials including a first material and a second material. The mixing tool has a shaft and a first mixing member. The first mixing member has a visual reference for indicating when a predetermined volume of the first material is deposited in the mixing container. | 2010-09-16 |
20100232253 | Concrete Containment and Washout Apparatus - A method, a system and an apparatus for removing cement residue located within a concrete discharge chute and controlling the collection of debris and wash water, in a concrete mixing truck. The concrete discharge chute comprises a main chute and an end chute connected to the main chute via a hinged connection. In addition, a barrier plate having a rubber seal is connected to the end chute. When concrete discharge is completed, the barrier plate automatically prevents the discharge of debris by closing off the discharge chute when the end chute is raised into an upright and secured position. The barrier plate also has an optimally placed opening to control material flow along the main chute. The opening is fitted with a valve which may be connected to a drain hose to collect wash water into a collection tank securely positioned on the concrete truck. | 2010-09-16 |
20100232254 | LIQUID STORAGE TANK WITH DRAFT TUBE MIXING SYSTEM - A drinking water distribution reservoir has a new draft tube mixing arrangement. An intermediate opening in the draft tube enables water to flow between the central passage of the draft tube and an intermediate portion of the tank. Directional walls can be provided on the intermediate opening to help direct flow, and a check valve can be used to prevent flow from the intermediate section of the tank into the draft tube or prevent flow from the draft tube into the intermediate section of the tank. A venturi portion can also be provided on the draft tube to help draw water from the intermediate portion of the tank into the draft tube. | 2010-09-16 |
20100232255 | MIXING APPARATUS AND METHOD OF DESIGNING A MIXING APPARATUS - The present application relates to an apparatus for inducing motion of particles of one or more substances and to methods of designing the same. The apparatus has a chamber ( | 2010-09-16 |
20100232256 | LID FOR A MIXING DEVICE - A lid that is removably mountable to an upper open end of a jar of a mixing device includes a generally circular base having a top surface and a opposing bottom surface. A pour spout extends generally vertically upwardly from the base when the lid is mounted to the upper end of the jar. The pour spout has a crisp edge for pouring foodstuff when the lid is mounted to the jar. Further, the lid includes a channel that generally surrounds the pour spout to collect errant drips of foodstuff when the lid is mounted to the jar and when foodstuff is poured through the pour spout. | 2010-09-16 |
20100232257 | ULTRASONIC PROBE AND ULTRASONIC IMAGING DEVICE - Provided is an ultrasonic probe for simultaneously achieving improvement of both of a generatable sound pressure and a gain. An upper electrode | 2010-09-16 |
20100232258 | METHODS AND SYSTEMS FOR SEISMIC SENSOR CALIBRATION - Methods and systems for calibrating seismic sensors configured or designed for use in seismic signal detection. According to certain embodiments of the present disclosure, a current is injected into a moving coil of a seismic sensor and a voltage is measured across the moving coil. The moving coil is locked by the injected current such that environmental noise is reduced while measuring the moving coil voltage. | 2010-09-16 |
20100232259 | FRACTURE CLUSTERS IDENTIFICATION - Method for identifying one or more fracture clusters in a formation surrounding a reservoir. In one implementation, the method may include generating a P to S image, comparing the P to S image to one or more images from a borehole, and identifying one or more fracture clusters using the P to S image and the borehole images. | 2010-09-16 |
20100232260 | ELECTROMAGNETIC SEISMOLOGY VIBRATOR SYSTEMS AND METHODS - Described herein are embodiments of an electromagnetic system that can be used to replace the traditional hydraulic oil systems that actuate mass movement. The embodiments described herein provide wide frequency range operation, ground force application with high fidelity, and low environmental impact. Embodiments described herein can be used for seismic exploration and vibroseis applications, among other uses. | 2010-09-16 |
20100232261 | Sunrise alarm clock - An alarm clock including a rectangular base, a housing mounted on the base, an opaque portion on the front of the housing, a translucent portion on the front of the housing, a time display located on the front of the housing, and a plurality of light emitting diodes mounted inside the housing behind the translucent portion, wherein a first time prior to a set time for an alarm a first number of the plurality of light emitting diodes are lit, wherein on successive times prior to the set time for the alarm successive numbers of the plurality of light emitting diodes are lit, and wherein at the set time for the alarm the entire plurality of light emitting diodes are lit. | 2010-09-16 |
20100232262 | GONG MOUNTING DEVICE FOR STRIKING WATCH - Gong mounting device designed to bear against a crystal ( | 2010-09-16 |
20100232263 | CATEGORY MANAGEMENT - An apparatus, system, and method for managing songs available for selection for play by a user is provided. Songs are assigned to one or more categories and time periods are set during which songs assigned to a category may be selected for play or may be blocked from being selected for play by a user. | 2010-09-16 |
20100232264 | OPTICAL INFORMATION RECORDER/REPRODUCER, OPTICAL INFORMATION RECORDING/REPRODUCING METHOD AND CONTROL CIRCUIT - A distance control circuit ( | 2010-09-16 |
20100232265 | DRIVE DEVICE, OPTICAL HEAD, AND OPTICAL DISK RECORDING/REPRODUCING DEVICE - A spherical aberration correction mechanism | 2010-09-16 |
20100232266 | RECORDING/REPRODUCING APPARATUS AND ADJUSTMENT METHOD THEREFOR - A recording/reproducing apparatus includes: a light source; a first correction section to correct a position of an objective lens that collects laser light from the light source on a surface of an optical disc based on a focus bias setting value obtained from a focus bias value; a second correction section to correct an aberration of the laser light based on an aberration correction setting value obtained from an aberration correction value; an evaluation value generation section to generate an evaluation value; a focus bias adjustment section to change plus/minus of the focus bias value and calculate a new focus bias value based on the evaluation value every time a first cycle passes; and an aberration adjustment section to change plus/minus of the aberration correction value and calculate a new aberration correction value every time a second cycle passes, in parallel with an update of the focus bias value. | 2010-09-16 |
20100232267 | INFORMATION RECORDING APPARATUS, METHOD OF OPC PROCESS FOR MULTILAYER INFORMATION RECORDING MEDIUM, AND PROGRAM - The invention is directed to provide an information recording apparatus having an adjusting process device which performs adjusting processes including an OPC process for optimizing a recording power for each of recording layers on a multilayer information recording medium, and an information recording device which performs an information recording process for each of the recording layers based on a result of the adjusting processes for each of the recording layers. The adjusting process device includes an initial adjusting process device which performs the adjusting processes at a start of information recording with the information recording device only for a start recording layer having the first recording start address, and an intermediate adjusting process device which performs the adjusting processes during information recording process with the information recording device for a recording layer other than the start recording layer. | 2010-09-16 |
20100232268 | METHOD AND APPARATUS FOR RECORDING AND REPRODUCING OPTICAL INFORMATION, AND RECORDING MEDIUM - Ordinary optical disks need the resetting of recording conditions in the course of recording to cope with changes in ambient temperature, laser temperature, and medium's recording sensitivity. Optical disks for super-resolution reproduction which are intended to reproduce record marks smaller than the optical resolution, thereby increasing the recording density, need the resetting of recording conditions as well as the condition of super-resolution reproduction because the quality of reproduced signals depends largely on the power for super-resolution reproduction. The power for recording as well as the power for super-resolution reproduction is therefore changed in the course of test recording to detect the deviation from the optimum value of the recording condition to obtain the optimum recording power. In this case, it is also desirable to change the power for super-resolution reproduction in proportion to the power for recording. | 2010-09-16 |
20100232269 | OPTICAL INFORMATION STORAGE MEDIUM REPRODUCTION APPARATUS AND CONTROL METHOD OF THE SAME - In an optical information storage medium reproduction apparatus ( | 2010-09-16 |
20100232270 | OPTICAL INFORMATION RECORDING MEDIUM, INFORMATION RECORDING APPARATUS, INFORMATION REPRODUCING APPARATUS, INFORMATION RECORDING METHOD, INFORMATION REPRODUCING METHOD AND METHOD FOR PRODUCING OPTICAL INFORMATION RECORDING MEDIUM - An optical information storage medium according to the present invention has at least one information storage layer. The optical information storage medium has a management area that stores at least one unit containing control information about the optical information storage medium. The control information includes a format number, which provides information about at least a write strategy type and a write pre-compensation type, and a write strategy parameter, which provides information about the magnitude of shift in an edge position, or variation in the pulse width, of a write pulse train to form a recording mark. And the value of the format number changes according to a combination of the write strategy type and the write pre-compensation type. | 2010-09-16 |
20100232271 | OPTICAL RECORDING/REPRODUCING METHOD, SYSTEM, AND PROGRAM - An optical recording/reproducing system | 2010-09-16 |