37th week of 2011 patent applcation highlights part 29 |
Patent application number | Title | Published |
20110222308 | LIGHT GUIDE FOR COUPLING DIFFERENTLY SHAPED LIGHT SOURCE AND RECEIVER - A light guide for interfacing between a light source having a light emitting surface with a first shape and a light receiver with a light receiving surface of a second shape. The light guide has a light emitting end having a first shape of substantially the same size as the first shape of the light emitting surface. A light receiving end has a second shape of substantially the same size as the second shape of the light receiving surface. A free form body between the light emitting end and the light receiving end causes a transition between the first and second shape. | 2011-09-15 |
20110222309 | OPTICAL ELEMENT AND LIGHT-EMITTING DEVICE - Provided are an optical element and a light-emitting device with which the illuminated area can be expanded in spite of a small light-emitting area, and that also enable the device to be downsize. The light-emitting device is equipped with sheet-like light-guide sections (a first light-guide section and a second light-guiding section) for guiding light, and a light-emitting member for emitting light. The second light-guide section has a prism section with a saw tooth-like cross-section for changing the direction of the light guided to one of its surfaces. In the prism section, the angle of incidence at which parallel light guided to the second light guide section enters reflective surface of saw teeth at positions away from the LED is set to be greater than the angle of incidence (δ) at which the light enters the reflective surface of the saw teeth at the side toward the LED. In addition, in the prism section, the angle of protrusion of the saw teeth at positions away from the LED is set to be greater than the angle of protrusion of the saw teeth at the side toward the LED. | 2011-09-15 |
20110222310 | LIGHT EMITTING PANEL ASSEMBLIES - Light emitting assembly comprises a light transition member and a light source mounted or positioned within the light transition member. A transparent light emitting panel member conducts light received from the light source. On or in one or more surfaces of the panel member is a pattern of light extracting deformities. A cavity or recess in the panel member is shaped to receive the light transition member to facilitate placement of the light source in a modular manner. | 2011-09-15 |
20110222311 | Web Converting Methods for Forming Light Guides and the Light Guides Formed Therefrom - A method of forming a light guide, web structures and light guide structures are described herein. The method includes cutting a web to provide film pieces, where a first major surface of each film piece is capable of emitting light when light is injected into the film piece from a first cut edge of the film piece. The step of cutting produces structures on the first edge of the film. | 2011-09-15 |
20110222312 | LIGHT EMITTING DEVICE PACKAGE, AND DISPLAY APPARATUS AND LIGHTING SYSTEM HAVING THE SAME - Disclosed are a light emitting device package, and a display apparatus and a lighting system having the same. The light emitting device package includes a body having a recess, a light emitting device received in the recess, and a lead frame connected to the light emitting device. The lead frame includes a bottom frame formed on a bottom surface of the recess, a first side-wall frame formed on a side wall of the recess, and a second side-wall frame formed on a side wall of the recess and bent at a predetermined angle. The second side-wall frame includes a side-wall portion positioned on the side wall of the recess and a protrusion portion bent from the side-wall portion, and the protrusion portion of the second side-wall frame is positioned on a top surface of the body. | 2011-09-15 |
20110222313 | POWER SUPPLY DEVICE AND IMAGE FORMING APPARATUS - A power supply device includes a transformer including a primary coil, a secondary coil, and a tertiary coil; a switching element connected via the primary coil to a direct-current power supply; a first rectifying-and-smoothing circuit rectifying and smoothing a voltage generated in the secondary coil; a control circuit turning on and off the switching element; a second rectifying-and-smoothing circuit rectifying and smoothing a voltage generated in the third coil to generate a driving voltage for the control circuit; and a starting circuit including a first transistor, a first resistor, and a first capacitor connected in series between the direct-current power supply and a ground, a second transistor connected between the direct-current power supply and the second rectifying-and-smoothing circuit, and a turn-off unit turning off at least the second transistor out of the first transistor and the second transistor when the first capacitor is charged to a predetermined voltage. | 2011-09-15 |
20110222314 | POWER SUPPLY WITH REDUCED POWER CONSUMPTION - A power supply includes an isolated power converter and a DC/DC converter. The isolated power converter includes a primary winding connected to a primary power stage, a secondary winding to generate a first output voltage, and an auxiliary winding at the primary side to generate a voltage signal proportional to the first output voltage to stabilize the first output voltage. The DC/DC converter converts the first output voltage into a second output voltage for supplying for a load. | 2011-09-15 |
20110222315 | CURRENT-SHARING POWER SUPPLY APPARATUS - A current-sharing power supply apparatus is applied to regulate voltage level of an input DC voltage, and the regulated DC voltage is stabilized in a predetermined voltage to be used on rear-end circuits. The current-sharing power supply apparatus includes a square-wave generating circuit, a rectifier circuit, a conversion circuit, a rectifier circuit, a filter circuit, a first output terminal, and a second output terminal. The current-sharing power supply apparatus provides two output voltages with a multiple relation from the first output terminal and the second output terminal, respectively. | 2011-09-15 |
20110222316 | ELECTRICALLY INSULATED SWITCHING ELEMENT DRIVER AND METHOD FOR CONTROLLING SAME - An electrically insulated switching element driver includes: a pulse transformer driving unit into which a switching element driving signal and a duty signal are input and which drives, in accordance with the duty signal, a first or second pulse transformer that is selected depending on a state of the switching element driving signal; a first edge detection unit that outputs an on-off signal according to an edge in a pre-rectification output of the first pulse transformer; a second edge detection unit that outputs an on-off signal according to an edge in a pre-rectification output of the second pulse transformer; and a control driving unit that drives a switching element to be driven, based on the output of the first and second edge detection units, wherein the first and second edge detection units and the control driving unit operate with power resulting from rectifying the output of the first and second pulse transformers. | 2011-09-15 |
20110222317 | CONVERTER CIRCUIT AND UNIT AND SYSTEM COMPRISING SUCH CONVERTER CIRCUIT - A converter circuit has a first resonant converter that is connected on the DC voltage side to a first energy storage circuit, and a transformer. A second resonant converter is connected on the AC voltage side to the secondary winding of the transformer and on the DC voltage side to a load converter, and a CLL resonant circuit is connected to the first resonant converter and to the primary winding of the transformer. The CLL resonant circuit has a resonant capacitance, a first resonant inductance and a second resonant inductance. | 2011-09-15 |
20110222318 | ISOLATED SWITCHING POWER SUPPLY APPARATUS - A switching power supply apparatus includes a PFC converter, a DC-DC converter, and primary-side and secondary-side digital control circuits that control the PFC converter and the DC-DC converter. On the basis of a voltage detected by an output voltage detection circuit, the primary-side digital control circuit transmits data about the on-time of a switching element of the DC-DC converter to the primary-side digital control circuit. On the basis of this data, the primary-side digital control circuit controls the on-time of the switching element. | 2011-09-15 |
20110222319 | SWITCHING POWER SUPPLY - A switching power supply includes a first auxiliary power supply for causing a first auxiliary winding of a transformer to induce voltage by ON/OFF control of a switching element connected to a primary winding of the transformer. The voltage induced by the first auxiliary winding charges a capacitor in the first auxiliary power supply. The switching power supply also includes a control circuit for starting and stopping the ON/OFF control of the switching element by comparing a voltage of the capacitor with a first threshold value, an activation circuit for charging the capacitor with voltage from the power supply input to the switching power supply, and a determination unit for determining a lifespan of the switching power supply based on the voltage of the capacitor after the voltage of the capacitor becomes greater than or equal to the first threshold value. | 2011-09-15 |
20110222320 | POWER CONVERSION CONTROL WITH ENERGY STORAGE - A power generation system includes a renewable power source for producing source power; a source side converter for converting the source power to converted DC power; a source side controller for driving the converted DC power towards a maximum power point; a DC link for receiving the converted DC power; a grid side converter coupled to the DC link for converting DC link power from the DC link to AC output power for a grid; a grid side controller for controlling the AC output power of the grid side converter to achieve grid interconnection requirements; an electrical energy storage device; an energy storage converter coupling the energy storage device to the DC link; an energy storage controller for controlling the energy storage converter to achieve a desired power balance on the DC link. | 2011-09-15 |
20110222321 | POWER CONVERTER AND METHOD FOR CONTROLLING THE SAME - An oscillation control part composed of a control switching element and a damping resistance connected in parallel is arranged between an input power supply and a main switching element of a power conversion circuit, and the control switching element and the main switching element have a relationship such as Ron(S2)2011-09-15 | |
20110222322 | DIGITAL DEVICE WITH BOOT STRAP CIRCUIT STIMULATOR - A digital device generates a fixed duty cycle signal with an internal oscillator after a Power-On-Reset (POR). This fixed duty cycle signal is output on a signal pin that normally is used for a PWM control signal. The fixed duty cycle signal is used to stimulate the voltage generation circuits so as to power up the digital device for initialization thereof. Once the digital device has powered-up and initialized, the digital device switches over to normal operation for control of the power system. | 2011-09-15 |
20110222323 | POWER CONVERTER WITH DISTRIBUTED CELL CONTROL - A device for converting a DC voltage into an AC voltage and vice versa comprises a control system to control the voltage conversion and at least one phase leg ( | 2011-09-15 |
20110222324 | CONTROL CIRCUIT, POWER CONDITIONER INCLUDING THE CONTROL CIRCUIT, AND PHOTOVOLTAIC SYSTEM - A power conditioner of a photovoltaic system is configured operate at higher accuracy. A chopper circuit, a capacitor connected in parallel to the chopper circuit, and a control circuit that controls an ON/OFF status of switch elements in the chopper circuit to control charging and discharging of the capacitor are provided. The control circuit includes a measurement control section that measures an inter-end voltage of the capacitor and a control circuit section that performs a predetermined control operation from a measurement output of the measurement circuit section. The measurement circuit section includes a differential amplifier circuit that differentially amplifies the inter-end voltage of the capacitor. The circuit control section calibrates an in-phase component in the output of the differential amplifier circuit as an in-phase error and performs the control from the calibrated output from the differential amplifier circuit. | 2011-09-15 |
20110222325 | SEMICONDUCTOR DEVICE - A semiconductor device of a three-level inverter circuit with a reduced number of power supplies for driving IGBTs. The semiconductor device includes a series-connected circuit of IGBTs between P and N of a DC power supply and an AC switch element that is connected between a series connection point of the series-connected circuit and a neutral point of the DC power supply. The series-connected circuit and the AC switch element are integrated into one module. The AC switch element is formed by connecting a collector of a first IGBT to which a diode is connected in reverse parallel and a collector of a second IGBT to which a diode is connected in reverse parallel, and an intermediate terminal is provided at a connection point between the collectors. | 2011-09-15 |
20110222326 | VARIABLE DUTY CYCLE SWITCHING WITH IMPOSED DELAY - Power conversion methods, systems, articles of manufacture, and devices are provided. The power conversion may include converting between direct current and alternating current wherein switching losses associated with latent electrical charges are reduced. Current sensing may be low-side bus reference. Solid-state implementations, code implementations, and mixed implementations are provided. | 2011-09-15 |
20110222327 | Photovoltaic Inverter Power System - A photovoltaic system may include a DC to AC inverter including a minimum operating power setting and a microprocessor for calculating a maximum available power output for a photovoltaic array. | 2011-09-15 |
20110222328 | DISTRIBUTED SEMICONDUCTOR DEVICE METHODS, APPARATUS, AND SYSTEMS - Some embodiments include a device having a number of memory cells and associated circuitry for accessing the memory cells. The memory cells of the device may be formed in one or more memory cell dice. The associated circuitry of the device may also be formed in one or more dice, optionally separated from the memory cell dice. | 2011-09-15 |
20110222329 | Semiconductor device having its standby current reduced - A semiconductor device includes a plurality of drain lines each being commonly connected to first nodes of a plurality of memory cells, a plurality of bit lines respectively connected to second nodes of the memory cells, a source line, a transistor that connects the drain lines to the source line, and a transistor that connects the source line to a ground potential in response to an access to the memory cell. Under control in which the memory cells are all deactivated, the semiconductor device controls the drain line to a drain potential that is higher than the ground potential, and controls the source line to be in a floating state by deactivating the transistors. | 2011-09-15 |
20110222330 | NONVOLATILE MEMORY DEVICE COMPRISING ONE-TIME-PROGRAMMABLE LOCK BIT REGISTER - A nonvolatile memory device comprises a one-time-programmable (OTP) lock bit register. The nonvolatile memory device comprises a variable-resistance memory cell array comprising an OTP block that store data and a register that stores OTP lock state information indicating whether the data is changeable. The register comprises a variable memory cell. An initial value of the OTP lock state information is set to a program protection state. | 2011-09-15 |
20110222331 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device in accordance with an embodiment includes: a memory cell array having memory cells disposed at respective intersections of first lines and second lines; and a control circuit configured to apply a first pulse voltage multiple times to selected one of the first lines and selected one of the second lines, such that a certain potential difference is applied to a selected memory cell thereby causing transition of a resistance state. The control circuit is configured to, when the selected memory cell is not caused to undergo transition of the resistance state even after application of the first pulse voltage a certain number of times, execute a rescue operation where a second pulse voltage is applied to the selected memory cell subsequent to application of the first pulse voltage, the second pulse voltage having a pulse width longer than that of the first pulse voltage. | 2011-09-15 |
20110222332 | Fully Balanced Dual-Port Memory Cell - The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes four sets of cascaded n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), each set of cascaded NMOSFETs having a pull-down device and a pass-gate device; and a first and second pull-up devices (PU | 2011-09-15 |
20110222333 | MAGNETIC MEMORY CELL AND MAGNETIC RANDOM ACCESS MEMORY - Provided is a highly-integrated magnetic memory which employs applied spin torque magnetization reversal and does not require the switching of the current direction at the time of rewrite. The magnetic memory includes a memory cell in which a fixed layer made of a ferromagnetic material, a nonmagnetic layer, a recording layer made of a ferromagnetic material, a nonmagnetic layer, and a magnetization rotation assist layer made of a ferromagnetic material are stacked one on top of another. The magnetic memory performs recording by making the magnetization direction of the recording layer substantially parallel or substantially antiparallel to the magnetization direction of the fixed layer. The magnetization directions of the fixed layer, the recording layer, and the magnetization rotation assist layer are all oriented in substantially in-plane directions of the respective magnetic layers, and the magnetization direction of the magnetization rotation assist layer is at substantially 90 degrees to the magnetization direction of the fixed layer. The write current is caused to flow in a direction from the fixed layer to the recording layer in both cases where the magnetization direction of the recording layer is rewritten from a direction parallel to the magnetization direction of the fixed layer to a direction antiparallel thereto and where the magnetization direction of the recording layer is rewritten from the antiparallel direction to the parallel direction parallel. | 2011-09-15 |
20110222334 | SPIN TRANSFER TORQUE MRAM, AND WRITE METHOD AND READ METHOD THEREFOR - A method of writing data into a memory cell of spin transfer torque magnetoresistive random access memory includes writing a first data into a first memory cell that includes a first magnetic-tunnel-junction element and a first selection transistor wherein an end of the first memory cell is connected to a first signal line and a different end of the first memory cell is connected to a common signal line during a first period, and writing a second data which is an opposite of the first data into the second memory cell that includes a second magnetic-tunnel-junction element and a second selection transistor wherein an end of the second memory cell is connected to a second signal line and a different end of the second memory cell is connected to the common signal line during a second period following the first period. | 2011-09-15 |
20110222335 | MAGNETORESISTIVE ELEMENT AND MAGNETORESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME - The present invention provides a low-resistance magnetoresistive element of a spin-injection write type. A crystallization promoting layer that promotes crystallization is formed in contact with an interfacial magnetic layer having an amorphous structure, so that crystallization is promoted from the side of a tunnel barrier layer, and the interface between the tunnel barrier layer and the interfacial magnetic layer is adjusted. With this arrangement, it is possible to form a magnetoresistive element that has a low resistance so as to obtain a desired current value, and has a high TMR ratio. | 2011-09-15 |
20110222336 | SEMICONDUCTOR DEVICE - The invention provides a semiconductor device where data can be written after the production and forgery caused by rewriting of data can be prevented, and which can be manufactured at a low cost using a simple structure and an inexpensive material. Further, the invention provides a semiconductor device having the aforementioned functions, where wireless communication is not blocked by the internal structure. The semiconductor device of the invention has an organic memory provided with a memory cell array including a plurality of memory cells, a control circuit for controlling the organic memory, and a wire for connecting an antenna. Each of the plurality of memory cells has a transistor and a memory element. The memory element has a structure where an organic compound layer is provided between a first conductive layer and a second conductive layer. The second conductive layer is formed in a linear shape. | 2011-09-15 |
20110222337 | FLOATING-BODY/GATE DRAM CELL - Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field effect transistor is used to drive the gate of the second transistor structure of a cell. | 2011-09-15 |
20110222338 | METHOD OF HANDLING REFERENCE CELLS IN NVM ARRAYS - A memory chip includes memory cells storing data to be read, at least one reference cell having a reference cell current level, at least one reference gate voltage memory cell storing a reference gate voltage value and a read circuit to read the memory cells with a fixed gate voltage with respect to at least one reference cell activated at a voltage having its associated stored reference gate voltage value. | 2011-09-15 |
20110222339 | NONVOLATILE MEMORY DEVICE FOR REDUCING INTERFERENCE BETWEEN WORD LINES AND OPERATION METHOD THEREOF - Provided are a nonvolatile memory device and a method of operating the same. The nonvolatile memory device in accordance with an embodiment of the inventive concept may include a string select line; a ground select line; a dummy word line adjacent to the ground select line; a first word line adjacent to the dummy word line; and a second word line disposed between the string select line and the first word line. The nonvolatile memory device is configured to apply a voltage to the dummy word line. When programming a memory cell connected to the first word line, a first dummy word line voltage lower than a voltage applied to the second word line is applied to the dummy word line. When programming a memory cell connected to the second word line, a second dummy word line voltage between a voltage applied to the first word line and the first dummy word line voltage is applied to the dummy word line. Accordingly, when a program operation is performed, a charge loss of a memory cell connected to a word line adjacent to a dummy word line can be reduced by changing a voltage applied to the dummy word line according to a select word line. | 2011-09-15 |
20110222340 | FLASH MEMORY DEVICE AND OPERATING METHOD FOR CONCURRENTLY APPLYING DIFFERENT BIAS VOLTAGES TO DUMMY MEMORY CELLS AND REGULAR MEMORY CELLS DURING ERASURE - Integrated circuit flash memory devices, such as NAND flash memory devices, include an array of regular flash memory cells, an array of dummy flash memory cells and an erase controller. The erase controller is configured to concurrently apply a different predetermined bias voltage to the dummy flash memory cells than to the regular flash memory cells during an erase operation of the integrated circuit flash memory device. Related methods are also described. | 2011-09-15 |
20110222341 | MULTI-LEVEL CELL PROGRAMMING SPEED IMPROVEMENT THROUGH PROGRAM LEVEL EXCHANGE - A method of storing data in a multi-level charge-trapping memory array is described. An incidence-of-occurrence (i.e., frequency) analysis is performed on data to be programmed to identify data words combining a high programming voltage with a high frequency of occurrence. Those words are reassigned in order to reduce programming time. | 2011-09-15 |
20110222342 | DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF - A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern. | 2011-09-15 |
20110222343 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline. | 2011-09-15 |
20110222344 | METHOD FOR MODIFYING DATA MORE THAN ONCE IN A MULTI-LEVEL CELL MEMORY LOCATION WITHIN A MEMORY ARRAY - A method and apparatus for marking a block of multi-level memory cells for performance of a block management function by programming at least one bit in a lower page of the memory cell block such that a first logic state is stored in the at least one bit in the lower page; programming at least one bit in an upper page of the memory cell block such that the first logic state is stored in the at least one bit in the upper page; reprogramming the at least one bit in the upper page such that the at least one bit transitions from the first logic state to a second logic state; identifying the first logic state in the at least one bit of a lower page and the transition of at least one corresponding bit in the upper page from the first logic state to the second logic state; and in response, marking the corresponding memory cell block for performance of a block management function. | 2011-09-15 |
20110222345 | Non-Volatile Memory and Method With Power-Saving Read and Program-Verify Operations - A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has features to reduce power consumption during read, and program/verify operations. A read or program verify operation includes one or more sensing cycles relative to one or more demarcation threshold voltages to determine a memory state. In one aspect, selective memory cells among the group being sensed in parallel have their conduction currents turned off when they are determined to be in a state not relevant to the current sensing cycle. In another aspect, a power-consuming period is minimized by preemptively starting any operations that would prolong the period. In a program/verify operation cells not to be programmed have their bit lines charged up in the program phase. Power is saved when a set of these bit lines avoids re-charging at every passing of a program phase. | 2011-09-15 |
20110222346 | NAND-TYPE FLASH MEMORY - A NAND-type flash memory has a bit line; a source line; and a NAND string that is configured by connecting a plurality of memory cells, into which data can be electrically rewritable, in series. The NAND-type flash memory has a drain-side selection gate transistor that has a gate to which a drain-side selection gate line is connected and that is connected between one end of the NAND string and the bit line; and a source-side selection gate transistor that has a gate to which a source-side selection gate line is connected and that is connected between the other end of the NAND string and the source line. The NAND-type flash memory has a row decoder that selects the memory cell by controlling voltages applied to control gates of the memory cells and that controls voltages applied to the drain-side selection gate line and the source-side selection gate line; and a bit line control circuit that controls a voltage of the bit line. | 2011-09-15 |
20110222347 | NAND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITE METHOD FOR NAND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a NAND nonvolatile semiconductor memory device comprises memory cell transistors and a write circuit. The memory cell transistors are arranged in a matrix in a column direction and in a row direction. Each of the memory cell transistors comprises a charge accumulation layer and a control gate electrode configured to control the charge accumulation state of the charge accumulation layer. The write circuit carries out write on the memory cell transistors. The memory cell transistors arranged in the same line include first memory cell transistors and second memory cell transistors that are smaller than the first memory cell transistors in the column direction. The write circuit carries out write on a predetermined first memory cell transistor and then on another first memory cell transistor. After the write on the another first memory cell transistor, the write circuit carries out write on the second memory cell transistor. | 2011-09-15 |
20110222348 | Nonvolatile Memory Devices Having Memory Cell Arrays with Unequal-Sized Memory Cells and Methods of Operating Same - Nonvolatile memory devices include a two-dimensional array of nonvolatile memory cells having a plurality of memory cells of unequal size therein. These memory cells may include those that have unequal channel widths associated with respective word lines and those having unequal channel lengths associated with respective bit lines that are connected to corresponding strings of nonvolatile memory cells (e.g., NAND-type strings). Control circuitry is also provided that is electrically coupled to the two-dimensional array of nonvolatile memory cells. This control circuitry may operate to concurrently program first and second nonvolatile memory cells having unequal sizes from an erased state (e.g., logic 1) to an equivalent programmed state (e.g., logic 0). This is done by establishing unequal first and second word line-to-channel region voltages in the first and second nonvolatile memory cells, respectively, during an operation to program a row of memory cells in the two-dimensional array of nonvolatile memory cells, which includes the first and second nonvolatile memory cells of unequal size. | 2011-09-15 |
20110222349 | TRANSFER CIRCUIT, NONVOLATILE SEMICONDUCTOR DEVICE USING THE SAME, AND TRANSFER METHOD OF THE SAME - According to one embodiment, a transfer circuit includes a first inverter, a second inverter, a first line, a second line, a first holder, and a second holder. The first inverter inverts data at a first node and transfers the inverted data to a second node. The second inverter inverts the data at the second node and transfers the inverted data to the first node. The first line connected to the first node. The second line connected to the second node. The first holder may output data to the first node. The second holder may output data to the second node. When the first holder outputs the data to the first line, the first and second inverters are turned off. When the second holder outputs the data to the first line through the second node, the first inverter is turned off. | 2011-09-15 |
20110222350 | MULTI-LEVEL CELL ACCESS BUFFER WITH DUAL FUNCTION - An access buffer, such as page buffer, for writing to non-volatile memory, such as Flash, using a two-stage MLC (multi-level cell) operation is provided. The access buffer has a first latch for temporarily storing the data to be written. A second latch is provided for reading data from the memory as part of the two-stage write operation. The second latch has an inverter that participates in the latching function when reading from the memory. The same inverter is used to produce a complement of an input signal being written to the first latch with the result that a double ended input is used to write to the first latch. | 2011-09-15 |
20110222351 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises memory cells which includes a selection transistor and a memory transistor; selection gate lines coupled to a gate of the selection transistor; control gate lines coupled to the control gate of the memory transistor; source lines coupled to a source of the memory transistor; bit lines coupled to the selection transistor; a selection gate line driver circuit; a control gate line driver circuit; and a source line driver circuit, wherein the selection gate line driver circuit comprises a first transistor including a first gate insulation film and drives the selection gate line with a first driving voltage, and the control gate line driver circuit and the source line driver circuit comprises a second transistor including second gate insulation films and drives the control gate line and the source line with a boost voltage higher than the first driving voltage. | 2011-09-15 |
20110222352 | METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE TO REDUCE FLOATING-GATE-TO-FLOATING-GATE COUPLING EFFECT - A method for programming a non-volatile memory array comprising a plurality of memory cells. Each cell is adapted to store a lower and an upper page of data. The method: programs the lower page of predetermined memory cells with first predetermined data and the upper page with second predetermined data. One of the lower page or the upper page of the predetermined memory cells is reprogrammed with the first or second predetermined data, respectively. | 2011-09-15 |
20110222353 | SENSING OPERATIONS IN A MEMORY DEVICE - Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell. | 2011-09-15 |
20110222354 | METHOD AND SYSTEM FOR MINIMIZING NUMBER OF PROGRAMMING PULSES USED TO PROGRAM ROWS OF NON-VOLATILE MEMORY CELLS - A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry. | 2011-09-15 |
20110222355 | Control voltage generation circuit and nonvolatile storage device having the same - Disclosed herein is a control voltage generation circuit including: a reference voltage generation circuit adapted to generate a reference voltage; and a voltage conversion circuit adapted to generate, based on the reference voltage, a control voltage to be supplied to the gate of a clamping transistor connected between a bit line and a sense amplifier to adjust the voltage of the bit line, wherein the voltage conversion circuit outputs a voltage, which is the sum of a voltage proportional to the reference voltage and a voltage equivalent to the threshold voltage of the clamping transistor, to the gate of the clamping transistor as the control voltage. | 2011-09-15 |
20110222356 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region. | 2011-09-15 |
20110222357 | Process and Temperature Tolerant Non-Volatile Memory - A nonvolatile memory comprising an array of memory cells and sense amplifiers, each sense amplifier using a keeper circuit to provide an amount of current to compensate for bit line leakage current in the memory array. The amount of current from the keeper depends on the temperature of the memory and the speed of the process used to make the memory. | 2011-09-15 |
20110222358 | Memory Systems and Methods for Dynamically Phase Adjusting A Write Strobe and Data To Account for Receive-Clock Drift - A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write strobe to compensate for timing drift at the memory device. The memory controller uses the read strobe as a measure of the drift. | 2011-09-15 |
20110222359 | APPARATUS AND METHOD FOR TRANSMITTING/RECEIVING SIGNALS AT HIGH SPEED - A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal. | 2011-09-15 |
20110222360 | SEMICONDUCTOR STORAGE DEVICE AND ITS CELL ACTIVATION METHOD - A semiconductor storage device in accordance with the present invention includes a first SRAM cell that stores data, and a word line circuit that outputs a first control signal used to activate the first SRAM cell. The word line control circuit gradually raises the voltage level of the first control signal from a substrate potential to a first power supply potential in a first activation period, maintains the voltage level of the first control signal at the first power supply potential in a second activation period subsequent to the first activation period, and raises the voltage level of the first control signal from the first power supply potential to a second power supply potential in a third activation period subsequent to the second activation period. | 2011-09-15 |
20110222361 | NANO-SENSE AMPLIFIER - A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter. | 2011-09-15 |
20110222362 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state. | 2011-09-15 |
20110222363 | LUG TYPE EXTRUDER SCREW - An extruder screw that enables mixing of viscous materials, such as rubber mixtures and thermoplastic materials, is disclosed. The screw includes a core extending from a sealing end to a nose cone end. At least one flight extends radially from the core in a quasi-helical pattern, wherein flights adjacent one another form channels therebetween. A plurality of elongate lugs extend radially from the core and are disposed in the channels. The shape as well as the number of lugs can be varied to ensure the requirements for a thorough and turbulent deflection and mixing of the material stream. | 2011-09-15 |
20110222364 | KNEADING ROTOR, BATCH KNEADER AND METHOD OF KNEADING MATERIALS - Provided is a kneading rotor, a batch kneader and a method of kneading materials capable of obtaining kneaded materials with higher quality in comparison to conventional kneaded materials when the materials to be kneaded are kneaded in a high temperature state. The kneading rotor comprises a rotor portion which is disposed in a kneading chamber of a chamber of a batch kneader, and applies shear force, by using a plurality of kneading blades, to materials to be kneaded which pass through a tip clearance. A first long blade of the plurality of kneading blades has an apex for forming, with the inner surface of the chamber forming the kneading chamber, three-staged tip clearances of different sizes configured from a combination of a large tip clearance, a mid tip clearance that is smaller than the large tip clearance, and a small tip clearance that is smaller than the mid tip clearance so as to be arranged in the longitudinal direction of the first long blade. Each of a second long blade, a first short blade and a second short blade of the plurality of kneading blades has an apex for forming, with the inner surface of the chamber forming the kneading chamber, a tip clearance of a size that is larger than or equal to the small tip clearance and smaller than or equal to the large tip clearance. | 2011-09-15 |
20110222365 | Apparatus for restarting a gas-solids contactor - A gas-solids contactor modification is described which provides for starting or restarting the gas flow to the gas-solids contactor when it is filled with solid particles while preventing the solids from entering and blocking one or more gas inlets which have diameters greater than the solid particle diameters. The apparatus modification comprises a gas plenum and one or more chambers within the gas plenum located between the contactor inlet and the gas inlet. The wall of the chamber has multiple passageways therethrough that are smaller in diameter than the majority of the bed particles. Gas feed to the plenum must pass through the passageways in the chamber walls before entering the contactor. In one embodiment the total open area of the passageways is at least as large as the cross-sectional area of the gas inlet and the inlet to the contactor. | 2011-09-15 |
20110222366 | INJECTOR DEVICE - An injector device is disclosed, the injector device comprising an elongated mixing container extending along a first axis, and a piston member slidably positioned in the mixing container. The injector device comprises a mixing device comprising a mixing member, an elongated member parallel to the first axis and a handle member. The piston member comprises a piston head and a first locking arm flexibly connected to the piston head, such that the first locking arm in a first position extends substantially parallel to the elongated member and engages with the mixing device in such a way that the piston member moves in a first direction along the first axis with the mixing device. In a second position, the first locking arm may allow the mixing device to move relative to the mixing container independently of the piston member. | 2011-09-15 |
20110222367 | Flexible Touchpad for a Kitchen Appliance - A flexible touchpad for a kitchen appliance includes a first surface having at least one button feature integrally molded therein and extending outwardly in a first direction beyond a surrounding portion of the first surface. An opposing second surface has at least one post extending outwardly in a second direction beyond a surrounding portion of the second surface. The at least one post defines a first end, an opposing second free end and a longitudinal axis extending therebetween. The longitudinal axis is generally aligned with the at least one button feature. | 2011-09-15 |
20110222368 | Detecting Seismic Data in a Wellbore - In one general embodiment, a seismic tool system includes a cable adapted to be deployed within a borehole; and one or more seismic tools suspendable from the cable in the borehole. At least one of the seismic tools includes at least one seismic sensor enclosed within a housing; one or more rollers attached to the housing and adapted to engage the borehole; and a bow spring attached to the housing and including one or more rollers adapted to engage the borehole. The one or more of the rollers are in acoustic communication with the seismic sensor. | 2011-09-15 |
20110222369 | Acoustic Transducer with a Liquid-Filled Porous Medium Backing and Methods of Making and Using Same - In one aspect, the disclosure provides an apparatus that includes an acoustic transducer, and a backing coupled to the transducer, wherein the backing includes solid grains with fluid between the grains. | 2011-09-15 |
20110222370 | METHODS AND SYSTEMS FOR PERFORMING AZIMUTHAL SIMULTANEOUS ELASTIC INVERSION - An improved method for analyzing seismic data to obtain elastic attributes is disclosed. In one embodiment, a reflectivity series is determined for at least one seismic trace of seismic data obtained for a subterranean formation, where the reflectivity series includes anisotropy properties of a formation. One or more synthetic seismic traces are obtained by convolving the reflectivity series with a source wavelet. The one or more synthetic seismic traces are inverted to obtain elastic parameters estimates. According to one aspect, the data inputs are angle-azimuth stacks. According to another aspect, the data inputs are azimuthal Fourier coefficients, u | 2011-09-15 |
20110222371 | Using Seismic Sensor Transfer Functions for High Fidelity Seismic Imaging - A technique includes deploying seismic sensors to perform a seismic survey and during the deployment of the seismic sensors, testing each of the seismic sensors to determine an associated sensor transfer function. The technique includes determining an associated operator to apply to seismic data acquired by each of the seismic sensors in the seismic survey based at least in part on a frequency dependent variation between the associated sensor transfer function and a nominal response for the seismic sensor. The technique includes processing the seismic data, including applying the associated operators to the seismic data. | 2011-09-15 |
20110222372 | METHOD AND SYSTEM FOR DEREVERBERATION OF SIGNALS PROPAGATING IN REVERBERATIVE ENVIRONMENTS - The dereverberation of signals in reverberating environments is carried out via acquiring the representation (image) of spatial distribution of the signals in space of interest and automatic identification of reflections of the source signal in the reverberative space. The technique relies on identification of prominent features at the image, as well as corresponding directions of propagation of signals manifested by the prominent features at the image, and computation of similarity metric between signals corresponding to the prominent features in the image. The time delays between the correlated signals (i.e., source signal and related reflections) are found and the signals are added coherently. Multiple beamformers operate on the source signal and corresponding reflections, enabling one to improve the signal-to-noise ratio in multi-path environments. | 2011-09-15 |
20110222373 | METHODS, SYSTEMS, AND APPARATUS TO CALCULATE DISTANCE FROM AUDIO SOURCES - Systems, methods, articles of manufacture and apparatus are disclosed to calculate distance from audio sources. An example method disclosed herein includes receiving, at the reference audio collecting device, a first radio frequency (RF) signal from the portable audio collecting device, in response to receiving the RF signal, storing ambient audio to a memory as reference data samples, each of the reference data samples associated with an indication of a respective time of acquisition, and receiving a second RF signal containing portable data samples of the ambient audio, each of the portable data samples associated with an indication of a respective time of acquisition. The example method also includes computing a correlation value between a set of the portable data samples and a plurality of the reference data samples, selecting a set of samples having a highest correlation value, subtracting the indication of times of the pair of samples to form a difference value, and calculating a distance between the portable audio device and the reference audio collecting device based on the difference value. | 2011-09-15 |
20110222374 | OCEAN BOTTOM SEISMIC STATION - Methods and apparatus for cable termination and sensor integration at a sensor station within an ocean bottom seismic (OBS) cable array are disclosed. The sensor stations include a housing for various sensor components. Additionally, the sensor stations can accommodate an excess length of any data transmission members which may not be cut at the sensor station while enabling connection of one or more cut data transmission members with the sensor components. The sensor stations further manage any strength elements of the cable array. | 2011-09-15 |
20110222375 | Ultraviolet ray measuring apparatus and electronic wristwatch equipped with ultraviolet ray measuring function - The ultraviolet ray sensor measures the intensity of ultraviolet rays irradiated to the ultraviolet ray receiving surface. The CPU performs control to measure ultraviolet intensity in a case in which the ultraviolet ray receiving surface of the ultraviolet ray sensor faces in a predetermined direction. | 2011-09-15 |
20110222376 | DRIVING MECHANISM FOR A CLOCK MOVEMENT - A driving member for a timepiece movement includes a shaft, and a drum and a rotating member both mounted on the shaft. The drum and the rotating member are able to rotate with respect to each other and include teeth on their periphery. First and second superposed spiral springs have outer ends fixed to the drum and to the rotating member respectively and inner ends connected to each other to connect the springs in series. The drum and the rotating member fit together at least in the area of the peripheral wall of the drum so as to together form a closed housing containing the springs. | 2011-09-15 |
20110222377 | OSCILLATOR SYSTEM - An oscillator system ( | 2011-09-15 |
20110222378 | AT LEAST PARTIALLY ENAMELLED RELIEF DIAL - The invention relates to an at least partially enamelled dial whose visible surface includes areas standing out in relief, including a first part made of ceramic material or another compatible substrate that may or may not be coated with enamel including at least one through hole and at least one second part made of ceramic material or another compatible substrate that may or may not be coated with enamel. According to the invention, said at least one second part includes a main, projecting face which is larger than the section of said at least one hole and said at least one second part is secured to the first part to totally cover the periphery of said at least one hole without the second part projecting into the hole, so as to form a relief dial with improved rendering. | 2011-09-15 |
20110222379 | METHOD FOR CONTROLLING OVERWRITING OF DATA BY TAPE RECORDING APPARATUS , PROGRAM FOR CONTROLLING OVERWRITING , AND TAPE RECORDING APPARATUS - A data-overwriting technique that facilitates determining whether data is new or old, when reading thereof. A tape recording apparatus includes: a receiving unit for receiving information on overwrite starting position and an overwrite request; a trying unit for trying to determine a beginning position of a data unit based on the information on an overwrite starting position, wherein the data unit is a unit of writing data recorded on a tape medium; an overwrite executing unit for executing overwriting from the determined overwrite starting position in response to a success of the determination by the trying unit; and a type judging unit for judging whether the data unit that is recorded at the overwrite starting position is a null data unit or not in response to a failure of the determination by the trying unit. The trying unit responds to judgment that the data unit is the null data unit by trying to determine a beginning of a data unit following the data unit as the overwrite starting position. | 2011-09-15 |
20110222380 | OPTICAL DISC APPARATUS, OPTICAL DISC, RECORDING METHOD, AND REPRODUCTION METHOD - It takes time to read management information and the like from a recording layer in starting reproduction of an optical disc, thus posing a problem of poor usability. Moreover, a light beam needs to be largely moved in a radial direction in recording or reproducing the next layer, thus posing a problem that the time to interrupt recording or reproduction increases. The above-described problems can be resolved by enabling a reference layer to be recorded and reproduced, and recording disc management information and the like in this reference layer, and reproducing this information. Moreover, the reference layer comprises two layers having the spiral directions of the track different from each other, and the reference layer, on which a light beam is focused, is changed according to a layer to be recorded or reproduced in the recording layer. | 2011-09-15 |
20110222381 | WRITE-ONCE TYPE MULTILAYER OPTICAL DISC, RECORDING METHOD, REPRODUCING METHOD, AND RECORDING DEVICE - Manufacturing of a higher quality write-once type multilayer optical disc is facilitated. The optical disc includes a plurality of recording layers in which recording or reproduction is carried out by a blue or blue-violet laser beam of a wavelength of about 405 nm. Each of the recording layers includes a recording layer which uses an organic dye. The plurality of recording layers includes a layer in which a groove pattern around a recording mark is deformed when information is recorded, and a layer in which the groove pattern around the recording mark is not deformed when information is recorded. | 2011-09-15 |
20110222382 | OPTICAL DISC DRIVE AND METHOD FOR READING DATA FROM OPTICAL DISC - An optical disc drive and optical disc reading method according to the present invention is designed to perform a read operation with good stability even on a slim disc that could produce a significant axial runout. For that purpose, the optical disc drive determines, by the time it has taken for the number of revolutions of a motor that rotates the optical disc loaded to reach a predetermined number, whether the disc loaded is a lightweight disc or not (in Step | 2011-09-15 |
20110222383 | WRITING METHOD FOR OPTICAL DISK DRIVE - A writing method for an optical disk drive includes receiving a command to write a disc; implementing an optimum power control (OPC) test for a predetermined data transfer rate to obtain a relation of a beta parameter to writing power; acquiring a writing power for the predetermined data transfer rate with a target beta parameter; calculating the energy area ratio of writing strategies for every data transfer rate; multiplying the energy area ratio by the writing power for the predetermined data transfer rate to produce the writing power for every data transfer rate; and compensating the writing power with automatic writing control. | 2011-09-15 |
20110222384 | OPTICAL DISC DEVICE AND OPTICAL DISC DEVICE DRIVE METHOD - An optical disc apparatus of the present invention records and/or reproduces data to/from an optical disc where data is recorded on one of a groove track and a land track. The optical disc apparatus includes an identification section for identifying the type of the optical disc as being either an optical disc where data is recorded or reproduced to/from a groove track or an optical disc where data is recorded or reproduced to/from a land track. The identification section identifies the type of the optical disc while in a state where a focus control is being performed and a tracking control is not being performed. | 2011-09-15 |
20110222385 | APPARATUS AND METHOD FOR TESTING SPOKE SENSOR - An apparatus and a method for testing spoke sensor are disclosed. A drive unit is started to rotate a test disc to a predetermined rotation speed. A module test unit is electrically connected to a spoke sensor under test of a spindle motor module. The module test unit is started to drive the spoke sensor to detect the spoke signals of the test disc and record the number of detected spoke signals. Within a test time, a comparison unit is used for comparing the number of spoke signals with a threshold, and only when the detected number is larger than a threshold will the spoke sensor be assembled to the product. Thus, the product quality is assured. | 2011-09-15 |
20110222386 | OPTICAL DISK DRIVE - There is provided an optical disk drive that pursues power saving and simultaneously assures data recording quality. A servo processor of the optical disk drive has a low frequency equalizer, a high frequency equalizer, a limiter, and an adder. A limit voltage value of the limiter is set by means of a control command from a system controller. The limit voltage value is set so as to become greater during a data recording period than in a data regeneration period. An output from the adder is supplied as a tracking drive signal to a tracking actuator or as a focus drive signal to a focus actuator. | 2011-09-15 |
20110222387 | OPTICALLY LOCKED PHOTON ECHO APPARATUS AND METHOD - Disclosed herein is an optically locked photon echo apparatus and method, which can solve the problem of limited echo efficiency and can overcome constraints on the conventional storage time being limited to the spin dephasing time. The optically locked photon echo apparatus of the present invention includes a nonlinear optical medium and an optical pulse generation unit. The nonlinear optical medium is provided with three energy levels | | 2011-09-15 |
20110222388 | ODD RAID DRIVING METHOD - This document relates to an optical disk drive RAID driving method. In an embodiment of this document, data to be suited for a RAID level is transformed and stored in a buffer area allocated in a storage and the data stored in the buffer area is distributively recording in a plurality of optical disks through a plurality of optical disk drives according to the RAID level. | 2011-09-15 |
20110222389 | LASER CONVERGING APPARATUS, OPTICAL PICKUP DEVICE, AND OPTICAL DISC RECORDING/REPRODUCING APPARATUS - A laser converging apparatus includes a polarizing hologram element having a first area defined by a numerical aperture corresponding to a thickness of a first protective layer of a first disk medium and a second area inside the first area, the second area defined by a numerical aperture corresponding to a thickness of a second protective layer (>the thickness of the first protective layer) of a second disk medium. A wavelength selecting nonpolarizing hologram element has a third area defined by a numerical aperture corresponding to a thickness of a third protective layer (>the thickness of the first protective layer) of a third disk medium. The laser converging apparatus also includes an objective lens having the numerical aperture corresponding to the thickness of the first protective layer, and a holder that holds the polarizing hologram element, the nonpolarizing hologram element, and the objective lens. | 2011-09-15 |
20110222390 | Method and Apparatus for Selecting Options Located on a Media Disc - A method and apparatus for selecting options on a media disc containing data. In one embodiment, an option identifier associated with an external surface of the media disc by a sensor unit coupled to a media player is detected, wherein the external surface is an outer surface of the media disc. A presentation option corresponding to the option identifier is identified to form an identified presentation option. Media content associated with the media disc is presented in a format corresponding to the presentation option. | 2011-09-15 |
20110222391 | METHOD FOR MANUFACTURING MEDIUM ON WHICH INFORMATION IS RECORDED IN PIT PATTERN - A method by which depressions and projections (pit pattern) can be formed directly and easily in a substrate made of inorganic material is provided. A method for forming a medium on which information is recorded in a pit pattern comprises the steps of: forming a recording material layer ( | 2011-09-15 |
20110222392 | READ-ONLY OPTICAL INFORMATION RECORDING MEDIUM AND SPUTTERING TARGET FOR DEPOSITING REFLECTIVE FILM FOR THE OPTICAL INFORMATION RECORDING MEDIUM - Provided is a read-only optical information recording medium (for instance, a dual-layer BD-ROM), which uses blue laser and is provided with a reflecting film which has sufficiently high reflectivity while ensuring optical transparency required in manufacture, has excellent reproduction stability when used for an optical information recording medium and has excellent durability. The read-only optical information recording medium includes a structure wherein a plurality of laminated layers of the reflecting film and the optical transparent layer are formed on a substrate, and reproduces information by means of blue laser. The reflecting film closest to the substrate among the reflecting films is substantially composed of an Al-based alloy containing 0.5-3.0 atm % of Ti, and has a film thickness of 10 nm or more but not more than 30 nm. | 2011-09-15 |
20110222393 | METHOD OF TRANSMITTING CONTROL SIGNALS IN WIRELESS COMMUNICATION SYSTEM - A method of transmitting control signals in a wireless communication system includes multiplexing a first control signal with a second control signal in a slot, the slot comprising a plurality of orthogonal frequency division multiplexing (OFDM) symbols in time domain, the plurality of OFDM symbols being divided into a plurality of data OFDM symbols and a plurality of reference signal (RS) OFDM symbols, wherein the first control signal is mapped to the plurality of data OFDM symbols after the first control signal is spread by a base sequence in the frequency domain, the RS is mapped to the plurality of RS OFDM symbols, the second control signal is mapped to at least one of the plurality of RS OFDM symbols, and transmitting the first control signal and the second control signal in the slot. | 2011-09-15 |
20110222394 | FABRIC EXTRA TRAFFIC - A method of forwarding traffic through a network node including an ingress IO card, an egress IO card, and a pair of parallel switch fabric cards. One of the switch fabric cards is designated as a working switch fabric card, and the other one of the switch fabric cards is designated as a protection switch fabric card. In the ingress IO card, the traffic flow is divided into a committed information rate (CIR) component and an extra information rate (EIR) signal. Under a normal operating condition of the node, the ingress IO card forwards the CIR traffic component through the working switch fabric card, and forwards the EIR traffic component through the protection switch fabric card. Upon detection of a failure impacting the working switch fabric card, the ingress IO card drops the EIR traffic component and forwards the CIR traffic component through the protection switch fabric card. | 2011-09-15 |
20110222395 | DUAL PORT ETHERNET COMMUNICATION DEVICE WITH BYPASS FUNCTION - Provided is a dual port Ethernet communication device which allows data received via any one communication port to be bypassed to other communication port. Since the Ethernet communication device performs such bypass operation itself, the communication data can be kept transferred to other terminal unit even though the terminal unit equipped with the Ethernet communication device does not operate normally due to causes such as a break down. In particular, if it is used in each terminal unit forming a closed loop in a closed loop power system, the communication on the closed loop remains such that the adjacent terminal unit can perform backup interrupt function even though a failure happens in a specific terminal unit forming the closed loop. | 2011-09-15 |
20110222396 | COMMUNICATION APPARATUS, SYSTEM, AND METHOD - A communication apparatus used as a first communication apparatus in a communication system having a ring network, the communication apparatus including: a storage unit configured to store information indicating a correspondence between a state of a path provided on the ring network, a state of a first link established between the first and third communication apparatuses, a state of a second link established between the second and third communication apparatuses, and a direction of forwarding the data; and a control unit configured to monitor links that are included in the ring network, and presence or absence of a failure occurring in each of the first and second links, and determine a direction of forwarding data to which path identification information corresponding to the third communication apparatus is added based on a result of the monitoring and the information stored in the storage unit. | 2011-09-15 |
20110222397 | PACKET BUFFERING BASED AT LEAST IN PART UPON PACKET RECEIPT TIME INTERVAL WEIGHTED MOVING AVERAGE - An embodiment may include circuitry to be comprised in a node. The node may be communicatively coupled to a network and may include a host processor to execute at least one communication protocol-related process. The circuitry may determine, at least in part, whether to buffer, at least in part, at least one packet received from the network based at least in part upon whether a weighted moving average exceeds a first threshold and is less than a second threshold. The average may be determined based at least in part upon one or more time intervals between one or more packet receptions from the network. Many alternatives, variations, and modifications are possible. | 2011-09-15 |
20110222398 | PROTOCOL WITH IMPROVED SPATIAL REUSE - According to an embodiment, a method, apparatus, and computer readable medium can provide an efficient mechanism to improve data rates of nodes suffering high interference without sacrificing performance of nodes that do not need interference-free channels to communicate. A node can receive two or more RTS packets and identify the RTS packet corresponding to its own cell, as well as RTS packets belonging to interferers. Based on the interference level estimated from the RTS packets, the node can decide if the channel needs to be interference-free for the intended transmission or if the current level of interference is acceptable. According to the embodiment, there can be two or more different types of CTS packets. A node can decide which type of CTS packet to transmit based on the information, signal level, interference level, or a combination therein, of at least two RTS channels, and based on measurements performed on these RTS channels, or other channels. | 2011-09-15 |
20110222399 | QUALITY OF SERVICE MANAGEMENT METHOD, DEVICE AND SYSTEM (Amended) - A quality of service QoS management method, apparatus and system are disclosed. The method includes: receiving Qos information requested by a core network device, wherein the Qos information is assigned to a current originated session according to a Qos negotiation result during a user equipment UE session origination phase; according to the requested Qos information assigned to the current originated session, Qos information occupied by a current serving session of an access point AP accessed by the UE, and Qos associated information of the AP, determining and recording the Qos information occupied by the current originated session; and the AP establishing a wireless bearer with the UE according to the QoS information occupied by the current originated session. | 2011-09-15 |
20110222400 | VIDEO PACKET MULTIPLEXER WITH INTELLIGENT PACKET DISCARD - A IP video delivery system ( | 2011-09-15 |
20110222401 | Method and Apparatus for Selecting Frequency Layer for Connected Mode UE in an MBMS Mobile Communication System - A method and apparatus for selecting the PL of an interested MBMS service for a UE in an MBMS mobile communication system are provided. A connected mode UE receives FLC applicability information for an interested MBMS service and keeps a current frequency or reselects to the PL of the MBMS service according to the FLC applicability information. Even if the FLC applicability information restricts FLC from the connected mode UE, the connected mode UE can reselect to the PL of the MBMS service according to its priority level. | 2011-09-15 |
20110222402 | ETHERNET EXTENSION FOR THE DATA CENTER - The present invention provides methods and devices for implementing a Low Latency Ethernet (“LLE”) solution, also referred to herein as a Data Center Ethernet (“DCE”) solution, which simplifies the connectivity of data centers and provides a high bandwidth, low latency network for carrying Ethernet and storage traffic. Some aspects of the invention involve transforming FC frames into a format suitable for transport on an Ethernet. Some preferred implementations of the invention implement multiple virtual lanes (“VLs”) in a single physical connection of a data center or similar network. Some VLs are “drop” VLs, with Ethernet-like behavior, and others are “no-drop” lanes with FC-like behavior. Some preferred implementations of the invention provide guaranteed bandwidth based on credits and VL. Active buffer management allows for both high reliability and low latency while using small frame buffers. Preferably, the rules for active buffer management are different for drop and no drop VLs. | 2011-09-15 |
20110222403 | METHOD FOR REPORTING QOS CONTROL-RELATED INFORMATION IN NETWORK AND NETWORK ENTITY THEREFOR - A method for reporting Quality of Service (QoS) control-related information in a network is provided, in which an intermediate network entity located within an end-to-end path generates the QoS control-related information by measuring a channel state, and reports the QoS control-related information to another network entity controlling the QoS. | 2011-09-15 |
20110222404 | HTTP OPTIMIZATION, MULTI-HOMING, MOBILITY AND PRIORITY - Combining parallel Hypertext Transfer Protocol (HTTP) connections and pipelining overcomes an impact of increasing Round Trip Time (RTT) by varying in real time the number of parallel connections and pipelined requests such that the number of outstanding requests is minimal and the link remains fully utilized. Optimal construction and scheduling of requests and connections in an HTTP stack improves page load time and also provides for greater responsiveness to changes in object priorities. Multi-homing and mobility at the application layer for HTTP are addressed. Multi-homing provides for simultaneous use of multiple interfaces, for example WWAN and WLAN interfaces which improves download time, especially in the case that the available bandwidth the interfaces is of the same order of magnitude. Mobility provides for switching connections as the device moves. In combination they provide for smoother mobility. Mobility can be provided this way without server or network support. | 2011-09-15 |
20110222405 | SYSTEM AND METHOD FOR DETERMINING A STATE OF A NETWORK SERVICE - A system and method for determining a state of a network service. Frames per second at an interface are measured to determine congestion. An effective throughput at the interface is measured to determine the congestion. An average packet size for a number of frames communicated through the interface is determined. The state for the network service is determined in response to the congestion and the average packet size. The state indicates whether the SLA is violated. A throughput rate communicated through the interface is adjusted in response to the state. | 2011-09-15 |
20110222406 | Method And Device For Enabling Indication Of Congestion In A Telecommunications Network - The invention relates to a first communication device arranged to provide congestion indications to a second communication device. The first communication device comprises a control unit arranged to determine to apply an indicating congestion mechanism on a first radio bearer to the second communication device based on a quality of service setting of the first radio bearer. The control unit is further arranged to set a congestion threshold value and a first drop threshold value of a packet buffer associated to the first determined radio bearer. The congestion threshold value indicates that when buffered packets in the packet buffer exceeds the set congestion threshold value the control unit is arranged further to transmit over a transmitting arrangement at least one congestion indication to the second communication device. The first drop threshold value indicates a level of the packet buffer that when buffered packets exceeds the first drop threshold value the control unit is arranged to drop at least one packet. | 2011-09-15 |
20110222407 | Simulation of Multiple Nodes in an Internetwork - A method is provided for simulation of multiple network nodes in an internetwork. A range of a plurality of network addresses are assigned to a simulation node. The simulation node monitors network communications to listen for packets. Upon receipt of a packet having a destination address within the assigned range, a command is forwarded to an end-use application, such as firmware. The end-use application processes the command and returns a result. A response packet having the result is transmitted to the back office server with the destination address of the received packet as the source of the response packet. | 2011-09-15 |