37th week of 2012 patent applcation highlights part 30 |
Patent application number | Title | Published |
20120230052 | ELECTRONIC EQUIPMENT PROVIDED WITH DISPLAY PORTION - An LCD indicator unit contains an LCD indicator with a display portion that includes set temperature and current temperature display portions, a diffusion sheet disposed on the rear surface side of the LCD indicator, a reflective frame body disposed on the rear surface side of the diffusion sheet, a light guide plate disposed on the rear surface side of the reflective frame body such that an outer peripheral portion thereof is covered with the reflective frame body, and an LCD indicator control substrate disposed on the rear surface side of the light guide plate, with LEDs serving as light sources for the LCD indicator mounted on a right-side outer peripheral portion on the front surface side of the LCD indicator control substrate. Light emitted from the LEDs is caused to enter a side wall surface portion of the light guide plate to irradiate the display portion of the LCD indicator. | 2012-09-13 |
20120230053 | LARGE AREA LIGHT PANEL AND SCREEN - Embodiments of a panel lighting apparatus and methods of its manufacture are described. In one embodiment, the apparatus can include a light source, an at least partially transparent panel comprising a planar front surface and a planar back surface, the panel disposed in conjunction with the light source such that light from the light source is input into at least one edge of the panel and guided therein, and a plurality of light extraction dots disposed on the planar back surface, the plurality of light extraction dots configured to reflect light incident on the planar back surface and extract light from the light source propagating in the panel through the planar front surface. | 2012-09-13 |
20120230054 | LARGE AREA LIGHT PANEL AND SCREEN - Embodiments of a panel lighting apparatus and methods of its manufacture are described. In one embodiment, the apparatus can include a light source, an at least partially transparent panel comprising a planar front surface and a planar back surface, the panel disposed in conjunction with the light source such that light from the light source is input into at least one edge of the panel and guided therein, and a plurality of light extraction dots disposed on the planar back surface, the plurality of light extraction dots configured to reflect light incident on the planar back surface and extract light from the light source propagating in the panel through the planar front surface. | 2012-09-13 |
20120230055 | FRONT LIGHT ILLUMINATION DEVICE AND REFLECTIVE DISPLAY DEVICE EMPLOYING THE SAME - A display device includes a display layer and a light guide plate (LGP) arranged on the display layer. The LGP includes a first surface facing away from the display layer, an opposite second surface, and a lateral surface between the first and second surfaces, the lateral surface having a light incident portion. A light source and a scanning mirror are arranged on the lateral surface of the LGP. The light source configured to emit a light beam toward the scanning mirror, the scanning mirror being reciprocally rotatable about a rotating axis at a given frequency, the scanning mirror configured to reflect and direct the light beam from the light source to enter into the LGP through the light incident portion. | 2012-09-13 |
20120230056 | LIGHT SOURCE MODULE AND ELECTRONIC DEVICE INCLUDING SAME - A light source module of the present invention includes: a plurality of light guide bodies ( | 2012-09-13 |
20120230057 | LED READING LIGHT - A drop-in assembly which fits in the socket of an existing reading light. The assembly comprises a truncated cone of plastic or other translucent material which transmits light generated by an LED light source. The assembly has a central core of air surrounded by the plastic material and at a wide end of the assembly and positioned over a central core is a disk of diffusing material. At a narrow end of the assembly is a metal structure which fits into the existing socket structure and functions as both an electrical contact and a heat transfer element which promotes dissipation of heat generated by the LED light source | 2012-09-13 |
20120230058 | NON-CONTACT POWER TRANSMISSION APPARATUS - A non-contact power transmission apparatus includes a high-frequency converting section, which converts input voltage to high-frequency voltage and outputs it, a primary coil, which receives high-frequency voltage from the high-frequency converting section, and a secondary coil, which receives electric power from the primary coil. The non-contact power transmission apparatus further includes a load to which the electric power received by the secondary coil is supplied, a rectifier located between the secondary coil and the load, and an output adjusting section, which supplies, as pulses, output voltage to the high-frequency converting section. The output adjusting section is configured to increase or reduce output to the load by adjusting a duty cycle of the pulse output. | 2012-09-13 |
20120230059 | DEVICE FOR AVOIDING HARD SWITCHING IN RESONANT CONVERTER AND RELATED METHOD - A control device controls a switching circuit for a converter. The switching circuit comprises a half-bridge having a high-side transistor and a low-side transistor. The control device comprises a controller configured to control turning on and turning off said two transistors, so that a square-wave voltage is applied to the transformer primary. The controller is configured to start switching the half-bridge by turning on the low-side transistor. The control device comprises a first timer configure to initially turn on the low-side transistor for a duration given by a first time period useful for pre-charging a bootstrap capacitor couplable to the middle point of the half-bridge, and a second timer configured to keep the low-side transistor and the high-side transistor turned off for a second time period immediately following the first time period and having a longer duration than the first time period. | 2012-09-13 |
20120230060 | PFC CONVERTER - A PFC converter that reduces a superimposed voltage generated by an inrush current into a filter capacitor operates such that, when a commercial alternating-current power supply is connected to input terminals of a PFC converter, a rectified voltage is applied to a filter capacitor via a diode bridge and a charging current flows through the filter capacitor. At the same time, the rectified voltage is also applied to a series circuit including a diode and a capacitor and a charging current for the capacitor flows through the series circuit. Accordingly, a charging time constant becomes large and a superimposed voltage generated by the inductance component of a line or a line filter connected to the line and the charging current becomes low. | 2012-09-13 |
20120230061 | SELF-EXCITED SWITCHING POWER SUPPLY CIRCUIT - There is provided a self-excited switching power supply circuit which shifts to continuous oscillating operation immediately after the self-excited switching power supply circuit is connected to an AC power supply and started and which does not cause start-up failure while using a start-up resistor of a high resistance value to maintain standby power consumption at a low level. A bypass charging circuit connected in series to a start-up resistor is connected between a high-voltage side terminal of a DC input power supply and the gate of an oscillation field effect transistor. A charging current flowing in the start-up resistor, and additionally, a charging current to charge a start-up capacitor through the bypass charging circuit flow in a transitional period during which the voltage of the DC input power supply increases. | 2012-09-13 |
20120230062 | DC-DC CONVERTER - A DC-DC converter includes a series circuit including a primary transformer coil and a main switch element connected between a power input terminal and a ground terminal. A secondary transformer coil is connected to a rectifying/smoothing circuit including rectification-side and commutation-side synchronous rectifiers, a smoothing capacitor, and a choke coil. The output voltage from the rectifying/smoothing circuit is supplied to a load connected to a power output terminal. An input voltage detection circuit detects the voltage between the power input terminal and the ground terminal, and supplies a detection signal to a VIN terminal of a switching control circuit. The switching control circuit performs PWM control to maintain a constant output voltage output to the load, reduces the switching frequency when the input voltage input to the VIN terminal is low, and increases the switching frequency in accordance with an increase in the input voltage. | 2012-09-13 |
20120230063 | SELF-EXCITED SWITCHING POWER SUPPLY CIRCUIT - There is provided a self-excited switching power supply circuit. A cycle control capacitor is charged with a flyback voltage generated in a feedback winding of a transformer during OFF operation period in which an exciting current does not flow in a primary winding of the transformer. An OFF control capacitor the charging speed of which changes ON operation period is charged with the charging voltage of the cycle control capacitor during the ON operation period in which an exciting current flows in the primary winding. The charging voltage of the cycle control capacitor is changed with a periodic cycle Tc sufficiently longer than an oscillation cycle To to make the oscillation cycle To of continuous oscillating operation variable based on the periodic cycle Tc. As a result, the frequency of a harmonic is distributed. | 2012-09-13 |
20120230064 | SWITCHING CONTROLLER WITH VALLEY-LOCK SWITCHING AND LIMITED MAXIMUM FREQUENCY FOR QUASI-RESONANT POWER CONVERTERS - The present invention provides a controller for a power converter. The controller comprises a PWM circuit, a detection circuit, a signal generator, an oscillation circuit, a valley-lock circuit, a timing circuit and a burst circuit. The PWM circuit generates a switching signal coupled to switch a transformer of the power converter. A feedback signal is coupled to control and disable the switching signal. The detection circuit is coupled to the transformer via a resistor for generating a valley signal in response to a waveform obtained from the transformer. The signal generator is coupled to receive the feedback signal and the valley signal for generating an enabling signal. The oscillation circuit generates a maximum frequency signal. The maximum frequency signal associates with the enabling signal to generate a turning-on signal. The turning-on signal is coupled to enable the switching signal. A maximum frequency of the turning-on signal is limited. | 2012-09-13 |
20120230065 | Two-Peak Current Control for Flyback Voltage Converters - A system including a switch configured to supply power to a load. A first comparator is configured to compare a first current through the switch to a first threshold. A second comparator is configured to compare the first current through the switch to a second threshold. The second threshold is greater than the first threshold. A current control module is configured to turn off the switch (i) for a first duration in response to the first current through the switch being greater than or equal to the first threshold and (ii) for a second duration in response to the first current through the switch being greater than or equal to the second threshold. The current control module is configured to adjust the second duration based on a difference between an estimated current through the load and a desired current through the load. | 2012-09-13 |
20120230066 | PHOTOVOLTAIC POWERED SYSTEM - A photovoltaic powered system and an alternating current (AC) module thereof are disclosed. The photovoltaic powered system provides a direct current (DC) power through a photovoltaic module and converts the DC power into an AC power, which is grid-connected to an AC utility power. The AC module of the photovoltaic powered system produces a continuous quasi-sinusoidal current and the quasi-sinusoidal current is converted into a sinusoidal current. The high-frequency harmonic components of the sinusoidal current are filtered to produce a sinusoidal output current in phase with the AC utility power, thus realizing the maximum power point tracking (MPPT) of the photovoltaic module and feeding unity-power-factor power into the AC utility power. | 2012-09-13 |
20120230067 | POWER CONVERTER - This current converter is formed to short-circuit input-side terminals of a plurality of power conversion portions, to parallelly connect output-side terminals of the plurality of power conversion portions with each other and to couple inductors provided on the plurality of power conversion portions respectively with each other, to be capable of performing an operation of moving currents between windings of the coupled inductors on the basis of ON-/OFF-states of pluralities of one-way switches. | 2012-09-13 |
20120230068 | CONVERTER WITH POWER FACTOR CORRECTION - A converter for converting an input-side alternating current into an output-side DC current, with a power factor correction being provided, wherein the converter comprises a transformer having at least two serially arranged primary windings, a first switch is used to switch a storage capacitor unit in series with a first primary winding to the alternating current in a clocked manner via rectification elements and a second primary winding is switchable to the storage capacitor unit in a clocked manner by a second switch. | 2012-09-13 |
20120230069 | STARTUP CONTROL CIRCUIT WITH ACCELERATION STARTUP FUNCTION AND METHOD FOR OPERATING THE SAME - A startup control circuit with an acceleration startup function and a method for operating the same are disclosed. The startup control circuit is applied to a power supply. A power switch, which is coupled to a primary-side winding of a transformer, is switched to control the transformer, thus adjusting the output voltage of the power supply. The startup control circuit mainly includes a capacitor and a startup control apparatus. The startup control apparatus includes an enable switch unit and a power control unit. By turning on and turning off the enable switch unit of the startup control apparatus, the acceleration startup control and the stable output power of the power supply can be implemented. | 2012-09-13 |
20120230070 | Method And System For Controlling A Power Converter System Connected To A DC-Bus Capacitor - A method and system for controlling a power converter system with a direct current (DC)-bus capacitor connected to at least a first converter and a second converter. The first converter is with associated first current and the second converter is with associated second current. Switching states of the first and second converters are determined. The switching states of the second converter are sequenced relative to the first converter to reduce a difference of sums of the associated first and second currents between adjacent time intervals. | 2012-09-13 |
20120230071 | POWER SUPPLY CIRCUIT SYSTEM - A power supply circuit system includes a ring oscillator provided with a variable resistance circuit, a charge pump circuit outputting a boosted voltage in response to an oscillation output signal from the ring oscillator, a voltage regulator circuit adjusting the boosted voltage from the charge pump circuit, a first current comparator circuit comparing a first current flowing through the voltage regulator circuit with a first reference current, a second current comparator circuit comparing the first current with a second reference current, and a control circuit outputting control signals to control a resistance value of the variable resistance circuit in accordance with a first comparison signal from the first current comparator circuit and a second comparison signal from the second current comparator circuit. | 2012-09-13 |
20120230072 | CIRCUIT ASSEMBLY HAVING A CONVERTER PART COMPRISING A CENTRAL CONTROL UNIT - Circuit assembly ( | 2012-09-13 |
20120230073 | TWO-WIRE DIMMER SWITCH FOR LOW-POWER LOADS - A two-wire load control device (such as, a dimmer switch) for controlling the amount of power delivered from an AC power source to an electrical load (such as, a high-efficiency lighting load) includes a thyristor coupled between the source and the load, a gate coupling circuit coupled between a first main load terminal and the gate of the thyristor, and a control circuit coupled to a control input of the gate coupling circuit. The control circuit generates a drive voltage for causing the gate coupling circuit to conduct a gate current to thus render the thyristor conductive at a firing time during a half cycle of the AC power source, and to allow the gate coupling circuit to conduct the gate current at any time from the firing time through approximately the remainder of the half cycle, where the gate coupling circuit conducts approximately no net average current to render and maintain the thyristor conductive. | 2012-09-13 |
20120230074 | ELECTRICAL ISOLATORS - Disclosed is an electrical isolator circuit comprising an input stage comprising first and second inputs, the input stage being configured to receive an input voltage signal; an output stage comprising first and second outputs electrically connected across a load capacitor; and a DC isolator comprising a first capacitor between said first input and said first output and second capacitor between said second input and said second output. The first and second plates of each of the first, second and load capacitors are defined by conductive layers of a printed circuit board and the dielectric of each of the first, second and load capacitors are defined by a non-conducting part of the printed circuit board. | 2012-09-13 |
20120230075 | POWER CONVERSION APPARATUS AND POWER CONVERSION METHOD THEREOF - An apparatus/method is provided. The power conversion apparatus includes: a rectifying unit including a silicon-controlled rectifier thyristor (SCR) for rectifying single-phase power externally inputted; a power factor correcting unit configured to correct a power factor of the power rectified by the rectifying unit; and a control signal generating unit configured to detect a zero-crossing point based on the single-phase power inputted and generate a pulse single of which a width increases as time elapses based on the detected zero-crossing point. The rectifying unit rectifies the single-phase power by using the pulse signal inputted to a gate terminal of the SCR. | 2012-09-13 |
20120230076 | VOLTAGE BALANCING - This invention generally relates to voltage balancing among series-connected power switching devices comprising one or more insulated gate bipolar transistor (IGBT), and more particularly to a method controlling sharing of voltage among series-connected power switching devices, wherein at least one said device is an insulated gate bipolar transistor (IGBT), the method comprising: controlling the IGBT dependent on a reference signal and collector or emitter voltage of the IGBT such that during an off period of said IGBT said reference signal limits an absolute value of collector-emitter voltage of said IGBT to be within a range; and control to temporarily change during said limiting said reference signal from an initial value to a temporary clamp value to reduce said range, said change when each of said devices is in a substantially non-conducting state. | 2012-09-13 |
20120230077 | Automated Mechanical Disconnection of an Electrical Converter Module in a Frequency Converter Arrangement - An arrangement is described for receiving an electrical converter module for converting a first frequency of an electrical input signal into a second frequency of an electrical output signal. A rack includes input terminals for receiving the electrical input signal and output terminals for providing the electrical output signal. A slot receives the converter module in a first and second positions where in first position the converter module is electrically connected both to the input and output terminals and in the second position the converter module is electrically disconnected both from the input and output terminals. An actuator, which is mounted to the rack and which, in response to a disconnect trigger signal, is adapted to move the electrical converter module from the first position to the second position. A frequency converter system equipped with such an arrangement and a method for disconnecting a converter module are provided | 2012-09-13 |
20120230078 | STORAGE CIRCUIT - A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a data signal supplied to the volatile storage portion can be held even after supply of power supply voltage is stopped. A wiring which supplies a power supply voltage and is connected to a protective circuit provided for a wiring for supplying the clock signal is provided separately from a wiring which supplies a power supply voltage and which is connected to the storage circuit. The timing of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the protective circuit is different from that of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the storage circuit. | 2012-09-13 |
20120230079 | ACTUATOR AND STORAGE DEVICE - In one embodiment, an actuator has a movable member, a frame, and first and second electrodes. Each of the first electrodes has a pair of first and second planes perpendicular to a third direction which is orthogonal to the first and the second directions approximately. The second electrodes are provided alternately with the first electrode respectively and with a distance from the first electrode. Each of the second electrodes has a pair of third and fourth planes perpendicular to the third direction. The first and the second planes have a deviation in the third direction with respect to the third and the fourth planes, respectively. The amount of the deviation is larger than a maximum value of the amount of displacement of the movable member in the third direction. The amount of displacement is produced by gravity when a component of the gravity in the third direction is maximum. | 2012-09-13 |
20120230080 | Variable Resistance Device, Semiconductor Device Including The Variable Resistance Device, And Method Of Operating The Semiconductor Device - According to an example embodiment, a method of operating a semiconductor device includes applying a first voltage to the variable resistance device so as to change a resistance value of the variable resistance device from a first resistance value to a second resistance value that is different from the first resistance value, sensing first current flowing through the variable resistance device to which the first voltage is applied, determining a second voltage used to change the resistance value of the variable resistance device from the second resistance value to the first resistance value based on a distribution of the sensed first current, and applying the determined second voltage to the variable resistance device. | 2012-09-13 |
20120230081 | CELL-STATE MEASUREMENT IN RESISTIVE MEMORY - Apparatus and method for measuring the state of a resistive memory cell. A bias voltage controller applies a bias voltage to the cell and controls the level of the bias voltage. A feedback signal generator senses cell current due to the bias voltage and generates a feedback signal (S | 2012-09-13 |
20120230082 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF RESETTING THE SAME - A nonvolatile semiconductor memory device includes: a plurality of memory cell arrays stacked on a semiconductor substrate and including a plurality of first wires, a plurality of second wires and memory cells disposed at intersections of the first wires and the second wires and having a rectifier element and a variable resistive element are connected in series; and a control circuit configured to selectively drive the first wires and the second wires. The control circuit executes a resetting operation to change a state of the variable resistive element from a low resistance state to a high resistance state. At a time of executing the resetting operation, the control circuit increases a pulse voltage to be applied to the variable resistive element to a first voltage, and then decreases the pulse voltage to a second voltage lower than the first voltage and higher than the ground voltage. | 2012-09-13 |
20120230083 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprising: a memory cell array in which memory cells each containing a variable resistive element and a rectifier element connected in series are arranged at intersections of a plurality of first wirings and a plurality of second wirings; and a control circuit for selectively driving said first wirings and said second wirings; wherein said control circuit applies a first voltage to said selected first wiring, and changes said first voltage based on the position of said selected memory cell within said memory cell array to apply a second voltage to said selected second wiring, so that a predetermined potential difference is applied to a selected memory cell arranged at the intersection between said selected first wiring and said selected second wiring. | 2012-09-13 |
20120230084 | APPARATUS FOR VARIABLE RESISTIVE MEMORY PUNCHTHROUGH ACCESS METHOD - Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode. | 2012-09-13 |
20120230085 | FORMING METHOD OF PERFORMING FORMING ON VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE - In forming, an automatic forming circuit ( | 2012-09-13 |
20120230086 | STATIC RANDOM ACCESS MEMORY CELL AND METHOD OF OPERATING THE SAME - A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit. | 2012-09-13 |
20120230087 | SRAM CIRCUITS FOR CIRCUIT IDENTIFICATION USING A DIGITAL FINGERPRINT - Circuitry that includes static random access memory (SRAM) access circuitry and a group of SRAM memory cells is disclosed. A digital fingerprint of the group of SRAM memory cells is determined by using the SRAM access circuitry to force at least a portion of the group of SRAM memory cells into a metastable state and then releasing the portion of the SRAM memory cells. Each SRAM memory cell that was released then selects one of two stable states and the SRAM access circuitry provides a selection profile based on the selections. The digital fingerprint is based on the selection profile. | 2012-09-13 |
20120230088 | 8T SRAM Cell With One Word Line - An integrated circuit with SRAM cells containing dual passgate transistors and a read buffer, all connected to one word line is disclosed. The read buffer and one passgate transistor may be variously configured to a separate read data line and write data line, or a combined data line, in different embodiments. The read buffer in addressed SRAM cells may be biased during read operations. The read buffer in half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line. The read buffer in addressed and half-addressed SRAM cells may be biased or floated, depending on the configuration of the read data line and the write data line. | 2012-09-13 |
20120230089 | MAGNETORESISTANCE ELEMENT AND NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE USING SAME MAGNETORESISTANCE ELEMENT - A magnetoresistance element is disclosed. The magnetoresistance element includes a magnetic tunnel junction portion configured by sequentially stacking a perpendicularly magnetized first magnetic body, an insulation layer, and a perpendicularly magnetized second magnetic body. The second magnetic body has a configuration wherein a ferromagnetic layer and a rare earth-transition metal alloy layer are stacked sequentially from the insulation layer side interface. A heat assist layer that heats the second magnetic body with a heat generated based on a current flowing through the magnetic tunnel junction portion is further provided. | 2012-09-13 |
20120230090 | SEMICONDUCTOR MEMORY - A semiconductor memory has a first switch circuit and a second switch circuit. The semiconductor memory has a row decoder that controls a voltage of a word line. The semiconductor memory has a first writing circuit including a first signal terminal connected to one end of the first switch circuit to input and output a writing current. The semiconductor memory has a second writing circuit including a second signal terminal connected to a one end of the second switch circuit to input and output the writing current. The semiconductor memory has a select transistor including a control terminal connected to the word line. The semiconductor memory has a resistance change element that is connected in series with the select transistor between the first bit line and the second bit line and varies in resistance value depending on an applied current. | 2012-09-13 |
20120230091 | MAGNETIC MEMORY - According to one embodiment, a magnetic memory includes at least one memory cell including a magnetoresistive element, and first and second electrodes. The element includes a first magnetic layer, a tunnel barrier layer, a second magnetic layer, and a third magnetic layer provided on the second magnetic layer and having a magnetization antiparallel to the magnetization direction of the second magnetic layer. A diameter of an upper surface of the first magnetic layer is smaller than that of a lower surface of the tunnel barrier layer. A diameter of a lower surface of the second magnetic layer is not more than that of an upper surface of the tunnel barrier layer. | 2012-09-13 |
20120230092 | THERMALLY ASSISTED MULTI-BIT MRAM - Methods of writing to a multi-bit MRAM memory unit are described. The method includes to self-detected writing to a multi-bit (i.e., multilevel) thermally assisted MRAM. The self-detected writing increases a reading margin between data state levels and decreases reading margin variability due to cell resistance variation. | 2012-09-13 |
20120230093 | TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT - A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor. | 2012-09-13 |
20120230094 | BIT LINE CHARGE ACCUMULATION SENSING FOR RESISTIVE CHANGING MEMORY - A memory array includes a plurality of magneto-resistive changing memory cells. Each resistive changing memory cell is electrically between a source line and a bit line and a transistor electrically between the resistive changing memory cell and the bit line. The transistor has a gate electrically between a source region and a drain region and the source region being electrically between the r magneto-resistive changing memory cell and the gate. A word line is electrically coupled to the gate. A bit line charge accumulation sensing for magneto-resistive changing memory is also disclosed. | 2012-09-13 |
20120230095 | NON-VOLATILE MAGNETIC MEMORY ELEMENT WITH GRADED LAYER - A non-volatile magnetic memory element includes a number of layers one of which is a free layer which is graded. The graded free layer may include various elements with each element having a different anisotropy or it may include nonmagnetic compounds and magnetic regions with the non-magnetic compounds forming graded contents forming a unique shape such as cone shaped, diamond shaped or other shapes and whose thickness is based on the reactivity of the magnetic compound. | 2012-09-13 |
20120230096 | DEVICES AND METHODS TO PROGRAM A MEMORY CELL - Subject matter disclosed herein relates to memory devices and, more particularly, to programming a memory cell. | 2012-09-13 |
20120230097 | DETERMINING CELL-STATE IN PHASE-CHANGE MEMORY - A method, an apparatus, and a device for determining the state of a phase-change memory cell. The method includes the steps of: biasing a cell with a time-varying read voltage (V | 2012-09-13 |
20120230098 | PROGRAMMING OF PHASE-CHANGE MEMORY CELLS - A method and apparatus for programming a phase-change memory cell. A bias voltage signal (V | 2012-09-13 |
20120230099 | PHASE CHANGE MEMORY - A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region. | 2012-09-13 |
20120230100 | PROGRAMMABLE PHASE-CHANGE MEMORY AND METHOD THEREFOR - A non-volatile memory is disclosed. A contiguous layer of phase change material is provided. Proximate the contiguous layer of phase change material is provided a first pair of contacts for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a first region. Also adjacent the contiguous layer is provided a second pair of contacts disposed for providing an electrical current therebetween, the electrical current for passing through the contiguous layer of phase change material for inducing heating thereof within a second region thereof, the second region different from the first region. | 2012-09-13 |
20120230101 | METHOD AND APPARATUS FOR WRITING TO A MAGNETIC TUNNEL JUNCTION (MTJ) BY APPLYING INCREMENTALLY INCREASING VOLTAGE LEVEL - A method of writing to magnetic tunnel junctions (MTJs) of a magnetic memory array includes storing in-coming data in a cache register, reading the present logic state of a first one of a set of at least two MTJs, the set of at least two MTJs including the first MTJ and a second MTJ. The in-coming data is to be written into the second MTJ. Further steps are storing the read logic state into a data register, swapping the contents of the data register and the cache register so that the cache register stores the read logic state and the data register stores the in-coming data, applying a first predetermined voltage level to the set of MTJs thereby causing the first MTJ to be over-written, applying a second predetermined voltage level to the set of MTJs, and storing the in-coming data into the second MTJ. | 2012-09-13 |
20120230102 | FLASH MEMORY STORAGE APPARATUS - A flash memory storage apparatus is provided. The flash memory storage apparatus includes a substrate, a control and storage circuit unit, a ground lead, at least a signal lead, and a power lead. The control and storage circuit unit, the power lead, the signal lead, and the ground lead are disposed on the substrate, in which the power lead, the signal lead, and the ground lead respectively electrically connect to the control and storage circuit unit. Moreover, the flash memory storage apparatus further includes an extra ground lead electrically connected to the ground lead or a protrusion on the substrate, such that the ground lead first electrically connects to a host when the flash memory storage apparatus is plugged into the host. | 2012-09-13 |
20120230103 | Nonvolatile Memory Device And Operating Method Thereof - According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases. | 2012-09-13 |
20120230104 | NON-VOLATILE MEMORY DEVICE AND READ METHOD THEREOF - Disclosed is a non-volatile memory device which includes a memory cell array having memory cells arranged in rows and columns, a page buffer circuit configured to read data from the memory cell array, and a control logic and input/output interface block including a normal read scheduler controlling a normal read operation and a data recover read scheduler controlling a data recover read operation and configured to control the page buffer circuit at a read request. One of the normal read scheduler and the data recover read scheduler is selected according to selection information provided from an external device. | 2012-09-13 |
20120230105 | Semiconductor Integrated Circuit - In one embodiment, a semiconductor integrated circuit has memory cells. Each of the memory cells has non-volatile memories and switching elements. The non-volatile memories and switching elements are connected in series between a first power source and a second power source. Output wirings of at least two of the memory cells are connected to each other. Input wirings are connected with control gates of the switching elements included in each of the at least two memory cells. A plurality of the switching elements included in one of the at least two of the memory cells is turned off, when an input signal or an inverted signal is inputted. Further, another plurality of the switching elements included in another one of the at least two of memory cells other than the one of the memory cells is turned on, when the input signal or the inverted signal is inputted. | 2012-09-13 |
20120230106 | SEMICONDUCTOR MEMORY DEVICES, READING PROGRAM AND METHOD FOR MEMORY DEVICES - A semiconductor memory device, having a memory array which has two memory banks which can be accessed simultaneously is provided. A word line selection circuit selects the word line according to the row address information, and a controller controls the word line selection circuit according to the received instruction. The controller performs the first read operation of the word line selection circuit in response to a first read command, and performs the second read operation of the word line selection circuit in response to a second read command. The first read operation selects the n-th word line of one of the memory banks and selects the (n+1)-th or (n−1)-th word line of the other memory bank, and the second read operation selects the n-th word line of one of the memory banks and selects the n-th word line of the other memory bank. | 2012-09-13 |
20120230107 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY BLOCK CONFIGURATION - A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad. | 2012-09-13 |
20120230108 | MEMORY DEVICE WITH MULTIPLE PLANES - Disclosed herein is a device that comprises at least one selection/non-selection voltage receiving line, at least one word line operatively coupled to the selection/non-selection voltage receiving line, and a plurality of memory cells coupled to the word line; a selection voltage source line; and a selection voltage supply circuit comprising a first switch circuit and a first driver circuit driving the first switch circuit to be turned ON or OFF, the first switch circuit including a first node coupled to the selection voltage source line, a second node coupled to the selection/non-selection voltage receiving line of the first memory plane and a third node coupled to the selection/non-selection voltage receiving line of the second memory plane, and the first driver circuit being provided in common to the first and second memory planes. | 2012-09-13 |
20120230109 | Method of Setting Trim Codes for a Flash Memory and Related Device - A flash memory device with auto-trimming functionality includes a memory cell array comprising first memory cells and a fuse sector, a read circuit for reading a memory state of the first memory cells, an offset circuit for outputting offset current values, and an auto-trimming circuit. The auto-trimming circuit has a register for storing a current characteristic, a current control module for modifying input current applied to a first memory cell under test at a first address according to the memory state, and updating the current characteristic to the modified input current, an address counter for starting application of the modified input current to a second memory cell at a second address for test when reading the first memory cell passes, and a programming circuit for programming the fuse sector according to the current characteristic and the offset current values. | 2012-09-13 |
20120230110 | METHOD AND APPARATUS FOR ADDRESSING MEMORY ARRAYS - The present description relates to non-volatile memory arrays and the operation thereof In at least one embodiment, the non-volatile memory array may include a plurality of memory modules coupled in a daisy chain with enable in/out signals, and a single chip enable signal coupled in parallel to each memory module. With such a configuration, all memory units within each of the memory modules of each memory array may be addressed with the single chip enable | 2012-09-13 |
20120230111 | LEVEL SHIFTING CIRCUIT - A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the second voltage level is higher than the first voltage level. Level shifting circuit embodiments having two or more parallel coupled depletion mode transistors coupled to a high voltage source and further coupled to the output by an enhancement mode transistor, and an additional transistor coupled between a first signal and the output of the level shifting circuit where the first signal has the same logic level of the input are disclosed. | 2012-09-13 |
20120230112 | NONVOLATILE MEMORY DEVICE, DRIVING METHOD THEREOF, AND MEMORY SYSTEM HAVING THE SAME - A nonvolatile memory device (NVM), memory system and apparatus include control logic configured to perform a method of applying negative voltage on a selected wordline of the NVM. During a first time a first high voltage level is applied to the channel of a transistor of a address decoder and a ground voltage is applied to the well of the transistor. And, during a second time a second high voltage level is applied to the channel of the transistor, and within the second time interval a first negative voltage is applied to the well of the transistor. The first high voltage level is higher than the second high voltage level, and a voltage applied on the selected wordline is negative within the second time interval. | 2012-09-13 |
20120230113 | RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES - Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal. | 2012-09-13 |
20120230114 | SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device to reduce variation in the threshold voltages of memory cells after writing, reduce the operation voltage, or increase the storage capacity. The semiconductor device includes memory cells each including a transistor including an oxide semiconductor, a driver circuit that drives the memory cells, a potential generating circuit that generates potentials supplied to the driver circuit, and a write completion detecting circuit that detects all at once whether rewriting of data into the memory cells is completed or not. The driver circuit includes a data buffer, a writing circuit that writes one potential of the potentials into each of the memory cells as data, a reading circuit that reads the data written into the memory cells, and a verifying circuit that verifies whether the read data agrees with the data held in the data buffer or not. | 2012-09-13 |
20120230115 | HIGH-SPEED VERIFIABLE SEMICONDUCTOR MEMORY DEVICE - A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing. | 2012-09-13 |
20120230116 | SENSE OPERATION IN A STACKED MEMORY ARRAY DEVICE - Methods for sensing and memory devices are disclosed. One such method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers). | 2012-09-13 |
20120230117 | NONVOLATILE SEMICONDCUTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes semiconductor regions provided on a substrate and electrically separated from each other, a memory cell block provided in each of the semiconductor regions and includes nonvolatile memory cells, word lines connected to control gates of memory transistors so as to commonly connect memory transistors in a same row, select gate lines connected to gates of select transistors so as to commonly connect select transistors in a same row, and a row decoder configured to apply a first negative voltage to a selected word line from which data is erased, and to apply a second positive voltage to a non-selected word lines from which data is not erased while an erasing voltage is applied to the semiconductor region upon erasing operation. | 2012-09-13 |
20120230118 | NON-VOLATILE MEMORY CELL HAVING A HEATING ELEMENT AND A SUBSTRATE-BASED CONTROL GATE - The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing. | 2012-09-13 |
20120230119 | WORD LINE DRIVER IN FLASH MEMORY - A memory device of the non-volatile type including a memory array having a plurality of memory cells organized as sectors, each sector having a main word line associated with a plurality of local word lines, each local word line coupled to the main word line by a respective local word line driver circuit, each of the local word line driver circuits consisting of a first MOS transistor coupled between the respective main word line and a respective local word line and a second MOS transistor coupled between the respective local word line and a first biasing terminal. | 2012-09-13 |
20120230120 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND ERASING METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device including a first bit line commonly coupling drain sides memory cells; a word line commonly coupling control gates of memory cell transistors; a column decoder coupled to a second bit line; a row decoder coupled to a word line; a first transistor having a source coupled to the first bit line and having a drain electrically coupled to the column decoder via the second bit line; and a first control unit for controlling potential of a gate of the first transistor, the memory cell transistor being formed over a first well, the first transistor being formed over a second well electrically isolated from the first well, a film thickness of a gate insulation film of the first transistor being smaller than that of a gate insulation film of a second transistor formed in the row decoder and coupled to the word line. | 2012-09-13 |
20120230121 | DATA BUS POWER-REDUCED SEMICONDUCTOR STORAGE APPARATUS - In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of the present invention comprises a DRF bus, a DR11F bus, a GDRF bus and a GDR11F bus. The DRF bus and DR11F bus, and the GDRF bus and GDR11F bus, are placed in parallel for the purpose of reducing the number of times toggle operations of a data bus are performed at the time of a data transmission. The DR11F bus is added to make the DRF11F bus perform a toggle operation only when the DRF buses on both sides are made to perform a toggle operation if the data transmission were performed in a conventional system. | 2012-09-13 |
20120230122 | Memory device and method of controlling a write operation within a memory device - A memory device and method are provided incorporating a technique for controlling a write operation within the memory device. The memory device has an array of memory cells, each memory cell supporting writing and simultaneous reading of that memory cell. Write circuitry is arranged, during a write operation, to provide write data to a number of addressed memory cells within the array, whilst word line select circuitry is responsive to the start of the write operation to assert a write word line signal that enables those addressed memory cells to store the write data. Comparing circuitry is arranged, during the write operation, to compare the write data with data currently stored in the addressed memory cells. On detecting that the write data matches the data currently stored in the addressed memory cells, the comparing circuitry asserts a control signal to the word line select circuitry to cause the word line select circuitry to de-assert the write word line signal. As a result, the pulse width of the asserted write word line signal is dependent on time taken by the addressed memory cells to store the write data, thereby leading to a significant reduction in the size of the pulse width when compared with known prior art techniques. | 2012-09-13 |
20120230123 | Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell. | 2012-09-13 |
20120230124 | LATCH SYSTEM APPLIED TO A PLURALITY OF BANKS OF A MEMORY CIRCUIT - A latch system applied to a plurality of banks of a memory circuit includes a front latch circuit and a plurality of rear latch circuit. The front latch circuit is used for receiving a datum and a front latch enabling signal, and generating and outputting an intermediate signal according to the datum and the front latch enabling signal. Each rear latch circuit of the plurality of rear latch circuits is coupled to an output terminal of the front latch circuit for receiving the intermediate signal, and generating and outputting a rear latch datum to a corresponding bank of the plurality of banks according to the intermediate signal and a corresponding rear latch enabling signal, where only one rear latch enabling signal is enabled at any time. | 2012-09-13 |
20120230125 | SEMICONDUCTOR MEMORY DEVICE AND METHODS THEREOF - According to example embodiments, a semiconductor memory device includes a memory cell array, a multi-purpose register, a data output circuit, and a mode register. The memory cell array is configured to store data. The multi-purpose register is configured to store a data pattern. The data output circuit is configured to output the stored data during a first output mode and output the stored data pattern during a second output mode. The mode register is configured to set the first or second output mode according to a logic level of a portion of a content of the mode register. | 2012-09-13 |
20120230126 | MEMORY VOLTAGE REGULATOR WITH LEAKAGE CURRENT VOLTAGE CONTROL - A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells. | 2012-09-13 |
20120230127 | Providing Row Redundancy to Solve Vertical Twin Bit Failures - A circuit includes a failure address register configured to store a first row address, a row address modifier coupled to the failure address register, wherein the row address modifier is configured to modify the first row address received from the failure address register to generate a second row address. A first comparator is configured to receive and compare the first row address and a third row address. A second comparator is configured to receive and compare the second row address and the third row address. The first and the second row addresses are failed row addresses in a memory. | 2012-09-13 |
20120230128 | Integrated Circuitry, Switches, and Methods of Selecting Memory Cells of a Memory Device - Some embodiments include switches that have a graphene structure connected to a pair of spaced-apart electrodes. The switches may further include first and second electrically conductive structures on opposing sides of the graphene structure from one another. The first structure may extend from one of the electrodes, and the second structure may extend from the other of the electrodes. Some embodiments include the above-described switches utilized as select devices in memory devices. Some embodiments include methods of selecting memory cells. | 2012-09-13 |
20120230129 | Method of altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device - A method is provided for altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device. The method comprises identifying a subset of the memory cells whose value of the chosen characteristic is within a predetermined end region of the distribution, and then performing a burn-in process during which one or more operating parameters of the memory device are set to induce aging of the memory cells. During the burn-in process, for each memory cell in the subset, the value stored in that memory cell is fixed to a selected value which exposes that memory cell to a stress condition. In contrast, for each memory cell not in the subset, the value stored in that memory cell is alternated during the burn-in process in order to alleviate exposure of that memory cell to the stress condition. Such an approach allows a tightening of the distribution of the chosen characteristic, thus improving the worst case memory cells. | 2012-09-13 |
20120230130 | Memory Cell System and Method - A memory cell system/method incorporating reduced transistor counts and/or improved design-for-manufacturability (DFM) is disclosed. The system/method incorporates cross-coupled feedthru ( | 2012-09-13 |
20120230131 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes cells, and a sense amplifier. Each of the cells is connected to a bit line. The sense amplifier reads out data. The sense amplifier includes a first transistor to third transistor, and a switch. The first transistor has one end of a current path, the other end, and a gate. The second transistor has one end, and the other end. The second transistor has one of a first and a second supply ability. The third transistor has one end, and the other end. The third transistor has one of a third and a fourth supply ability. The switch grounds the second and the third transistors. The sense amplifier turns off the first transistor after transferring the data to an outside, and supplies the second signal to the switch to set gates of the second transistor and third transistor to ground. | 2012-09-13 |
20120230132 | DATA PROCESSING DEVICE AND METHOD OF READING TRIMMING DATA - A data processing device including a nonvolatile memory comprising a plurality of memory regions in which a same trimming data is stored, and a trimming data read control circuit configured to read the trimming data from a random memory region. The trimming data read control circuit comprises a region selection signal generation circuit configured to generate a region selection signal that specifies a random memory region among the memory regions, and a read circuit configured to read the trimming data from the random one memory region in response to the region selection signal. The region selection signal generation circuit comprises a clock counter configured to count a clock signal until a reset signal is input, and a signal generation circuit configured to generate the region selection signal based on a count value of the clock counter. The reset signal is input to the clock counter at a random timing. | 2012-09-13 |
20120230133 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA WRITING METHOD - A nonvolatile semiconductor memory quickly and precisely accumulates a desired amount of charges corresponding to data-to-be-written in a charge accumulating part of a memory cell. When charges are injected into the charge accumulating part of the memory cell by applying a writing voltage corresponding to the data-to-be-written to the drain or source region of the memory cell, the writing voltage is reduced on the basis of an increase in the amount of charges accumulated in the charge accumulating part. | 2012-09-13 |
20120230134 | DRAM SENSE AMPLIFIER THAT SUPPORTS LOW MEMORY-CELL CAPACITANCE - The disclosed embodiments provide a sense amplifier for a dynamic random-access memory (DRAM). This sense amplifier includes a bit line to be coupled to a cell to be sensed in the DRAM, and a complement bit line which carries a complement of a signal on the bit line. The sense amplifier also includes a p-type field-effect transistor (PFET) pair comprising cross-coupled PFETs that selectively couple either the bit line or the complement bit line to a high bit-line voltage. The sense amplifier additionally includes an n-type field effect transistor (NFET) pair comprising cross-coupled NFETs that selectively couple either the bit line or the complement bit line to ground. This NFET pair is lightly doped to provide a low threshold-voltage mismatch between NFETs in the NFET pair. In one variation, the gate material for the NFETs is selected to have a work function that compensates for a negative threshold voltage in the NFETs which results from the light substrate doping. In another variation, the sense amplifier additionally includes a cross-coupled pair of latching NFETs. These latching NFETs are normally doped and are configured to latch the voltage on the bit line after the lightly doped NFETs finish sensing the voltage on the bit line. | 2012-09-13 |
20120230135 | DELAY LOCKED LOOP CIRCUIT AND METHOD - Delay locked loop circuits and methods are disclosed. In the embodiments, a delay locked loop may include a phase detector to detect a phase difference between a clock signal and a reference clock signal, and a charge pump that receives the detected phase difference. A low pass filter may filter an output from the charge pump. The delay locked loop may further include a delay line having a plurality of delay elements, the plurality of delay elements including a first selectable group and a second selectable group that is larger than the first selectable group. A first clock signal from the first group of delay elements may be provided to the phase detector to first synchronize the delay locked loop, and following the synchronization, a second clock signal from the second group may be employed to synchronize the delay locked loop. | 2012-09-13 |
20120230136 | SELECTABLE REPAIR PASS MASKING - The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method comprises performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the embedded memory module and, in response to identifying the non-operational memory elements, generating a plurality of corresponding repair solutions. The method further comprises storing the plurality of corresponding repair solutions in a non-volatile storage element and determining from a mask a subset of the plurality of repair solutions that should be restored. | 2012-09-13 |
20120230137 | MEMORY DEVICE AND TEST METHOD FOR THE SAME - A memory device includes a first bank, a second bank, a plurality of interface pads, and a data output unit configured to output compressed data of the first bank through at least one interface pad among the plurality of interface pads and subsequently output compressed data of the second bank through the one interface pad. | 2012-09-13 |
20120230138 | MEMORY ELEMENT AND SIGNAL PROCESSING CIRCUIT - A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor. | 2012-09-13 |
20120230139 | SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE SCHEME - A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell. | 2012-09-13 |
20120230140 | MAINTENANCE OF AMPLIFIED SIGNALS USING HIGH-VOLTAGE-THRESHOLD TRANSISTORS - Systems, apparatus, memory devices, sense amplifiers and methods are provided, such as a system that includes an input node, a first transistor having a gate that couples to the input node, and a second transistor having another gate that couples to the input node. In one or more embodiments, the second transistor has a greater activation voltage threshold than does the first transistor and the first transistor amplifies a signal that is present on the input node. In one such embodiment, after the first transistor amplifies the signal, the second transistor maintains the amplified signal on the input node while the first transistor is deactivated. | 2012-09-13 |
20120230141 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - Disclosed herein is a semiconductor device comprising local bit lines, a global bit line, local switch control lines, main switch control lines, hierarchical switches controlling electrical connections between the local bit lines and the global bit line in response to potentials of the local switch control lines, local switch drivers driving the local switch control lines in response to potentials of the main switch control lines, and main switch drivers selectively activating the main switch control lines. | 2012-09-13 |
20120230142 | TABLE LOOKUP VOLTAGE COMPENSATION FOR MEMORY CELLS - Systems and methods of regulating voltage at a memory cell are disclosed. An address for the memory cell is determined. Table lookups based on the address are performed. The table lookups yield voltage compensation parameters that can be used to set voltages on the terminals (e.g., source and drain) of the memory cell. | 2012-09-13 |
20120230143 | STATIC MEMORY WITH SEGMENTED CLEAR - Described embodiments provide a static memory system with multiple memory cell that, in response to a reset signal, simultaneously resets or clears a segment of the memory cells in the memory. Clearing the entire memory or a portion thereof is accomplished by sequencing though a subset of address bits while asserting the reset signal. | 2012-09-13 |
20120230144 | SEMICONDUCTOR DEVICE - A device includes a first clock generation circuit that receives an external clock signal supplied to the device, delays the external clock signal to output a first clock signal synchronized with the external clock signal, and a circuit that generates a control signal to control output of data, based on second clock signals obtained by dividing an internal clock signal generated from the external clock signal, and third clock signals obtained by dividing the first clock signal. | 2012-09-13 |
20120230145 | LOW-TURBULENT AERATOR AND AERATION METHOD - A low-turbulent aspirating type aerator, introduced into a body of liquid, comprising of: a gas conveyance tube having a gas inlet end and a gas outlet end; a gas-liquid mixture chamber incorporating; an impeller affixed to a rotatable shaft, at the least one gas intake opening and at the least one gas-liquid discharge opening at or near bottom end of gas-liquid mixture chamber. | 2012-09-13 |
20120230146 | MIXING SILO - A mixing silo for free-flowing finely divided solid materials, in particular for powdered, fibrous and/or granular mixed material, especially polymer granules, specifically suited for mixing polymer granules, having an excellent mixing quality and at the same time a simplified and improved suitability for washing out in order to avoid cross contamination. The mixing silo may be used for homogenizing possibly inhomogeneous polymer granule batches in the form of a stream of product from a process producing polymer granules. | 2012-09-13 |
20120230147 | PORTABLE CEMENT MIXING APPARATUS - A system for forming a cementitous slurry comprising at least water or other liquid and at least one flowable particulate mass such as sand or cement has computerized control of loading the ingredients into a mixing chamber. The mixing chamber has a scale that provides a signal indicating the current weight of the mixing chamber. The computer monitors the weight of the mixing chamber as these ingredients are individually loaded into the mixing chamber. When the desired weight of a particular ingredient has been loaded, the computer halts the delivery of that ingredient. Ingredients are loaded first at a relatively high rate, and then as the desired weight of material in the mixing chamber approaches, the rate slows. | 2012-09-13 |
20120230148 | Dispenser for Beverages Having an Ingredient Mixing Module - The present application provides an ingredient mixing module for mixing a number of ingredients. The mixing module may include a mixing chamber, a number of entry ports positioned about the mixing chamber, a mixer positioned within the mixing chamber, a brushless motor positioned about the mixing chamber so as to drive the mixer, and a nozzle downstream of the mixing chamber. | 2012-09-13 |
20120230149 | METHODS, SYSTEMS AND APPARATUS FOR PROMOTING THE POURABILITY OF SEMI-FROZEN AND SEMI-FLUIDIC BEVERAGES FROM BEVERAGE CONTAINERS - A beverage blender includes a beverage container, one or more vibrating mechanisms permanently or releasably attached to the beverage container (e.g., to a bottom portion or handle of the beverage container) or integrated within one or more walls of the beverage container, and a blender base that includes a motor for turning a blade in the beverage container when the beverage container is docked to the blender base. The one or more vibrating mechanisms is/are activated while the beverage is being poured so that vibrations from the one or more vibrating mechanisms are mechanically transmitted to the beverage container. The mechanically transmitted vibrations promote the pourability of the beverage from the beverage container, including dislodging beverage ingredients that are lodged or trapped in crevices of the beverage container and freeing up beverage ingredients that may have accumulated at the bottom of the beverage container during blending. | 2012-09-13 |
20120230150 | Method for determining positions of sensor streamers during geophysical surveying - The geodetic position of a point on a streamer towed by a vessel in a body of water may be determined. Geodetic positions of a plurality positions along at least two of a plurality streamers towed in the body of water may be determined. Positions may be selected from the plurality of positions. Distances between pairs of the selected positions and between each of the selected positions and the point may be determined. Geodetic position of the point may be determined using the geodetic positions and distances. | 2012-09-13 |
20120230151 | Borehole Imaging And Orientation Of Downhole Tools - Methods of generating radial survey images of a borehole and methods of orienting downhole operational tools are disclosed. The disclosed techniques are used to generate a radial survey of the borehole in the form of one or more rose-plots and/or a radial image of the borehole and surrounding area that can be used to properly orient downhole operational tools in the desired direction. The tool string includes, from the top to bottom, a telemetry module, a non-rotating centralizer, a motor module, an imaging sonde used to survey the borehole, a rotating centralizer and a downhole operational tool. The motor module can be used to rotate the imaging sonde to generate the radial survey and then rotate the downhole operational tool to the desired direction based upon a review of the radial survey. | 2012-09-13 |