37th week of 2012 patent applcation highlights part 21 |
Patent application number | Title | Published |
20120229152 | MEASURING METHOD FOR DEGREE OF DEGRADATION OF LUBRICATING OIL, AND MEASURING DEVICE THEREFOR, AS WELL AS LUBRICATING OIL MONITORING SYSTEM IN MACHINE AND DEVICE - Provided are a method of measuring a degree of degradation of a lubricating oil and a measuring device therefor, in which (a) acidity is measured through use of an ISFET of hydrogen ion sensitive type and (b) dielectric constants or electrostatic capacitances at two or more different frequencies are obtained, to thereby determine a degradation state of the lubricating oil based on the acidity and a plurality of values of the dielectric constants or the electrostatic capacitances. Accordingly, the degree of degradation of the lubricating oil can be measured easily and precisely and a degradation mechanism of the lubricating oil can be predicted. | 2012-09-13 |
20120229153 | SYSTEMS AND METHODS FOR DETECTING SURFACE CHARGE - Systems and methods are provided for detecting surface charge on a semiconductor substrate having a sensing arrangement formed thereon. An exemplary sensing system includes the semiconductor substrate having the sensing arrangement formed thereon, and a module coupled to the sensing arrangement. The module obtains a first voltage output from the sensing arrangement when a first voltage is applied to the semiconductor substrate, obtains a second voltage output from the sensing arrangement when a second voltage is applied to the semiconductor substrate, and detects electric charge on the surface of the semiconductor substrate based on a difference between the first voltage output and the second voltage output. | 2012-09-13 |
20120229154 | METHOD FOR DISTINGUISHING, CLASSIFYING AND MEASURING SOFT AND HARD INCLUSIONS IN LIQUID METAL - The present invention is a method for distinguishing, classifying and measuring soft and hard inclusions in a liquid metal that includes obtaining a flow through cell disposed on a tube with a top to allow the liquid metal to flow through the flow through cell and into the tube. There is also a mounting and a vacuum system disposed on top of the tube to draw the liquid metal through the flow through cell and into the tube that utilizes a pair of electrodes set inside and outside of the tube to apply an electric current to the liquid metal passing through the flow through cell. An electric resistance change is then measured and an electric resistance pulse is applied to the liquid metal to measure deformed behavior of the inclusions. The resistance pulse method can be used with liquid droplets, steel slag, bubbles and other deformable inclusions. | 2012-09-13 |
20120229155 | SEMICONDUCTOR INTEGRATED CIRCUIT, FAILURE DIAGNOSIS SYSTEM AND FAILURE DIAGNOSIS METHOD - A semiconductor integrated circuit includes a memory containing multiple memory bits that store predetermined data placed in a first address direction and a second address direction. The semiconductor integrated circuit includes a BIST (Built-in Self-Test) circuit that diagnoses a failure of the memory. | 2012-09-13 |
20120229156 | TESTING APPARATUS AND RELATIVE METHOD - Embodiments of the invention may provide a testing apparatus that is used to test solar cells or other electronic devices. The testing apparatus may comprise a substantially flat support that is configured to support a substrate or other device that is to be electrically tested and a plurality of testing probes. The support comprises a plurality of through holes, each suitable for the insertion of a corresponding testing probe, to allow each probe to make contact with a testing area formed on the substrate. The testing apparatus may comprise a suction device that is associated or associable with the support, and is able to exert a holding force on the substrate that counteracts the thrusting force exerted by the testing probes. | 2012-09-13 |
20120229157 | PROBE CARD AND MANUFACTURING METHOD THEREOF - In one embodiment, a probe card is provided. The probe card includes: a substrate having a first surface and a second surface opposite to the first surface; a through hole formed through the substrate and extending between the first surface and the second surface; an elastic member formed in the through hole to extend to the first surface; a through electrode formed in through hole to extend to the second surface; a first trace on a surface of the elastic member to be electrically connected to the through electrode; and a contact bump on the elastic member via the first trace to be electrically connected to the first trace, wherein the contact bump is electrically connected to an electrode pad formed on a DUT (device under test) when an electrical testing is performed on the DUT using the probe card. | 2012-09-13 |
20120229158 | APPARATUS FOR TESTING A SEMICONDUCTOR DEVICE AND METHOD OF TESTING A SEMICONDUCTOR DEVICE - An apparatus for testing a semiconductor device includes a test socket, a test board, an ID reader, and an accumulator. The test socket comprises an ID information pattern and is configured to receive the semiconductor device. The test board is configured to detachably receive the test socket and electrically connect to the test socket. The ID reader is configured to read the ID information pattern and generate an ID signal corresponding to the test socket each time a semiconductor test is performed in the test socket. The accumulator is electrically connected to the ID reader and is configured to accumulate a plurality of ID signals, and store a test number equal to the number of times the test socket is used to perform the semiconductor test. The test number is based on the accumulated ID signals. | 2012-09-13 |
20120229159 | TEST INTERFACE BOARD AND TEST SYSTEM INCLUDING THE SAME - A test interface board includes a wiring group, a plurality of contact portions, and a control device. The wiring group includes a main wire operatively coupled to a channel of a tester, and a plurality of sub-wires operatively coupled to the main wire. The plurality of contact portions are operatively coupled to the plurality of sub-wires, and contact first electrodes of a plurality of semiconductor devices. The control device includes a plurality of switching devices operatively coupled to the plurality of sub-wires, a memory configured to store an identification number, and a controller configured to open and close the plurality of switching devices in response to a control signal corresponding to the identification number from among a plurality of control signals. | 2012-09-13 |
20120229160 | WIRING BOARD FOR ELECTRONIC PARTS INSPECTING DEVICE AND ITS MANUFACTURING METHOD - A wiring board for an electronic parts inspecting device that can be designed and produced relatively quickly, inexpensively, and with few jigs is provided. In certain embodiments the wiring board includes a base board made of an insulating material having a front surface and a back surface, the base board including a plurality of first via conductors as well as first terminals on the front surface and outer terminals on the back surface that are connected to the ends of the first via conductors, and a mounting board on the front surface of the base board having a front side that includes, a plurality of probe pads, a plurality of second terminals that are electrically connected to the first terminals of the base board, and front surface wirings that connect the probe pads to the second terminals. Lastly, a method of manufacturing the same is provided. | 2012-09-13 |
20120229161 | Method For Detecting Underperforming Solar Wafers In A Solar Panel or Underperforming Solar Panel in a Solar Array - A method in a solar panel including one or more bypass diodes coupled to one or more sections of solar wafers includes measuring a current flowing through each section of the solar panel; measuring a current flowing through each bypass diode; and assessing the measured current value of the one or more sections of the solar panel and the measured current values of the bypass diodes to determine if the solar panel is malfunctioning. In another embodiment, the method measures a current flowing through the solar panel and through the bypass diodes to determine if the solar panel is malfunctioning. In another embodiment, a method in a solar array determines an underperforming solar panel by measuring the output current and the output voltage of the solar panels in the array. | 2012-09-13 |
20120229162 | Non-Contact Testing Devices for Printed Circuit Boards Transporting High-Speed Signals - Non-contact testing devices formed on a printed circuit board (PCB), to enable testing high-speed signals propagating along at least one signal track located on a signal layer of the PCB, and methods of testing high-speed signals using thereof are provided. A non-contact testing device includes a non-contact testing track formed on a layer of the PCB, and having at least one portion substantially parallel with the at least one signal track and a testing point located at an end of the non-contact testing track. | 2012-09-13 |
20120229163 | Dynamic Pad Hardware Control - Some embodiments of the present disclosure relate to dynamic hardware pad control that is triggered by an intelligent hardware module that monitors an operational state of an IC pin. This hardware module then provides a control signal, which is based on the operational state of the IC pin, to a multiplexer control block that selects one of several different configurations for the IC pin. Because the control signal is provided by the hardware module, the techniques disclosed herein allow precise switching between a number of different IC pin configurations in a fast and efficient manner. | 2012-09-13 |
20120229164 | OUTPUT CIRCUIT AND OUTPUT CONTROL SYSTEM - An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor. | 2012-09-13 |
20120229165 | CONFIGURATION AND METHOD FOR IMPROVING NOISE IMMUNITY OF A FLOATING GATE DRIVER CIRCUIT - A floating gate driver circuit includes a level shifter, a pass element, a bistable circuit and a control logic circuit, to shift the voltage level of a control signal from a lower one to a higher one. The level shifter or the pass element has loads dynamically controlled by the control logic circuit to filter malfunction caused by dv/dt noise induced by a floating node. | 2012-09-13 |
20120229166 | Semiconductor Device and a Display Device - A standard cell used for the logic synthesis and the routing of layout is configured by a logic circuit on an output side and a logic circuit on an input side, and a driving capacity of the logic circuit on the output side is made large while gate input capacitance of the logic circuit on the input side is made small. | 2012-09-13 |
20120229167 | Twin-Drain Spatial Wavefunction Switched Field-Effect Transistors - A field-effect transistor is provided and includes source, gate and drain regions, where the gate region controls charge carrier location in the transport channel, the transport channel includes a asymmetric coupled quantum well layer, the asymmetric quantum well layer includes at least two quantum wells separated by a barrier layer having a greater energy gap than the wells, the transport channel is connected to the source region at one end, and the drain regions at the other, the drain regions include at least two contacts electrically isolated from each other, the contacts are connected to at least one quantum well. The drain may include two regions that are configured to form the asymmetric coupled well transport channel. In an embodiment, two sources and two drains are also envisioned. | 2012-09-13 |
20120229168 | NOISE REDUCTION CIRCUIT AND SEMICONDUCTOR DEVICE PROVIDED WITH NOISE REDUCTION CIRCUIT - Noise reduction circuit includes first and second reset signal generation circuits generating first and second reset signals activated when a data input signal goes to a low level or a high level and are deactivated in synchronization with a clock signal when a high or low level is maintained, and first and second counter circuits that count an inverted signal of clock signal and are reset by the first or second reset signal. The noise reduction circuit further includes a data output circuit including a selector circuit and an output flip-flop circuit that outputs a signal selected by the selector circuit in synchronization with the clock. The selector circuit selects and outputs any of: signal fixed at a high level or low level, and output signal of the output flip-flop circuit, according to logic levels of output signals of the first and second counter circuit. | 2012-09-13 |
20120229169 | Techniques For Measuring Voltages in a Circuit - A circuit includes a comparator, a programmable current source, and a control circuit. The comparator is operable to compare an internal supply voltage of the circuit to a reference voltage. The programmable current source is operable to supply a first current for the reference voltage. The control circuit is operable to control the first current through the programmable current source based on an output signal of the comparator. | 2012-09-13 |
20120229170 | Methods and Systems for Detection of Zero Crossings in a Signal - Methods and systems for detection of zero crossings in a signal are described. For example, true zero crossings in an alternating voltage power source signal can be detected in the presence of noise pulses. The zero crossing detections are performed by establishing a value of a signal status counter, and at a repeating interval if the signal is a logic low value, the value of the signal status counter is decremented if the signal status counter is greater than a first value otherwise a flag is set to enable detection of a zero crossing in the signal. In addition, at the repeating interval, if the signal is a logic high value, the value of the signal status counter is incremented, and if after incrementing the signal status counter is equal to a second value and the flag is set, a zero crossing of the signal is declared. | 2012-09-13 |
20120229171 | FREQUENCY SYNTHESIZER AND FREQUENCY SYNTHESIZING METHOD FOR CONVERTING FREQUENCY'S SPURIOUS TONES INTO NOISE - One of the advantages of direct frequency synthesis technique (e.g., flying-adder architecture) is its capability of generating arbitrary frequency by utilizing the time-average-frequency concept. In the clock output of the direct frequency synthesizer, instead of one type of cycle, there are two types of cycles. Unlike the conventional one-type-cycle clock wherein clock energy is concentrated at its designed frequency, Time-Average-Frequency based clock spreads some of its energy into spurious tones, which could be harmful to certain applications. The spurious tones are caused by the periodic carry sequence generated from a fractional part accumulator inside the frequency synthesizer. The invention suggests a method and an apparatus to break this periodicity and convert the spurious tones into broadband noise. | 2012-09-13 |
20120229172 | POWER SUPPLY SWITCHING CIRCUIT - Provided is a power supply switching circuit with a smaller circuit scale. When a detector ( | 2012-09-13 |
20120229173 | Rapid switchable HV P-MOS power transistor driver with constant gate-source control voltage - Systems and methods for providing a rapid switchable high voltage power transistor driver with a constant gate-source control voltage have been disclosed. A low voltage control stage keeps the gate-source voltage constant in spite of temperature and process variations. A high voltage supply voltage can vary between about 5.5 Volts and about 40 Volts. The circuit allows a high switching frequency of e.g. 1 MHz and minimizes static power dissipation. | 2012-09-13 |
20120229174 | OUTPUT STAGE CIRCUIT FOR OUTPUTTING A DRIVING CURRENT VARYING WITH A PROCESS - An output stage circuit includes a first P-type metal-oxide-semiconductor transistor, a second P-type metal-oxide-semiconductor transistor, an N-type metal-oxide-semiconductor transistor, and a current source. A voltage of a third terminal of the first P-type metal-oxide-semiconductor transistor is a first voltage minus a voltage drop between a first terminal and a second terminal of the first P-type metal-oxide-semiconductor transistor. The N-type metal-oxide-semiconductor transistor is coupled between the third terminal of the first P-type metal-oxide-semiconductor transistor and the current source. A second terminal of the second P-type metal-oxide-semiconductor transistor is coupled to the third terminal of the first P-type metal-oxide-semiconductor transistor. When a second terminal of the N-type metal-oxide-semiconductor transistor receives a kick signal, a driving current flowing through the second P-type metal-oxide-semiconductor transistor is relevant to the voltage of the third terminal of the first P-type metal-oxide-semiconductor transistor. | 2012-09-13 |
20120229175 | Coupling Circuit, Driver Circuit and Method for Controlling a Coupling Circuit - A coupling circuit has a first and a second transistor (P | 2012-09-13 |
20120229176 | Integrated Semiconductor Device - A III-nitride device that includes a silicon body having formed therein an integrated circuit and a III-nitride device formed over a surface of the silicon body. | 2012-09-13 |
20120229177 | MIXING CIRCUIT - There is provided a mixing circuit in which a rise of the consumption current can be suppressed while decreasing a non-linear component. The mixing circuit includes: an input unit | 2012-09-13 |
20120229178 | Method and apparatus for calibrating frequency - Methods and apparatuses for calibrating frequency are provided according to the embodiment of the present disclosure. A method for calibrating frequency may comprise: providing an actual frequency of a reference frequency signal and a frequency offset between the actual frequency of the reference frequency signal and the expected frequency of the reference frequency signal; determining a frequency division ratio according to the frequency of a target frequency signal and the expected frequency of the reference frequency signal; determining a calibration value of the frequency division ratio according to the frequency offset; providing a calibrated frequency division ratio by calibrating the frequency division ratio according to the calibration value; and providing the target frequency signal by dividing the frequency of the reference frequency signal according to the calibrated frequency division ratio. | 2012-09-13 |
20120229179 | PLL CIRCUIT AND OPTICAL DISC APPARATUS - A PLL circuit includes a polyphase reference clock output circuit that outputs reference clocks, a polyphase frequency divider circuit that outputs divided clocks, which is obtained by dividing frequencies of the reference clocks, a selection switch circuit that selects one of the reference clocks or one of the divided clocks, and outputs the selected clock as a selected clock, a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, where the output clock has a frequency that fluctuates according to a value of frequency control input data, and the ideal phase is calculated according to the output clock and the value of the frequency control input data, and a selection circuit that selects and outputs the output clock synchronized with the divided clocks according to the delay amount data. | 2012-09-13 |
20120229180 | Method and Device for Generating Low-Jitter Clock - The present invention discloses a method for generating a low jitter clock, including: inserting a time delay in each low-speed clock period to finely adjust a high-speed clock, and then performing frequency division operation on the adjusted high-speed clock to obtain the required low-speed clock. The present invention also discloses an apparatus for generating the low jitter clock at the same time. By using the method and the apparatus, the jitter of the low-speed clock can be decreased. The implementation method is simple and convenient and the device cost is saved. | 2012-09-13 |
20120229181 | ASYNCHRONOUS CIRCUIT - The asynchronous circuit includes a plurality of circuit blocks connected in a hierarchical structure, each circuit block including an arithmetic circuit and a control circuit that makes two-phase control on the arithmetic circuit, and a mode control circuit. The mode control circuit controls a circuit block in a first stage to start initialization when the circuit block starts idle phase and start working phase when a circuit block in a lowermost stage starts idle phase, and controls a circuit block in a second stage to start working phase when the circuit block in the first block starts initialization and start initialization when the circuit block in the first stage starts working phase. This improves the processing speed of a two-phase asynchronous circuit and suppresses an increase in circuit size. | 2012-09-13 |
20120229182 | SIGNAL GENERATING APPARATUS FOR GENERATING POWER-ON-RESET SIGNAL - A signal generating apparatus, for generating a power-on-reset signal, including a bias circuit and a power-on-reset signal generating circuit is disclosed. The bias circuit is for generating an output bias voltage, and includes at least one bipolar junction transistor (BJT), wherein a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to an emitter-to-base voltage of the BJT. The power-on-reset signal generating circuit is coupled to the bias circuit, and is for generating a duplicated voltage by duplicating the output bias voltage, wherein the power-on-reset signal is generated according to the duplicated voltage. | 2012-09-13 |
20120229183 | POWER-ON RESET CIRCUIT AND ELECTRONIC DEVICE HAVING THE SAME - A power-on reset circuit includes a current source circuit supplying a current that varies according to a temperature to a first node, a first transistor connected between the first node and a ground voltage and having a gate connected with a power supply voltage, and an output circuit connected with the first node and outputting a power-on reset signal in response to a signal applied to the first node. | 2012-09-13 |
20120229184 | All Digital Serial Link Receiver with Low Jitter Clock Regeneration and Method Thereof - An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus. | 2012-09-13 |
20120229185 | Time-to-Digital Converter with Successive Measurements - The invention relates to the conversion into digital information of the time difference between a first signal and a second signal. In particular, in order to determine a fractional part of the number of periods of a first signal for a period of a second signal, the following are alternately performed: /1/ delaying the second signal relative to the first signal and determining a first digital information item, a function of the fractional part, /2/ delaying the first signal relative to the second signal and determining a second digital information item, a function of the fractional part. Then the fractional part is calculated as a function of the previously obtained first and second digital information items. | 2012-09-13 |
20120229186 | MEMORY INTERFACE CIRCUIT AND DRIVE CAPABILITY ADJUSTMENT METHOD FOR MEMORY DEVICE - Provided is a memory interface circuit connected to a memory device that outputs a first data signal, and including: a first delay unit delaying a first strobe signal outputted from the memory device by a first delay amount to generate a first delayed strobe signal; a first data latch unit latching the first data signal as a first latched data signal in synchronization with the first delayed strobe signal; a first range calculating unit calculating a first delay range width that is a width of a range of values of the first delay amount which allow the first data latch unit to correctly latch the first data signal as the first latched data signal; and a drive capability setting unit adjusting the drive capability of the memory device so as to widen the first delay range width. | 2012-09-13 |
20120229187 | Storage circuitry and method with increased resilience to single event upsets - Storage circuitry is provided with increased resilience to single event upsets, along with a method of operation of such circuitry. The storage circuitry has a first storage block configured in at least one mode of operation to perform a first storage function, and a second storage block configured in at least one mode of operation to perform a second storage function distinct from said first storage function. Configuration circuitry is responsive to a predetermined mode of operation where the second storage function is unused, to configure the second storage block to operate in parallel with the first storage block. By arranging the two storage blocks in parallel when one of the storage blocks is otherwise performing no useful function, this in effect increases the size of the storage block that is still performing the useful storage function, and as a result increases its resilience to single event upsets. Such an approach has minimal area and power consumption overhead, and provides a small storage circuit that can be readily used in a wide variety of sequential cell designs. | 2012-09-13 |
20120229188 | SEMICONDUCTOR DEVICE AND OPERATION MODE SWITCH METHOD - A semiconductor device including an internal terminal, a first transistor of a first conductivity type that is coupled between a first reference potential and the internal terminal, and that includes a first control terminal, a second transistor of a second conductivity type that is coupled between a second reference potential and the internal terminal, and that includes a second control terminal, an oscillator that includes an output terminal to output a clock signal, and a comparator that is coupled to the internal terminal, and that compares a potential of the internal terminal when the internal terminal is coupled to the first reference potential with a potential of the internal terminal when the internal terminal is coupled to the second reference potential. Each control terminals is coupled to the output terminal to commonly receive the clock signal, and the first and second transistors exclusively operate in response to the clock signal. | 2012-09-13 |
20120229189 | HIGH SPEED LEVEL SHIFTERS AND METHOD OF OPERATION - A circuit comprising an inverter coupled to an input and receiving an input signal. A first pull-down transistor coupled to the inverter, pulling down an output when the input signal is low. A second pull-down transistor coupled to the input, pulling down a complementary output when the input signal is high. A first pull-up transistor coupled to the complementary output, pulling up the output when the input signal is high. A second pull-up transistor coupled to the output, pulling up the complementary output when the input signal is low. A first switch receiving a first control signal, coupled to the complementary output. A first strong pull-up transistor coupled to the first switch, assisting the pull up of the output. A second switch coupled to the output, receiving a second control signal. A second strong pull-up transistor coupled to the second switch, assisting the pull up of the complementary output. | 2012-09-13 |
20120229190 | POWER SOURCE CONTROLLER AND SEMICONDUCTOR INTEGRATED CIRCUIT - According to one embodiment, a power source controller has a first power source line supplied with a reference power source voltage, a second power source line connected to an internal circuit, a control circuit configured to control a connection between the first power source line and the second power source line, a control signal line connected to the control circuit, and configured to provide a control signal for controlling the connection, a transistor comprising a first terminal, a second terminal and a control terminal in the control circuit, the control terminal of the transistor being connected to the control signal line, a semiconductor substrate on which the transistor is formed, and first through third wires. | 2012-09-13 |
20120229191 | NEUTRAL SWITCHING HIGH SPEED AC TRANSFER SWITCH - A hybrid neutral transfer switch in an electrical system to transfer a load between multiple AC power sources is provided. The hybrid neutral transfer switch includes a neutral gate controlled device connected to a neutral input of each of the multiple power sources and a mechanical transfer switch that switches between the neutral input of each of the power sources. During the transfer of power from one power source to another power source, the neutral gate controlled devices are activated and/or deactivated in conjunction with the switching of the mechanical transfer switch from one neutral input to another neutral input. | 2012-09-13 |
20120229192 | SEMICONDUCTOR INTEGRATED CIRCUIT AND HIGH FREQUENCY MODULE WITH THE SAME - A semiconductor integrated circuit which reduces an increase in the level of a harmonic signal of an RF transmission output signal at the time of supplying an RF transmission signal to a bias generation circuit of an antenna switch, including an antenna switch having a bias generation circuit, a transmitter switch, and a receiver switch. The on/off state of a transistor of the transmitter switch coupled between a transmitter port and an I/O port is controlled by a transmit control bias. The on/off state of the transistors of the receiver switch coupled between the I/O port and a receiver port is controlled by a receiver control bias. An RF signal input port of the bias generation circuit is coupled to the transmit port, and a negative DC output bias generated from a DC output port is supplied to a gate control port of transistors of the receiver switch. | 2012-09-13 |
20120229193 | System and Method for Temperature Based Control of a Power Semiconductor Circuit - In a method for operating a power semiconductor circuit a power semiconductor chip is provided which includes a power semiconductor switch with a first load terminal and with a second load terminal. Further, a first temperature sensor which is thermally coupled to the power semiconductor switch and a second temperature sensor are provided. The power semiconductor switch is switched OFF or kept switched OFF if the temperature difference between a first temperature of the first temperature sensor and a second temperature of the second temperature sensor is greater than or equal to a switching-OFF threshold temperature difference which depends, following an inconstant first function, on the voltage drop across the power semiconductor switch between the first load terminal and the second load terminal. | 2012-09-13 |
20120229194 | TOUCH PANEL HAVING NON-INTEGRATED AND SECURELY ATTACHED PORTIONS OF A SUBSTRATE - A touch panel having non-integrated and securely attached portions of a substrate has a substrate and an extended portion. The substrate takes a regular form and has two opposite surfaces, multiple edge walls and a transparent electrode layer. The transparent electrode layer is formed on one of the opposite surfaces of the substrate. The extended portion has a thickness matching that of each edge wall and is securely attached to one of the edge walls. Accordingly, a substrate having a specific form can be formed by non-integrated parts without cutting off unnecessary material during a specific cutting process, thereby simplifying the fabrication process and saving the material cost. | 2012-09-13 |
20120229195 | CAPACITANCE TYPE INPUT DEVICE - A capacitance type input device includes: a film base material; a driving electrode patterned at a sensor side of the film base material; and a detection electrode patterned to output capacitance between the driving electrode and the detection electrode, opposite to the driving electrode through a sensor side insulating layer, in which reference capacitor portions having reference capacitance for capacitance between the driving electrode and the detection electrode are patterned at the side of a circuit portion opposite to the sensor portion of the film base material. The reference capacitor portion includes a first conductive layer conductively connected with the detection electrode and a second conductive layer opposite to the first conductive layer through a circuit side insulating layer. | 2012-09-13 |
20120229196 | CAPACITANCE TYPE INPUT DEVICE - A detection electrode and an X-driving electrode (first driving electrode) are stacked through a sensor side insulating layer, at the side of a sensor portion of a film base material, and a Y-driving electrode (second driving electrode) is formed on the same forming surface as the detection electrode. The X-driving electrode is formed of a first conductive layer, the detection electrode and the Y-driving electrode are formed in a stacked structure of a second conductive layer having a resistance lower than the first conductive layer and a third conductive layer having a resistance higher than the first conductive layer and the second conductive layer. | 2012-09-13 |
20120229197 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values. | 2012-09-13 |
20120229198 | POWER SUPPLY REGULATOR - Power supply regulators, integrated circuits including a power supply regulator, and methods of regulating a power supply are provided. In one embodiment, a power supply regulator includes a first self-bias circuit configured to receive a supply voltage from a power supply, a second self-bias circuit coupled to a reference voltage, and a clamping circuit coupled between the first and second self-bias circuits. The clamping circuit includes a NMOS transistor coupled to the first self-bias circuit and a PMOS transistor coupled to the second self-bias circuit. The clamping circuit is further configured to generate an output voltage less than the supply voltage at substantially the same time as when the supply voltage is received from the power supply. | 2012-09-13 |
20120229199 | BANDGAP CIRCUIT AND START CIRCUIT THEREOF - A start circuit adapted to start a reference circuit including a plurality of bias nodes is provided. The start circuit includes a current source, a current minor, a load device, and a control device. The current source determines whether or not to generate an internal current according to a plurality of bias voltages on a part of the bias nodes. The current minor duplicates the internal current to produce a mirrored current. The load device adjusts a control voltage according to the mirrored current. The control device determines whether or not to generate a start voltage according to the control voltage, and transmits the start voltage to one of the part of the bias nodes, so as to break the reference circuit away from a zero-current state. | 2012-09-13 |
20120229200 | GATE DRIVE CIRCUIT AND POWER SEMICONDUCTOR MODULE - A gate drive circuit capable of operating at high speed and with low loss without erroneously operating the switching element is provided with a small number of components and a simple and easy circuit configuration. A primary side of a transformer is connected to an output terminal of a low-side gate drive circuit, and a secondary side of the transformer is connected to a gate input side of a high-side switching element. As a positive gate drive voltage is output from the low-side drive circuit, a negative voltage is applied between the gate and source of a high-side switching element, and a gate voltage is suppressed to be equal to or lower than a threshold value. Therefore, the high-side switching element maintains a turn-off state when the low-side switching element is turned on. | 2012-09-13 |
20120229201 | FILTER DEVICE - A filter device includes a filter that separates a steady component and a non-steady component included in an input signal, a synthesis unit that synthesizes the separated steady component and the separated non-steady component according to a given ratio, and an evaluation unit that evaluates the magnitude of the amount of the non-steady component in the input signal, wherein the synthesis unit sets the given ratio to a first ratio in an instance in which the evaluation unit determines the amount of the non-steady component to be equal to or less than a predetermined reference, and sets the given ratio to a second ratio, in which the proportion of the non-steady component is less than that of the first ratio, in an instance in which the evaluation unit determines the amount of the non-steady component to be greater than the predetermined reference. | 2012-09-13 |
20120229202 | Power efficient generation of band gap referenced supply rail, voltage and current references, and method for dynamic control - Circuits and methods for power efficient generation of supply voltages and currents in an integrated circuit by reducing the power consumption of all core analog circuit blocks by a pulsed operation mode are disclosed. In a preferred embodiment of the invention the invention has been applied to a power management chip. Pulsed Mode of Operation of ALL core analog blocks—internal LDO/s, VREF an IBIAS generators, results in significantly reduced power consumption. New circuit realizations and control algorithms to improve the ON/OFF ratio of the Pulsed Mode Operation yield in better power efficiency. Innovative circuit implementation consisting of an additional Top Up Buffer Amplifier stage ensures a fast recharge of VREF output, thus allowing shorter ON times and respectively even better power efficiency. Bypassing a low bandwidth and slow to start LDO with a fast Bypass Comparator supplies a LDO rail in Pulsed Mode of operation. A Dynamic Control of the Commutating Components ensures least disturbance of the voltage potentials, thus allowing shorter ON times and respectively better power efficiency. The invention can also be applied to reference voltage and to bias current generator circuits. | 2012-09-13 |
20120229203 | CALIBRATING DEVICE PERFORMANCE WITHIN AN INTEGRATED CIRCUIT - A multi-fingered device can be calibrated for performance. The multi-fingered device can include a first finger configured to remain active and a second finger that is initially deactivated concurrent with the first finger being active. A measure of degradation for the multi-fingered device within an IC can be determined. The measure of degradation can be compared with a degradation threshold. Responsive to determining that the measure of degradation meets the degradation threshold, a finger of the multi-fingered device can be activated. | 2012-09-13 |
20120229204 | SWITCHED CAPACITOR CIRCUIT - According to the present invention, a switched capacitor circuit comprises: an inverting amplifier for removing the offset by using a chopper stabilization circuit; a sampling unit which is connected between an input terminal and the inverting amplifier; and a feedback unit which is connected to the inverting amplifier in parallel. | 2012-09-13 |
20120229205 | AMPLIFIER CIRCUIT - An amplifier circuit capable of reducing load of a circuit at the previous stage by providing increased input impedance producing less noises. The amplifier circuit includes a fully-differential operational amplifier composed of an inverting input terminal, a non-inverting input terminal receiving a signal different from a signal to be input to the inverting input terminal, an inverting output terminal with the same polarity of the inverting input terminal, and a non-inverting output terminal with reverse polarity; an input impedance element with one end connected to the inverting input terminal; an input impedance element with one end connected to the non-inverting input terminal; and positive feedback impedance elements, with one end of connected to the other end of the input impedance element and the other end connected to the inverting output terminal or to the non-inverting output terminal. | 2012-09-13 |
20120229206 | Minimum Feedback Radio Architecture with Digitally Configurable Adaptive Linearization - Included is a radio transmission system comprising a plurality of power amplifiers (PAs); a plurality of Volterra Engine (VE) linearizers corresponding to the PAs; a plurality of feedback loops corresponding to the PAs; at least one digital hybrid matrix (DHM) coupled to the VE linearizers; and an analog hybrid matrix (AHM) coupled to the PAs, wherein the feedback loops are connected to the AHM and the VE linearizers but not to the PAs to reduce the number of feedback loops. Also included is a radio system comprising a plurality of PAs; a Volterra DHM (VDHM) coupled to the PAs; a plurality of feedback loops corresponding to the PAs; and an AHM coupled to the PAs, wherein the feedback loops are connected to the AHM but not to the PAs to reduce the number of feedback loops. | 2012-09-13 |
20120229207 | PULSE WIDTH MODULATION SIGNAL GENERATING CIRCUIT AND AMPLIFIER CIRCUIT WITH BEAT FREQUENCY CANCELLATION CIRCUIT - A beat frequency cancellation circuit, for an amplifier, includes a coupling device connected between two signal processing paths of the amplifier for compensating for beat frequency effects of output signals between the signal processing paths. | 2012-09-13 |
20120229208 | Power Control - There is provided an amplification stage comprising: an input scaling block for scaling an input signal in dependence on an input scaling factor to generate a scaled version of the input signal; a power amplifier for generating an amplified version of the scaled input signal; an envelope detector for generating a signal representing the envelope of the input signal; an envelope scaling block for scaling the envelope signal in dependence on an envelope scaling factor to generate a scaled version of the envelope signal; a non-linear mapping block for generating a voltage representative of the supply voltage in dependence on the scaled envelope signal; a modulator for generating a power supply voltage for the amplifier in dependence on the voltage generated by the non-linear mapping block; and a power control block for maintaining a linear relationship between the envelope scaling factor and the input scaling factor. | 2012-09-13 |
20120229209 | POWER AMPLIFICATION DEVICE, TRANSMITTER, AND POWER AMPLIFICATION CONTROL METHOD - A power amplifier amplifies a signal. An error signal calculating unit calculates an error signal in accordance with an input signal and an output from the power amplifier. A distortion compensation unit performs predistortion on the input signal by using distortion compensation coefficients that are generated in accordance with a plurality of delay signals obtained by giving different amounts of delay to the input signal and by using an error signal and outputs the input signal subjected to the predistortion to the signal amplifying unit. A tap interval control unit controls the delay intervals of the delay signals that are used for the predistortion performed by the distortion compensation unit in accordance with signal correlation information calculated from the input signal. | 2012-09-13 |
20120229210 | OVERLAY CLASS F CHOKE - Embodiments of the present disclosure relate to an overlay class F choke of a radio frequency (RF) power amplifier (PA) stage and an RF PA amplifying transistor of the RF PA stage. The overlay class F choke includes a pair of mutually coupled class F inductive elements, which are coupled in series between a PA envelope power supply and a collector of the RF PA amplifying transistor. In one embodiment of the RF PA stage, the RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor. The collector of the RF PA amplifying transistor provides the RF stage output signal. The PA envelope power supply provides an envelope power supply signal to the overlay class F choke. The envelope power supply signal provides power for amplification. | 2012-09-13 |
20120229211 | AMPLIFIER USING FAST DISCHARGING REFERENCE - Techniques are disclosed relating to charging and discharging a gate of transistor. In one embodiment, an apparatus is disclosed that includes a driver configured to discharge a gate of a transistor. The driver is configured to discharge the gate at a first rate until reaching a Miller plateau for the transistor, and to discharge the gate at a second rate after reaching the Miller plateau. In such an embodiment, the first rate is greater than the second rate. In some embodiments, the driver is also configured to charge the gate of the transistor at a third rate until reaching a Miller plateau for the transistor, and to charge the gate at a fourth rate after reaching the Miller plateau, the third rate being greater than the fourth rate. In some embodiments, the apparatus is a class D amplifier. | 2012-09-13 |
20120229212 | AMPLIFIER USING MASTER-SLAVE CONTROL SCHEME - Techniques are disclosed relating to charging and discharging gates of transistors. In one embodiment, an apparatus includes first and second drivers. The first driver is configured to discharge a gate of a first transistor, and to send a charge indication to the second driver in response to reaching a Miller plateau for the first transistor. The second driver is configured to charge a gate of a second transistor above a threshold voltage in response to receiving the charge indication. In some embodiments, the second driver is configured to begin charging the gate of the second transistor to a voltage below the threshold voltage when the first driver begins discharging the gate of the first transistor begins, and to wait to charge the gate of the second transistor above the threshold voltage until the charge indication has been received. | 2012-09-13 |
20120229213 | AMPLIFYING DEVICE - To provide an envelope tracking type amplifier that has high efficiency and small fluctuations, an output unit supplies an output signal that is adjusted corresponding to an input signal to a power supply terminal of the amplifier. The output unit includes an analog amplifying circuit that amplifies the input signal; a digital circuit that selectively outputs a first voltage or a second voltage that is lower than the first voltage; and first and second output circuits. The first output circuit includes a first integrating circuit that integrates an output signal of the digital circuit; and a combining section that combines an output signal of the first integrating circuit and an output signal of the analog amplifying circuit and outputs the combined signal to a power supply terminal of the amplifier. The second output circuit includes a second integrating circuit that integrates the output signal of the digital circuit; a resistor having two ends, one end being connected to an output terminal of the second integrating circuit, the other end being connected to an output terminal of the analog amplifying circuit; and a load connected to the output terminal of the second integrating circuit. The digital circuit outputs the first voltage where a voltage applied at the one end of the resistor is lower than the voltage applied at the other end of the resistor and the digital circuit outputs the second voltage when the voltage applied at the one end of the resistor is higher than the voltage applied at the other end of the resistor. | 2012-09-13 |
20120229214 | Amplifier Circuit and Method - A differential amplifier circuit comprises a differential pre-amplifying stage which is designed to allow an input signal with a first common mode voltage range, and to generate an output which has a narrower common mode voltage variation. This pre-amplifier stage is designed to accept a large common mode input voltage and to process the signal so that it can be amplified by a main amplifying stage which is designed to allow an input signal with a smaller common mode voltage range. | 2012-09-13 |
20120229215 | AMPLIFIER ASSEMBLY HAVING CONTROLLED RETURN OF POWER LOSS - An amplifier assembly includes an input signal determiner that determines a first input signal and a second input signal based on an initial signal having an amplitude and an initial frequency. Amplifiers amplify the first and second input signal to form first and second output signals having a phase offset with respect to one another. The first and second amplified output signals are fed to a common coupling element that forms a useful signal and a loss signal, such that a total power of the useful signal and loss signal is independent of the phase offset, the power of the useful signal has a maximum corresponding to a predetermined value of the phase offset, and the partial power of the useful signal decreases with a deviation of the phase offset from the predetermined value. The coupling element feeds the useful signal to a load and the loss signal to a rectifier device that feeds a rectified loss signal to a power supply device, wherein the rectifier device includes active components as rectifier elements, which are controlled synchronously with respect to the initial frequency. | 2012-09-13 |
20120229216 | Distributed amplifier with improved stabilization - A distributed amplifier with improved stabilization includes an input transmission circuit, an output transmission circuit, at least one cascode amplifier coupled between said input and output transmission circuits. Each cascode amplifier includes a common-gate configured transistor coupled to the output transmission circuit, and a common-source configured transistor coupled between the input transmission circuit and the common-gate configured transistor. The distributed amplifier also includes a non-parasitic resistance and capacitance coupled in series between a drain and a gate of at least one of the common-gate configured transistors for increasing the amplifier stability. | 2012-09-13 |
20120229217 | HIGH-FREQUENCY POWER AMPLIFIER - There is a need to provide a high-frequency power amplifier capable of reducing a talk current and reducing a phase deviation in output. The high-frequency power amplifier includes differently sized first through fifth power amplification transistors and impedance matching circuits for example. The high-frequency power amplifier changes a signal path to be used in accordance with a power specification signal. The high-frequency power amplifier uses a signal path from the first transistor to the second transistor in high power mode. The high-frequency power amplifier uses a signal path from the first transistor to the third transistor in medium power mode. The high-frequency power amplifier uses a signal path from the fourth transistor to the fifth transistor in low power mode. The high-frequency power amplifier is configured so that each of the signal paths includes the same number of stages of power amplification transistors and impedance matching circuits. | 2012-09-13 |
20120229218 | CIRCUIT FOR COMPENSATING BASE CURRENT OF TRANSISTOR AND AMPLIFIER CIRCUIT PROVIDED WITH THE SAME - According to one embodiment, a circuit for compensating fluctuation of a base current of a transistor is presented. The transistor has a base connected with an input terminal. The compensation circuit is provided with a first transistor, a current mirror circuit and a second transistor. The current mirror circuit mirrors a current which is supplied to a base of the first transistor. Further, the current mirror circuit supplies the obtained mirror current to the base of the transistor to be compensated. A base of the second transistor is connected with the input terminal electrically. The second transistor causes an early effect in the first transistor. | 2012-09-13 |
20120229219 | MULTI-LEVEL POWER AMPLIFICATION SYSTEM - In general, in accordance with an exemplary aspect of the present invention, an electrical system configured to use power combining of microwave signals, such as those from monolithic microwave integrated circuits or MMICs is provided. In one exemplary embodiment, the system of the present invention further comprises a low loss interface that the circuits are directly connected to. In another exemplary embodiment, the circuits are connected to a pin which is connected to the low loss interface. In yet another exemplary embodiment of the present invention, a multi-layer power amplifier is provided that comprises two or more chassis and circuits attached to impedance matching interfaces according to the present invention. This multi-layered power amplifier is configured to amplify an energy signal and have a significantly reduced volume compared to existing power combiners. | 2012-09-13 |
20120229220 | Temperature compensated oscillator including MEMS resonator for frequency control - Disclosed is an oscillator that relies on redundancy of similar resonators integrated on chip in order to fulfill the requirement of one single quartz resonator. The immediate benefit of that approach compared to quartz technology is the monolithic integration of the reference signal function, implying smaller devices as well as cost and power savings. | 2012-09-13 |
20120229221 | OSCILLATOR CIRCUIT WHICH COMPENSATES FOR EXTERNAL VOLTAGE SUPPLY, TEMPERATURE AND PROCESS - Disclosed is an oscillator circuit which compensates for external voltage supply, temperature, and a process, includes: a reference voltage generation unit configured to generate reference voltage Vbp stabilized against a change in external voltage supply VDD and temperature; a temperature compensation unit configured to generate first reference voltage PVREF, second reference voltage IVREF, and third reference voltage RX_VREF; an internal voltage supply generation unit configured to generate internal voltage supply VPPI stabilized against the change in external voltage supply VDD and temperature by receiving the first reference voltage PVREF; a current supply unit configured to generate compensation current RX_IREF in proportion to or in inverse proportion to temperature by receiving the second reference voltage IVREF; a process compensation unit configured to perform process compensation by controlling an amount of the compensation current RX_IREF; and an oscillation signal generation unit configured to generate oscillation signals. | 2012-09-13 |
20120229222 | WRISTWATCH WITH ATOMIC OSCILLATOR - A wristwatch, which comprises an atomic oscillator comprising a system for detecting the beat frequencies obtained by the Raman effect. | 2012-09-13 |
20120229223 | VIBRATING ELEMENT, VIBRATOR, OSCILLATOR, AND ELECTRONIC DEVICE - A vibrating element includes a piezoelectric substrate having an excitation section adapted to excite a thickness-shear vibration, and provided with a step section in each of side surfaces on both ends, and a peripheral section having a thickness smaller than a thickness of the excitation section, and the peripheral section has at least one projection section disposed on both principal surfaces in an area where a vibratory displacement when the excitation section excites a vibration is sufficiently attenuated. | 2012-09-13 |
20120229224 | METHOD OF MANUFACTURING PIEZOELECTRIC VIBRATING REED, APPARATUS OF MANUFACTURING PIEZOELECTRIC VIBRATING REED, PIEZOELECTRIC VIBRATING REED, PIEZOELECTRIC VIBRATOR, OSCILLATOR, ELECTRONIC APPARATUS, AND RADIO-CONTROLLED TIMEPIECE - A photoresist film forming process to form a film through a spin coating method is included, a plurality of groove portions and a plurality of wall portions are formed in an upper surface of a flow regulating plate, among the plurality of groove portions, the diameter of the outer side surface of a first groove portion is set to be smaller than the longest distance from the rotation center to the outer edge of the square wafer, and is set to be larger than the shortest distance from the rotation center to the outer edge of the square wafer, and among the plurality of groove portions, the diameter of the outer side surface of a second groove portion is set to be smaller than the shortest distance from the rotation center to the outer edge of the square wafer. | 2012-09-13 |
20120229225 | PIEZOELECTRIC DEVICE AND ELECTRONIC APPARATUS - A piezoelectric device includes an insulating substrate, a piezoelectric vibration device that is mounted on a device mounting pad, a metal lid member that seals the piezoelectric vibration device in an airtight manner, an external pad that is arranged outside the insulating substrate, an oscillation circuit, a temperature compensation circuit, and a temperature sensor. The lid member and the temperature sensor or the lid member and the IC component are connected to each other so as to be heat-transferable, and a heat transfer member having thermal conductivity higher than that of the material of the insulating substrate is additionally included. | 2012-09-13 |
20120229226 | Micromechanical Resonator - The invention relates to a micromechanical resonator comprising a substrate ( | 2012-09-13 |
20120229227 | VECTOR MODULATOR USING TIME DELAY AND PHASE SHIFTER - An vector modulator using a time delay and a phase shifter is disclosed, the vector modulator including a time delay ( | 2012-09-13 |
20120229228 | MOBILE WIRELESS COMMUNICATIONS DEVICE WITH ADJUSTABLE IMPEDANCE MATCHING NETWORK AND ASSOCIATED METHODS - A mobile device includes an adjustable impedance matching network coupled between a power amplifier and an antenna and has an adjustable impedance element. An impedance sensor is coupled between the power amplifier and adjustable impedance matching network. A processor is configured to a) calculate a corrected antenna load impedance based upon a sensed impedance at inputs of the impedance matching network and a current value of the adjustable impedance element, and b) determine a new value for the adjustable impedance element based upon the corrected antenna load impedance. The processor is also configured to c) set the adjustable impedance element to the new value, and d) sense a new impedance at the inputs and determine if the sensed new impedance is within a threshold value of the power amplifier impedance, and repeat steps a), b), and c) if the sensed new impedance is not within the threshold value. | 2012-09-13 |
20120229229 | Microwave Transmission Assembly - According to one or more embodiments, a directional filter assembly ( | 2012-09-13 |
20120229230 | Impedance Transforming Coupler - A coupler circuit that includes two parallel coupled transmission lines (first transmission line and second transmission line) and a third transmission line, one end of the third transmission line connects to the end of first transmission line at one side, the other end of the third transmission line connects to the end of the second transmission line at the other side. Various coupling value and impedance transforming ratio can be achieved by select corresponding even and odd mode impedance of the coupled transmission lines and characteristic impedance of the crossing transmission line. | 2012-09-13 |
20120229231 | VARIABLE FILTER AND COMMUNICATION APPARATUS - A variable filter includes, on a dielectric substrate including ground conductor, first resonator including a transmission line connected to input terminal, second resonator including a transmission line connected to output terminal, and coupling portion including a transmission line having one end connected to the first and second resonators and another end being an open end, or structure having one end connected to the first and second resonators, including a serial connection of a transmission line and a variable capacitor, another end of the variable capacitor connected to the ground conductor, and adjusting means capable of changing electric length, in the first and second resonators and the coupling portion, wherein pass band width can be changed by changing ratio of electric transmission length of the coupling portion to electric transmission lengths of transmission line including the coupling portion, and the first and second resonators. | 2012-09-13 |
20120229232 | Rotatable Polarizer/Filter Device and Feed Network Using the Same - A feed network may include a cylindrical common waveguide terminating in a common port and an orthomode transducer having a first port for coupling a first linearly polarized mode to the cylindrical common waveguide and a second port for coupling a second linearly polarized mode to the cylindrical common waveguide, the second linearly polarized mode orthogonal to the first linearly polarized mode. A filter-polarizer element may be disposed within the cylindrical common waveguide. The filter-polarizer element may be rotatable about an axis of the cylindrical common waveguide. The filter-polarizer element may be configured to cause a predetermined relative phase shift between a first signal and a second signal propagating in the cylindrical common waveguide. The filter-polarizer element may be further configured to suppress propagation of at least one undesired mode in the cylindrical common waveguide. | 2012-09-13 |
20120229233 | Dielectric Waveguide Filter | 2012-09-13 |
20120229234 | SAFETY DEVICE - Contact terminals ( | 2012-09-13 |
20120229235 | Magnetic Attachment System Having Composite Magnet Structures - A magnetic attachment system for attaching a first object to a second object. A first magnet structure is attached to the first object and a second magnet structure is attached to the second object. The first and second objects are attached by virtue of the magnetic attraction between the first magnet structure and second magnet structure. The magnet structures comprise magnetic elements arranged in accordance with patterns based on various codes. In one embodiment, the code has certain autocorrelation properties. In further embodiments the specific type of code is specified. In a further embodiment, an attachment and a release configuration may be achieved by a simple movement of the magnet structures. In a further embodiment, the magnetic field structure may comprise multiple structures based on multiple codes. | 2012-09-13 |
20120229236 | Magnetic Attachment System Having a Non-Magnetic Region - A magnetic attachment system for attaching a first object to a second object. A first magnet structure is attached to the first object and a second magnet structure is attached to the second object. The first and second objects are attached by virtue of the magnetic attraction between the first magnet structure and second magnet structure. The magnet structures comprise magnetic elements arranged in accordance with patterns based on various codes. In one embodiment, the code has certain autocorrelation properties. In further embodiments the specific type of code is specified. In a further embodiment, an attachment and a release configuration may be achieved by a simple movement of the magnet structures. In a further embodiment, the magnetic pattern may include a non-magnetic region. | 2012-09-13 |
20120229237 | BIONIC TELESCOPIC MATRIX UNIT - A bionic telescopic matrix unit is disclosed, which is composed of a slide shaft ( | 2012-09-13 |
20120229238 | Magnetic Member and Electronic Component - A magnetic member includes a plurality of superparamagnetic particles held by the magnetic member. Each of the plurality of superparamagnetic particles is formed with a particle size which is set at least such that a Neel relaxation time τn in the each of the superparamagnetic particles becomes shorter than a cycle P of an alternating current magnetic field applied to the magnetic member (τn | 2012-09-13 |
20120229239 | Layered magnet - A layered magnet for a magnet arrangement of an electrical machine includes a number of primary magnet layers and a number of subordinate magnet layers, wherein each magnet layer includes a ferromagnet with a layer concentration of a lanthanide, and wherein the layer concentration of the lanthanide is greatest in a primary magnet layer. Further, a method of manufacturing such a layered magnet and an electrical machine with a magnet arrangement are provided. | 2012-09-13 |
20120229240 | R-Fe-B RARE EARTH SINTERED MAGNET AND METHOD FOR PRODUCING SAME - In a method for producing an R—Fe—B based rare-earth sintered magnet according to the present invention, first, provided is an R—Fe—B based rare-earth sintered magnet body including, as a main phase, crystal grains of an R | 2012-09-13 |
20120229241 | Magnetic Attachment System - A magnetic attachment system is described. The magnetic attachment system has a first plurality of magnetic sources arranged in accordance with a first pattern and a second polarity of magnetic sources arranged in accordance with a second pattern. The first pattern and second pattern are self-complementary, where the magnetic attachment system will correlate and align with a duplicate magnetic attachment system. | 2012-09-13 |
20120229242 | JACKET MEMBER - A jacket member for fitting on a pole of a resolver stator. Enameled wires can be wound around the jacket member to indirectly form coils on the pole of the resolver stator. The jacket member includes a hoop body for fitting on the pole of the resolver stator, whereby the enameled wires can be wound around the hoop body to form the coils. The jacket member further includes multiple projections disposed on the hoop body and projecting therefrom. After the enameled wires are wound around the hoop body, the terminals of the enameled wires can be hooked and located on the projections. | 2012-09-13 |
20120229243 | INTEGRATED CIRCUIT FOR INFORMATION TRANSFER - An integrated circuit for information transfer, having a substrate, at least one Hall element which is integrated into the substrate or situated on the substrate, a first coil which is situated essentially concentrically with respect to the Hall element and at a distance from the Hall element in the vertical direction and galvanically separated therefrom, and at least one second coil which is situated essentially concentrically with respect to the Hall element and galvanically separated therefrom and situated at a distance from the Hall element and the first coil in the vertical direction. The first coil and the second coil are electrically connected in series so that a current flow in the same direction results in the coils. | 2012-09-13 |
20120229244 | DUST CORE AND METHOD FOR PRODUCING THE SAME - There are provided a dust core in which, even if the surface of a heat-treated compact is ground, the insulation between soft magnetic particles on the ground surface can be ensured in the grinding step, and a method for producing the dust core. | 2012-09-13 |
20120229245 | SOFT MAGNETIC POWDER, GRANULATED POWDER, DUST CORE, ELECTROMAGNETIC COMPONENT, AND METHOD FOR PRODUCING DUST CORE - Provided is a soft magnetic powder used for obtaining a dust core having a low hysteresis loss, in particular, in a high temperature range. A soft magnetic powder includes an aggregate of composite magnetic particles, each including a soft magnetic particle containing Fe, Si, and Al, and an insulating coating film disposed on the surface thereof, and satisfies the expressions (1) and (2) below: Expression (1) . . . 27≦2.5a+b≦29 and Expression (2) . . . 6≦b≦9, where a represents the Si content (mass %) and b represents the Al content (mass %). The soft magnetic powder is capable of reducing the hysteresis loss, in a high-temperature environment, of a dust core obtained using the soft magnetic powder. | 2012-09-13 |
20120229246 | OVERVOLTAGE PROTECTION ELEMENT - An overvoltage protection element with a housing, an overvoltage-limiting component arranged in the housing, and with two connection elements for electrically connecting the overvoltage protection element to the current or signal path to be protected, wherein, normally, the connection elements are each in electrically conductive contact with a pole of the overvoltage-limiting component. Reliable and effective electrical connection in the normal state and reliable isolation of a defective overvoltage-limiting component are ensured by the fact that a thermally expandable material is arranged within the housing in a way that, in the event of thermal overloading of the overvoltage-limiting component, the position of the overvoltage-limiting component is changed by expansion of the thermally expandable material relative to the position of the connection elements in a way that causes at least one pole of the overvoltage-limiting component to be out of electrically conductive contact with the corresponding connection element. | 2012-09-13 |
20120229247 | SHUNT RESISTOR AND METHOD FOR MANUFACTURING THE SAME - Provided is a shunt resistor which has an excellent accuracy of current detection and a small temperature drift as well as a compact structure, and improves the operability. The shunt resistor is provided with a resistance body ( | 2012-09-13 |
20120229248 | MULTIPURPOSE CONTROLLER FOR ELECTRONIC DEVICES, FACIAL EXPRESSIONS MANAGEMENT AND DROWSINESS DETECTION - A hands-free controller, a facial expression management system, a drowsiness detection system and methods for using them are disclosed. The controller monitors facial expressions of the user, monitors motions of the user's body, generates commands for an electronic device based on the monitored facial expressions and body motions, and communicates the commands to the electronic device. Monitoring facial expressions can include sensing facial muscle motions using facial expression sensors. Monitoring user body motions can include sensing user head motions. Facial expression management can includes monitoring user facial expressions, storing monitored expressions, and communicating monitored expressions to an electronic device. Drowsiness detection can include monitoring eye opening of the user, generating an alert when drowsiness is detected, monitoring proper usage of the device, and generating a warning when improper usage is detected. | 2012-09-13 |
20120229249 | METHOD AND APPARATUS FOR CONTROLLING THE STATUS OF A DEVICE - The status of a device is controlled by detecting ( | 2012-09-13 |
20120229250 | HOST APPARATUS, ACCESSORY APPARATUS, AND AUTHENTICATING AND CONTROLLING METHOD THEREOF - A method for authenticating an accessory apparatus by a host apparatus is provided. The method includes receiving authentication information from the accessory apparatus, comparing the received authentication information and pre-stored authentication information and performing authentication with respect to the accessory apparatus based on a result of the comparing, and, if the authentication is normally performed, performing a function corresponding to the accessory apparatus, and, if the authentication is not normally performed, transmitting corresponding information to an external server. | 2012-09-13 |
20120229251 | LOCK - An electro-mechanical lock for cargo containers or similar enclosed spaces such as storage units. The locking mechanism includes a dual-ratcheting mechanism, which is normally in the locked position, and which firmly secures doors of a container or other enclosure. To unlock the device, the user obtains a temporary access code and unlocks the device, either by a wireless interface or by, for example, a key pad. The device incorporates a rolling access code algorithm that changes the access code based upon a pre-defined customer selected time period during which the code is valid. Once the validity period expires the user must obtain a new access code from a secure access code source to unlock the device. When access is desired, the user contacts a remote secure access code source, which provides the access code for the associated lock and time period. | 2012-09-13 |