37th week of 2012 patent applcation highlights part 16 |
Patent application number | Title | Published |
20120228651 | LIGHT-EMITTING-DIODE ARRAY - A light-emitting-diode (LED) array includes a first LED unit having a first electrode and a second LED unit having a second electrode. The first LED unit and the second LED unit are positioned on a common substrate and are separated by a gap. Two or more polymer materials form a multi-layered structure in the gap. A first polymer material substantially fills a lower portion of the gap and at least one additional polymer material substantially fills a remainder of the gap above the first polymer material. A kinematic viscosity of the first polymer material is less than a kinematic viscosity of the at least one additional polymer material. An interconnect, positioned on top of the at least one additional polymer material, electrically connects the first electrode and the second electrode. | 2012-09-13 |
20120228652 | LED LAMP AND MANUFACTURING METHOD THEREOF - An LED lamp (Light Emitting Diode) manufacturing method is disclosed. The method includes the steps as following. First, a fluorescent powder and a translucent plastic are mixed to be a mixed material, and the ratio of the fluorescent powder and the translucent plastic is below 80:100. Second, the mixed material is applied to form a lamp shell by the injection molding technology. Third, at least one LED is arranged at the center of the bottom of the lamp shell. | 2012-09-13 |
20120228653 | LIGHT EMITTING DEVICE - A light emitting device of embodiments is provided with a light-emitting element emitting excitation light of a first wavelength, a first phosphor layer containing a first phosphor that converts the excitation light into first converted light of a second wavelength longer than the first wavelength, a second phosphor layer provided between the light-emitting element and the first phosphor layer, receiving the excitation light, and containing a second phosphor that converts the excitation light into second converted light of a third wavelength longer than the second wavelength, and a filter layer provided between the first phosphor layer and the second phosphor layer and constituted of a two-dimensional photonic crystal or a three-dimensional photonic crystal that transmits the excitation light and the second converted light and reflects the first converted light. | 2012-09-13 |
20120228654 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor light emitting device includes a structure including a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a light emitting layer provided between the first semiconductor layer and the second semiconductor layer. The device also includes an electrode layer provided on the second semiconductor layer side of the structure. The electrode layer includes a metal portion with a thickness of not less than 10 nanometers and not more than 100 nanometers. A plurality of openings pierces the metal portion, each of the openings having an equivalent circle diameter of not less than 10 nanometers and not more than 5 micrometers. The device includes an inorganic film providing on the metal portion and inner surfaces of the openings, the inorganic film having transmittivity with respect to light emitted from the light emitting layer. | 2012-09-13 |
20120228655 | LIGHT EMITTING DIODE WITH LARGE VIEWING ANGLE AND FABRICATING METHOD THEREOF - A light emitting diode includes a substrate, a plurality of pillar structures, a filler structure, a transparent conductive layer, a first electrode, and a second electrode. These pillar structures are formed on the substrate. Each of the pillar structures includes a first type semiconductor layer, an active layer, and a second type semiconductor layer. The first type semiconductor layers are formed on the substrate. The pillar structures are electrically connected with each other through the first type semiconductor layers. The filler structure is formed between the pillar structures. The filler structure and the second type semiconductor layers of the pillar structures are covered with the transparent conductive layer. The first electrode is in contact with the transparent conductive layer. The second electrode is in contact with the first type semiconductor layer. | 2012-09-13 |
20120228656 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - [PROBLEM] A light extraction efficiency increases by suppressing a reflection of a semiconductor layer and a transparent substrate. | 2012-09-13 |
20120228657 | Light-Emitting Element and Light-Emitting Device - To provide a light-emitting element or a light-emitting device in which power is not consumed wastefully even if a short-circuit failure occurs. The present invention focuses on heat generated due to a short-circuit failure which occurs in a light-emitting element. A fusible alloy which is melted at temperature T | 2012-09-13 |
20120228658 | SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING ELEMENT - There is provided a light-emitting element having a semiconductor film which includes a p-type current-spreading layer of GaInP or GaP; a first p-clad of AlInP; a second p-clad of AlGaInP; an active layer including of GaInP or AlGaInP; a first n-clad having a carrier density of 1×10 | 2012-09-13 |
20120228659 | LIGHT-EMITTING DIODE WITH METAL STRUCTURE AND HEAT SINK - A light-emitting diode has a metal structure, a light-emitting chip, and a bowl structure. The metal structure has a platform and a heat sink. The platform has a top face, a first side, and a second side opposite to the first side. A first reflector and a second reflector respectively extend from the first side and the second side. The heat sink extends below the top face and has a drop from the bottom surfaces of the first reflector and the second reflector. The light-emitting chip is disposed on the top face. The bowl structure covers the outer surface of the metal structure and shields the bottom surfaces of the first reflector and the second reflector. A thermal dispassion surface of the heat sink is exposed from the bowl structure. An inner surface of bowl wall has a plurality of reflection structures to promote the light extraction efficiency. | 2012-09-13 |
20120228660 | METHOD OF MANUFACTURING LEAD FRAME FOR LIGHT-EMITTING DEVICE PACKAGE AND LIGHT-EMITTING DEVICE PACKAGE - A method of manufacturing a lead frame for a light-emitting device package and a light-emitting device package are provided. The method of manufacturing a lead frame for a light-emitting device package includes: preparing a base substrate for the lead frame; forming diffusion roughness on the base substrate; and forming a reflective plating layer on the diffusion roughness formed base substrate. A lead frame for a light-emitting device and a light-emitting device package having a wide viewing angle and a wide radiation width by surface processing are provided. | 2012-09-13 |
20120228661 | SEMICONDUCTOR DEVICE - External light is reflected due to a difference in refractive indices of a black matrix and a glass substrate. When the black matrix is a black resin, there is a difference in refractive indices of the black resin and a first substrate. Also, there is a difference in refractive indices of the colored layer and the first substrate. Therefore, external light is slightly reflected. There is a problem in that the reflected light reduces contrast. A structure in which one polarizing element having dichroism is interposed between a pair of substrates is employed, and a light interference layer is provided between a color filter and a glass substrate, whereby a difference in refractive indices is moderated to reduce light reflection. | 2012-09-13 |
20120228662 | LIGHT EMITTING DEVICE - The light emitting device according to the present invention includes a resin molded body having a recess, a first electrically conductive member and a second electrically conductive member each having terminal portions respectively exposed from a first outer side surface and second outer side surface which are opposite outer side surfaces among the outer side surfaces of the resin molded body, and a light emitting element mounted on the first electrically conductive member exposed at a bottom surface of the recess. The recess has a first bottom surface on which the light emitting element is mounted and a second bottom surface arranged at a higher position of the outer periphery of the first bottom surface. | 2012-09-13 |
20120228663 | Optoelectronic Component Having a Semiconductor Body, an Insulating Layer, and a Planar Conductor Structure, and Method for the Production thereof - An optoelectronic component comprising at least one semiconductor body having a radiation exit side, said semiconductor body being arranged by a side lying opposite the radiation exit side on a substrate, wherein at least one electrical connection region, on which a metallization bump is arranged, is arranged on the radiation exit side, the semiconductor body is at least partly provided with an insulating layer, wherein the metallization bump projects beyond the insulating layer, and at least one planar conductor structure is arranged on the insulating layer for the purpose of making contact with the semiconductor body in planar fashion, said conductor structure being electrically conductively connected to the electrical connection region by the metallization bump. | 2012-09-13 |
20120228664 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention provides a nitride semiconductor light emitting device having an n-electrode that has an Au face excellent in ohmic contacts to an n-type nitride semiconductor and excellent in mounting properties, and a method of manufacturing the same. The nitride semiconductor light emitting device uses an n-electrode having a three-layer laminate structure that is composed of a first layer containing aluminum nitride and having a thickness not less than 1 nm or less than 5 nm, a second layer containing one or more metals selected from Ti, Zr, Hf, Mo, and Pt, and a third layer made of Au, from the near side of the n-type nitride semiconductor in order of mention. The n-electrode thus formed is then annealed to obtain ohmic contacts to the n-type nitride semiconductor. | 2012-09-13 |
20120228665 | METHOD OF MANUFACTURING GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - Provided are a method of manufacturing a gallium nitride-based compound semiconductor light-emitting device with a low driving voltage (VI) and high light outcoupling efficiency, a gallium nitride-based compound semiconductor light-emitting device, and a lamp. In the method of manufacturing the gallium nitride-based compound semiconductor light-emitting device, a transparent conductive oxide film ( | 2012-09-13 |
20120228666 | Optoelectronic Module - An optoelectronic module has at least one carrier with at least one contact location. A semiconductor chip emitting radiation includes a first contact surface and a second contact surface. An electrically insulating layer has a first and a second recess. The first contact surface is disposed on the side of the semiconductor chip emitting radiation facing away from the carrier. The electrically insulating layer is applied at least in places to the carrier. The semiconductor chip includes the first recess in the area of the first contact surface and the second recess in the area of the contact location. A electrically conductive conductor structure is disposed on the electrically insulating layer. The first contact surface electrically contacts the contact location of the carrier. The electrically insulating layer is formed predominately from a ceramic material. | 2012-09-13 |
20120228667 | STRENGTHENED COUNTER ELECTRODE OF ELECTROLUMINESCENT DEVICES - The present invention provides an electroluminescent device comprising a substrate (1) and stacked thereon in the order of mention a first transparent electrode (2), an electroluminescent stack (3), and a second electrode (4). Furthermore, the electroluminescent device comprises at least one additional hard layer (5) that is located underneath the second electrode and/or on top of the second electrode and that has a hardness larger than the hardness of the second electrode. Methods for the production of such electroluminescent devices are likewise provided. | 2012-09-13 |
20120228668 | Layered Element for Encapsulating a Sensitive Element - This layered element ( | 2012-09-13 |
20120228669 | HIGH-YIELD FABRICATION OF LARGE-FORMAT SUBSTRATES WITH DISTRIBUTED, INDEPENDENT CONTROL ELEMENTS - A large-format substrate with distributed control elements is formed by providing a substrate and a wafer, the wafer having a plurality of separate, independent chiplets formed thereon; imaging the wafer and analyzing the wafer image to determine which of the chiplets are defective; removing the defective chiplet(s) from the wafer leaving remaining chiplets in place on the wafer; printing the remaining chiplet(s) onto the substrate forming empty chiplet location(s); and printing additional chiplet(s) from the same or a different wafer into the empty chiplet location(s). | 2012-09-13 |
20120228670 | OPTICAL SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD OF THE SAME - An optical semiconductor element and a manufacturing method thereof that can improve the light extraction efficiency with maintaining the yield. The manufacturing method includes forming a plurality of recesses arranged at equal intervals along a crystal axis of a semiconductor film in a surface of the semiconductor film; and performing an etching process on the surface of the semiconductor film, thereby forming a plurality of protrusions arranged according to the arrangement form of the plurality of recesses and deriving from the crystal structure of the semiconductor film in the surface of the semiconductor film. | 2012-09-13 |
20120228671 | STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME - A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a SiN stress cap layer covering the gate stack to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided. | 2012-09-13 |
20120228672 | METHOD FOR FORMING A GE ON III/V-ON-INSULATOR STRUCTURE - The present invention concerns a method for forming a Semiconductor-On-Insulator structure that includes a semiconductor layer of III/V material by growing a relaxed germanium layer on a donor substrate; growing at least one layer of III/V material on the layer of germanium; forming a cleaving plane in the relaxed germanium layer; transferring a cleaved part of the donor substrate to a support substrate, with the cleaved part being a part of the donor substrate cleaved at the cleaving plane that includes the at least one layer of III/V material. The present invention also concerns a germanium on III/V-On-Insulator structure, a N Field-Effect Transistor (NFET), a method for manufacturing a NFET, a P Field-Effect Transistor (PFET), and a method for manufacturing a PFET. | 2012-09-13 |
20120228673 | FIELD-EFFECT TRANSISTOR, SEMICONDUCTOR WAFER, METHOD FOR PRODUCING FIELD-EFFECT TRANSISTOR AND METHOD FOR PRODUCING SEMICONDUCTOR WAFER - Provided is a field-effect transistor including a gate insulating layer, a first semiconductor crystal layer in contact with the gate insulating layer, and a second semiconductor crystal layer lattice-matching or pseudo lattice-matching the first semiconductor crystal layer. Here, the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer are arranged in the order of the gate insulating layer, the first semiconductor crystal layer, and the second semiconductor crystal layer, the first semiconductor crystal layer is made of In | 2012-09-13 |
20120228674 | SEMICONDUCTOR DEVICE, FIELD-EFFECT TRANSISTOR, AND ELECTRONIC DEVICE - Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon. | 2012-09-13 |
20120228675 | HIGH TEMPERATURE PERFORMANCE CAPABLE GALLIUM NITRIDE TRANSISTOR - A transistor device capable of high performance at high temperatures. The transistor comprises a gate having a contact layer that contacts the active region. The gate contact layer is made of a material that has a high Schottky barrier when used in conjunction with a particular semiconductor system (e.g., Group-III nitrides) and exhibits decreased degradation when operating at high temperatures. The device may also incorporate a field plate to further increase the operating lifetime of the device. | 2012-09-13 |
20120228676 | CHANNEL SURFACE TECHNIQUE FOR FABRICATION OF FinFET DEVICES - A FinFET (p-channel) device is formed having a fin structure with sloped or angled sidewalls (e.g., a pyramidal or trapezoidal shaped cross-section shape). When using conventional semiconductor substrates having a (100) surface orientation, the fin structure is formed in a way (groove etching) which results in sloped or angled sidewalls having a (111) surface orientation. This characteristic substantially increases hole mobility as compared to conventional fin structures having vertical sidewalls. | 2012-09-13 |
20120228677 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method for producing a semiconductor device includes a step of forming a conductor layer and a first semiconductor layer containing a donor impurity or an acceptor impurity on a first semiconductor substrate; a step of forming a second insulating layer so as to cover the first semiconductor layer; a step of thinning the first semiconductor substrate to a predetermined thickness; a step of forming, from the first semiconductor substrate, a pillar-shaped semiconductor having a pillar-shaped structure on the first semiconductor layer; a step of forming a first semiconductor region in the pillar-shaped semiconductor by diffusing the impurity from the first semiconductor layer; and a step of forming a pixel of a solid-state imaging device with the pillar-shaped semiconductor into which the impurity has been diffused. | 2012-09-13 |
20120228678 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to an embodiment of a semiconductor device and a method of manufacturing the same, buried gates are formed in a semiconductor substrate including a cell region and a peripheral region, with the cell region and the peripheral region formed to have a step therebetween. Next, a spacer is formed in a region between the cell region and the peripheral region to block an oxidation path between a gate oxide layer and another insulating layer. Embodiments may reduce damage to active regions and prevent IDD failure because a gate pattern is formed on a guard region provided at a periphery of the cell region. | 2012-09-13 |
20120228679 | METHOD FOR PROTECTING A GATE STRUCTURE DURING CONTACT FORMATION - Various methods for protecting a gate structure during contact formation are disclosed. An exemplary method includes: forming a gate structure over a substrate, wherein the gate structure includes a gate and the gate structure interposes a source region and a drain region disposed in the substrate; patterning a first etch stop layer such that the first etch stop layer is disposed on the source region and the drain region; patterning a second etch stop layer such that the second etch stop layer is disposed on the gate structure; and forming a source contact, a drain contact, and a gate contact, wherein the source contact and the drain contact extend through the first etch stop layer and the gate contact extends through the second etch stop layer, wherein the forming the source contact, the drain contact, and the gate contact includes simultaneously removing the first etch stop layer and the second etch stop layer to expose the gate, source region, and drain region. | 2012-09-13 |
20120228680 | FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SAME - Current drive efficiency is deteriorated in the conventional FET. The FET | 2012-09-13 |
20120228681 | IMAGE AND LIGHT SENSOR CHIP PACKAGES - An image or light sensor chip package includes an image or light sensor chip having a non-photosensitive area and a photosensitive area surrounded by the non-photosensitive area. In the photosensitive area, there are light sensors, a layer of optical or color filter array over the light sensors and microlenses over the layer of optical or color filter array. In the non-photosensitive area, there are an adhesive polymer layer and multiple metal structures having a portion in the adhesive polymer layer. A transparent substrate is formed on a top surface of the adhesive polymer layer and over the microlenses. The image or light sensor chip package also includes wirebonded wires or a flexible substrate bonded with the metal structures of the image or light sensor chip. | 2012-09-13 |
20120228682 | FIELD-EFFECT TRANSISTOR, FIELD-EFFECT TRANSISTOR MANUFACTURING METHOD, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - According to the present disclosure, it is possible to further miniaturize the gate electrode of the field-effect transistor. The field-effect transistor includes a substrate; a semiconductor layer configured to be formed on the substrate and have a fin region formed thereon with a source region and a drain region formed at both ends of the fin region; and a gate electrode configured to have a convex portion partially in contact with at least two faces of the fin region. | 2012-09-13 |
20120228683 | SPIN DEVICE, AND MAGNETIC SENSOR AND SPIN FET USING THE SAME - This spin device includes a semiconductor layer | 2012-09-13 |
20120228684 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A transistor is formed on a semiconductor substrate, and thereafter a first insulating film is formed. Subsequently, a ferroelectric capacitor is formed on the first insulating film, and then a second insulating film is formed on the ferroelectric capacitor. Thereafter, the upper surface of the second insulating film is planarized. Subsequently, a contact hole which reaches one of impurity regions of the transistor is formed, and thus a plug is formed by embedding a conductor in the contact hole. Thereafter, a hydrogen barrier layer is formed of aluminum oxide or the like. Then, a third insulating film is formed on the hydrogen barrier layer. Subsequently, contact holes which are connected to the ferroelectric capacitor and the plug are formed. Thereafter, a conductor is embedded in the contact holes, and thus interconnections are formed. | 2012-09-13 |
20120228685 | MAGNETIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A magnetic memory device and a method for manufacturing the same are disclosed. The magnetic memory device includes a plurality of gates formed on a semiconductor substrate, a source line connected to a source/drain region shared between the gates neighboring with each other, a plurality of magnetic tunnel junctions connected to non-sharing source/drain regions of the gates on a one-to-one basis, and a bit line connected to the magnetic tunnel junctions. The magnetic memory device applies a magnetic memory cell to a memory so as to manufacture a higher-integration magnetic memory, and uses the magnetic memory cell based on a transistor of a DRAM cell, resulting in an increase in the availability of the magnetic memory. | 2012-09-13 |
20120228686 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including, on the same semiconductor substrate, a transistor element, a capacitor, and a resistor. The capacitor is formed on an active region, and the resistor is formed on an element isolation region, both formed of the same polysilicon film. By CMP or etch-back, the surface is ground down while planarizing the surface until a resistor has a desired thickness. Owing to a difference in height between the active region and the element isolation region, a thin resistor and a thick upper electrode of the capacitor are formed to prevent passing through of a contact. | 2012-09-13 |
20120228687 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor film; a first gate insulating film covering the semiconductor film; a first gate electrode provided over the semiconductor film with the first gate insulating film interposed therebetween; a first conductive film which is provided over the first gate insulating film; an insulating film which is provided over the first gate insulating film, exposes top surfaces of the first gate electrode and the first conductive film, and has a groove portion between the first gate electrode and the first conductive film; an oxide semiconductor film which is provided over the insulating film and is in contact with the first gate electrode, the first conductive film, and the groove portion; a second gate insulating film covering the oxide semiconductor film; and a second gate electrode provided over the oxide semiconductor film and the groove portion with the second gate insulating film interposed therebetween. | 2012-09-13 |
20120228688 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as a cell transistor of a memory element in a memory device. Moreover, in order to reduce the area of a memory cell, the transistor is formed so that its source and drain are stacked in the vertical direction in a region where a bit line and a word line intersect each other. Further, a capacitor is stacked above the transistor. | 2012-09-13 |
20120228689 | WAFER WITH INTRINSIC SEMICONDUCTOR LAYER - The present invention relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The invention also relates to the wafer that is produced by the new method. | 2012-09-13 |
20120228690 | SEMICONDUCTOR DEVICE - To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner. | 2012-09-13 |
20120228691 | PN FLOATING GATE NON-VOLATILE STORAGE ELEMENT - Non-volatile storage elements having a PN floating gate are disclosed herein. The floating gate may have a P− region near the tunnel oxide, and may have an N+ region near the control gate. In some embodiments, a P− region near the tunnel oxide helps provide good data retention. In some embodiments, an N+ region near the control gate helps to achieve a good coupling ratio between the control gate and floating gate. Therefore, programming of non-volatile storage elements is efficient. Also erasing the non-volatile storage elements may be efficient. In some embodiments, having a P− region near the tunnel oxide (as opposed to a strongly doped p-type semiconductor) may improve erase efficiency relative to P+. | 2012-09-13 |
20120228692 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a plurality of stacked patterns where a tunnel insulation layer, a floating gate, and a dielectric layer are sequentially stacked over a substrate, trenches formed in the substrate between the stacked patterns, an isolation layer gap-filling the trenches and space between the stacked patterns, and a control gate formed over the dielectric layer. | 2012-09-13 |
20120228693 | Highly Reliable NAND Flash memory using a five side enclosed Floating gate storage elements - A NAND flash memory system with an array of individual charge storage elements, such as floating gates, arranged in a NAND string, each element being capable of selectively storing data in the form of charge there-in during a program or an erase operation, and during a read operation sensing the quantum of charge stored to provide reconstruction of data. Such a memory made with a floating gate that is spaced away from the diffusions and covered on all five sides except the channel side, by the control gate, there by having increased coupling with the associated advantage of lower high voltages, reduced impact of the unwanted disturb conditions, and providing for improved retention and reliability characteristics at higher operating temperatures is disclosed. The main emphasis in this technology is to provide a device with improved retention, endurance, and temperature characteristics meeting the Automotive specifications even with some area penalty. | 2012-09-13 |
20120228694 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device according to an embodiment, includes a dielectric film and an Si semiconductor part. The dielectric film is formed by using one of oxide, nitride and oxynitride. The Si semiconductor part is arranged below the dielectric film, having at least one element of sulfur (S), selenium (Se), and tellurium (Te) present in an interface with the dielectric film, and formed by using silicon (Si). | 2012-09-13 |
20120228695 | LDMOS WITH IMPROVED BREAKDOWN VOLTAGE - An LDMOS is formed with a field plate over the n | 2012-09-13 |
20120228696 | STACKED DIE POWER CONVERTER - A stacked die power converter package includes a lead frame including a die pad and a plurality of package pins, a first die including a first power transistor switch (first power transistor) attached to the die pad, and a first metal clip attached to one side of the first die. The first metal clip is coupled to at least one package pin. A second die including a second power transistor switch (second power transistor) is attached to another side on the first metal clip. A controller is provided by a controller die attached to a second metal clip on one side of the second die, a controller die attached to the second die, or the controller is integrated on the second die. The controller is coupled to both a first control node of the first power transistor and a second control node of the second power transistor. | 2012-09-13 |
20120228697 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device having a vertical structure and a method of manufacturing the same, the nonvolatile memory device including a channel region that vertically extends from a substrate; gate electrodes on the substrate, the gate electrodes being disposed along an outer side wall of the channel region and spaced apart from one another; and a channel pad that extends from one side of the channel region to an outside of the channel region, the channel pad covering a top surface of the channel region. | 2012-09-13 |
20120228698 | VERTICAL COMPLEMENTARY FET - A vertical complementary field effect transistor (FET) relates to the production technology of semiconductor chips and more particularly to the production technology of power integration circuit. A part of the substrate bottom of the invention extends into the middle layer and form the plug between the two MOS units. There is an output terminal under the substrate layer. When on-state voltage is applied on the gate electrode of the two MOS units, two conduction paths are formed from MOS unit-plug-substrate to the output terminal. This technology can integrate more than two MOS devices. Therefore, the die size is reduced. | 2012-09-13 |
20120228699 | METHODS FOR FABRICATING TRANSISTORS INCLUDING ONE OR MORE CIRCULAR TRENCHES - A transistor and a method of fabricating a transistor, including a metal oxide deposited on an epitaxial layer, a photo resist deposited and patterned over the metal oxide and the metal oxide and epitaxial layer are etched to form at least one circular trench, wherein the trench surfaces are defined by the epitaxial layer. An oxide layer is grown on the trench surfaces of each trench, and a gate conductor is formed within the at least one trench. | 2012-09-13 |
20120228700 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: an N-type drift layer; a P-type anode layer on the N-type drift layer; a trench penetrating the P-type anode layer; a conductive substance embedded in the trench via an insulating film; and an N-type buffer layer between the N-type drift layer and the P-type anode layer and having impurity concentration which is higher than that of the N-type drift layer. | 2012-09-13 |
20120228701 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In accordance with an embodiment, a semiconductor device includes a semiconductor layer of a first conductivity type with a recess in the surface of the semiconductor layer, a pocket region of the first conductivity type in the semiconductor layer, a source region of a second conductivity type in the semiconductor layer, a drain region of the first conductivity type in the semiconductor layer, a gate insulating film over the surface of the recess, and a gate electrode. The second conductivity type is different from the first conductivity type. The pocket region includes a part under the surface of the recess. The source region is located adjacent to the pocket region. The drain region is located away from the source region and the pocket region. The gate electrode is configured to fill the recess via the gate insulating film. | 2012-09-13 |
20120228702 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a semiconductor substrate having a groove and an active region adjacent to the groove; a buried gate electrode in the groove; and a capacitive contact including a first portion and a second portion over the first portion. The first portion is greater in horizontal dimension than the second portion. The first portion has a bottom surface that is in contact with an upper surface of the active region. | 2012-09-13 |
20120228703 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, and an insulating member. The semiconductor substrate has a trench formed in a top surface. The insulating member is provided in the trench. A space is formed between the semiconductor substrate and the insulating member. | 2012-09-13 |
20120228704 | High-Voltage MOSFET with High Breakdown Voltage and Low On-Resistance and Method of Manufacturing the Same - A high-voltage transistor is formed in a deep well of a first conductivity type that has been formed in a semiconductor substrate or epitaxial layer of a second conductivity type. A body region of the second conductivity type is formed in the deep well, into which a source region of the first conductivity type is formed. A drain region of the first conductivity type is formed in the deep well and separated from the body region by a drift region in the deep well. A gate dielectric layer is formed over the body region, and a first polysilicon layer formed over the gate dielectric layer embodies the gate of the transistor. The field plate dielectric layer is formed over the drift region after the gate has been formed. Finally, the field plate dielectric is covered by a second polysilicon layer having a field plate positioned over the field plate dielectric layer in the drift region. | 2012-09-13 |
20120228705 | LDMOS WITH IMPROVED BREAKDOWN VOLTAGE - An LDMOS is formed with a second gate stack over the n | 2012-09-13 |
20120228706 | SEMICONDUCTOR DEVICE - A memory includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. A first channel region of a first conductivity type is provided on a surface of the semiconductor layer below the gate insulating film. A diffusion layer of a second conductivity type is provided below the first channel region in the semiconductor layer. The diffusion layer contacts a bottom of the first channel region in a direction substantially vertical to a surface of the semiconductor layer. The diffusion layer forms a PN junction with the bottom of the first channel region. A drain of a first conductivity type and a source of a second conductivity type are provided on a side and another side of the first channel region. A sidewall film covers a side surface of the first channel region on a side of the diffusion layer. | 2012-09-13 |
20120228707 | STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME - A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a plurality of shallow trench isolation structures extending into the silicon substrate and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided. | 2012-09-13 |
20120228708 | STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME - A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer; and a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region, in which the source and the drain are a Si | 2012-09-13 |
20120228709 | INTEGRATED CIRCUIT STRUCTURE INCORPORATING ONE OR MORE ASYMMETRIC FIELD EFFECT TRANSISTORS AS POWER GATES FOR AN ELECTRONIC CIRCUIT WITH STACKED SYMMETRIC FIELD EFFECT TRANSISTORS - Disclosed is an integrated circuit having an asymmetric FET as a power gate for an electronic circuit, which has at least two stacked symmetric field effect transistors. The asymmetric FET has an asymmetric halo configuration (i.e., a single source-side halo or a source-side halo with a higher dopant concentration than a drain-side halo) and an asymmetric source/drain extension configuration (i.e., the source extension can be overlapped to a greater extent by the gate structure than the drain extension and/or the source extension can have a higher dopant concentration than the drain extension). As a result, the asymmetric FET has a low off current. In operation, the asymmetric FET is turned off when the electronic circuit is placed in a standby state and, due to the low off current (Ioff), effectively reduces standby leakage current from the electronic circuit. Additionally, avoiding the use of stacked asymmetric field effect transistors within the electronic circuit itself prevents performance degradation due to reduced linear drain current (Idlin). | 2012-09-13 |
20120228710 | Castellated gate MOSFET tetrode capable of fully-depleted operation - A method of fabricating a castellated-gate MOSFET tetrode device capable of fully depleted operation is disclosed. The device is formed on a semiconductor substrate region having an upper portion with a top surface and a lower portion with a bottom surface. A source region and a drain region are formed by ion implantation into the semiconductor substrate region, with adjoined primary and secondary channel-forming regions also disposed therein between the source and drain regions, thereby forming an integrated cascode structure. A plurality of thin semiconductor channel elements are formed by etching a plurality of spaced gate slots to a first predetermined depth into the substrate. The formation of first, second, and additional gate structures are described in two possible embodiments which facilitate the formation of self-aligned source and drain regions. | 2012-09-13 |
20120228711 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region . It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer , step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region , step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region. | 2012-09-13 |
20120228712 | NONVOLATILE MEMORY DEVICES - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays. | 2012-09-13 |
20120228713 | THREE-DIMENSIONAL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE - A three-dimensional complementary metal oxide semiconductor device comprises a bottom wafer having a first-type strained MOS transistor; a top wafer stacked on the bottom wafer face to face or face to back, having a second-type strained MOS transistor arranged opposite to the first-type strained MOS transistor, and having a plurality of metal pads and a plurality of TSVs connected to the metal pads; and a hybrid bonding layer arranged between the bottom wafer and the top wafer, having metallic-bonding areas connecting the first-type and second-type MOS transistors to TSVs and a non-metallic bonding area filled in all space except the metallic bonding areas, so as to bond the bottom and top wafers. | 2012-09-13 |
20120228714 | SRAM CELLS USING SHARED GATE ELECTRODE CONFIGURATION - An SRAM cell includes a first PMOS pass transistor comprising a first gate electrode disposed on a first PMOS active region, a first NMOS pass transistor comprising a second gate electrode disposed on a first NMOS active region, a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween, a second PMOS pass transistor comprising a fourth gate electrode disposed on a second PMOS active region, a second NMOS pass transistor comprising a fifth gate electrode disposed on a second NMOS active region and a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween. | 2012-09-13 |
20120228715 | ENGINEERED OXYGEN PROFILE IN METAL GATE ELECTRODE AND NITRIDED HIGH-K GATE DIELECTRICS STRUCTURE FOR HIGH PERFORMANCE PMOS DEVICES - A PMOS transistor is disclosed which includes a nitrogen containing barrier to oxygen diffusion between a gate dielectric layer and a metal gate in the PMOS transistor, in combination with a low oxygen region of the metal gate in direct contact with the nitrogen containing barrier and an oxygen rich region of the metal gate above the low oxygen content metal region. The nitrogen containing barrier may be formed by depositing nitrogen containing barrier material on the gate dielectric layer or by nitridating a top region of the gate dielectric layer. The oxygen rich region of the metal gate may be formed by depositing oxidized metal on the low oxygen region of the metal gate or by oxidizing a top region of the low oxygen region of the metal gate. | 2012-09-13 |
20120228716 | METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE - A structure including an NFET having an embedded silicon germanium (SiGe) plug in a channel of the NFET; a PFET having a SiGe channel; and a trench isolation between the NFET and the PFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects. | 2012-09-13 |
20120228717 | SCHOTTKY DIODE AND METHOD OF MANUFACTURE - A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells ( | 2012-09-13 |
20120228718 | METHOD OF FORMING AN ELECTRICAL FUSE AND A METAL GATE TRANSISTOR AND THE RELATED ELECTRICAL FUSE - The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method simultaneously forms a dummy gate stack of a transistor and a dummy gate stack of an e-fuse; and simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region. Thereafter, the work function metal layer disposed in the opening of the e-fuse region is removed; and the opening in the transistor region and the opening in the e-fuse region with metal conductive structures are filled to form an e-fuse and a metal gate of a transistor. | 2012-09-13 |
20120228719 | SEMICONDUCTOR DEVICE WITH RESISTANCE CIRCUIT - Provided is a resistance circuit having a resistance element with high resistance and high accuracy. An insulating film such as a silicon nitride film is formed on the resistance element made of a thin film material whose thickness is reduced to 500 Å or smaller. The insulating film prevents passing through of the contact hole arranged on the resistance element during etching for forming the contact hole. | 2012-09-13 |
20120228720 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS - Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas. | 2012-09-13 |
20120228721 | SEMICONDUCTOR DEVICE AND REFERENCE VOLTAGE GENERATION CIRCUIT - In a gate electrode ( | 2012-09-13 |
20120228722 | SRAM CELL WITH T-SHAPED CONTACT - An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. | 2012-09-13 |
20120228723 | GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure. | 2012-09-13 |
20120228724 | Non-Volatile Anti-Fuse With Consistent Rupture - In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped. | 2012-09-13 |
20120228725 | Multi-Stage Stopper System for MEMS Devices - A MEMS sensing system includes a movable mass having at least one contact surface, a stopper system for stopping the movement of the mass, the stopper system having at least one contact surface that contacts a corresponding contact surface of the mass if a sufficient movement of the mass occurs in a direction, at least one stopper gap formed between the at least one contact surface of the stopper system and the corresponding contact surface of the mass, and a spring system in communication with the at least one stopper gap. | 2012-09-13 |
20120228726 | MEMS AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a MEMS includes a first electrode, a first auxiliary structure and a second electrode. The first electrode is provided on a substrate. The first auxiliary structure is provided on the substrate and adjacent to the first electrode. The first auxiliary structure is in an electrically floating state. The second electrode is provided above the first electrode and the first auxiliary structure, | 2012-09-13 |
20120228727 | METHOD AND STRUCTURE FOR FORMING A GYROSCOPE AND ACCELEROMETER - A method for fabricating a micro electromechanical device includes providing a first substrate including control circuitry. The first substrate has a top surface and a bottom surface. The method also includes forming an insulating layer on the top surface of the first substrate, removing a first portion of the insulating layer so as to form a plurality of standoff structures, and bonding a second substrate to the first substrate. The method further includes thinning the second substrate to a predetermined thickness and forming a plurality of trenches in the second substrate. Each of the plurality of trenches extends to the top surface of the first substrate. Moreover, the method includes filling at least a portion of each of the plurality of trenches with a conductive material, forming the micro electromechanical device in the second substrate, and bonding a third substrate to the second substrate. | 2012-09-13 |
20120228728 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device in which MRAM is formed in a wiring layer A contained in a multilayered wiring layer, the MRAM having at least two first magnetization pinning layers in contact with a first wiring formed in a wiring layer and insulated from each other, a free magnetization layer overlapping the two first magnetization pinning layers in a plan view, and connected with the first magnetization pinning layers, a non-magnetic layer situated over the free magnetization layer, and a second magnetization pinning layer situated over the non-magnetic layer. | 2012-09-13 |
20120228729 | STAGGERED MAGNETIC TUNNEL JUNCTION - A staggered magnetic tunnel junction includes a free magnetic layer extending in a lateral direction between a first end portion and an opposing second end portion and a tunneling barrier disposed between a reference magnetic layer and the first end portion and forming a magnetic tunnel junction. Current flows through the free magnetic layer in the lateral direction to switch the magnetic tunnel junction between a high resistance state and a low resistance state. | 2012-09-13 |
20120228730 | MICROCHIP AND SOI SUBSTRATE FOR MANUFACTURING MICROCHIP - A plasma treatment or an ozone treatment is applied to the respective bonding surfaces of the single-crystal Si substrate in which the ion-implanted layer has been formed and the quartz substrate, and the substrates are bonded together. Then, a force of impact is applied to the bonded substrate to peel off a silicon thin film from the bulk portion of single-crystal silicon along the hydrogen ion-implanted layer, thereby obtaining an SOI substrate having an SOI layer on the quartz substrate. A concave portion, such as a hole or a micro-flow passage, is formed on a surface of the quartz substrate of the SOI substrate thus obtained, so that processes required for a DNA chip or a microfluidic chip are applied. A silicon semiconductor element for the analysis/evaluation of a sample attached/held to this concave portion is formed in the SOI layer. | 2012-09-13 |
20120228731 | METHOD FOR FORMING A COMPOUND SEMI-CONDUCTOR THIN-FILM - A method is provided for fabricating a thin film semiconductor device. The method includes providing a plurality of raw semiconductor materials. The raw semiconductor materials undergo a pre-reacting process to form a homogeneous compound semiconductor target material. The compound semiconductor target material is deposited onto a substrate to form a thin film having a composition substantially the same as a composition of the compound semiconductor target material. | 2012-09-13 |
20120228732 | PHOTOELECTRIC CONVERSION DEVICE AND MANUFACTURING METHOD THEREOF - A photoelectric conversion device including a first substrate; a second substrate located generally opposite to the first substrate; a first grid pattern located on the first substrate, wherein the first grid pattern includes a first finger electrode; a first collector electrode spaced from the first finger electrode and extending in a direction that intersects the first finger electrode; and a first connecting electrode connecting the first finger electrode and the first collector electrode; and a second grid pattern located on the second substrate, wherein the second grid pattern includes a second finger electrode; a second collector electrode spaced from the second finger electrode and extending in a direction that intersects the second finger electrode; and a second connecting electrode connecting the second finger electrode and the second collector electrode, wherein the first connecting electrode and the second connecting electrode are arranged alternately and do not overlap each other. | 2012-09-13 |
20120228733 | MEMS-BASED GETTER MICRODEVICE - A MEMS (micro-electro-mechanical system) getter microdevice for controlling the ambient pressure inside the hermetic packages that enclose various types of MEMS, photonic, or optoelectronic devices. The getter microdevice revolves around a platform suspended at a height above a substrate, and which is supported by supporting legs having low thermal conductance. Layers are deposited on the platform, such layers including a properly patterned resistor element, a heat-spreading layer and, finally, a thin-film getter material. When an electrical current flows through it, the resistor element heats the thin-film getter material until it reaches its activation temperature. The getter material then absorbs the gas species that could be present in the hermetic package, such gas species possibly impairing the operation of the devices housed in the packages while reducing their lifetime. The weak thermal conductance between the platform and the substrate helps in preventing damages to the surrounding devices when the MEMS getter microdevice is heated at its activation temperature, and it reduces the electrical power required for reaching the activation temperature as well. | 2012-09-13 |
20120228734 | HIGH BREAKDOWN VOLTAGE SEMICONDUCTOR RECTIFIER - A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor. | 2012-09-13 |
20120228735 | FUSE PATTERNS AND METHOD OF MANUFACTURING THE SAME - The present invention provides fuse patterns and a method of manufacturing the same. According to the present invention, an insulating layer and a contact plug are filled between fuse patterns which are formed to have their ends broken and are isolated from each other. In case of a fail cell, the insulating layer is broken owing a difference in an electrical bias (current or voltage) between a metal wire and the fuse patterns, and a short is generated between the fuse patterns. Accordingly, embodiments avoid damage to a semiconductor substrate associated with a conventional fuse repair method employing laser energy, and the area of a fuse box can be reduced. | 2012-09-13 |
20120228736 | TECHNIQUE TO CREATE A BURIED PLATE IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE - A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench. | 2012-09-13 |
20120228737 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a power supply line connected to a power supply terminal, a ground line connected to a ground terminal and a plurality of capacitors connected in parallel between the power supply line and the ground line. The plurality of capacitors include a first capacitor arranged at a first distance from one of the terminals and a second capacitor arranged at a second distance which is larger than the first distance from the one of the terminals, and the first capacitor has a larger area than the second capacitor. | 2012-09-13 |
20120228738 | PROTECTING ELEMENT - With a microwave FET, an incorporated Schottky junction capacitance or PN junction capacitance is small and such a junction is weak against static electricity. However, with a microwave device, the method of connecting a protecting diode cannot be used since this method increases the parasitic capacitance and causes degradation of the high-frequency characteristics. In order to solve the above problems, a protecting element, having a first n | 2012-09-13 |
20120228739 | HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS - An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate. | 2012-09-13 |
20120228740 | SEMICONDUCTOR DEVICE - A semiconductor device including a substrate, an insulation film being embedded into the substrate and having multiple openings, multiple dummy diffusion layers formed in the substrate and located in the openings, multiple resistance elements being formed over the insulation film so as not to overlap the dummy diffusion layers in a plan view in a resistance element forming region and extending in a first direction, and multiple dummy resistance elements being formed over the insulation film and the dummy diffusion layers and extending in the first direction in the resistance element forming region, in which each of the dummy resistance elements overlaps at least two dummy diffusion layers aligning in a second direction perpendicular to the first direction in a plane horizontal to the substrate in a plan view. | 2012-09-13 |
20120228741 | POWER MODULE - A power module includes a first semiconductor device having a collector terminal and an emitter terminal which extend outwardly from a molded resin, wherein at least one of the collector and emitter terminals is a bilaterally extending terminal extending outwardly from two opposite surfaces of the molded resin, and a second semiconductor device having the same construction as the first semiconductor device. The bilaterally extending terminal of the first semiconductor device is connected to a bilaterally extending terminal of the second semiconductor device. | 2012-09-13 |
20120228742 | METHODS FOR FORMING ARRAYS OF SMALL, CLOSELY SPACED FEATURES - Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. | 2012-09-13 |
20120228743 | Methods of Manufacturing Semiconductor Devices and Optical Proximity Correction - Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined. | 2012-09-13 |
20120228744 | WAFER AND METHOD OF MANUFACTURING PACKAGE PRODUCT - To provide a wafer in which out-gas emitted between wafers during bonding of the wafers can be easily discharged to the outside and the bonded wafers can be favorably cut to improve the yields, and a method of manufacturing a package product using the wafer. A groove portion is formed in a wafer for lid substrate along a plurality of imaginary straight lines passing through a center in a diameter direction of the wafer for lid substrate and extending in the diameter direction. The groove portion is divided into a plurality of groove portions in the diameter direction placed such that the groove portions are not in contact with each other. | 2012-09-13 |
20120228745 | SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor package structure and a manufacturing method thereof are provided. The semiconductor package structure includes a semiconductor die, a thermally conductive film, a substrate, a plurality of electrically conductive film patterns, and at least one insulator. The thermally conductive film is disposed on the bottom of the semiconductor die. The substrate is substantially comprised of the electrically conductive material or semiconductor material. Furthermore, a first hole is disposed on and passed all the way through the substrate, and the semiconductor die is disposed in the first hole. The electrically conductive film patterns are disposed on the substrate, and not contacting with each other. In addition, the insulator is connected between the semiconductor die and the substrate. | 2012-09-13 |
20120228746 | SEMICONDUCTOR DEVICE, FABRICATION PROCESS, AND ELECTRONIC DEVICE - A semiconductor device includes: a semiconductor substrate that includes a semiconductor; an electrode layer formed on a first surface side inside the semiconductor substrate; a frame layer laminated on the first surface of the semiconductor substrate; a conductor layer formed in an aperture portion formed by processing the semiconductor substrate and the frame layer in such a manner as to expose the electrode layer on the first surface of the semiconductor substrate; a vertical hole formed through the semiconductor substrate from a second surface of the semiconductor substrate to the conductor layer; and a wiring layer that is electrically connected to the electrode layer via the conductor layer at an end portion of the vertical hole, and that extends to the second surface of the semiconductor substrate. | 2012-09-13 |
20120228747 | RESIST PATTERN IMPROVING MATERIAL, METHOD FOR FORMING RESIST PATTERN, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - To provide a resist pattern improving material, containing: water; and benzalkonium chloride represented by the following general formula (1): | 2012-09-13 |
20120228748 | PASSIVATION LAYER SURFACE TOPOGRAPHY MODIFICATIONS FOR IMPROVED INTEGRITY IN PACKAGED ASSEMBLIES - A structure and method for producing the same is disclosed. The structure includes an organic passivation layer with solids suspended therein. Preferential etch to remove a portion of the organic material and expose portions of such solids creates enhanced surface roughness, which provides a significant advantage with respect to adhesion of that passivation layer to the packaging underfill material. | 2012-09-13 |
20120228749 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER SEMICONDUCTOR DIE MOUNTED TO TSV INTERPOSER - A semiconductor device has a plurality of conductive vias formed partially through a substrate. A conductive layer is formed over the substrate and electrically connected to the conductive vias. A semiconductor die is mounted over the substrate. An encapsulant is deposited over the semiconductor die and substrate. A trench is formed through the encapsulant around the semiconductor die. A shielding layer is formed over the encapsulant. The trench is formed partially through the substrate and the shielding layer is formed in the trench partially through the substrate. An insulating layer can be formed in the trench prior to forming the shielding layer. A portion of the substrate is removed to expose the conductive vias. An interconnect structure is formed over the substrate opposite the semiconductor die. The interconnect structure is electrically connected to the conductive vias. The shielding layer is electrically connected to the interconnect structure. | 2012-09-13 |
20120228750 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention includes a semiconductor chip having a front surface and a rear surface, a sealing resin layer stacked on the front surface of the semiconductor chip, a post passing through the sealing resin layer in the thickness direction and having a side surface flush with a side surface of the sealing resin layer and a forward end surface flush with a front surface of the sealing resin layer, and an external connecting terminal provided on the forward end surface of the post. | 2012-09-13 |