37th week of 2008 patent applcation highlights part 15 |
Patent application number | Title | Published |
20080217604 | Organic Semiconductor Film, Electron Device Using the Same and Manufacturing Method Therefor - An organic semiconductor film that can be used for an electron device, for example, particularly can be used for organic TFTs so as to allow the TFTs to have advanced performance, is provided and a manufacturing method therefor is provided. For instance, the organic semiconductor film contains the organic conductive high polymer compound such as polythiophene represented by the below formula (I). The organic semiconductor film is formed by forming a solution in a thin film form, the solution showing two or more spectral peaks (spectral state B) in a wavelength region of 300 to 800 nm by measurement using a visible and ultraviolet absorption spectral method; and drying the solution formed in the thin film form. Alternatively, the organic semiconductor film can be formed by the method in which the organic conductive high polymer compound has a molecular weight distribution range Mw/Mn from 1.00 to 1.85, obtained by dividing a weight-average molecular weight Mw by a number-average molecular weight Mn. With these methods, principal chains of the organic conductive high polymer compound molecules are arranged substantially in parallel, thus enhancing carrier mobility. | 2008-09-11 |
20080217605 | Oligomers and Polymers - An optionally substituted oligomer or polymer comprising a repeat unit of formula (I); wherein each Ar | 2008-09-11 |
20080217606 | Organic light emitting diode containing a Ir complex having a novel ligand as a phosphorescent emitter - An organic light emitting diode with Ir complex is disclosed in this specification, wherein the Ir complex is used as the phosphorous emitter. The chemical containing pyridyl triazole or pyridyl imidazole functional group is used as the auxiliary monoanionic bidentate ligand in the mentioned Ir complex, so that the CIE coordinate of the mentioned Ir complex is adjustable and the light emitting performance of the Ir complex is improved. | 2008-09-11 |
20080217607 | Protein Switches Incorporating Cytochrome C3 in Monolayers and Method for Producing Same - A biomolecular electronic switch includes a first electrical contact, a second electrical contact, a programmable monolayer of either cytochrome c or cytochrome c | 2008-09-11 |
20080217608 | Light-Emitting Element, Light-Emitting Device, Electronic Device and Quinoxaline Derivative - The present invention provides light-emitting element having long lifetime, and light-emitting devices and electronic devices having long lifetime. A light-emitting element comprises a first layer and a second layer including a light-emitting substance between a first electrode and a second electrode. The first layer includes a first organic compound and a second organic compound, the first layer is formed between the second layer and the second electrode, the first layer includes the first organic compound more than the second organic compound, the first organic compound is an organic compound having an electron-transporting property, the second organic compound is an organic compound having an electron-trapping property, an energy gap of the second organic compound is larger than that of the light-emitting substance; and a voltage is applied such that a potential of the first electrode is higher than that of the second electrode, so that the light-emitting layer emits light. | 2008-09-11 |
20080217609 | ORGANIC TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS INCLUDING THE SAME - An organic transistor includes a source electrode and a drain electrode, an organic semiconductor layer disposed across between the source electrode and the drain electrode, a gate insulating layer, and a gate electrode opposing the source and drain electrodes with the organic semiconductor layer and the gate insulating layer therebetween. The organic semiconductor layer includes a first semiconductor portion in a region where the gate electrode and the source electrode oppose each other, a second semiconductor portion in a region where the gate electrode and the drain electrode oppose each other, and a third semiconductor portion between the first semiconductor portion and the second semiconductor portion. The first semiconductor portion, the second semiconductor portion, and the third semiconductor portion satisfy the relationships W | 2008-09-11 |
20080217610 | THIN FILM TRANSISTOR HAVING N-TYPE AND P-TYPE CIS THIN FILMS AND METHOD OF MANUFACTURING THE SAME - Provided is a thin film transistor (TFT) which uses CIS (CuInSe | 2008-09-11 |
20080217611 | Ultraviolet Sensor - A diode type ultraviolet sensor having a layered-structure body including a conductive layer composed of a sintered ceramic body having conductivity and a semiconductor layer composed of an oxide semiconductor including ZnO. The semiconductor layer is disposed on a principal surface of the conductive layer and forms a heterojunction with the conductive layer. The ultraviolet sensor is used in such a condition that the semiconductor layer is positioned at a light-receiving side irradiated by ultraviolet rays. The semiconductor layer is preferably composed of a sintered body. The sintered body serving as the conductive layer and sintered body serving as the semiconductor layer are preferably formed by co-firing. Terminal electrodes are provided on a principal surface and the other principal surface of the layered-structure body, respectively. | 2008-09-11 |
20080217612 | STRUCTURE AND METHOD OF MAPPING SIGNAL INTENSITY TO SURFACE VOLTAGE FOR INTEGRATED CIRCUIT INSPECTION - Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage. | 2008-09-11 |
20080217613 | POSITIONAL OFFSET MEASUREMENT PATTERN UNIT FEATURING VIA-PLUG AND INTERCONNECTIONS, AND METHOD USING SUCH POSITIONAL OFFSET MEASUREMENT PATTERN UNIT - In a positional offset measurement pattern unit formed in an insulating layer, a first interconnection is formed in the insulating layer. A via-plug is formed in the insulating layer so as to be electrically connected to the first interconnection. A second interconnection is formed in the insulating layer at substantially the same level as the first interconnection so as to be spaced from the first interconnection by a given distance. A voltage is applied between the first and second interconnections to measure a relative positional offset amount between the via-plug and the second interconnection. | 2008-09-11 |
20080217614 | Systems and Methods for Controlling of Electro-Migration - Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed. | 2008-09-11 |
20080217615 | Method for arranging chips of a first substrate on a second substrate - The invention relates to a method for arranging chips of a first substrate on a second substrate, in which the chips are grouped at least into first chips and into second chips, the first chips of the first substrate are singulated and the singulated first chips are arranged on the second substrate in such a way that each of the first chips on the second substrate is unambiguously assigned to the associated first chip on the first substrate. | 2008-09-11 |
20080217616 | Semiconductor integrated circuit device and a method of fabricating the same - A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern. | 2008-09-11 |
20080217617 | Thin Film Transistor, Wiring Board and Methods of Manufacturing the Same - A gate electrode or a gate wiring of a thin-film transistor has a four-layer structure including an adhesive base layer, a catalyst layer, a wiring metal layer, and a wiring metal anti-diffusion layer which are laminated in this order. With this structure, adhesion and flatness are improved. In this case, the adhesive base layer is formed by a resin having a structure capable of coordinating to a metal. Hence, adhesion with an insulating substrate can be improved. Further, the wiring metal anti-diffusion layer is formed on the wiring metal layer, so that diffusion of a wiring metal can be inhibited. Thus, characteristics of the thin-film transistor can be improved. | 2008-09-11 |
20080217618 | Thin Film Circuits - A thin film circuit comprises a plurality of thin film transistors, each having a light shield portion ( | 2008-09-11 |
20080217619 | THIN FILM TRANSISTOR AND DISPLAY DEVICE - The fully depleted thin film transistor (TFT) formed on a semiconductor film ( | 2008-09-11 |
20080217620 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE INCLUDING THE SAME - A thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region, source and drain regions, and edge regions having a first impurity formed at edges of the source and drain regions, and optionally, in the channel region; a gate insulating layer insulating the semiconductor layer; a gate electrode insulated from the semiconductor layer by the gate insulating layer; and source and drain electrodes electrically connected to the semiconductor layer. | 2008-09-11 |
20080217621 | ACTIVE DEVICE ARRAY SUBSTRATE - A method of fabricating an active device array substrate is provided. A substrate having scan lines, data lines and active devices formed thereon is provided. Each of the active devices is electrically connected to the corresponding scan line and data line. An organic material layer is formed over the substrate to cover the scan lines, the data lines and the active devices. Then, a plasma treatment is performed to the surface of the organic material layer to form a number of concave patterns. The dimension of each of the concave patterns is smaller than one micrometer. Afterward, pixel electrodes are formed on the organic material layer and each of the pixel electrodes is electrically connected to one of the corresponding active devices. | 2008-09-11 |
20080217622 | Novel, semiconductor-based, large-area, flexible, electronic devices - Novel articles and methods to fabricate the same resulting in flexible, large-area, triaxially textured, single-crystal or single-crystal-like, semiconductor-based, electronic devices are disclosed. Potential applications of resulting articles are in areas of photovoltaic devices, flat-panel displays, thermophotovoltaic devices, ferroelectric devices, light emitting diode devices, computer hard disc drive devices, magnetoresistance based devices, photoluminescence based devices, non-volatile memory devices, dielectric devices, thermoelectric devices and quantum dot laser devices. | 2008-09-11 |
20080217623 | OPTICAL SENSOR ELEMENT AND METHOD FOR DRIVING THE SAME - An optical sensor element includes: an n-type semiconductor region formed on a substrate; an i-type semiconductor region which is formed on the substrate between the p-type semiconductor region and the n-type semiconductor region and which is lower in impurity concentration than the p-type semiconductor region and the n-type semiconductor region; an anode electrode formed on the insulation film and connected to the p-type semiconductor region; and a cathode electrode formed on the insulation film and connected to the n-type semiconductor region. A reverse bias voltage V | 2008-09-11 |
20080217624 | CAPACITOR AND LIGHT EMITTING DISPLAY USING THE SAME - A capacitor including a polysilicon layer doped with impurities to be conductive, a first dielectric layer formed on the polysilicon layer, a first conductive layer formed on the first dielectric layer, a second dielectric layer formed on the first conductive layer, and a second conductive layer formed on the first dielectric layer. The second conductive layer is coupled to the polysilicon layer. | 2008-09-11 |
20080217625 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a nitride semiconductor device with low parasitic resistance by lowering barrier height to reduce contact resistance at an interface of semiconductor and metal. The nitride semiconductor device includes a GaN layer, a device isolation layer, an ohmic electrode, an n-type Al | 2008-09-11 |
20080217626 | DIAMOND SEMICONDUCTOR ELEMENT AND PROCESS FOR PRODUCING THE SAME - An integrated optical waveguide has a first optical waveguide, a second optical waveguide, and a groove. The second optical waveguide is coupled to the first optical waveguide and has a refractive index that is different from the first optical waveguide. The groove is disposed so as to traverse an optical path of the first optical waveguide and is separated from an interface between the first optical waveguide and the second optical waveguide by a predetermined spacing. The spacing from the interface and the width of the groove are determined such that reflection at a boundary between the first optical waveguide and the second optical waveguide is weakened. A semiconductor board may be disposed at a boundary between the first optical waveguide and the second optical waveguide. In this case, the width of the groove and the thickness of the semiconductor board are determined such that light reflected off an interface between the first optical waveguide and the groove is weakened by light reflected from an interface between the groove and the semiconductor board, and by light reflected from an interface between the semiconductor board and the second optical waveguide. | 2008-09-11 |
20080217627 | SiC-PN Power Diode - An integrated vertical SiC—PN power diode has a highly doped SiC semiconductor body of a first conductivity type, a low-doped drift zone of the first conductivity type, arranged above the semiconductor body on the emitter side, an emitter zone of a second conductivity type, applied to the drift zone, and at least one thin intermediate layer of the first conductivity type. The intermediate layer is arranged inside the drift zone, has a higher doping concentration than the drift zone, and divides the drift zone into at least one first anode-side drift zone layer and at least one second cathode-side drift zone layer. There is also disclosed a circuit configuration with such SiC—PN power diodes. | 2008-09-11 |
20080217628 | LIGHT EMITTING DEVICE - The present invention relates to a light emitting device having a light emitting diode package with a plurality of light emitting cells and an integrated electronic element formed on the same substrate. The light emitting device comprises a substrate, a light emitting cell block having a first array with a plurality of light emitting cells formed on one region of the substrate arranged therein, a second array formed on the same region as the first array, and electrodes for AC power connecting the first and second arrays in reverse parallel; and at least one integrated electronic element formed on another region of the same substrate as the light emitting cell block. | 2008-09-11 |
20080217629 | Ac Light Emitting Diode Having Improved Transparent Electrode Structure - Disclosed is an AC light emitting diode having an improved transparent electrode structure. The light emitting diode comprises a plurality of light emitting cells formed on a single substrate, each of the light emitting cells having a first conductive type semiconductor layer, a second conductive type semiconductor layer positioned on one region of the first conductive type semiconductor layer, and an active layer interposed between the first and second conductive type semiconductor layers. A transparent electrode structure is positioned on each of the light emitting cells. The transparent electrode structure includes at least two portions separated from each other, or a center portion and branches laterally extending from both sides of the center portion. Meanwhile, wires electrically connect adjacent two of the light emitting cells. Accordingly, a plurality of light emitting cells are electrically connected, whereby a light emitting diode can be provided which can be driven under AC power source. Also, an improved transparent electrode structure is employed, so that the current density can be prevented from being locally increased. | 2008-09-11 |
20080217630 | Light emission device - The invention relates to a light emission device, comprising at least two light-emitting semiconductor chips and a substrate. At least one first semiconductor chip ( | 2008-09-11 |
20080217631 | Semiconductor light emitting apparatus and the manufacturing method thereof - A semiconductor light emitting apparatus is provided. The semiconductor light emitting apparatus includes a light-emitting device, a transparent material and at least one transparent film. The light-emitting device is located in a package substrate. The transparent material covers the light-emitting device. The transparent film is located between the light-emitting device and the transparent material. The refractive index of the transparent film is between the refractive index of the light-emitting device and the transparent material. A method for manufacturing the semiconductor light emitting apparatus is also disclosed. | 2008-09-11 |
20080217632 | Gan-Based III-V Compound Semiconductor Light-Emitting Element and Method for Manufacturing Thereof - A GaN-based III-V group compound semiconductor light-emitting element having high light-emitting efficiency and high reliability at a light-emitting wavelength of 440 nm or more is provided. | 2008-09-11 |
20080217633 | LIGHT EMITTING DIODE STRUCTURE - Disclosed is a new LED structure comprising a substrate, and a light emitting die entrained on the substrate. The substrate is made of the lower temperature co-fired ceramic or high temperature co-fired ceramic. The substrate is provided with a printed circuit which can be electrically in connection with an electric circuit board when it entrains the light emitting die. On the surface of the substrate where the light emitting die is to be set, is formed of a flared annular groove which has a light reflection pallet affixed to its lower surface. The surface of the light reflection pallet is coated with the silver glue, fluorescent powder, or other metallic substances. Under the annular groove and above the substrate is interposed an insulation bottom plate to entrain the light emitting die on and the die is connected to the positive and negative electrodes of the substrate with conductors. A number of pores are formed in the substrate and filled with heat dissipation substances. | 2008-09-11 |
20080217634 | VERTICAL LIGHT-EMITTING DIODE STRUCTURE WITH OMNI-DIRECTIONAL REFLECTOR - A vertical light-emitting diode (VLED) structure with an omni-directional reflector (ODR) that may offer increased light extraction and greater luminous efficiency when compared to conventional VLEDs is provided. | 2008-09-11 |
20080217635 | Light emitting devices having current reducing structures and methods of forming light emitting devices having current reducing structures - A light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, and an active region between the n-type semiconductor layer and the p-type semiconductor layer. A non-transparent feature, such as a wire bond pad, is on the p-type semiconductor layer or on the n-type semiconductor layer opposite the p-type semiconductor layer, and a reduced conductivity region is in the p-type semiconductor layer or the n-type semiconductor layer and is aligned with the non-transparent feature. The reduced conductivity region may extend from a surface of the p-type semiconductor layer opposite the n-type semiconductor layer towards the active region and/or from a surface of the n-type semiconductor layer opposite the p-type semiconductor layer towards the active region. | 2008-09-11 |
20080217636 | Electroluminescence Device - An electroluminescence device comprising at least one electroluminescence light source ( | 2008-09-11 |
20080217637 | Light Emitting Diode and Method of Fabricating the Same - The present invention relates to a light emitting diode and a method of fabricating the same, wherein the distance between a fluorescent substance and a light emitting diode chip is uniformly maintained to enhance luminous efficiency. To this end, there is provided a light emitting diode comprising at least one light emitting diode chip, lead terminals for use in applying electric power to the light emitting diode chip, and a frame that is used for mounting the light emitting diode chip thereon and is formed to have a predetermined height and a shape corresponding to that of the light emitting diode chip. | 2008-09-11 |
20080217638 | Semiconductor Light Emitting Device and Fabrication Method Thereof - A semiconductor light emitting device includes a first semiconductor layer having a bottom surface with uneven patterns, an active layer formed on the first semiconductor layer, a second semiconductor layer formed on the active layer, a second electrode formed on the second semiconductor layer, and a first electrode formed under the first semiconductor layer. | 2008-09-11 |
20080217639 | Photonic crystal light emitting device using photon-recycling - A photonic crystal light emitting device including: a light emitting diode (LED) light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first and second conductive semiconductor layers; and a first photon-recycling light emitting layer formed on one surface of the first conductive semiconductor layer, opposite to the active layer, wherein the first photon-recycling light emitting layer absorbs a primary light emitted from the LED light emitting structure and emits a light having a different wavelength from that of the primary light, and a photonic crystal structure is formed on an entire thickness of the first photon-recycling light emitting layer. | 2008-09-11 |
20080217640 | Semiconductor Light emitting device, LED package using the same, and method for fabricating the same - A semiconductor light emitting device is provided which can prevent the reflectance of a metal film from deteriorating due to heat aging and can prevent wire bonding performance of the semiconductor light emitting element from deteriorating due to the diffusion of Ni contained in a Ni barrier metal layer to the reflection layer during die-bonding of the semiconductor light emitting element. The semiconductor light emitting device includes a metal film formed on a substrate and a semiconductor light emitting element. The metal film includes a barrier metal layer configured to prevent a predetermined material from being diffused into the substrate, a metal layer formed on the barrier metal layer; and a reflection layer formed on the metal layer. The reflection layer is configured to reflect light emitted from the semiconductor light emitting element, and the metal layer is made of Ti or Pd. | 2008-09-11 |
20080217641 | LIGHT EMITTING DEVICES HAVING A ROUGHENED REFLECTIVE BOND PAD AND METHODS OF FABRICATING LIGHT EMITTING DEVICES HAVING ROUGHENED REFLECTIVE BOND PADS - Light emitting devices include an active region of semiconductor material and a first contact on the active region. The first contact is configured such that photons emitted by the active region pass through the first contact. A photon absorbing wire bond pad is provided on the first contact. The wire bond pad has an area less than the area of the first contact. A reflective structure is disposed between the first contact and the wire bond pad such that the reflective structure has substantially the same area as the wire bond pad. A second contact is provided opposite the active region from the first contact. The reflective structure may be disposed only between the first contact and the wire bond pad. Methods of fabricating such devices are also provided. | 2008-09-11 |
20080217642 | LIGHT EMITTING DIODE WITH A STEP SECTION BETWEEN THE BASE AND THE LENS OF THE DIODE - [Problem to be Solved]It is to be made easy to arrange light emitting diodes, each including a lens having a hemispherical light emitting surface, and cover the base of the light emitting diodes with resin material.
| 2008-09-11 |
20080217643 | Light-emitting diode and heat radiating unit therefor - A light-emitting diode (LED) is mounted on a heat radiating unit therefor. The LED includes a metal carrier having two through holes, and a light-emitting chip packaged on the metal carrier and having a positive and a negative pin fixed to and insulated from the through holes by sintered glass. The heat radiating unit includes a seat and a hold-down plate closed onto a top of the seat. The seat is formed with a plurality of cavities and provided at an underside with a plurality of radiating fins; the hold-down plate is formed with a plurality of openings corresponding to the cavities on the seat. The LED is mounted in the cavity to expose to external space via the openings on the hold-down plate. Heat produced by the LED during working is transferred via the metal carrier to the heat radiating unit and radiated quickly. | 2008-09-11 |
20080217644 | Containment Structure and Method - Containment structures for an organic composition, comprising a first zone having a first surface energy, and a second zone having a second surface energy different than the first surface energy, and methods for making the same. | 2008-09-11 |
20080217645 | Thick nitride semiconductor structures with interlayer structures and methods of fabricating thick nitride semiconductor structures - A semiconductor structure includes a substrate, a nucleation layer on the substrate, a compositionally graded layer on the nucleation layer, and a layer of a nitride semiconductor material on the compositionally graded layer. The layer of nitride semiconductor material includes a plurality of substantially relaxed nitride interlayers spaced apart within the layer of nitride semiconductor material. The substantially relaxed nitride interlayers include aluminum and gallium and are conductively doped with an n-type dopant, and the layer of nitride semiconductor material including the plurality of nitride interlayers has a total thickness of at least about 2.0 μm. | 2008-09-11 |
20080217646 | Nitride semiconductor light emitting device - The present invention presents a nitride semiconductor light emitting device including a substrate, a first n-type nitride semiconductor layer, a light emitting layer, a p-type nitride semiconductor layer, a p-type nitride semiconductor tunnel junction layer, an n-type nitride semiconductor tunnel junction layer, and a second n-type semiconductor layer, in which the p-type and n-type nitride semiconductor tunnel junction layers form a tunnel junction, at least one of the p-type and n-type nitride semiconductor tunnel junction layers contains In, at least one of In-containing layers contacts with a layer having a larger band gap than the In-containing layer, and at least one of shortest distances between an interface of the In-containing layer and the layer having a larger band gap and an interface of the p-type and n-type nitride semiconductor tunnel junction layers is less than 40 nm. | 2008-09-11 |
20080217647 | METHOD OF FORMING NITRIDE SEMICONDUCTOR LAYER ON PATTERNED SUBSTRATE AND LIGHT EMITTING DIODE HAVING THE SAME - A method of forming high quality nitride semiconductor layers on a patterned substrate and a light emitting diode having the same are disclosed. After forming a nucleation layer on the patterned substrate, a first 3D and 2D growth layers are formed thereon in this order by growing nitride semiconductor layers in 3D and 2D growth conditions. Then, a second 3D growth layer is formed on the first 2D growth layer by growing a nitride semiconductor layer in another 3D growth condition, and a second 2D growth layer is formed on the second 3D growth layer by growing a nitride semiconductor layer in another 2D growth condition. As such, the thickness of the 3D growth layer can be reduced by alternately forming the 3D and 2D growth layers, thereby preventing the 3D growth layer from having a rough surface and improving crystal quality of the final 2D growth layer. | 2008-09-11 |
20080217648 | LIGHT-EMITTING ELEMENT AND LIGHT-EMITTING DEVICE - An object is to provide a light-emitting element and a light-emitting device each of which consumes less power and has high emission efficiency, high performance, and high reliability. A light-emitting element has an EL layer provided with a light-emitting layer, which includes an inorganic light-emitting material containing a mixed-valence compound, between a pair of electrode layers. When an element in a given compound has a plurality of valences, this element is in a state that is referred to as a mixed-valence state and this compound is referred to as a mixed-valence compound. The mixed-valence compound affects charge mobility and emission color, and a light-emitting device having such a light-emitting element consumes less power, has high reliability and high image quality, and emits various colors of light. | 2008-09-11 |
20080217649 | POWER SEMICONDUCTOR DEVICE AND POWER CONVERSION DEVICE USING THE SAME - A power semiconductor device having a low loss and a high reliability and a power conversion device using the power semiconductor device are provided. In the power semiconductor device, a plurality of MOS type trench gates are positioned to be spaced by at-least two types of intervals therebetween, a low-resistance floating n | 2008-09-11 |
20080217650 | Semiconductor circuit including electrostatic discharge circuit having protection element and trigger transistor - A semiconductor circuit includes, a first pad for a first power source, a second pad for a second power source, a third pad for an input/output signal, a protection element arranged between the third pad and the second pad; and a transistor functioning as a trigger element for use in flowing a trigger current to the protection element. The transistor includes a gate and a backgate being connected to the first pad and is connected to the protection element such that a source potential of the transistor becomes lower than a potential of the third pad, based on a voltage drop caused by the protection element, when potentials of the first pad and the third pad are kept at a power supply voltage level. | 2008-09-11 |
20080217651 | Photodetector - A photodetector is provided. The photodetector includes a base piece; a germanium layer mounted on the base piece and including a first area and a second area; a first metal electrode mounted on the first area; an insulation layer mounted on the second area; and a second metal electrode mounted on the insulation layer. | 2008-09-11 |
20080217652 | Growth of AsSb-Based Semiconductor Structures on InP Substrates Using Sb-Containing Buffer Layers - This invention provides high quality and low defect density Sb-containing alloys on lattice-mismatched substrates using Sb-containing buffer layers. More specifically, provided is a method of forming an epitaxial semiconductor alloy on a substrate, comprising: providing a substrate (such as InP); growing an Sb-containing buffer layer on the substrate; and growing a layer of As/Sb-containing semiconductor alloy on the buffer layer. | 2008-09-11 |
20080217653 | Method of Manufacturing a Semiconductor Device with an Isolation Region and a Device Manufactured by the Method - A method of manufacturing a semiconductor device includes forming trench isolation structures, exposing some of the trench isolation structures | 2008-09-11 |
20080217654 | Semiconductor device and method of fabricating the same - A semiconductor device includes an element isolation film having an inclined portion and a flat portion, a protective film formed not on the inclined portion but on the flat portion of the element isolation film, and an outer base layer formed to extend from on a surface of an active region surrounded by the element isolation film to on the protective film. | 2008-09-11 |
20080217655 | INTEGRATED CIRCUIT WITH BURIED CONTROL LINE STRUCTURES - An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines. | 2008-09-11 |
20080217656 | I/O CIRCUIT WITH ESD PROTECTING FUNCTION - For ensuring the complete turn-off state of an ESD protecting device and preventing leakage current from a chip, an alternative conducting path is formed in the chip for bypassing an external current. The chip further includes an internal circuit and a conducting circuit. | 2008-09-11 |
20080217657 | Power Semiconductor Device and Method of Manufacturing a Power Semiconductor Device - A semiconductor power switch having an array of basic cells in which peripheral regions in the active drain region extend beside the perimeter of the base-drain junction, the peripheral regions being of higher dopant density than the rest of the second drain layer. Intermediate regions in the centre of the active drain region are provided of lighter dopant density than the rest of the second drain layer. This provides an improved compromise between the on-state resistance and the breakdown voltage by enlarging the current conduction path at in its active drain region. On the outer side of each edge cell of the array, the gate electrode extends over and beyond at least part of the perimeters of the base-source junction and the base-drain junction towards the adjacent edge of the die. Moreover, on the outer side of each edge cell, the second drain layer includes a region of reduced dopant density that extends beyond the gate electrode right to the adjacent edge of the die | 2008-09-11 |
20080217658 | ELECTRICAL ANTIFUSE WITH INTEGRATED SENSOR - The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry. | 2008-09-11 |
20080217659 | Device and Method To Reduce Cross-Talk and Blooming For Image Sensors - An image sensor device includes a semiconductor substrate having a first type of conductivity, a first layer overlying the semiconductor substrate and having the first type of conductivity, a second layer overlying the first layer and having a second type of conductivity different than the first type of conductivity, and a plurality of pixels formed in the second layer. | 2008-09-11 |
20080217660 | Solid Image Pick-Up Element and Method of Producing the Same - A solid image pick-up element comprises: a photoelectric converting portion; a charge transmitting portion comprising a charge transmitting electrode that transmits a charge generated by the photoelectric converting portion; and a peripheral circuit portion connected to the charge transmitting portion, wherein a surface level of a field oxide film provided at the peripheral circuit portion and the charge transmitting portion to surround an effective image pick-up region of the photoelectric converting portion is to a degree the same as a surface level of the photoelectric converting portion. | 2008-09-11 |
20080217661 | TWO-DIMENSIONAL TIME DELAY INTEGRATION VISIBLE CMOS IMAGE SENSOR - A two dimensional time delay integration CMOS image sensor having a plurality of pinned photodiodes, each pinned photodiode collects a charge when light strikes the pinned photodiode, a plurality of electrodes separating the plurality of pinned photodiodes, the plurality of electrodes are configured for two dimensional charge transport between two adjacent pinned photodiodes, and a plurality of readout nodes connected to the plurality of pinned photodiodes via address lines. | 2008-09-11 |
20080217662 | Space-efficient package for laterally conducting device - Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package. | 2008-09-11 |
20080217663 | Enhanced Transistor Performance by Non-Conformal Stressed Layers - NFET and PFET devices with separately strained channel regions, and methods of their fabrication is disclosed. A stressing layer overlays the device in a manner that the stressing layer is non-conformal with respect the gate. The non-conformality of the stressing layer increases the amount of stress that is imparted onto the channel of the device, in comparison to stressing layers which are conformal. The method for overlaying in a non-conformal manner includes non-conformal deposition techniques, as well as, conformal depositions where subsequently the layer is turned into a non-conformal one by etching. | 2008-09-11 |
20080217664 | Gate self aligned low noise JFET - The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation. | 2008-09-11 |
20080217665 | SEMICONDUCTOR DEVICE STRUCTURE HAVING ENHANCED PERFORMANCE FET DEVICE - A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench. | 2008-09-11 |
20080217666 | CMOS IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - A floating node structure of a CMOS image sensor disposed in a floating node region defined by an isolation structure of a substrate is described. The floating node structure comprises an n-doped region within the floating node region, a p-well surrounding the periphery and the bottom of the n-doped region in the substrate within the folating node region, a surface passivation layer disposed at least on the surface of the p-well, and a contact plug coupling the n-doped region to a source follower transistor of the CMOS image sensor. | 2008-09-11 |
20080217667 | IMAGE SENSING DEVICE - An image sensing device includes a substrate with a photo sensing and a transistor region, a photo diode, a transistor, a dielectric layer, a metal interconnect, a metal conductive line, a conformal passivation layer, a color filter, a lens planar layer, and a microlens. The photo diode is in the substrate within the photo sensing region. The transistor is on the substrate in the transistor region. The dielectric layer is on the substrate. Except the photo sensing region, the metal interconnect and the metal conductive line are respectively located in and on the dielectric layer. The conformal passivation layer is on the dielectric layer and covers the metal conductive line. The color filter is on the conformal passivation layer in the photo sensing region and the bottom thereof is lower than the bottom of the metal conductive line. The lens planar layer and the microlens are sequentially on precedent structure. | 2008-09-11 |
20080217668 | Semiconductor device and method of manufacturing the same - After a ferroelectric capacitor ( | 2008-09-11 |
20080217669 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - According to an aspect of the present invention, there is provided a semiconductor memory device comprising, a first transistor and a second transistor formed on a semiconductor substrate, a memory capacitor formed above the first transistor, the memory capacitor being connected to the first transistor, a dummy memory capacitor formed above the second transistor, a wiring layer formed above the memory capacitor and the dummy memory capacitor, the wiring layer being connected to the first transistor and the memory capacitor, a first plug connecting between the second transistor and the dummy memory capacitor, and a second plug connecting between the dummy memory capacitor and the wiring layer. | 2008-09-11 |
20080217670 | Methods of manufacturing a semiconductor device; method of manufacturing a memory cell; semiconductor device; semiconductor processing device; integrated circuit having a memory cell - Methods of manufacturing a semiconductor device, a method of manufacturing a memory cell, a semiconductor device, a semiconductor processing device, and a memory cell, are provided. In one embodiment a method of manufacturing a semiconductor device is provided including forming a metal doped chalcogenide layer using light irradiation at least partially during provision of the metal. | 2008-09-11 |
20080217671 | METHODS FOR FORMING SEMICONDUCTOR STRUCTURES WITH BURIED ISOLATION COLLARS AND SEMICONDUCTOR STRUCTURES FORMED BY THESE METHODS - A semiconductor structure including a trench formed in a substrate and a buried isolation collar that extends about sidewalls of the trench. The buried isolation collar is constituted by an insulator formed from a buried porous region of substrate material. The porous region is formed from a buried doped region defined using masking and ion implantation or by masking the trench sidewalls and using dopant diffusion. Advantageously, the porous region is transformed to an oxide insulator by an oxidation process. The semiconductor structure may be a storage capacitor of a memory cell further having a buried plate about the trench and a capacitor node inside the trench that is separated from the buried plate by a node dielectric formed on the trench sidewalls. | 2008-09-11 |
20080217672 | INTEGRATED CIRCUIT HAVING A MEMORY - An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements. | 2008-09-11 |
20080217673 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a stack structure in which multiple channel layers are stacked on a substrate so as to be sandwiched between bit line layers, a gate electrode that is provided to the side of the lateral surface of an interior of a groove portion formed within the stack structure, and a charge storage layer that is provided between the gate electrode and the channel layer. | 2008-09-11 |
20080217674 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATION OF THE SAME - A semiconductor memory device includes a first memory cell transistor. The first memory cell transistor includes a tunnel insulation film provided on a semiconductor substrate, a floating electrode provided on the tunnel insulation film, an inter-gate insulation film provided on the floating electrode, and a control electrode provided on the inter-gate insulation film. The floating electrode includes a first floating electrode provided on the tunnel insulation film and a second floating electrode provided on one end portion of the first floating electrode, the floating electrode having an L-shaped cross section in a wiring direction of the control electrode. | 2008-09-11 |
20080217675 | Novel profile of flash memory cells - A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate. | 2008-09-11 |
20080217676 | ZIRCONIUM SILICON OXIDE FILMS - Electronic apparatus and systems include structures having a dielectric layer containing a zirconium silicon oxide film. A zirconium silicon oxide film may be disposed in an integrated circuit, as well as in a variety of other electronic devices. Additional apparatus, systems, and methods are disclosed. | 2008-09-11 |
20080217677 | Non-volatile semiconductor memory device with alternative metal gate material - A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material. | 2008-09-11 |
20080217678 | Memory Gate Stack Structure - A memory gate stack structure ( | 2008-09-11 |
20080217679 | MEMORY UNIT STRUCTURE AND OPERATION METHOD THEREOF - A memory unit is proposed. The memory unit includes a Si substrate, a trapping layer formed on the Si substrate, a first and a second doping regions formed in the Si substrate on either side of the trapping layer, a gate formed on the trapping layer, a first oxide layer formed between the gate and the trapping layer, a high-Dit material layer formed between the Si substrate and the trapping layer, and a second oxide layer formed between the high-Dit material layer and the trapping layer, wherein an interface trap density (Dit) between the high-Dit material layer and the Si substrate is in a rang from 10 | 2008-09-11 |
20080217680 | NON-VOLATILE SEMICONDUCTOR MEMORY USING CHARGE-ACCUMULATION INSULATING FILM - There is provided a non-volatile semiconductor memory having a charge accumulation layer of a configuration where a metal oxide with a dielectric constant sufficiently higher than a silicon nitride, e.g., a Ti oxide, a Zr oxide, or a Hf oxide, is used as a base material and an appropriate amount of a high-valence substance whose valence is increased two levels or more (a VI-valence) is added to produce a trap level that enables entrance and exit of electrons with respect to the base material. | 2008-09-11 |
20080217681 | Charge trap memory device and method of manufacturing the same - Provided are a charge trap memory device and method of manufacturing the same. A charge trap memory device may include a tunnel insulating layer on a substrate, a charge trap layer on the tunnel insulating layer, and a blocking insulating layer formed of a material including Gd or a smaller lanthanide element on the charge trap layer. | 2008-09-11 |
20080217682 | SELECTIVE INCORPORATION OF CHARGE FOR TRANSISTOR CHANNELS - A device and method for selective placement of charge into a gate stack includes forming gate stacks including a gate dielectric adjacent to a transistor channel and a gate conductor and forming doped regions for transistor operation. A layer rich in a passivating element is deposited over the doped regions and the gate stack, and the layer rich the passivating element is removed from selected transistors. The layer rich in the passivating element is than annealed to drive-in the passivating element to increase a concentration of charge at or near transistor channels on transistors where the layer rich in the passivating element is present. The layer rich in the passivating element is removed. | 2008-09-11 |
20080217683 | SELF-ALIGNED DOUBLE LAYERED SILICON-METAL NANOCRYSTAL MEMORY ELEMENT, METHOD FOR FABRICATING THE SAME, AND MEMORY HAVING THE MEMORY ELEMENT - A nanocrystal memory element and a method for fabricating the same are proposed. The fabricating method involves selectively oxidizing polysilicon not disposed beneath and not covered with a plurality of metal nanocrystals, and leaving intact the polysilicon disposed beneath and thereby covered with the plurality of metal nanocrystals, with a view to forming double layered silicon-metal nanocrystals by self-alignment. | 2008-09-11 |
20080217684 | Semiconductor device and manufacturing method thereof and power supply apparatus using the same - A semiconductor device comprises a trench-gate type field-effect transistor on a semiconductor substrate having a first main surface and a second main surface oppositely positioned in a thickness direction, wherein the trench-gate type field-effect transistor comprises a first semiconductor region at the first main surface side; a second semiconductor region at the second main surface; a semiconductor well region between the first semiconductor region and the second semiconductor region; a trench formed so as to protrude in a first direction intersecting the second main surface; a gate electrode formed on an inner surface of the trench via a gate insulating film, and a bottom of the gate electrode is in the first semiconductor region, and a well bottom has a well deep portion and a well shallow portion, and the well deep portion is in a region more distant from the gate insulating film compared to the well shallow portion. | 2008-09-11 |
20080217685 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an isolation layer for dividing a silicon substrate into an active region and an inactive region, a gate electrode formed over the silicon substrate, a gate oxide layer formed around a sidewall of the gate electrode to expose an upper portion of the sidewall of the gate electrode, a gate insulation layer formed between the silicon substrate and the gate electrode, an epitaxial layer formed over the gate electrode and the active region around the gate electrode; a lightly doped drain region formed in a surface of the silicon substrate around the gate electrode, a gate spacer formed around the sidewall of the gate electrode including the gate oxide layer; source and drain regions formed in the surface of the silicon substrate at sides of the gate spacer, and a protective layer formed over the entire surface of the silicon substrate. | 2008-09-11 |
20080217686 | ULTRA-THIN SOI CMOS WITH RAISED EPITAXIAL SOURCE AND DRAIN AND EMBEDDED SIGE PFET EXTENSION - A method for improving channel carrier mobility in ultra-thin Silicon-on-oxide (UTSOI) FET devices by integrating an embedded pFET SiGe extension with raised source/drain regions. The method includes selectively growing embedded SiGe (eSiGe) extensions in pFET regions and forming strain-free raised Si or SiGe source/drain (RSD) regions on CMOS. The eSiGe extension regions enhance hole mobility in the pFET channels and reduce resistance in the pFET extensions. The strain-free raised source/drain regions reduce contact resistance in both UTSOI pFETs and nFETs. | 2008-09-11 |
20080217687 | Active device array substrate and repairing method thereof - A simple active device array substrate and an easy repairing method thereof are provided. The pattern layer of the drain electrode has an extended portion extending to the region between an adjacent pixel electrode and the substrate. Once the pixel is found to be a white defect, a laser beam is used to irradiate the overlapped region of the extended portion of the pattern layer of the drain electrode and the adjacent pixel electrode. Then, the current pixel will have the same brightness and color with the adjacent pixel, such that the repairing purpose is achieved. | 2008-09-11 |
20080217688 | SEMICONDUCTOR DEVICE AND MANUFACTURE METHOD THEREOF - An object is to provide an element structure of a semiconductor device for increasing an etching margin for various etching steps and a method for manufacturing the semiconductor device having the element structure. An island-shaped semiconductor layer is provided over an insulator having openings. The island-shaped semiconductor layer includes embedded semiconductor layers and a thin film semiconductor layer. The embedded semiconductor layers have a larger thickness than that of the thin film semiconductor layer. | 2008-09-11 |
20080217689 | SEMICONDUCTOR DEVICES HAVING SILICON-ON-INSULATOR (SOI) SUBSTRATES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices are provided including gate patterns on a substrate and isolation regions on the substrate. Insulating patterns are provided in the substrate below the gate patterns. Source/drain regions are provided in the substrate. Related methods of fabricating semiconductor devices are also provided. | 2008-09-11 |
20080217690 | Latch-Up Resistant Semiconductor Structures on Hybrid Substrates and Methods for Forming Such Semiconductor Structures - Latch-up resistant semiconductor structures formed on a hybrid substrate and methods of forming such latch-up resistant semiconductor structures. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up. | 2008-09-11 |
20080217691 | HIGHER PERFORMANCE CMOS ON (110) WAFERS - A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures. | 2008-09-11 |
20080217692 | ASYMMETRICALLY STRESSED CMOS FINFET - A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ polysilicon layer on one side of the channel region and a P+ polysilicon layer on an opposite side of the channel region, thereby, partitioning the fin structure into a first side and a second side, respectively. The channel region is in mechanical tension on the first side and in mechanical compression on the second side. The FinFET may comprise any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the first side, and wherein the pFET comprises a P-channel inversion region in the second side. The CMOS device may further comprise a tensile film and a relaxed film on opposite sides of the fin structure adjacent to the source and drain regions, and an oxide cap layer over the fin structure. | 2008-09-11 |
20080217693 | Structure to improve MOS transistor on-breakdown voltage and method of making the same - A novel MOS transistor structure and methods of making the same are provided. The structure includes a MOS transistor formed on a semiconductor substrate of a first conductivity type with a plug region of first conductivity type formed in the drain extension region of second conductivity type (in the case of a high voltage MOS transistor) or in the lightly doped drain (LDD) region of second conductivity type (in the case of a low voltage MOS transistor). Such structure leads to higher on-breakdown voltage. The inventive principle applies to MOS transistors formed on bulky semiconductor substrate and MOS transistors formed in silicon-on-insulator configuration. | 2008-09-11 |
20080217694 | SPACERS FOR FINFETS (FIELD EFFECT TRANSISTORS) - A spacer structure for FinFETs. The structure includes (a) a substrate, (b) a semiconductor fin region on top of the substrate, (c) a gate dielectric region on side walls of the semiconductor fin region, and (d) a gate electrode region on top and on side walls of the semiconductor fin region. The gate dielectric region (i) is sandwiched between and (ii) electrically insulates the gate electrode region and the semiconductor fin region. The structure further includes a first spacer region on a first side wall of the gate electrode region. A first side wall of the semiconductor fin region is exposed to a surrounding ambient. A top surface of the first spacer region is coplanar with a top surface of the gate electrode region. | 2008-09-11 |
20080217695 | Heterogeneous Semiconductor Substrate - A substrate comprising a first region of a first semiconductor and a second region of second semiconductor, wherein the first semiconductor and the second semiconductor are different, is disclosed. The substrate is particularly supportive of p-channel MOSFETs and n-channel MOSFETs having carrier mobility that is closer than in substrates comprising a single semiconductor. | 2008-09-11 |
20080217696 | METHOD AND STRUCTURE FOR CONTROLLING STRESS IN A TRANSISTOR CHANNEL - A method for manufacturing a device including an n-type device and a p-type device. In an aspect of the invention, the method involves forming a shallow-trench-isolation oxide (STI) isolating the n-type device from the p-type device. The method further involves adjusting the shallow-trench-isolation oxide corresponding to at least one of the n-type device and the p-type device such that a thickness of the shallow-trench-isolation oxide adjacent to the n-type device is different from a thickness of the shallow-trench-isolation oxide adjacent to the p-type device, and forming a strain layer over the semiconductor substrate. | 2008-09-11 |
20080217697 | CONTROL OF POLY-Si DEPLETION IN CMOS VIA GAS PHASE DOPING - A method to control the poly-Si depletion effect in CMOS structures utilizing a gas phase doping process which is capable of providing a high concentration of dopant atoms at the gate dielectric/poly-Si interface is provided. The present invention also provides CMOS structure including, for example, nFETs and/or pFETs, that are fabricated utilizing the gas phase doping technique described herein. | 2008-09-11 |
20080217698 | METHODS AND SEMICONDUCTOR STRUCTURES FOR LATCH-UP SUPPRESSION USING A CONDUCTIVE REGION - Semiconductor structures and methods for suppressing latch-up in bulk CMOS devices. The semiconductor structure comprises first and second adjacent doped wells formed in the semiconductor material of a substrate. A trench, which includes a base and first sidewalls between the base and the top surface, is defined in the substrate between the first and second doped wells. The trench is partially filled with a conductor material that is electrically coupled with the first and second doped wells. Highly-doped conductive regions may be provided in the semiconductor material bordering the trench at a location adjacent to the conductive material in the trench. | 2008-09-11 |
20080217699 | Isolated Bipolar Transistor - An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains the bipolar transistor. The collector of the bipolar transistor may comprise the floor isolation region. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same. | 2008-09-11 |
20080217700 | Mobility Enhanced FET Devices - NFET and PFET devices with separately stressed channel regions, and methods of their fabrication is disclosed. A FET is disclosed which includes a gate, which gate includes a metal in a first state of stress. The FET also includes a channel region hosted in a single crystal Si based material, which channel region is overlaid by the gate and is in a second state of stress. The second state of stress of the channel region is of an opposite sign than the first state of stress of the metal included in the gate. The NFET channel is usually in a tensile state of stress, while the PFET channel is usually in a compressive state of stress. The methods of fabrication include the deposition of metal layers by physical vapor deposition (PVD), in such manner that the layers are in stressed states. | 2008-09-11 |
20080217701 | Design solutions for integrated circuits with triple gate oxides - An integrated circuit includes a first core circuit and a second core circuits. The first core circuit includes a first MOS device, wherein a first gate dielectric of the first MOS device has a first thickness. The second core circuit includes a second MOS device, wherein a second gate dielectric of the second MOS device has a second thickness less than the first thickness. A first power supply line having a first power supply voltage is connected to the first and the second core circuits a first power supply voltage. | 2008-09-11 |
20080217702 | Semiconductor device and method of fabricating isolation region - A semiconductor device according to an embodiment of the present invention includes: a semiconductor substrate; an isolation region including a liner film formed so as to contact a lower surface and a lower side surface of an inner wall of a trench formed in the semiconductor substrate, a first insulating film formed so that at least a part of a side surface and a lower surface of the first insulating film contact the liner film within the trench, and a second insulating film formed so as to contact an upper side of the first insulating film and formed so as to contact an upper side surface of the inner wall of the trench, the second insulating film having a higher etching resistance than that of the first insulating film; and a plurality of semiconductor elements disposed on the semiconductor substrate so as to be isolated from one another by the isolation region. | 2008-09-11 |
20080217703 | HIGHLY SELECTIVE LINERS FOR SEMICONDUCTOR FABRICATION - A method for manufacturing an isolation structure is disclosed that protects the isolation structure during etching of a dichlorosilane (DCS) nitride layer. The method involves the formation of a bis-(t-butylamino)silane-based nitride liner layer within the isolation trench, which exhibits a five-fold greater resistance to nitride etching solutions as compared with DCS nitride, thereby allowing protection against damage from unintended over-etching. The bis-(t-butylamino)silane-based nitride layer also exerts a greater tensile strain on moat regions that results in heightened carrier mobility of active regions, thereby increasing the performance of NMOS transistors embedded therein. | 2008-09-11 |