36th week of 2011 patent applcation highlights part 17 |
Patent application number | Title | Published |
20110215813 | FUEL PROPERTY SENSOR ABNORMALITY DETERMINING DEVICE - A plurality of capacitance values at different obtained fuel temperatures are obtained. Ethanol concentrations of fuel to be measured are obtained from these capacitance values after correcting for an amount of change in the capacitance values due to a temperature characteristic. The correction according to the temperature characteristic is realized according to a map stored in a control apparatus. It is determined that there is an abnormality in an alcohol concentration sensor if the difference among the obtained ethanol concentrations is equal to or greater than a predetermined value. | 2011-09-08 |
20110215814 | ADVANCED OBSCURED FEATURE DETECTOR - A surface-conforming obscured feature detector includes a plurality of sensor plates, each having a capacitance that varies based on the dielectric constant of the materials that compose the surrounding objects and the proximity of those objects. A sensing circuit is coupled to the sensor plates | 2011-09-08 |
20110215815 | OBSCURED FEATURE DETECTOR WITH ADVANCED TRACE PROPERTIES - A surface-conforming obscured feature detector includes a plurality of sensor plates, each having a capacitance that varies based on the dielectric constant of the materials that compose the surrounding objects and the proximity of those objects. A sensing circuit is coupled to the sensor plates | 2011-09-08 |
20110215816 | OBSCURED FEATURE DETECTOR HOUSING - A surface-conforming obscured feature detector includes a plurality of sensor plates, each having a capacitance that varies based on the dielectric constant of the materials that compose the surrounding objects and the proximity of those objects. A sensing circuit is coupled to the sensor plates | 2011-09-08 |
20110215817 | OBSCURED FEATURE DETECTOR WITH MULTIPLE MODES OF OPERATION - A surface-conforming obscured feature detector includes a plurality of sensor plates, each having a capacitance that varies based on the dielectric constant of the materials that compose the surrounding objects and the proximity of those objects. A sensing circuit is coupled to the sensor plates | 2011-09-08 |
20110215818 | SURFACE-CONFORMING OBSCURED FEATURE DETECTOR - A surface-conforming obscured feature detector includes a plurality of sensor plates flexibly connected together, each having a capacitance that varies based on the dielectric constant of the materials that compose the surrounding objects and the proximity of those objects. A sensing circuit is coupled to the sensor plates to measure the capacitances of the sensor plates. A controller is coupled to the sensing circuit to analyze the capacitances measured by the sensing circuit. One or a plurality of indicators are coupled to the controller, and are selectively activated to identify the location of a relative high capacitance, which can be indicative of an obscured feature behind a surface. | 2011-09-08 |
20110215819 | OBSCURED FEATURE DETECTOR WITH BUILT-IN CORRECTION MODULE - A surface-conforming obscured feature detector includes a plurality of sensor plates, each having a capacitance that varies based on the dielectric constant of the materials that compose the surrounding objects and the proximity of those objects. A sensing circuit is coupled to the sensor plates | 2011-09-08 |
20110215820 | Delta detection method for detecting capacitance changes - A delta detection method for detecting capacitance changes caused by relative movement between a physical object and a capacitance sensor. | 2011-09-08 |
20110215821 | EMITTER WHEEL ASSEMBLY - This abstract refers to an invention patent related to an emitter wheel assembly, more particularly with the association of a special sensitizer ring set ( | 2011-09-08 |
20110215822 | STATIONARY FEATURE DETECTOR - An obscured feature detector operates from a stationary position on a surface being examined. The detector includes a plurality of sensor plates positioned in an array on the underside of the device, which sense the examined surface. The sensor plates are connected to a capacitance sensing circuit, which connects to indicators positioned on the back side of the detector through additional circuitry. A handle positioned on the back of the detector allows the user to grasp the device and place it in a stationary position on the surface being examined while also observing the indicators on the back side of the detector. Increases in capacitance caused by the presence of features behind or within the surface being examined are detected by the sensor plates and the capacitance sensing circuit. The indicators identify locations of larger capacitances, associated with the presence of a feature, such as a stud, beam, or electrical wiring. | 2011-09-08 |
20110215823 | APPARATUS AND METHOD FOR MONITORING CURRENT FLOW TO INTEGRATED CIRCUIT IN TEMPERATURE-COMPENSATED MANNER - A circuit and method for monitoring current flow to an integrated circuit (IC), alone or mounted on a substrate, in a temperature-compensated manner. In accordance with a preferred embodiment, a plurality of resistances having substantially equal temperature coefficients establishes a ratio of an output voltage and an internally measured voltage, with the output voltage corresponding to a voltage drop across an inherent resistance within the IC or on the substrate. | 2011-09-08 |
20110215824 | OPERATION VOLTAGE SUPPLY APPARATUS - The voltage application probe and the voltage measurement probe are connected to the voltage application pad and the voltage measurement pad of the semiconductor device. The voltage application pad and the voltage measurement pad are connected by the conductor, measuring the voltage applied to the voltage application pad through the voltage measurement probe. The voltage compensation circuit in the voltage development device operates to make the voltage applied to the voltage application pad equal to the set voltage for the voltage development device. Even when the resistance between the voltage application probe and the voltage application pad increases, the accurate setting voltage is applied to the voltage application pad. | 2011-09-08 |
20110215825 | SYSTEM AND METHOD FOR TEMPERATURE CYCLING - A system and method for non-isothermal temperature cycling (also called Conduction Temperature Cycling) of a semiconductor device. The method includes inserting a semiconductor device into a testing chamber and thermally coupling the semiconductor device to a heating and cooling element via a vacuum holding component. The method further includes heating and cooling a die portion of the semiconductor device with the heating and cooling element and testing the semiconductor device for component failure caused by thermo-mechanical stress induced by the non-isothermal temperature cycling. In one embodiment, the heating and cooling comprises non-isothermal temperature cycling. | 2011-09-08 |
20110215826 | Semiconductor Package Test Apparatus - A semiconductor package test apparatus having a test head and a test handler is provided. The semiconductor package test apparatus may include an insert in which a plurality of semiconductor packages are stacked and received in an offset fashion. Further, the semiconductor package test apparatus may include a plurality of sockets located adjacent to the insert and each of the inserts may have a plurality of socket pins. The sockets have different surface levels and are aligned with the semiconductor packages. | 2011-09-08 |
20110215827 | Method and Apparatus for Testing a Memory Device - In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data. | 2011-09-08 |
20110215828 | TEST METHOD FOR PASSIVE DEVICE EMBEDDED PRINTED CIRCUIT BOARD - A method of testing a passive device embedded printed circuit board is disclosed. The method in accordance with an embodiment of the present invention includes: applying an AC power to a printed circuit board in which a filter including at least two of a resistor, an inductor and a capacitor is embedded; measuring a property of the filter for the applied AC power; and determining whether or not the printed circuit board is defective by comparing the measured property of the filter with a design value. | 2011-09-08 |
20110215829 | IDENTIFICATION OF DEVICES USING PHYSICALLY UNCLONABLE FUNCTIONS - A method of generating a response to a physically unclonable function, said response being uniquely representative of the identity of a device having challengeable memory, the memory comprising a plurality of logical locations each having at least two possible logical states, the method comprising applying a challenge signal to an input of said memory so as to cause each of said logical locations to enter one of said two possible logical states and thereby generate a response pattern of logical states, said response pattern being dependent on said physically unclonable function which is defined by, the physical characteristics of said memory, the method further comprising reading out said response pattern. | 2011-09-08 |
20110215830 | OUTPUT BUFFER CIRCUIT AND DIFFERENTIAL OUTPUT BUFFER CIRCUIT, AND TRANSMISSION METHOD - An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant. | 2011-09-08 |
20110215831 | LOW POWER TELEMETRY SYSTEM AND METHOD - A telemetry system is described in which a plurality of channels are coupled to a bus. A control subsystem controls the channels so that one of the channels presents to the bus during its designated time period a channel characteristic. The control subsystem interrogates in the analog domain each of the channels during its designated time period, and forms a signal representative of the channel characteristic. The control subsystem may combine one or more of the signals into a digital packet, and transmit the same over a network. Each channel in the telemetry system can include a sample-and-hold circuit, a variable resistor circuit, and a control element. The sample-and-hold circuit is configured to hold a sample of a signal. The variable resistor circuit is configured to present a variable impedance to one or more signal lines during a time period designated for the channel an impedance representative of the sample held by the sample-and-hold circuit. The control element is configured to control the variable resistor circuit to present to the one or more signal lines an open circuit equivalent impedance during times other than the time period designated for the channel. In some implementations, the channel also includes a switch which decouples the sample-and-hold circuit from the variable resistor circuit during times other than the time period designated for the channel. In some implementations, the control element is a programmable control element that is programmable with a unique channel identifier, and may include a timing element which is updated responsive to a control signal. The programmable control element determines that the designated time period for the channel is occurring or will occur based on a comparison of the contents of the timing element with the unique channel identifier. The control element can be a zero power control element. | 2011-09-08 |
20110215832 | APPARATUS OF LOW POWER, AREA EFFICIENT FINFET CIRCUITS AND METHOD FOR IMPLEMENTING THE SAME - A novel implementation of a majority gate and a 2-1 MUX by using both gates of FinFET transistors as inputs is presented. A general methodology of using both gates of FinFET as inputs to implement any digital logic circuit is also presented. Circuits implemented using this methodology have significant advantages over CMOS logic counterpart and pass transistor logic counterpart in terms of power consumption and cell area. | 2011-09-08 |
20110215833 | PROGRAMMABLE ON-CHIP LOGIC ANALYZER APPARATUS, SYSTEMS, AND METHODS - Apparatus, systems, and methods disclosed herein may cause an event trigger state machine associated with a programmable on-chip logic analyzer (POCLA) to transition to a programmable state at a programmable number of occurrences of a programmable set of events associated with a first subset of signals on a first subset of input signal paths. States associated with a second subset of signals on a second subset of input signal paths may be stored at a time relative to a transition to the programmable state if a set of storage criteria have been met. Additional embodiments are disclosed and claimed. | 2011-09-08 |
20110215834 | PROGRAMMABLE INTEGRATED CIRCUIT WITH MIRRORED INTERCONNECT STRUCTURE - A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interconnect column includes programmable interconnect blocks ( | 2011-09-08 |
20110215835 | QUAD STATE LOGIC DESIGN METHODS, CIRCUITS AND SYSTEMS - Quad-state logic elements and quad-state memory elements are used to reduce the wiring density of integrated circuits. The resulting reduction in wiring interconnects between memories and logic elements results in higher speed, higher density, and lower power integrated circuit designs. | 2011-09-08 |
20110215836 | OUTPUT BUFFER - According to one embodiment, a clamp transistor is inserted in series between a P-channel field effect transistor and an N-channel field effect transistor and an intermediate level between a high potential supplied to a source of the P-channel field effect transistor and a low potential supplied to a source of the N-channel field effect transistor is input into a gate of the clamp transistor to clamp a drain potential of the N-channel field effect transistor. | 2011-09-08 |
20110215837 | CLOCK GENERATOR CIRCUITS FOR GENERATING CLOCK SIGNALS - The present invention relates to a circuit for generating a clock signal. The circuit comprises a current source to generate a reference current and provide a first voltage V | 2011-09-08 |
20110215838 | DIGITAL NOISE FILTER - A digital noise filter circuit includes a gating clock generating circuit and a noise filter circuit. The gating clock generating circuit compares logic levels of an input signal and an output signal of the noise filter circuit. The gating clock generating circuit supplies a gating clock as an operating clock to the noise filter circuit when the logic levels of both signals do not coincide, and halts supply of the gating clock when the logic levels of both signals do coincide. The noise filter circuit removes noise from the input signal and outputting the resultant signal as the output signal. | 2011-09-08 |
20110215839 | Input circuit and semiconductor integrated circuit including the same - An input circuit, includes a first buffer circuit, a second buffer circuit, a first differential amplification circuit that includes a first input coupled to a first external power source terminal, a second input coupled to an output of the first buffer circuit, and an output coupled to an input of the first buffer circuit, and a second differential amplification circuit that includes a first input coupled to a second external power source terminal, a second input coupled to an output of the second buffer circuit, and an output coupled to an input of the second buffer circuit. | 2011-09-08 |
20110215840 | GATE DRIVE CIRCUIT - A switch device comprised of a wide band gap semiconductor is provided. The switch device comprises a drain, a source, a gate and a gate voltage clamp circuit, which is connected between a signal terminal, to which a signal for driving the gate is input, and the gate through a series circuit of a capacitor and a resistance, and which comprises a diode and a voltage limiter circuit provided between the drain and the gate. | 2011-09-08 |
20110215841 | DEVICE FOR AND A METHOD OF GENERATING SIGNALS | 2011-09-08 |
20110215842 | PROGRAMMABLE DIGITAL CLOCK SIGNAL FREQUENCY DIVIDER MODULE AND MODULAR DIVIDER CIRCUIT - A programmable digital clock signal frequency divider module has a module clock input, module clock output, a scaling factor input, two programming inputs, and a tertiary input. A primary divider module with a primary divider module output and a clock input are coupled to the module clock input. A secondary divider module includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output. In operation, logic values applied to the scaling factor input, and the programming inputs, result in the primary divider module processing a first sequence of cycles of a primary digital clock signal into a first base clock signal and processing a subsequent second sequence of cycles into a second base clock signal. The first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module. Edges of the sequence of clock pulses trigger the divide by two latch, which results in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch. Logic values at the tertiary input select either the sequence of clock pulses or the latch output clock signal to be a module clock output signal at the module clock output. | 2011-09-08 |
20110215843 | Frequency Generator - A frequency generator comprising an oscillator that generates I and Q signals and a prescaler with a clock phase generator that uses the I and Q signals as input and can generate a predetermined number of phases, a switch bank with a number of switches corresponding to the number of phases that can be generated by the clock phase generator, and a clock select logic component. The prescaler comprises a state machine that can assume a predetermined number of states as output. The output state is input to the clock select logic component and determines which switch to use as output from the switch bank and as “clock” input to the state machine, with one of the outputs of the state machine being a signal f | 2011-09-08 |
20110215844 | FREQUENCY MULTIPLIER CIRCUIT - A frequency multiplier circuit, comprising a first stage including a first differential pair of amplifier elements having respective current conduction paths connected in parallel between first and second nodes and respective control terminals connected to receive input signals of opposite polarity at an input frequency in the radio frequency range, the first and second nodes being connected to respective bias voltage supply terminals through first and second impedances respectively so that current flowing differentially in the current conduction paths of the first differential pair of amplifier elements produces a voltage difference across the first and second nodes at a frequency which contains a harmonic of the input frequency, and a second stage including a second differential pair of amplifier elements coupled at the harmonic of the input frequency with the first and second nodes to amplify differentially the voltage difference and produce an output signal at the harmonic of the input frequency. Radio frequency connections apply the voltage difference across the first and second nodes at the frequency of the harmonic to the second differential pair of amplifier elements and block direct current, and separate direct current connections connect respectively the first differential pair of amplifier elements and the second differential pair of amplifier elements across the bias voltage supply terminals. | 2011-09-08 |
20110215845 | POWER-UP SIGNAL GENERATOR FOR USE IN SEMICONDUCTOR DEVICE - In an apparatus for generating a power-up signal, a mode register set (MRS) and other circuits are prevented from being reset, thereby providing stable circuit operation. A final power-up signal is not disabled even though an internal voltage generating unit is turned off at a test mode. The apparatus includes a power-up signal generator for producing a power-up signal; a multiplexing unit for selectively outputting the power-up signal or a static voltage signal in a test mode; and a power-up signal generator for producing a final power-up signal in response to the power-up signal of the power-up signal generator and an output signal of the multiplexing unit as the final power-up signal. | 2011-09-08 |
20110215846 | PHASE LOCKED LOOP CIRCUIT AND CONTROL METHOD THEREOF - A phase locked loop circuit according to the present invention includes a selector that selects an input clock, a 1/m frequency divider that divides a frequency of the input clock, a 1/n frequency divider that divides a frequency of a feedback clock, a phase difference detector, a first voltage controlled oscillator that includes a first voltage holding circuit, a second voltage controlled oscillator that includes a second voltage holding circuit, and a selection circuit that outputs any output of the first and second voltage controlled oscillators as an output clock and outputs any output of the first and second voltage controlled oscillators as a feedback clock. The input clock is switched when the voltage controlled oscillator in a holding mode generates the output clock and the voltage controlled oscillator in a normal mode generates the feedback clock. | 2011-09-08 |
20110215847 | Frequency synthesizer - The frequency synthesizer has two fixed frequency dividers, two charge pumps, five capacitors, a voltage controlled oscillator, and a transconductance voltage amplifier. The pulse widths of the input reference signal and the output signal are compared and the resultant signal is coupled to the oscillator to adjust its frequency. The circuit exhibits accurate frequency synthesizing, and thus can be used in wireless communication and signal processing systems. It provides a precise integer and fractional frequency division with a low phase noise. Moreover, it has a simple and compact structure that can be implemented in integrated circuit technologies such as CMOS. | 2011-09-08 |
20110215848 | FREQUENCY SYNTHESIZER - A frequency synthesizer includes a controlled oscillator configured to extend a temperature range and phase noise of the synthesizer without compromising the frequency coverage of the synthesizer. The frequency synthesizer also includes bias generation circuitry that sets a bias current of a charge pump to reduce bandwidth variations of the synthesizer. The frequency synthesizer further includes switching circuitry to dynamically turn a charge pump on and off to reduce effects of current leakage in the charge pump. | 2011-09-08 |
20110215849 | CHARGE PUMP FOR PHASE LOCKED LOOP - A charge pump includes a charge pump core circuit having a first current source transistor, a second current source transistor and an output terminal ( | 2011-09-08 |
20110215850 | METHOD FOR TRACKING DELAY LOCKED LOOP CLOCK - A method for tracking a delay locked loop (DLL) clock is described. An external clock signal is allowed to pass through delay cells of a DLL during a first period of the external clock signal when a transition edge of a track signal applied on the DLL occurs. Then, when a transition edge of a sensing signal applied on the DLL occurs at a start of a second period of the external clock signal, the external clock signal is inhibited to pass through the delay cells and the number of the delay cells through which the external signal pass during the first period of the external clock signal is counted. When a reset signal is asserted, a delay time of each delay cell is reset such that a ratio of the delay time to the period of the external clock signal is kept from 10% to 15%. | 2011-09-08 |
20110215851 | DLL INCLUDING 2-PHASE DELAY LINE AND DUTY CORRECTION CIRCUIT AND DUTY CORRECTION METHOD THEREOF - Provided are a delay locked loop (DLL), which is capable of being adopted at a data processing system and include a duty correction circuit, and a duty correction method at the DLL. The duty correction method includes generating first and second delay clock signals having different phase shifts by delaying an external clock signal by as much as first and second set phases in response to a delay control signal, generating first and second first signals respectively synchronized with the first and second delay clock signals, and generating an output clock signal having a set duty ratio by using the first and second pulse signals. According to the foregoing, a more accurate duty correction operation is performed without a half cycle time delay line or a matching delay line. | 2011-09-08 |
20110215852 | HIGH SPEED LATCH CIRCUIT WITH METASTABILITY TRAP AND FILTER - A synchronizer constituted of a first and second set of three serially coupled latches coupled to a common clocking signal, the first and the ultimate latch of the first set responsive to a first edge of a common clocking signal and the penultimate latch responsive to an opposing edge of the common clocking signal, the second set being respectively responsive to the respective complementary edges of the clocking signal; an input lead arranged to receive a signal to be synchronized, the input lead coupled to the input of the first latch of the first set and to the input of the first latch of the second set; and a filter arranged to pass the output of each of the first set and the second set responsive to the penultimate latch of the set exhibiting a consistent output for two consecutive opposing edges. | 2011-09-08 |
20110215853 | DATA TRANSFER CIRCUIT - A data transfer circuit includes primary data holding circuits that hold input data according to a first clock pulse signal and output data being held; and secondary data holding circuits that hold the output data of the primary data holding circuits according to a second clock pulse asynchronous to the first clock pulse and output data being held. Pulse signal generator generates a pulse signal synchronous with the second clock pulse signal when a pulse edge of the first clock pulse signal and a pulse edge of the second clock pulse signal occur at different timings and generates a pulse signal having the pulse edge the second clock pulse signal removed therefrom when the pulse edge of the the first clock pulse signal and the pulse edge of the the second clock pulse signal occur at the same timing. The secondary data holding circuits hold the output data of the primary data holding circuits synchronously with the pulse signal generated by the pulse signal generator. | 2011-09-08 |
20110215854 | Clock Distribution Network Architecture with Clock Skew Management - Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by respective clock waveforms, each of which has a frequency in common with the reference clock. The digital system further includes a phase detector coupled to the first and second clock domains to generate a phase difference signal based on the clock waveforms, and a control circuit coupled to the phase detector and configured to adjust the adjustable delay element based on the phase difference signal. | 2011-09-08 |
20110215855 | VOLTAGE GENERATING CIRCUIT - A voltage generating circuit has: an operational amplifier, first to third voltage generating units, a first resistor and a second resistor. The operational amplifier generates a control signal depending on first and second voltages that are input thereto. The first voltage generating unit generates the first voltage depending on the control signal and outputs the first voltage from a first node. The second voltage generating unit generates the second voltage depending on the control signal and outputs the second voltage from a second node. The third voltage generating unit generates a third voltage as a reference voltage depending on the control signal and outputs the third voltage from a reference voltage output node. The first resistor is connected between the first node and the reference voltage output node. The second resistor connected between the second node and the reference voltage output node. | 2011-09-08 |
20110215856 | Method And Apparatus For Automatic Gain Control for Nonzero Saturation Rates - A method for automatic gain control comprising the steps of measuring a signal using compressed sensing to produce a sequence of blocks of measurements, applying a gain to one of the blocks of measurements, adjusting the gain based upon a deviation of a saturation rate of the one of the blocks of measurements from a predetermined nonzero saturation rate and applying the adjusted gain to a second of the blocks of measurements. Alternatively, a method for automatic gain control comprising the steps of applying a gain to a signal, computing a saturation rate of the signal and adjusting the gain based upon a difference between the saturation rate of the signal and a predetermined nonzero saturation rate. | 2011-09-08 |
20110215857 | DC OFFSET CANCELLER, RECEIVING APPARATUS AND DC OFFSET CANCELLATION METHOD - According to an embodiment, a DC offset canceller includes a first DA converter, a first adder, an amplifier, a comparator, an averaging circuit, and a successive approximation register. The first DA converter is configured to DA-convert first correction data into a first correction voltage. The first adder is configured to add an input signal and the first correction voltage to output a first added signal. The amplifier is configured to amplify the first added signal to output an amplified signal. The comparator is configured to compare the amplified signal and a reference voltage to output a comparison result. The averaging circuit is configured to receive the comparison results of the comparator to obtain a majority decision result by performing majority decision on logical values of the comparison results in a predetermined time period. The successive approximation register is configured to sequentially set each bit of the first correction data based on the majority decision result so that a DC offset in the amplified signal decreases. | 2011-09-08 |
20110215858 | CONTROLLING THE RECOMBINATION RATE IN A BIPOLAR SEMICONDUCTOR COMPONENT - Disclosed is a method for controlling the recombination rate in the base region of a bipolar semiconductor component, and a bipolar semiconductor component. | 2011-09-08 |
20110215859 | CURRENT SOURCE CIRCUIT AND SEMICONDUCTOR DEVICE - A current source circuit includes a reference current source circuit; a reference voltage source circuit generating a voltage proportional to a thermal voltage based on the reference current; a first transistor connected between the reference voltage source circuit and the second power supply voltage and through which a first current flows; a second transistor which has a gate applied with a voltage as a result of addition of the voltage generated by the reference voltage source circuit and a voltage between a source and a drain of the first transistor and through which a second current flows; a current source supplying a third current of a current value proportional to that of the first current; and a third transistor through which a difference current between the second current and the third current flows. An output current is supplied based on the difference current. | 2011-09-08 |
20110215860 | DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER - The invention provides a data-path cell specifically adapted to its environment for use in an integrated circuit produced on a semiconductor-on-insulator (SeOI) substrate. The data-path cell includes an array of field-effect transistors, each transistor having a source region, a drain region and a channel region formed in the thin semiconductor layer of the SeOI substrate, and further having a front gate control region formed above the channel region. In particular, one or more transistors of the data-path cell further includes a back gate control region formed in the bulk substrate beneath the channel region and configured so as to modify the performance characteristics of the transistor in dependence on its state of bias. Also, an integrated circuit including one or more of the data-path cells and methods for designing or driving these data-path cells. | 2011-09-08 |
20110215861 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device includes a photodiode, a first transistor, a second transistor, and a third transistor. The second transistor and the third transistor have a function of retaining a charge accumulated in a gate of the first transistor. In a period during which the second transistor and the third transistor are off, a voltage level of a voltage applied to a gate of the second transistor is set to be lower than a voltage level of a source of the second transistor and a voltage level of a drain of the second transistor, and a voltage level of a voltage applied to a gate of the third transistor is set to be lower than a voltage level of a source of the third transistor and a voltage level of a drain of the third transistor. | 2011-09-08 |
20110215862 | INTERNAL SUPPLY VOLTAGE CIRCUIT OF AN INTEGRATED CIRCUIT - The disclosure relates to a method for generating a setpoint voltage in an integrated circuit, comprising generating a substantially constant reference voltage, and generating from the reference voltage, a setpoint voltage comprising a component equal to the highest threshold voltage of all the CMOS transistors of a circuit of the integrated circuit and a component which may be equal to zero. The disclosure applies in particular to the provision of a power supply voltage of a circuit based on CMOS transistors. | 2011-09-08 |
20110215863 | Integrated Voltage Regulator with Embedded Passive Device(s) - A method of supplying voltage to a die mounted on a packaging substrate includes mounting an active portion of a voltage regulator on the packaging substrate. The method also includes coupling the active portion of the voltage regulator to at least one passive component at least partially embedded in the packaging substrate and coupling the die to the at least one passive component. Mounting the active portion of the voltage regulator includes mounting the die on the packaging substrate where the die includes the active portion of the voltage regulator. | 2011-09-08 |
20110215864 | SWITCHED CAPACITOR AMPLIFIER - Provided is a switched capacitor amplifier capable of outputting a stable output voltage. The switched capacitor amplifier is capable of operating so as to eliminate a charge/discharge time difference between an input capacitor ( | 2011-09-08 |
20110215865 | POWER AMPLIFIER - Disclosed herein is a power amplifier. The power amplifier includes N power amplification means, a transformer, and a harmonic elimination unit. Each of the N power amplification means amplifies an input signal into a predetermined level. The transformer includes N/2 primary windings respectively connected to the output terminals of the power amplification means and a secondary winding configured such that coil elements are connected in series between an output terminal and a ground, and sums power transmitted from the primary windings. The harmonic elimination unit is disposed across both ends of the secondary winding of the transformer, and eliminates the output of the harmonic frequencies of a preset frequency. | 2011-09-08 |
20110215866 | ASYMMETRIC MULTILEVEL OUTPHASING ARCHITECTURE FOR RF AMPLIFIERS - A radio frequency (RF) circuit includes a power supply configured to generate a plurality of voltages, a plurality of power amplifiers, each having an RF output port and a power supply input port, a switch network having a plurality of input ports coupled to the power supply and a plurality of switch network output ports coupled to the power supply input ports of the plurality of power amplifiers, wherein the switch network is configured to output selected ones of the plurality of voltages from the plurality of switch network output ports, at least two of the switch network output port voltages capable of being different ones of the plurality of voltages, and an RF power combiner circuit having a plurality of input ports coupled to RF output ports of the plurality of power amplifiers and an output port at which is provided an output signal of the RF circuit. | 2011-09-08 |
20110215867 | REDUCING PULSE ERROR DISTORTION - A class D amplifier that includes circuitry to apply a non-linear correction to pulse error distortion. The amplifier includes an output voltage controlling circuit, comprising at least two switches, controlled by a modulator; an output inductor, coupling the switching circuit to an output terminal; and correction circuitry to provide to the modulator a correction signal characterized by a non-linearity. The correction circuitry includes a current sensor that senses the current from the output inductor to the output terminal. | 2011-09-08 |
20110215868 | Operational Amplifier Having Improved Slew Rate - A slew rate improved operational amplifier circuit is provided to improve the slew rates of an operational amplifier with minimal sacrifices in power dissipation and other operational amplifier parameters. To improve the slew rates of operational amplifiers, additional current sources are activated when a slewing operation is detected. The detection of slewing operations and the activation of current sources upon detection can be implemented using two comparator circuits—one for a positive slewing operation, and one for a negative slewing operation. A sub-45 nm FinFET implementation of this slew rate improvement concept was implemented and compared against slew rate optimized individual two-stage operational amplifiers. Simulations show that slew rates were significantly improved by the implementation of the comparator circuits (5590 V/μs vs. 273 V/μs), with minimal increases in power dissipation (78 μW vs. 46 μW). | 2011-09-08 |
20110215869 | PARTIAL CASCODE IN COMBINATION WITH FULL CASCODE OPERATIONAL TRANSCONDUCTANCE AMPLIFIER - An amplifier circuit includes a first stage and a second stage. The first stage includes a differential input circuit coupled to a differential input node. The first stage includes a first partial cascode circuit including devices of a first type, the first partial cascode circuit being coupled to a first power supply node, a first bias node, and the differential input stage. The first stage includes a second partial cascode circuit including devices of a second type, the second partial cascode circuit being coupled to a second power supply node and the differential input circuit. The second stage is coupled to the first stage. The second stage includes a first full cascode circuit coupled to an output node. | 2011-09-08 |
20110215870 | BURST MODE AMPLIFIER - An integrator circuit cancels a DC offset component related to an average DC value of a burst mode input signal from the output of an amplifier. The integrator circuit outputs an average DC value of the input signal in a response time that is shorter than the preamble of a burst mode signal. The integrator output signal remains stable within selected amplitude limits for a length of time corresponding to the data portion of a burst mode signal. A transimpedance amplifier embodiment of the invention comprises a TIA gain stage, an integrator, and a voltage-controlled current course. Other embodiments comprise an amplifier for converting single-ended input signals to differential output signals, an amplifier for differential output offset cancellation, a monolithic semiconductor integrated circuit die, and a packaged semiconductor integrated circuit device. | 2011-09-08 |
20110215871 | Electronic circuits including a MOSFET and a dual-gate JFET - Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths. | 2011-09-08 |
20110215872 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes: digitally controlled oscillators; a phase-data output unit; an integration processing unit; a filter unit; a multiplier (a first multiplier) that outputs, as an oscillator tuning word, a value obtained by multiplying an output signal subjected to time division from the filter unit with a predetermined coefficient; and an output selector (a tuning-word separating unit) that allocates the oscillator tuning word to the digitally controlled oscillators in synchronization with a reference frequency. | 2011-09-08 |
20110215873 | NOVEL SWITCHED PHASE AND FREQUENCY DETECTOR BASED DPLL CIRCUIT WITH EXCELLENT WANDER AND JITTER PERFORMANCE AND FAST FREQUENCY ACQUISITION - Some embodiments of the present invention may include a DPLL circuit comprising a firmware. The firmware may comprise a re-sampled NCO phase detector capable of receiving a reference clock timing signal and a VCXO clock timing signal. The re-sampled NCO phase detector may comprise a resampler capable of receiving phase output and the VCXO clock timing signal and resampling the phase output; and a subtractor capable of receiving the resampled phase output and subtracting the resampled phase output from a calculated mean value of the phase output. The firmware may further comprise a frequency detector capable of receiving the reference clock timing signal and the VCXO clock timing signal; and a multiplexer capable of switching between the re-sampled NCO phase detector and the frequency detector dependent upon a frequency lock status. | 2011-09-08 |
20110215874 | NON-LINEAR OSCILLATOR - A non-linear oscillator for generating a first sinusoidal signal and a second sinusoidal signal includes a comparing device, a computing device, an integrator device, and a feedback device. The comparing device is operable to compare a reference signal with a feedback signal and output a comparison signal based on result of comparison made thereby. The computing device is operable to output first and second combined signals according to a predetermined frequency value, the comparison signal, the feedback signal and the first and second sinusoidal signals. The integrator device is operable to perform integration upon the first and second combined signals to output the first and second sinusoidal signals. The feedback device is operable to output the feedback signal to the comparing device and the computing device according to a first predetermined amplitude value and the first and second sinusoidal signals from the integrator device. | 2011-09-08 |
20110215875 | Phase-locked loop circuit, semiconductor integrated circuit, electronic device, and control method of phase-locked loop circuit - A phase-locked loop circuit includes: a phase and frequency comparing section configured to compare a phase of an external reference clock signal with a phase of a comparison clock signal, and generate an error signal corresponding to a result of comparison; an oscillating section configured to generate an internal clock signal of an oscillation frequency corresponding to the error signal; a frequency dividing section configured to generate the comparison clock signal by frequency-dividing the internal clock signal by a predetermined frequency dividing ratio; an oscillator control section configured to generate an oscillation control signal for controlling frequency of the internal clock signal output from the oscillating section on a basis of the error signal; and a frequency divider control section configured to generate a frequency division control signal for controlling a bias current of the frequency dividing section on a basis of the error signal. | 2011-09-08 |
20110215876 | METHOD AND ARRANGEMENT FOR VOLTAGE CONTROLLED OSCILLATOR DEVICE - Embodiments of the present invention relate to a self injection locked voltage controlled oscillator arrangement, a pair of coupled first and second voltage controlled oscillator devices are arranged on a chip, an amplifier device is arranged on the same of the refection type chip, and an off-chip delay line is arranged with one terminal connected to an output terminal of the coupled first and second voltage controlled oscillator devices, and on terminal adapted to reflect a signal from the output terminal, the amplifier device being arranged to amplify an injection signal from said output terminal and to supply the amplified injection signal to one of said first and second voltage controlled oscillation devices to provide a VCO arrangement that exhibits low phase noise and a small size. | 2011-09-08 |
20110215877 | MEMS RESONATOR - A MEMS circuit comprises a MEMS device arrangement with temperature dependent output; a resistive heating circuit; and a feedback control system for controlling the resistive heating circuit to provide heating in order to maintain a MEMS device at a constant temperature. The heating is controlled in dependence on the ambient temperature, such that a MEMS device temperature is maintained at one of a plurality of temperatures in dependence on the ambient temperature. This provides power savings because the temperature to which the MEMS device is heated can be kept within a smaller margin of the ambient temperature. | 2011-09-08 |
20110215878 | ATOMIC OSCILLATOR - An atomic oscillator, attention is paid to the fact that the degree of change of the energy difference between the two ground levels of the alkali metal atom with respect to the change of the magnetic field intensity is specific to each of the magnetic quantum numbers, a resonant light pair to cause a transition between the two ground levels corresponding to each of the plural magnetic quantum numbers is sequentially generated, plural pieces of profile information capable of specifying the energy difference between the two ground levels corresponding to each of the magnetic quantum numbers are sequentially acquired based on the detection signal, the change amount of the magnetic field intensity is specified based on the acquired plural pieces of profile information, and the control is performed so that the intensity of the magnetic field becomes constant. | 2011-09-08 |
20110215879 | PIEZOELECTRIC VIBRATOR MANUFACTURING METHOD, PIEZOELECTRIC VIBRATOR, OSCILLATOR, ELECTRONIC DEVICE, AND RADIO-CONTROLLED TIMEPIECE - A method for manufacturing a piezoelectric vibrator is provided. The piezoelectric vibrator includes: a package in which a first substrate and a second substrate are superimposed so as to form a cavity therebetween; extraction electrodes which are formed on the first substrate so as to be extracted from the inner side of the cavity to an outer edge of the first substrate; a piezoelectric vibrating reed which is sealed in the cavity and electrically connected to the extraction electrodes at an inner side of the cavity; and outer electrodes which are formed on an outer surface of the package so as to be electrically connected to the extraction electrodes at the outer side of the cavity. The method includes: a bonding film forming step of forming a bonding film on at least one of the first substrate and the second substrate using a low-melting-point glass so as to bond the two substrates; a mounting step of electrically connecting the piezoelectric vibrating reed to the extraction electrodes formed on the first substrate; and a bonding step of superimposing the first substrate and the second substrate onto each other with the bonding film disposed therebetween while heating the bonding film to a predetermined bonding temperature to thereby bond the two substrates by the bonding film. | 2011-09-08 |
20110215880 | Method and System for Flip Chip Configurable RF Front End With an Off-Chip Balun - Methods and systems for a flip chip configurable RF front end with an off-chip balun may include bonding a balun package to a single integrated circuit (IC) comprising an integrated transmitter and a receiver. The balun package may comprise one or more layers and may be electrically coupled to the IC. The balun package may comprise various devices such as, for example, inductors, capacitors, resistors, and/or switches, which may be on an exterior surface and/or inner layers of the balun package. Accordingly, the balun package and/or the IC may be configured for receiving RF signals and/or transmitting RF signals. The balun package and/or the IC may also be configured for single-ended RF input, single-ended RF output, differential RF input, and/or differential RF output. An off-chip amplifier may be used to amplify signals on the single transmit line in the single-ended RF output mode of operation. | 2011-09-08 |
20110215881 | Electrical Prism: A High Quality Factor Filter for Millimeter-Wave and Terahertz Frequencies - Filters and methods which may be used with millimeter-wave and terahertz frequency range are disclosed. The filter is formed as an electrical prism which may include a first lattice forming an interface with a second lattice. Each lattice may include a plurality of passive elements, such as inductors, capacitors, and the like. The first lattice may include an input disposed at an input boundary thereof, while the second lattice may include an output disposed at an output boundary thereof. Furthermore, the first and second lattices may be configured to receive a signal at the input of the first lattice, propagate the signal to the interface, and direct the signal to the outputs of the second lattice. | 2011-09-08 |
20110215882 | Interconnect for High-Frequency Printed Circuit - The invention relates to a printed circuit for high-frequency signals, and more particularly to interconnect means between transmission lines situated on different faces of the printed circuit. According to the invention, in the vicinity of the interconnect means, the transmission lines each extend in a main direction. The interconnect means comprise two vias each extending along an axis. In a plane containing the main direction of a first of the transmission lines and perpendicular to the face bearing the first transmission line, an orthogonal fix is formed whose abscissa is borne by the main direction of the first transmission line. The abscissae of the axes of the vias or of their projection on the plane, perpendicularly to the plane, are separate. | 2011-09-08 |
20110215883 | ACOUSTIC WAVE RESONATOR AND ACOUSTIC WAVE FILTER USING THE SAME - An acoustic wave resonator includes a piezoelectric substrate and first and second comb-shaped electrodes provided on the piezoelectric substrate and interdigitating with each other. The first comb-shaped electrode includes a first busbar and first electrode fingers extending in a direction non-perpendicular to a direction in which the first busbar extends. The second comb-shaped electrode includes a second busbar and second electrode fingers extending from the second busbar and interdigitating with the first electrode fingers at an interdigitating region. This acoustic wave resonator can suppress a spurious response due to a transverse mode and has a high Q value. | 2011-09-08 |
20110215884 | LADDER-TYPE FILTER - A ladder-type filter having plural elastic-wave resonators provided on a series arm and a parallel arm in a ladder shape on a piezoelectric substrate. Each of the elastic-wave resonators has an interdigital electrode. The interdigital electrode has plural electrode finger pairs formed of electrode fingers extending from first and second bus bars. The interdigital electrode included in the elastic-wave resonator provided on the parallel arm has an electrode cross width of the electrode fingers extending from the first and second bus bars 23 times or more of the wavelength of elastic waves excited by the interdigital electrodes. | 2011-09-08 |
20110215885 | Broadband Coupling Filter - A broadband coupling filter for generating a notch filtering effect is disclosed. In the broadband coupling filter, a substrate includes a first layer, a second layer and a third layer. A first signal terminal, a second signal terminal, and a block transmission line are formed in the first layer, wherein the first signal terminal is used for receiving a signal, and the second signal terminal is used for outputting a filtering result of the signal. A grounding plate is formed in the second layer, having a hole. A third signal terminal, a forth signal terminal and a second block transmission line are formed in the third layer. A connection unit is further formed in the third layer, for connecting the third signal terminal and the forth signal terminal. | 2011-09-08 |
20110215886 | MULTIROLE CIRCUIT ELEMENT CAPABLE OF OPERATING AS VARIABLE RESONATOR OR TRANSMISSION LINE AND VARIABLE FILTER INCORPORATING THE SAME - A variable resonator includes a first transmission line | 2011-09-08 |
20110215887 | WAVEGUIDE - A waveguide is provided that includes an elongate dielectric inner region, and an electrically conducting outer region spaced apart from the dielectric inner region. The dielectric inner region may be arranged to be flexible, and in some examples may be formed from powdered dielectric contained in a polymer tube or matrix, or in other examples may be formed from a plurality of segments. In some examples of the waveguide, each segment may be formed to have lenticular end faces, and may be formed from sintered BaTi | 2011-09-08 |
20110215888 | WIRELESS CONTROL OF MICROROBOTS - Wireless control of a microrobot can be performed using a magnetic field originating from a localized control magnet source relative to a body into which the microrobot is placed. Torque forces which contribute to rotation (and propulsion) of the microrobot can overcome magnetic forces which produce attraction or repulsion between the microrobot and the control magnet. | 2011-09-08 |
20110215889 | Stabilized ball bearings for camera lens - Systems and methods are disclosed for cameras using ball bearings to guide the movements of movable parts as e.g. a lens barrel wherein the repulsive force of magnets is used to hold the ball bearings together an hence the movable parts in place in case of a mechanical shock. In a first embodiment of the invention the magnets and the ball bearings are on a same side of the lens barrel. In a second embodiment of the invention the magnets and the ball bearings are on an opposite side of the lens barrel. Furthermore a camera has been disclosed wherein the shutter is moved by a linear motor and an integrated circuit controls the motor moving the shutter and the actuators moving the lens barrel. | 2011-09-08 |
20110215890 | Providing A Transformer For An Inverter - In one embodiment, a transformer is provided for coupling between a utility connection and a plurality of power cells of a drive system. The transformer may be of a horizontal arrangement and include a housing and a core configured within the housing and having multiple columns each adapted along a horizontal axis. Each column corresponds to a phase, and each phase includes a coil having primary winding and multiple secondary windings concentrically adapted about the column horizontal axis to provide an air gap between adjacent ones of the primary and secondary windings. In addition, the transformer may include a baffler adapted about the core and configured within the housing to prevent air flow at a periphery of the coils and to direct air flow through the air gaps of the coils. | 2011-09-08 |
20110215891 | INDUCTOR ASSEMBLY - An assembly includes a toroidal induction component, a potting cup, and potting material. The toroidal induction component includes a conductive winding, where at least ends of the conductive winding define a lead set of the toroidal induction component. The potting cup is configured to accept the toroidal induction component and its lead set. Techniques for forming the assembly are also described. | 2011-09-08 |
20110215892 | COIL ASSEMBLY HAVING PIN SUPPORT PORTIONS OF DIFFERENT LENGTH - A coil assembly having a simplified bobbin structure and facilitating connection of a draw-out portion of a wire to a pin terminal. A coil assembly includes first and second pin support portions protruding in a protruding direction from a terminal base. First and second pin terminals protrude in the protruding direction from free end faces of the first and second pin support portions, respectively. The draw-out portion is electrically connected to an associated one of the pin terminals. The second pin support portion provides a protruding length from the terminal base greater than that of the first pin support portion, and the free end face of the second pin support portion is positioned downstream, in the protruding direction, of an imaginary linear draw-out portion directed linearly from the wire engaging portion to the first pin terminal, such that the second pin support portion is positioned and sized to intersect with the imaginary linear draw-out portion. | 2011-09-08 |
20110215893 | PLANAR AUDIO AMPLIFIER OUTPUT INDUCTOR WITH CURRENT SENSE - An audio amplifier, that includes a planar inductor structure that includes a first plurality of windings, formed on layers of a first circuit board and a second plurality of windings, formed on layers of a second circuit board. The planar inductor structure may further include a sense winding. | 2011-09-08 |
20110215894 | SEMICONDUCTOR CERAMIC AND POSITIVE TEMPERATURE COEFFICIENT THERMISTOR - A semiconductor ceramic includes a Ba | 2011-09-08 |
20110215895 | SEMICONDUCTOR CERAMIC AND POSITIVE TEMPERATURE COEFFICIENT THERMISTOR - A semiconductor ceramic includes a Ba | 2011-09-08 |
20110215896 | SAFETY APPARATUS HAVING A CONFIGURABLE SAFETY CONTROLLER - A safety apparatus having a configurable safety controller ( | 2011-09-08 |
20110215897 | KEY CONTROL AND RELATED FLEET MANAGEMENT METHODS AND SYSTEMS - A method and system for managing a fleet of vehicles including a reservation system for generating a reservation code; a key cabinet including user-entry means for entering said reservation code and one or more key compartments storing keys for each vehicle in the fleet; a control module in communication with the reservation system and the key cabinet for assigning an unlocked condition to at least one of the key compartments based on entry of a reservation code. | 2011-09-08 |
20110215898 | LOCKING SYSTEM - An electronic locking system in which the control computer and a plurality of locking devices are connected by a data bus, and in which the communication between the external computers and each locking device is carried out by element of commands sent through the data bus. | 2011-09-08 |
20110215899 | METHOD AND SYSTEM FOR AUTHORIZING A VEHICLE DRIVEAWAY - Various embodiments may include methods and systems for authorizing a vehicle driveaway. A vehicle driveaway authorization code may be received by, for example, a computer system and circuit configured to receive the vehicle authorization code. The vehicle driveaway authorization code may have a corresponding user authorization code. Input may be received at the vehicle that defines the user authorization code. An identifying signal may also be wirelessly received to identify a wireless nomadic device in a vicinity of the vehicle. It may be determined whether the nomadic device was previously wirelessly paired with the vehicle based on the identifying signal. The vehicle driveaway authorization code may be compared to the user authorization code. If the nomadic device was previously wirelessly paired with the vehicle and if the vehicle driveaway authorization code corresponds to the user authorization code, a vehicle drive may be enabled. | 2011-09-08 |
20110215900 | MOBILE DEVICE COMMUNICATIONS MANAGEMENT - Implementation of mobile device communications (MCD) management is provided. A method includes intercepting an input command received on an MCD, the command intercepted in response to detecting a presence of a fixed communications device (FCD), which is embedded in a vehicle within range of the MCD. The method also includes acquiring biometric data from a user of the MCD. The method includes determining an activity status of the vehicle. If the activity status reflects the vehicle is active, the method includes acquiring biometric data for an operator of the vehicle via a biometric scanner of the vehicle and comparing the biometric data from the vehicle with the biometric data for the user of the MCD. If the biometric data from the vehicle matches the biometric data from the MCD, the method includes retrieving an account record for the user and implementing an action specified in the account record. If the activity status reflects the vehicle is inactive, the method includes executing the command. | 2011-09-08 |
20110215901 | METHOD AND SYSTEM FOR ENABLING AN AUTHORIZED VEHICLE DRIVEAWAY - Various embodiments may include methods and system for enabling an authorized vehicle driveaway. A vehicle driveaway authorization code for authorizing a vehicle to be driven and a user authorization code that corresponds to the vehicle driveaway authorization code may be generated. The codes may be generated by, for example, at least one server configured to generate the authorization codes. The at least one server may be communicating with a nomadic device and a vehicle driveaway authorization system. A vehicle driveaway request signal may be received. In response to a receipt of the vehicle driveaway request signal, the vehicle driveaway authorization code may be transmitted to the vehicle driveaway authorization system and the user authorization code may be transmitted to the nomadic device for input to the vehicle driveaway authorization system in order to enable the vehicle to be driven. | 2011-09-08 |
20110215902 | CUSTOMER RECOGNITION METHOD AND SYSTEM - Disclosed embodiments describe a customer recognition method and system. The customer recognition system has an acknowledgment server that carries out the customer recognition method. The customer recognition method may include storing customer profile data related to a customer and identity device data related to an identity device; receiving a unique device identifier from a sensor within communication range of the identity device; retrieving customer profile data from the profile database based on the received identifier; sending the customer profile data to the sensor; and receiving an acknowledgement status relating to the customer. | 2011-09-08 |
20110215903 | Apparatus and Associated Methods - In one or more embodiments described herein, there is provided an apparatus configured to identify a particular motion state of a portable electronic device, and vary the geographical location data sampling rate for the portable electronic device based on the identified particular motion state of the portable electronic device. | 2011-09-08 |
20110215904 | SHELF LAVEL MANAGINGSYSTEM, SHELF LABEL MANAGING METHOD AND SHELF LABEL MANAGING APPARATUS - Provided is a shelf label management system that offers improved convenience to a user. Each of a plurality of electronic shelf label terminals detects power-on and determines, based on the detection of the power-on, whether a system ID, which indicates the shelf label management system in which the electronic shelf label terminal is to enter, is recorded in a storage unit. If the system ID is not recorded in the storage unit, the electronic shelf label terminal transmits, to a shelf label management apparatus, a system entry request containing the terminal ID of the electronic shelf label terminal. The shelf label management apparatus receives the system entry request from the each of the plurality of electronic shelf label terminals in a period from a start time of a registration request receiving period to an ending time thereof, and registers, with a shelf label management table in a database, the terminal ID of the electronic shelf label terminal that has made the system entry request, as a terminal ID of an electronic shelf label terminal that can be registered in the shelf label management apparatus. The shelf label management apparatus then transmits, in response to the reception of the system entry request, a system entry completion notification to the electronic shelf label terminal that has transmitted the system entry request. | 2011-09-08 |
20110215905 | METHOD FOR PROTECTING DATA PRIVACY AND WIRELESS COMMUNICATION SYSTEM - A method for protecting data privacy of a mobile communication device includes detecting whether any RFID tag data is received, determining whether an RFID tag data is equal to a first RFID tag data corresponding to an RFID tag device stored in the mobile communication device when the RFID tag data is received, and prohibiting a specified service of the communication device from being accessed when the RFID tag data is not equal to the first RFID tag data. | 2011-09-08 |
20110215906 | INTERROGATOR AND CONTROL METHOD OF INTERROGATOR - An interrogator includes: an acquisition unit acquiring an identifier which is stored in a wireless tag and specifies a type of the wireless tag; and a communication unit executing wireless communication using a communication command at transmission power according to the acquired identifier. | 2011-09-08 |
20110215907 | RADIO FREQUENCY IDENTIFCATION (RFID) TAG AND OPERATION METHOD THEREOF, AND SYSTEM AND METHOD FOR CONTROLLING NETWORK ACCESS BASED ON MOBILE RFID - Disclosed are a radio frequency identification (RFID) tag capable of supplying an Internet service quickly and conveniently, an operation method thereof, and a system and method for controlling network access based on a mobile RFID. Network access data is generated by communication between an RFID terminal and an RFID tag. The mobile RFID terminal connects with a network gateway by reading the network access data, thereby supplying the Internet service quickly and conveniently. | 2011-09-08 |
20110215908 | RADIO SECURITY LEADER CONTROLLING OPERATION MODE, AND RADIO SECURITY TAG SUPPORTING SECURITY MODE AND NORMAL MODE - Disclosed are a radio secure reader and a radio secure tag for supporting a secure mode and a normal mode. The radio secure reader for controlling an operation mode of the radio secure tag may include a reader modem to receive the operation mode from the radio secure tag, and a reader processing unit to identify the received operation mode as a normal mode or a secure mode, and to control the radio secure tag based on the identified operation mode. | 2011-09-08 |
20110215909 | STRUCTURE INCLUDING AT LEAST TWO INTEGRATED MICROCIRCUIT DEVICES WITH CONTACTLESS COMMUNICATION - A structure including at least two separate integrated microcircuit devices with contactless communication, each including at least one chip and at least one antenna, said at least two integrated microcircuit devices being placed in or on the structure such that any simultaneous reading of more than one of the integrated microcircuit devices by an external reader is impossible in at least one position of the structure relative to the external reader. | 2011-09-08 |
20110215910 | Emergency ingress/egress monitoring system - A system to monitor the entry and exit of individuals from a facility and to identify individuals who safely evacuated the facility and those who have entered, but apparently have not safely evacuated it and indicated safe evacuation by use of a card reader or similar device at an emergency reporting area. The system also indicates the most likely area of a facility in which an individual may be found. Such census information is made available to emergency workers and is of significant value in rescue efforts following facility evacuations. A modification of the systems allows an attendant to monitor the entry, exit, and re-entry of individuals traveling in two or more vehicles following stops. Finally, the system includes a head count census of individuals entering large facilities in which individual identity is effectively impossible to follow and a head count census of individuals evacuating the facility identified by specific parts of the facility. | 2011-09-08 |
20110215911 | Method and system for monitoring data of personnel - A method and system ( | 2011-09-08 |
20110215912 | RFID TAG READER/WRITER - According to one embodiment, an RFID tag reader/writer includes a handle section, an operation input section arranged on the upper part of the handle section to receive an operation input and an antenna section rotatably supported by the handle section such that the antenna section is foldable and unfoldable against the handle section. | 2011-09-08 |