35th week of 2012 patent applcation highlights part 56 |
Patent application number | Title | Published |
20120221836 | Synchronizing Commands and Dependencies in an Asynchronous Command Queue - Provided are techniques for the managing of command queue dependencies and command queue synchronization. Incoming commands are actively tracked through their dependency relationships. Command dependencies may be tracked across multiple lists, including a submission list and a completion list. Each command on the submission list is prepared for processing and ultimately submitted to command processing logic. Command completion processing is performed on each command on the completion list, including by not limited to removing dependencies from pending commands and possibly queuing pending commands for submission to the command processing logic. Also provided as features of a command queue are a standby barrier, an active barrier and a marker. Standby and active barriers are employed to synchronize and track commands through the command queue. Markers are employed to track commands through the command queue. | 2012-08-30 |
20120221837 | RUNNING MULTIPLY-ACCUMULATE INSTRUCTIONS FOR PROCESSING VECTORS - The described embodiments include RunningMAC1P and RunningMAC2P instructions. In the described embodiments, a processor receives a first input vector, a second input vector, a third input vector, and a control vector. Upon executing a RunningMAC1P or a RunningMAC2P instruction, the processor sets a base value equal to a value from an element at a key element position in the first input vector. Next, the processor generates the result vector by, for each element of the result vector to the right of the key element position, setting the element in the result vector equal to a sum of the base value and a result of multiplying a value in each relevant element of the second input vector by a value in a corresponding element of the third input vector, from an element at the key element position to and including a predetermined element in the second input vector. | 2012-08-30 |
20120221838 | SOFTWARE PROGRAMMABLE HARDWARE STATE MACHINES - The present invention provides software programmable hardware state machines to detect a cause of an error in a processor and prevent the error from occurring. A processor core is provided that includes an execution unit, a programmable mask register and a buffer that stores values representing instructions dispatched to the execution unit. The processor core also includes control logic to determine whether there is a match between a sequence in the mask register and a sequence in the buffer and, upon detecting a match, to generate control signals to perform a desired action. The desired action prevents an unwanted change from occurring to the architectural state of the processor. The processor core further comprises a programmable fix register. In an embodiment, the control logic generates the control signals based on control bits stored in the fix register. | 2012-08-30 |
20120221839 | Memory Initialization method and Serial Peripheral Interface Using the Same - A memory initialization method for writing a system management firmware and a Basic Input/output system (BIOS) in a memory of an information system is disclosed. The memory initialization method includes writing the BIOS in the memory, arranging a Read-Only Memory (ROM) hole in the memory, and writing the system management firmware in the ROM hole. | 2012-08-30 |
20120221840 | ELECTRONIC DEVICE AND METHOD FOR STARTING APPLICATIONS IN THE ELECTRONIC DEVICE - An electronic device sets run types and startup information for applications within the electronic device, where each run type is associated with a signal triggered by a hardware component of the electronic device and the startup information of each application comprises a run type and a starting time of the application. In response to detecting a signal triggered by a hardware component of the electronic device, and having an application having a run type associated with the signal, the electronic device further determines if a time of triggering the signal accords with a starting time of the application. The application is started if the time of triggering the signal accords with the starting time of the application. | 2012-08-30 |
20120221841 | SYSTEM AND METHOD FOR SURELY BUT CONVENIENTLY CAUSING RESET OF A COMPUTERIZED DEVICE - Enhanced reset logic is included in a user's computerized device so that the device owner (e.g., the user's employer) can assure prompt reset (e.g., to insure device use of newly downloaded software versions or other control or security data) while still allowing user convenience (e.g., some limited continued normal use of the device before reset is forced upon the user thus permitting the user to avoid possibly aggravating losses of data and/or ongoing usage). | 2012-08-30 |
20120221842 | PROVISIONING OF OPERATING ENVIRONMENTS ON A SERVER IN A NETWORKED ENVIRONMENT - A computer deploys an operating environment onto a provisionable server. The computer assigns an operating environment from an operating environment configuration management database to the provisionable server in response to detecting a provisioning event. The computer stores a record of the assignment in a deployment configuration management database and updates a management server with a designated operating environment identifier of the assignment. | 2012-08-30 |
20120221843 | MULTI-PHASE RESUME FROM HIBERNATE - Resume of a computing device from hibernation may be performed in multiple phases. Each phase may partially restore a state of the computing device to an operational state and may establish an environment in which another phase of the resume is performed. The hibernation information may be partitioned to store separately data to be used at each resume phase. The information may be stored in a compressed form. In a first phase, a boot-level resume loader may restore a portion of the operating system based on a portion of the hibernation information. The restored portion may be used in a second phase to retrieve hibernation information from another portion through the operating system (OS). Multiple processors supported by the OS may read and decompress the hibernation information that is then moved back to operational memory. The operating system may support asynchronous disk input/output or other functions that accelerate the resume process. | 2012-08-30 |
20120221844 | OPERATING SYSTEM EXPERIENCE STATES - Aspects of the subject matter described herein relate to operating system experience states. Input may be received that requests a change from a current experience state to a target experience state. In response, state data may be obtained that indicates allowed experience states as well as component data that indicates components and relationships between components in the target experience state. This state data may then be used to change from the current experience state to a target experience state. The target experience state may be used, for example, to configure a server or other operating system. | 2012-08-30 |
20120221845 | SYSTEMS AND METHODS FOR MIGRATING DATA AMONG CLOUD-BASED STORAGE NETWORKS VIA A DATA DISTRIBUTION SERVICE - Embodiments relate to systems and methods for migrating data between cloud networks via a data distribution service. In aspects, an administrator of a data payload may wish to migrate the data payload from a host cloud network to a target cloud provider to leverage cost, security, redundancy, consolidation, or other advantages. The data distribution service can identify target cloud providers with sets of resources that are capable of hosting the data payload. Further, the data distribution service can determine that the target cloud providers are connected to or capable of being connected to the data distribution service via a set of dedicated communication channels. According to aspects, the data distribution service can receive the data payload from the host cloud network, and transport the data payload to a selected target cloud provider via the set of dedicated communication channels. | 2012-08-30 |
20120221846 | CRYPTOGRAPHIC SANCTION SERVER AND METHODS FOR USE THEREWITH - A sanction server includes a network interface that receives a request for media content from a client device and transmits first sanction data to a caching server and second sanction data to the client device. A sanction processing module generates the first sanction data based on a random number and generates the second sanction data based on the random number. The caching server generates first cryptographic data based on the first sanction data and sends the first cryptographic data to the client device. The client device generates second cryptographic data based on the first sanction data and sends the second cryptographic data to the caching server. The caching server generates a scrambling control word based on the first sanction data and the second cryptographic data. The client device generates the scrambling control word based on the second sanction data and the first cryptographic data. | 2012-08-30 |
20120221847 | SANCTIONED CLIENT DEVICE AND METHODS FOR USE THEREWITH - A client device includes a network interface that transmits a request for the media content to the sanction server, receives second sanction data from the sanction server, transmits second cryptographic data to the caching server, receives first cryptographic data from the caching server and that receives scrambled media content from the caching server. A random number generator generates a random number. A client processing module, in response to the second sanction data, generates the second cryptographic data based on the random number and the second sanction data, generates a scrambling control word based on the second sanction data and the first cryptographic data and descrambles the scrambled media content based on the scrambling control word. | 2012-08-30 |
20120221848 | SANCTIONING CONTENT SOURCE AND METHODS FOR USE THEREWITH - A content source includes a random number generator that generates scrambling control word based on at least one random number. A source processing module generates proxy data that includes cryptographic parameters that are based on the scrambling control word, generates cryptographic data and generates scrambled media content based on the scrambling control word. A network interface sends the proxy data to a sanction server, and sends the cryptographic data and the scrambled content to a caching server. | 2012-08-30 |
20120221849 | Scalable Distributed Web-Based Authentication - Web-based authentication includes receiving a packet in a network switch having at least one associative store configured to forward packet traffic to a first one or more processors of the switch that are dedicated to cryptographic processing if a destination port of the packet indicates a secure transport protocol, and to a second one or more processors of the switch that are not dedicated to cryptographic processing if the destination port does not indicate a secure transport protocol. If a source of the packet is an authenticated user, the packet is forwarded via an output port of the switch, based on the associative store. If the source is an unauthenticated user, the packet is forwarded to the first one or more processors if the destination port indicates a secure transport protocol, and to the second one or more processors if the destination port does not indicate a secure transport protocol. | 2012-08-30 |
20120221850 | System and Method for Reducing Computations in an Implicit Certificate Scheme - There are disclosed systems and methods for reducing the number of computations performed by a computing device constructing a public key from an implicit certificate associated with a certificate authority in an implicit certificate scheme. In one embodiment, the device first operates on the implicit certificate to derive an integer e. The device then derives a pair of integers (e | 2012-08-30 |
20120221851 | SOURCE CENTRIC SANCTION SERVER AND METHODS FOR USE THEREWITH - A sanction server includes a network interface that receives proxy data from a content source that includes cryptographic parameters that are based on a scrambling control word used to scramble the media content, receives a request for the media content from a client device, transmits the proxy data to the client device and transmits notification data to a caching server. The content source generates cryptographic data and sends the cryptographic data and the scrambled media content to the caching server. The caching server forwards the cryptographic data and the scrambled media content to the client device. The client device generates the scrambling control word for descrambling the scrambled media content based on the proxy data and the cryptographic data. | 2012-08-30 |
20120221852 | SANCTIONED CACHING SERVER AND METHODS FOR USE THEREWITH - A caching server includes a network interface receives first sanction data from the sanction server and transmits first cryptographic data to a client device, receives second cryptographic data from the device and that transmits scrambled media content to the client device. A random number generator generates a random number. A caching processing module, in response to the first sanction data, generates the first cryptographic data based on the random number and the first sanction data, generates a scrambling control word based on the first sanction data and the second cryptographic data and that generates the scrambled media content based on the scrambling control word. | 2012-08-30 |
20120221853 | EFFICIENT KEY HIERARCHY FOR DELIVERY OF MULTIMEDIA CONTENT - A Digital Rights Management (DRM) system provides a lightweight layering of encryption and decryption of keys that allows efficient use of different cryptographic techniques to effect the secure delivery of multimedia content. Asymmetric cryptography, where a public key is used to encrypt information that can only be decrypted by a matched private key, is used by the DRM system to deliver symmetric keys securely. | 2012-08-30 |
20120221854 | SECURE DATA PARSER METHOD AND SYSTEM - A secure data parser is provided that may be integrated into any suitable system for securely storing and communicating data. The secure data parser parses data and then splits the data into multiple portions that are stored or communicated distinctly. Encryption of the original data, the portions of data, or both may be employed for additional security. The secure data parser may be used to protect data in motion by splitting original data into portions of data that may be communicated using multiple communications paths. | 2012-08-30 |
20120221855 | SECURE DATA PARSER METHOD AND SYSTEM - A secure data parser is provided that may be integrated into any suitable system for securely storing and communicating data. The secure data parser parses data and then splits the data into multiple portions that are stored or communicated distinctly. Encryption of the original data, the portions of data, or both may be employed for additional security. The secure data parser may be used to protect data in motion by splitting original data into portions of data that may be communicated using multiple communications paths. | 2012-08-30 |
20120221856 | SECURE DATA PARSER METHOD AND SYSTEM - A secure data parser is provided that may be integrated into any suitable system for securely storing and communicating data. The secure data parser parses data and then splits the data into multiple portions that are stored or communicated distinctly. Encryption of the original data, the portions of data, or both may be employed for additional security. The secure data parser may be used to protect data in motion by splitting original data into portions of data that may be communicated using multiple communications paths. | 2012-08-30 |
20120221857 | System And Method For Securing And Tracking Files - A method, system and computer program product for securing and tracking restricted files stored in a data processing system is provided. The data processing system is connected to a server for sharing information. An entity requesting to access a restricted file is authenticated, based on certain policies defined by a system administrator. Further, the system maintains a log of operations executed on the restricted file, and sends a record of the log to the server. | 2012-08-30 |
20120221858 | Accelerated Key Agreement With Assisted Computations - A method is provided for obtaining a secret value for use as a key in a cryptographic operation, the secret value combining a private key, x, of one computing device with a public key, Y, of another computing device to obtain a secret value xY. The method includes obtaining a pair of scalars x | 2012-08-30 |
20120221859 | STRONG AUTHENTICATION TOKEN WITH ACOUSTIC DATA INPUT - Strong authentication tokens for generating dynamic security values having an acoustical input interface for acoustically receiving input data are disclosed. The tokens may also include an optical interface for receiving input data and may have a selection mechanism to select either the acoustical or the optical input interface to receive data. A communication interface may be provided to communicate with a removable security device such as a smart card and the token may be adapted to generate dynamic security values in cooperation with the removable security device. The acoustic signal received by the token may be modulated using a frequency shift keying modulation scheme using a plurality of coding frequencies to code the acoustical signal where each coding frequency may be an integer multiple of a common base frequency. | 2012-08-30 |
20120221860 | METHOD AND APPARATUS FOR ENCODING AND DECODING DATA TRANSMITTED TO AN AUTHENTICATION TOKEN - Methods and apparatus for encoding and decoding data transmitted acoustically and/or optically to strong authentication tokens to generate dynamic security values are disclosed. The tokens may also include a selection mechanism to select either an acoustical or an optical input interface to receive data. A communication interface may be provided to communicate with a removable security device such as a smart card and the token may be adapted to generate dynamic security values in cooperation with the removable security device. | 2012-08-30 |
20120221861 | METHOD AND APPARATUS FOR PROVIDING END-TO-END SECURITY FOR DISTRIBUTED COMPUTATIONS - An approach is provided for providing end-to-end security in multi-level distributed computations. A distributed computation security platform determines one or more signatures associated with one or more computation closures of at least one functional flow. The distributed computation security platform also processes and/or facilitates a processing of the one or more signatures to generate at least one supersignature. The distributed computation security platform further determines to associate the at least one supersignature with the at least one functional flow. | 2012-08-30 |
20120221862 | Multifactor Authentication System and Methodology - A system is provided for authenticating a user who is accessing a secure network from a client device. The system comprises a software program resident on the client device, wherein said program is disposed in a tangible medium and contains suitable instructions for generating a session-specific, time-independent password on demand. | 2012-08-30 |
20120221863 | AUTHENTICATION SYSTEM - The present invention aims to provide an authentication system that can accurately identify a genuine product. In an authentication system, a host instructs an authentication chip master to start authentication. In conjunction with the authentication start execution instruction, the host instructs a timer counter to start timer counting. In response to the authentication start execution instruction from the host, the authentication chip master outputs a challenge code to an authentication chip slave. The authentication chip slave performs an encryption process with respect to the challenge code. Then, the authentication chip slave outputs a response code obtained as the result of the encryption process, to the authentication chip master. Then, the authentication chip master performs a response code matching process, and outputs the authentication result to the host. In response to the authentication result, the host stops timer counting, and performs a verification process to accurately identify the genuine chip. | 2012-08-30 |
20120221864 | METHOD AND APPARATUS FOR COMPUTER CODE OBFUSCATION AND DEOBFUSCATION USING BOOT INSTALLATION - In the field of computer software, obfuscation techniques for enhancing software security are applied to compiled (object) software code. The obfuscation results here in different versions (instances) of the obfuscated code being provided to different installations (recipient computing devices). The complementary code execution uses a boot loader or boot installer-type program at each installation which contains the requisite logic. Typically, the obfuscation results in a different instance of the obfuscated code for each intended installation (recipient) but each instance being semantically equivalent to the others. This is accomplished in one version by generating a random value or other parameter during the obfuscation process, and using the value to select a particular version of the obfuscating process, and then communicating the value along with boot loader or installer program software. | 2012-08-30 |
20120221865 | METHOD AND APPARATUS FOR PROTECTING CACHED STREAMS - A system and method for protecting cached streamed data is disclosed. The method may include the steps of generating an encryption key from the streamed data itself, encrypting the streamed data stored in the storage device and requesting the portion of the streamed data from the content server again when later playback is desired so as to allow the content server to enforce access limitations or takedown policies relating to the streamed data. The method may also include procedures for handling key generation over reliable or unreliable protocols. | 2012-08-30 |
20120221866 | SYSTEM AND METHOD FOR SECURELY STORING FIRMWARE - A mechanism for creating secure storage for firmware for a computing device. A designated secure storage area holding firmware that is executable prior to a loading of an operating system for the computing device is created during a build of a ROM image. The creating marks one or more files as requiring encrypted storage and the one or marked files are combined during the build into the designated secure storage area. The designated secure storage area is located outside the ROM image and includes, during the build of the ROM image, a reference to the designated secure storage area in a build of firmware placed in the ROM image. The reference includes a flag indicating a current encrypted status of the designated secure storage area. | 2012-08-30 |
20120221867 | SECURE CACHING TECHNIQUE FOR SHARED DISTRIBUTED CACHES - The present invention relates to a secure caching technique for shared distributed caches. A method in accordance with an embodiment of the present invention includes: encrypting a key K to provide a secure key, the key K corresponding to a value to be stored in a cache; and storing the value in the cache using the secure key. | 2012-08-30 |
20120221868 | POWER-ALLOCATION INTERFACE - Management of battery resources of an electronic device are disclosed. The electronic device has a battery, a display in communication with the battery, multiple subsystems in communication with the battery, and a user interface in communication with the subsystems. On the display is presented an indication of usage of the battery resources by the subsystems in executing functions by the device. With the interface, a user directive is received to reallocate the usage of the battery resources. The usage of the battery resources are thus reallocated in accordance with the user directive. | 2012-08-30 |
20120221869 | Accessory Power Management - Methods, apparatus, and circuits for managing power among portable computing devices and one or more accessories. One example provides commands to improve power management between a portable computing device and one or more accessories. Other examples provide commands that may allow a portable computing device to charge at a maximum available current level while providing an accessory with sufficient current for its proper operation. Another may help prevent a portable computing device from drawing a high level of current that could be detrimental to an accessory, while others provide commands that may allow a battery pack to instruct a portable computing device to not charge its internal battery. Another example may allow a portable computing device to determine which power supply among multiple power supplies should be used to power an accessory, while others may allow an accessory to retrieve charging current parameters from a portable computing device. | 2012-08-30 |
20120221870 | COMPUTER AND METHOD FOR CONTROLLING OPERATING STATE OF DEVICE THEREOF - A computer and a method for controlling an operating state of a device thereof are disclosed. The method comprises: detecting that a display portion and a host portion of the computer are in a state of being disconnected from each other; and generating a state event or a control instruction corresponding to the disconnected state for switching the device to an inactive state. With the present invention, when the state of a computer changes, e.g., when a display portion and a host portion of a portable computer are separated, an operating system can control a device to switch its operating state, e.g., deactivate the device, based on a generated state event. In this way, it is possible to avoid unnecessary power consumption of the entire computer due to the active state of the device, and any potential security risk can be eliminated. | 2012-08-30 |
20120221871 | METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING DETECTING AND CONTROLLING CURRENT RAMPS IN PROCESSING CIRCUIT - Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first indication of power consumed by the processor as a result of performing a first set of operations and a second indication of power consumed by the processor as a result of performing a second set of operations. The rate at which operations are performed by the processor may be adjusted when the comparison indicates that a difference between the first indication of power consumed by the processor and the second indication of power consumed by the processor is greater than a threshold value. | 2012-08-30 |
20120221872 | System and Method for Adapting a Power Usage of a Server During a Data Center Cooling Failure - A method includes detecting that a rate of temperature change in a server is above a threshold rate, changing the server to a lowest system performance state when the rate of the temperature change in the server is above the threshold rate, and reducing a fan speed to a minimum fan speed level when the rate of temperature change is above the threshold rate. | 2012-08-30 |
20120221873 | Method, Apparatus, and System for Energy Efficiency and Energy Conservation by Mitigating Performance Variations Between Integrated Circuit Devices - According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device. | 2012-08-30 |
20120221874 | Methods And Apparatuses For Controlling Thread Contention - An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first number based on processor clock cycles per instruction (CPI) associated with a second core is higher than a first threshold. The controller is operable to increase the operating point of the first core if the first number is lower than a second threshold. | 2012-08-30 |
20120221875 | MULTI-PHASE RESUME FROM HIBERNATE - Resume of a computing device from hibernation may be performed in multiple phases. Each phase may partially restore a state of the computing device to an operational state and may establish an environment in which another phase of the resume is performed. The hibernation information may be partitioned to store separately data to be used at each resume phase. The information may be stored in a compressed form. In a first phase, a boot-level resume loader may restore a portion of the operating system based on a portion of the hibernation information. The restored portion may be used in a second phase to retrieve hibernation information from another portion through the operating system (OS). Multiple processors supported by the OS may read and decompress the hibernation information that is then moved back to operational memory. The operating system may support asynchronous disk input/output or other functions that accelerate the resume process. | 2012-08-30 |
20120221876 | LOW POWER CONSUMPTION CIRCUIT AND METHOD FOR REDUCING POWER CONSUMPTION - An exemplary low power consumption circuit includes a microprocessor, a power supply switch module and a main circuit module. The microprocessor is capable of outputting a power control signal and changing a pulse characteristic of the power control signal when the microprocessor switches from a first working mode to a second working mode. The power supply switch module is capable of outputting a power supply signal. The power supply switch module is electrically coupled to the microprocessor to receive the power control signal and thereby modulates a duty cycle of the power supply signal according to a change of the pulse characteristic of the power control signal. The main circuit module is electrically coupled to the power supply switch module to receive the power supply signal and operative with energy provided by the power supply signal. Moreover, a method for reducing power consumption is also provided. | 2012-08-30 |
20120221877 | METHOD AND APPARATUS FOR MANAGING POWER LEVELS IN A HANDHELD MOBILE COMMUNICATION DEVICE - A method includes: monitoring a battery charge level in a mobile communication device operable to receive new e-mail messages when an e-mail polling operation is executed; and varying an email polling interval as a function of the battery charge level. | 2012-08-30 |
20120221878 | POWER ALLOCATION IN DEVICES - Management of power resources of an electronic device are disclosed. The electronic device has multiple subsystems in communication with a power supply, and an interface in communication with the subsystems. A directive is received with the interface to perform a function with the electronic device. A subset of the subsystems needed to perform the function are identified. For each identified subsystem and in response to receipt of the directive, a predicted power-resource quantity needed to perform the function is determined. A determination is made whether sufficient unallocated resources of the power supply are available to accommodate the predicted power-resource quantity for each identified subsystem. Respective portions of the available and unallocated resources of the power supply are accordingly allocated for use by respective identified subsystems in accordance with the determined power-resource quantities, with such allocation rendering the respective portions unavailable for use other than by the respective subsystems. | 2012-08-30 |
20120221879 | THREE STAGE POWER UP IN COMPUTER STORAGE SYSTEM - Following a loss of power, a storage system switches to a local power supply. The system switches to the local power supply, prevents the receipt of input/output commands and copies the content of cache memory to a local storage device. On detecting resumption of external power, the system charges a local power supply, copies the content of the local storage device to the cache memory and processes the content of the cache memory with respect to at least one storage volume. When the charge stored on the local power supply exceeds the charge required to copy the content of the cache memory to the local storage device by a predetermined amount, the system allows the receipt of input/output commands using a reduced portion of the cache memory. Once the charge stored on the local power supply has reached a predetermined level, the system allows the receipt of input/output commands using all cache memory. | 2012-08-30 |
20120221880 | MEMORY SYSTEM AND METHOD OF CONTROLLING SAME - A memory system comprises a controller that generates a processor clock, and a plurality of memory devices each comprising an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times. | 2012-08-30 |
20120221881 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR MEASURING A COMMUNICATION FROM A FIRST DEVICE TO A SECOND DEVICE - In response to communications from a first device to a second device, respective phase differences are estimated between a first clock of the first device and a second clock of the second device. A first average phase difference is computed within a percentile of a first subset of the respective phase differences. The percentile is less than 100. A second average phase difference is computed within the percentile of a second subset of the respective phase differences. The second subset is a modification of the first subset. The second average phase difference is computed in response to the first average phase difference and the modification. | 2012-08-30 |
20120221882 | Reducing Latency In Serializer-Deserializer Links - A system for increasing the efficiency of data transfer through a serializer-deserializer (SerDes) link, and for reducing data latency caused by differences between arrival times of the data on the SerDes link and the system clock with which the device operates. | 2012-08-30 |
20120221883 | DEVICE CONFIGURED TO SWITCH A CLOCK SPEED FOR MULTIPLE LINKS RUNNING AT DIFFERENT CLOCK SPEEDS AND METHOD FOR SWITCHING THE CLOCK SPEED - A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports. | 2012-08-30 |
20120221884 | ERROR MANAGEMENT ACROSS HARDWARE AND SOFTWARE LAYERS - Generally, this disclosure provides error management across hardware and software layers to enable hardware and software to deliver reliable operation in the face of errors and hardware variation due to aging, manufacturing tolerances, etc. In one embodiment, an error management module is provided that gathers information from the hardware and software layers, and detects and diagnoses errors. A hardware or software recovery technique may be selected to provide efficient operation, and, in some embodiments, the hardware device may be reconfigured to prevent future errors and to permit the hardware device to operate despite a permanent error. | 2012-08-30 |
20120221885 | MONITORING DEVICE, MONITORING SYSTEM AND MONITORING METHOD - A monitoring device including: a receiving unit configured to receive a malfunction notice of a data processing device, the data processing device being connected to the monitoring device which monitors running condition through a network; a malfunction device identification unit configured to identify a data processing device that is malfunctioning based on the received malfunction notice; a data obtaining unit configured to obtain running data and device data of the data processing device that is malfunctioning and an another data processing device; and a malfunction cause identification unit configured to identify a cause of the malfunction, based on the obtained running data and the obtained device data. | 2012-08-30 |
20120221886 | DISTRIBUTED JOB SCHEDULING IN A MULTI-NODAL ENVIRONMENT - Techniques are described for decentralizing a job scheduler in a distributed system environment. Embodiments of the invention may generally include receiving a job to be performed by a multi-nodal system which includes a cluster of nodes. Instead of a centralized job scheduler assigning the job to a node or nodes, each node has a job scheduler which scans a shared-file system to determine what job to execute on the node. In a job requiring multiple nodes, one of the nodes that joined the multi-nodal job becomes the primary node which then assigns and monitors the job's execution on the multiple nodes. | 2012-08-30 |
20120221887 | Migrating Virtual Machines Among Networked Servers Upon Detection Of Degrading Network Link Operation - Migrating virtual machines among networked servers, the servers coupled for data communications with a data communications network that includes a networking device, where migrating includes: establishing, by a virtual machine management module (‘VMMM’), one or more virtual machines on a particular server; querying, by the VMMM, the networking device for link statistics of a link coupling the network device to the particular server for data communications; determining, by the VMMM in dependence upon the link statistics, whether the link coupling the network device to the particular server is degrading; and if the link coupling the network device to the particular server is degrading, migrating a virtual machine executing on the particular server to a destination server. In some embodiments, migrating occurs is carried out only if non-degrading link is available. If no non-degrading links are available, the network device, rather than the link, may be failing. | 2012-08-30 |
20120221888 | METHOD AND APPARATUS FOR ADDRESSING ACTUAL OR PREDICTED FAILURES IN A FLASH-BASED STORAGE SYSTEM - Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of adapting to the failure of one or more FLASH memory devices in the memory system. The controller stores data in the form of page stripes, each page stripe composed of data pages, and each data page stored in a different FLASH memory device. The controller also detects failure of a FLASH memory device in which a data page of a particular page stripe is stored, reconstructs the data page, and stores the reconstructed data page in a new page stripe, where the number of data pages in the new page stripe is less than the number of data pages in the particular page stripe, and where no page of the new page stripe is stored in a memory location within the failed FLASH memory device. | 2012-08-30 |
20120221889 | SYSTEM AND METHOD FOR DUPLEXED REPLICATED COMPUTING - Systems and methods are disclosed herein for a replicated duplex computer system. The system includes a triplet of network elements, which each maintain a clock signal, and a monitor at each network element for monitoring incoming clock signals. Each network element interfaces with a fault containment region (FCR). The system provides the ability to transition to a duplex system if one of the fault containment regions fails. The three network elements are able to send their clock signals to the other network elements and receive their own clock signal and clock signals from the other elements. The monitors are configured to detect discrepancies in the clock signals of the network elements. If a monitor determines that an FCR has failed, each network element is reconfigured so that the FTPP system operates in a duplex mode without the faulty FCR by replacing the clock signal from the faulty element with its own clock signal. | 2012-08-30 |
20120221890 | MECHANISM FOR MANAGING KERNEL APPLICATION BINARY INTERFACE/APPLICATION PROGRAMMING INTERFACE-BASED DISCREPANCIES RELATING TO KERNEL PACKAGES - A method for managing kernel interface-based discrepancies may include finding a software package having a first version of a kernel package, and retrieving a first kernel interface information from a first file within the kernel package. The first kernel interface information relates to kernel interfaces associated with the kernel package, wherein the interfaces include kernel application binary interface (kABI). The method may further include forming a first dataset including the first kernel interface information relating to the first version of the kernel package, and detecting kernel discrepancies by comparing the first dataset with a second dataset relating to a second version of the kernel package. | 2012-08-30 |
20120221891 | PROGRAMMABLE CONTROLLER - A CPU saves a portion of device data stored in a device memory into a save memory every time a scanning process is performed so that the device data can be reliably saved even if a voltage holding time is shortened due to degradation of an electrolytic capacitor, and when a power-failure detecting circuit detects power failure of a main power supply, the CPU saves a remaining portion of the device data stored in the device memory using a power supply held by the electrolytic capacitor. When a capacity of the electrolytic capacitor detected by a capacitor-capacity detecting circuit is reduced, the CPU changes a size of the device data to be saved by a saving process performed every time the scanning process is performed according to the capacity of the electrolytic capacitor detected by the capacitor-capacity detecting circuit such that the size of the device data to be saved every time the scanning process is performed is increased. | 2012-08-30 |
20120221892 | COMPUTER SYSTEM, CONTROL METHOD THEREOF AND RECORDING MEDIUM STORING COMPUTER PROGRAM THEREOF - A computer system, a control method thereof and a recording medium storing a computer program thereof are provided to recover a program efficiently and be resistant to viruses, worms, and user error. The control method of computer system receives a user's request for a recovery of a program which is installed in a first storage unit. A file system of a second storage unit is determined which stores therein a recovery program corresponding to the program for which the recovery is requested. The recovery program is read from the second storage unit with reference to the determined file system, and the program in the first storage unit is recovered by using the read recovery program. | 2012-08-30 |
20120221893 | MANAGING TEST AUTOMATION - Systems, methods and computer program products relating to test automation management are described. In some aspects, a request for initiating at least one test automation task is received by an electronic computing device from a mobile device. A web service associated with the received request and at least one automation tool are identified. At least one automation tool is launched in response to the received request. The launched at least one automation tool executes at least one test script based on the received request, the at least one test script can include a sequence of instructions. Test data are loaded based on at least a portion of the executed a sequence of instructions for the at least one test automation task, and one or more test results associated with the executed at least one test script are stored. | 2012-08-30 |
20120221894 | TEST DATA MANAGEMENT SYSTEM AND METHOD - In a test data management method, an electronic signal that needed to be tested of an electronic device is select. A predefined template file of a test report of the electronic signal is generated. Test data of the electronic signal is obtained from a test file, and is inserted into predetermined locations of the template file. The test report of the electronic signal is generated according to the template file and the inserted test data, and the test report is stored into a storage system of a computing device. | 2012-08-30 |
20120221895 | SYSTEMS AND METHODS FOR COMPETITIVE STIMULUS-RESPONSE TEST SCORING - Systems and methods for competitively scoring a stimulus-response test are disclosed. Competitive scoring may be based upon: i) a combination of response time and response type (e.g., false start, coincident false start, fast, slow, lapse, timeout, etc.); ii) response time and response latency correction data (e.g., a latency correction parameter corresponding to the test-taker's test system); and iii) a composite score metric comprising any function, rule of categorization, classification system, scoring system and/or the like that can be applied to at least two stimulus-response rounds of one or more test takers to determine a score for each test-taker. | 2012-08-30 |
20120221896 | GENERATION OF REALISTIC FILE CONTENT CHANGES FOR DEDUPLICATION TESTING - Data to be processed through deduplication product testing is arranged into a single, continuous stream. At least one of a plurality of random modifications are applied to the arranged data in a self-similar pattern exhibiting scale invariance. A plurality of randomly sized subsets of the arranged data modified with the self-similar pattern is mapped into each of a plurality of randomly sized deduplication test files. | 2012-08-30 |
20120221897 | Method and Device for Performing Failsafe Hardware-Independent Floating-Point Arithmetic - A method and device offering a software diversity of the cited type for floating-point arithmetic, which is applicable in a realtime environment, wherein the method and a device for high-performance validation of the calculation use floating-point numbers of any accuracy within the context of functional safety in accordance with International Electrotechnical Commission (IEC) standard 61508. The method utilizes a specific form of software diversity and has effects on both the runtime environment and the engineering environment. | 2012-08-30 |
20120221898 | SYSTEM AND METHOD FOR DETERMINATION OF THE ROOT CAUSE OF AN OVERALL FAILURE OF A BUSINESS APPLICATION SERVICE - An ontology is generated for a business application on an enterprise network that describes one or more nodes that communicate with each other during the execution of the business application. An alert condition of the business application is detected, and the ontology for the business application is processed to determine one or more components of the ontology that are in an alert state. Further, a root cause view that indicates the one or more alert state components is generated and displayed to a user. | 2012-08-30 |
20120221899 | METHODS, SYSTEMS, AND COMPUTER READABLE MEDIA FOR POLICY AND CHARGING RULES FUNCTION (PCRF) FAULT TOLERANCE - Methods, systems, and computer readable media for PCRF fault tolerance are disclosed. One exemplary method for PCRF fault tolerance includes sending, from the PCRF to a Diameter peer, a message concerning Diameter application session state information associated with Diameter application sessions currently or previously managed by the PCRF. The method further includes receiving, by the PCRF, a message from the Diameter peer in response to the message concerning the Diameter application session state information. The method further includes, determining, by the PCRF and based on the response, whether the Diameter application session state information maintained by the PCRF is accurate. The method further includes, in response to determining that the Diameter application session state information maintained by the PCRF is not accurate, requesting, by the PCRF, Diameter application session state information. | 2012-08-30 |
20120221900 | SYSTEM DEPLOYMENT DETERMINATION SYSTEM, SYSTEM DEPLOYMENT DETERMINATION METHOD, AND PROGRAM - A system deployment determination system is provided that can appropriately define the number of information processing apparatuses that satisfies availability defined in an SLA as the number of information processing apparatuses used in a target system to be configured. The list generating means | 2012-08-30 |
20120221901 | ERROR REPORT MANAGEMENT - Apparatuses, systems and methods are provided for managing error reporting in an information technology environment in which a plurality of information technology devices are connected to a network. | 2012-08-30 |
20120221902 | BIT-REPLACEMENT TECHNIQUE FOR DRAM ERROR CORRECTION - The disclosed embodiments provide a dynamic memory device, comprising a set of dynamic memory cells and a set of replacement dynamic memory cells. The set of replacement dynamic memory cells includes data cells which contain replacement data bits for predetermined faulty cells in the set of dynamic memory cells, and address cells which contain address bits identifying the faulty cells, wherein each data cell is associated with a group of address cells that identify an associated faulty cell in the set of dynamic memory cells. The dynamic memory device also includes a remapping circuit, which remaps a faulty cell in the set of dynamic memory cells to an associated replacement cell in the set of replacement cells. | 2012-08-30 |
20120221903 | TESTING METHOD, NON-TRANSITORY, COMPUTER READABLE STORAGE MEDIUM AND TESTING APPARATUS - A method for testing data, has writing, in a first area of the test-target area, a test pattern, transferring, to a second area of the test-target area, the test pattern that has been written in the first area, transferring, to the first area, the test pattern that has been transferred to the second area, using as a transfer start address an address that is shifted by a predetermined amount, and inspecting whether or not the data is correctly written in and read from the test-target area by comparing the base patterns disposed next to each other in the base-pattern pair included in the test pattern that has been transferred from one of the first area and the second area to the other of the first area and the second area and by determining whether or not the base patterns disposed next to each other are identical to one another. | 2012-08-30 |
20120221904 | NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A nonvolatile memory device includes a first storage unit configured to store a plurality of first fault address information provided in a first test operation, a second storage unit configured to store a plurality of second fault address information provided in a second test operation which is performed later than the first test operation; a redundancy operation unit configured to, in performing a redundancy operation, determine the number of operation circuits corresponding to the first fault address information and the number of operation circuits corresponding to the second fault address information among a plurality of redundancy operation circuits based on address number information; and an address providing unit configured to read the plurality of first fault address information and the plurality of second fault address information, and sequentially provide the read information to the redundancy operation unit, wherein the address providing unit is further configured to detect the number of the first fault address information and generate the address number information. | 2012-08-30 |
20120221905 | Managing Memory Faults - Embodiments are described for managing memory faults. An example system can include a memory controller module to manage memory cells and report memory faults. An error buffer module can store memory fault information received from the memory controller. A notification module can be in communication with the error buffer module. The notification module may generate a notification of a memory fault in a memory access operation. A system software module can provide services and manage executing programs on a processor. In addition, the system software module can receive the notifications of the memory fault for the memory access operation. A notification handler may be activated by an interrupt when the notification of the memory fault in the memory access operation is received. | 2012-08-30 |
20120221906 | SCAN-BASED MCM INTERCONNECTING TESTING - A multi-die chip module (MCM) comprises a first die containing a first test controller and a second die containing a second test controller coupled to the first die via an interconnect. The first test controller is configured to place the first die in either a shift mode or a capture mode. The second controller is configured to place the second die in either the shift mode or the capture mode. After a scan shift operation, scan cells are initialized to predetermined values. During the capture operation one die remains in the shift mode and the other die enters the capture mode so that as test bits are shifted into registers associated with output pads on the die in the shift mode, the other die is in the capture mode and captures signals on input pads associated with that die, enabling scan based at-speed testing of the interconnect. | 2012-08-30 |
20120221907 | HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATED CIRCUITS - An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation. | 2012-08-30 |
20120221908 | JTAG BUS COMMUNICATION METHOD AND APPARATUS - The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state. | 2012-08-30 |
20120221909 | SHADOW ACCESS PORT METHOD AND APPARATUS - The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal. | 2012-08-30 |
20120221910 | MICROCONTROLLER FOR LOGIC BUILT-IN SELF TEST (LBIST) - Built-in self-test (BIST) microcontroller integrated circuit adapted for logic verification. Microcontroller includes a plurality of hardware description language files representing a hierarchical description of the microcontroller, the plurality of hardware description language files including a library of circuit design elements, a plurality of library design circuit elements adapted to store a uniquely defined set of input and output signals to enable a logic BIST, and a plurality of latches adapted to store a plurality of values corresponding to a behavioral profile of a test clock. | 2012-08-30 |
20120221911 | EMBEDDED PROCESSOR - Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed. | 2012-08-30 |
20120221912 | OPTICAL TRANSMISSION AND RECEPTION SYSTEM AND OPTICAL RECEPTION DEVICE - An object of the invention of the present patent application is to provide a frame synchronization technique that will not be prone to enter a frame asynchronization state even if a bit error occurs over a transmission path and the technique serves to convert a received optical signal into an electric signal, correct an error of the electric signal so as to cause a frame synchronization establishment state to occur, count the successive number of synchronization words that have bit errors in excess of an allowable value in an error-correction-coded electric signal after the frame synchronization establishment state has occurred, and determine that a frame asynchronization state has occurred when the successive number reaches a predetermined number. | 2012-08-30 |
20120221913 | ERROR CORRECTION CODES FOR INCREMENTAL REDUNDANCY - A method includes accepting input including at least part of a codeword that has been encoded by an ECC defined by a set of parity check equations. The codeword includes data bits and parity bits. A decoding process is applied to the codeword using the data bits and only a first partial subset of parity bits in the input, and using only a second partial subset of equations. Upon a failure to decode the codeword using the partial subsets, the codeword is re-decoded using the data bits and all parity bits in the input, and using all equations. The set of parity check equations is defined such that any parity bit in the codeword appears in multiple equations, and any parity bit in the first partial subset of the parity bits appears in a plurality of equations in the second partial subset of the equations. | 2012-08-30 |
20120221914 | Non-Concatenated FEC Codes for Ultra-High Speed Optical Transport Networks - A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture. | 2012-08-30 |
20120221915 | SATELLITE COMMUNICATION SYSTEM UTILIZING LOW DENSITY PARITY CHECK CODES - An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) coded message. The coded message is modulated according to a high order modulation scheme that has a signal constellation representing more than two symbols per signaling point—e.g., 8-PSK (Phase Shift Keying) and 16-QAM (Quadrature Amplitude Modulation). The system includes a transmitter configured to propagate the modulated signal over the satellite. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates. | 2012-08-30 |
20120221916 | MEMORY ARRAY ERROR CORRECTION APPARATUS, SYSTEMS, AND METHODS - Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles. | 2012-08-30 |
20120221917 | ERROR CONTROL IN MEMORY STORAGE SYSTEMS - A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors. | 2012-08-30 |
20120221918 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code. | 2012-08-30 |
20120221919 | ERROR DETECTION AND CORRECTION CIRCUITRY - Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error. | 2012-08-30 |
20120221920 | MULTIPLE ERASURE CORRECTING CODES FOR STORAGE ARRAYS - Embodiments of the invention relate to erasure correcting codes for storage arrays. An aspect of the invention includes receiving a read stripe from a plurality of storage devices. The read stripe includes a block of pages arranged in rows and columns, with each column corresponding to one of the storage devices. The pages include data pages and parity pages, with the number of parity pages at least one more than the number of rows and not a multiple of the number of rows. The method further includes reconstructing at least one erased page in response to determining that the read stripe includes the at least one erased page and that the number of erased pages is less than or equal to the number of parity pages. The reconstructing is responsive to a multiple erasure correcting code and to the block of pages. The reconstructing results in a recovered read stripe. | 2012-08-30 |
20120221921 | MEMORY DEVICE HAVING MULTIPLE CHANNELS AND METHOD FOR ACCESSING MEMORY IN THE SAME - According to one embodiment, a command generator sequentially and speculatively issues channel-by-channel access commands to a memory interface in a predetermined access process. A purger returns a series of unexecuted already-issued access commands using a purge response if an error occurs in any of memory accesses via a plurality of channels. A command progress manager updates command progress information such that the command progress on each of the plurality of channels returns to a position specified in an oldest access command of a series of the returned access commands issued to the channel. The command generator issues the channel-by-channel access commands including the oldest access command to the memory interface based on the updated command progress information. | 2012-08-30 |
20120221922 | MEMORY MANAGEMENT SYSTEM AND METHOD - A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval. | 2012-08-30 |
20120221923 | MEMORY SYSTEM AND MEMORY MODULE CONTROL METHOD - A memory system includes a memory module of first to eighth semiconductor memories of an n-bit input/output type; and a memory control unit configured to generate three n-bit error detection and correction codes based on four n-bit data received from an external system, respectively store the four n-bit data in the first to fourth semiconductor memories, and respectively store the three n-bit error detection and correction code in the fifth to seventh semiconductor memories. When reading the four n-bit data stored in the first to fourth semiconductor memories, the memory control unit executes error detection to every two of the four n-bit data read from the first to fourth semiconductor memories based on the three n-bit error detection and correction code stored in the fifth to seventh semiconductor memories and executes error correction to one n-bit data related to an error, of the four n-bit data. | 2012-08-30 |
20120221924 | APPARATUS, SYSTEM, AND METHOD FOR DETECTING AND REPLACING FAILED DATA STORAGE - An apparatus, system, and method are disclosed for detecting and replacing failed data storage. A read module reads data from an array of memory devices. The array includes two or more memory devices and one or more extra memory devices storing parity information from the memory devices. An ECC module determines, using an error correcting code (“ECC”), if one or more errors exist in tested data and if the errors are correctable using the ECC. The tested data includes data read by the read module. An isolation module selects a memory device in response to the ECC module determining that errors exists in the data read by the read module and that the errors are uncorrectable using the ECC. The isolation module also replaces data read from the selected memory device with replacement data and available data wherein the tested data includes the available data combined with the replacement data. | 2012-08-30 |
20120221925 | DATA RECOVERY METHOD AND ASSOCIATED DEVICE - A data recovery method includes the following steps. Firstly, plural sampling values are classified into a first group, a second group, a third group and a fourth group. A first channel estimation value and a second channel estimation value are generated according to the sampling values of the second group and the third group. A judging step is performed to judge whether a first sampling value of the first group is lower than the first channel estimation value or a second sampling value of the fourth group is higher than the second channel estimation value. If the judging condition is satisfied, a polarity of the first sampling value or the second sampling value is changed and then the plural sampling values are outputted. If the judging condition is not satisfied, the plural sampling values are directly outputted. | 2012-08-30 |
20120221926 | Nested Multiple Erasure Correcting Codes for Storage Arrays - Embodiments of the invention relate to storing data in a storage array. An aspect of the invention includes receiving write data. The write data is arranged into “r” rows and “n” columns of pages, with each page including a plurality of sectors. The write data is encoded using a plurality of horizontal and vertical erasure correcting codes on the pages. The encoding allows recovery from up to t | 2012-08-30 |
20120221927 | SEMICONDUCTOR APPARATUS AND DATA PROCESSING METHOD - A semiconductor apparatus includes a bus inversion information (DBI) processing unit configured to, when receiving multi-bit data, calculating DBI information of the data, and outputting a plurality of DBI flag signals, generate the plurality of DBI flag signals such that each DBI flag signal reflects DBI information of predetermined bits of the data, a first CRC processing unit configured to calculate cyclic redundancy check (CRC) information using the multi-bit data and partial DBI flag signals calculated among the plurality of DBI flag signals and output a plurality of CRC signals, and a second CRC processing unit configured to output CRC codes using the plurality of CRC signals and remaining DBI flag signals calculated among the plurality of the DBI flag signals. | 2012-08-30 |
20120221928 | CHECKSUM VERIFICATION ACCELERATOR - Disclosed a method for validating a data packet by a network processor supporting a first, network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet: identities a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The method produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The method validates the data packet by comparing the data packet checksum to the second checksum. | 2012-08-30 |
20120221929 | Touch Event Processing for Web Pages - One or more touch input signals can be obtained from a touch sensitive device. If the touch input signals are associated with one or more regions of a web page displayed on the touch sensitive device, a touch event associated with the regions of a web page is processed by the web page. Otherwise, the touch events can be processed by an application (e.g., a browser). | 2012-08-30 |
20120221930 | DYNAMIC PRELOADING OF WEB PAGES - In a system, in one embodiment, having a page server for transmitting pages upon request and a page client (or “web browser”) for requesting pages and presenting those pages to an operator, the page client dynamically identifies links subsequent to the loaded page and preloads pages identified by those links for subsequent presentation to the operator, so that the preloaded pages are preloaded dynamically in response to operator selections and are available for presentation to the operator when ultimately selected. The page server and the page client may act independently or may cooperate so as to dynamically select and preload pages from the page server to the page client using parameters indicated by the page client (such as parameters selected by the operator or adaptively determined by the page client), etc. The page client may dynamically save and recall behavior information about pages to be presented. | 2012-08-30 |
20120221931 | SYSTEM AND METHOD FOR DISPLAYING WEB PAGE CONTENT - A system and method for presenting web page content to a user. A plurality of links are identified on a web page which share a designated characteristic. A user action is detected that indicates a user's intent to select a particular link. As a response to the user action, the resource of the particular link is cached. In response to detecting that the user selects the particular link, content is presented to the user that is based at least in part on the cached resource. | 2012-08-30 |
20120221932 | RENDERING WEB CONTENT USING PRE-CACHING - A first resource is provided on a user device, the first resource including a plurality of links to other resources. At least one, but not all of the plurality of links are selected for pre-caching, and at least a portion of a second resource located by the first link is automatically cached. At least the portion of the second resource is provided in response to a designated triggering event. | 2012-08-30 |
20120221933 | METHOD AND SYSTEM TO BUILD INTERACTIVE DOCUMENTS - In one embodiment, during a design mode an editing interface is provided, the interface including a plurality of cells arranged in a layout. An instruction is received to cause binding of a widget to a first cell, and data is received at the first cell. During a production mode, a view of the document is displayed. The first cell is updated to reference changed data when it is detected that data within the widget is changed via user input at the widget. The widget is updated to reference changed data when it is detected that data within the first cell has changed for a reason other than user input at the widget. | 2012-08-30 |
20120221934 | FORM BUNDLING - A form management system is provided that bundles individual electronic form instances into a single bundled form. Form field names in the electronic form instances and scripts are renamed at the time the form instances are merged into a bundle. In this manner, common names can be assigned to individual form fields in individual forms and then only the form field names in electronic forms selected for the bundle are renamed. Furthermore, the same renaming scheme is also executed in the scripts associated with the individual form documents and fields. As such, the form field names in the scripts of bundled documents are altered to reference the renamed form fields in the corresponding component forms. | 2012-08-30 |
20120221935 | TABLE COLUMN SPANNING - Disclosed are a method and system for grouping columns of data into different levels for subsequent multiple level operations. The method comprises the steps of providing sub-columns within a single table column, said table columns and each of the sub-columns having an associated header; and using multiple dummy tables and displaying them separately on different locations, one of the dummy tables including one or more of the associated headers. The preferred embodiment of the invention uses a tool, referred to as the Jtable class, which is used to display and edit regular two-dimensional tables of cells. The present invention is able to support multilevel headers and column spanning by using multiple tables and displaying them separately. Preferably, this is done using another tool, GridBagLayout, which is associated with Jpanel tool. | 2012-08-30 |