35th week of 2013 patent applcation highlights part 54 |
Patent application number | Title | Published |
20130224887 | Method of Forming a Laminated Magnetic Core with Sputter Deposited and Electroplated Layers - A laminated magnetic core, which has a number of magnetic layers and a number of insulation layers which are arranged so that an insulation layer lies between each vertically adjacent pair of magnetic layers, is formed in a method that forms the magnetic layers with an electroplating process, and the insulation layers with a sputter depositing process. | 2013-08-29 |
20130224888 | SYSTEMS AND METHODS FOR FABRICATING SELF-ALIGNED RESISTIVE/MAGNETIC MEMORY CELL - Systems and methods are disclosed to form a resistive random access memory (RRAM) by forming a first metal electrode layer; depositing an insulator above the metal electrode layer and etching the insulator to expose one or more metal portions; depositing a Pr | 2013-08-29 |
20130224889 | CHARGED PARTICLE BEAM APPARATUS, THIN FILM FORMING METHOD, DEFECT CORRECTION METHOD AND DEVICE FORMING METHOD - A charged particle beam apparatus is provided that enables faster semiconductor film deposition than the conventional deposition that uses silicon hydrides and halides as source gases. The charged particle beam apparatus includes a charged particle source | 2013-08-29 |
20130224890 | Feedback Control Using Detection Of Clearance And Adjustment For Uniform Topography - A method of controlling polishing includes storing a desired ratio representing a ratio for a clearance time of a first zone of a substrate to a clearance time of a second zone of the substrate. During polishing of a first substrate, an overlying layer is monitored, a sequence of measurements is generated, and the measurements are sorted a first group associated with the first zone of the substrate and a second group associated with the second zone on the substrate. A first time and a second time at which the overlying layer is cleared is determined based on the measurements from the first group and the second group, respectively. At least one adjusted polishing pressure is calculated for the first zone based on a first pressure applied in the first zone during polishing the first substrate, the first time, the second time, and the desired ratio. | 2013-08-29 |
20130224891 | MANUFACTURING METHOD OF SEMICONDUCTOR MODULE - Parts of electronic components are not exposed to temperature deviating from an appropriate operation temperature range when an electric characteristic test of a semiconductor module having an interposer substrate over which plural kinds of electronic components are mounted is carried out. A heat sink for an electronic component is incorporated in a lid of a test socket used for an electric characteristic test of an MCM. A heat dissipation sheet is attached to part of the bottom face of the heat sink and an adiabatic sheet is attached to another part. The heat dissipation sheet has thermal conductivity larger than the adiabatic sheet and transfers heat generated from an electronic component of a high heat value to the heat sink during operation. The adiabatic sheet inhibits the heat generated from an electronic component of high heat value from being transferred to another electronic component through the heat sink. | 2013-08-29 |
20130224892 | OMNIDIRECTIONAL REFLECTOR - A system and method for manufacturing an LED is provided. A preferred embodiment includes a substrate with a distributed Bragg reflector formed over the substrate. A photonic crystal layer is formed over the distributed Bragg reflector to collimate the light that impinges upon the distributed Bragg reflector, thereby increasing the efficiency of the distributed Bragg reflector. A first contact layer, an active layer, and a second contact layer are preferably either formed over the photonic crystal layer or alternatively attached to the photonic crystal layer. | 2013-08-29 |
20130224893 | METHOD FOR MAKING LIGHT EMITTING DIODE - A method of making a LED includes following steps. A substrate is provided, and the substrate includes an epitaxial growth surface. A buffer layer is grown on the epitaxial growth surface. A carbon nanotube layer is placed on the buffer layer. A first semiconductor layer, an active layer, and a second semiconductor layer are grown in that order on the buffer layer. A reflector and a first electrode are deposited on the second semiconductor layer in that order. The substrate and the buffer layer are removed. A second electrode is deposited on the first semiconductor layer. | 2013-08-29 |
20130224894 | METHOD FOR MANUFACTURING DISPLAY ELEMENT, MANUFACTURING APPARATUS OF DISPLAY ELEMENT AND DISPLAY DEVICE - A manufacturing apparatus of display element which forms highly reliable drive circuits or thin-film transistors on a flexible substrate, a manufacturing method, and a highly reliable display element are provided. A display element ( | 2013-08-29 |
20130224895 | CBD (CHEMICAL BATH DEPOSITION) FILM FORMATION APPARATUS AND METHOD FOR PRODUCING BUFFER LAYER - A support-heat unit that supports and heats a substrate from the back side of the substrate, a reaction bath having an opening for supplying a CBD reaction solution for forming a film onto a front surface of the substrate, which is supported by the support-heat unit, and a reaction bath forward-backward drive unit that can press the opening onto the front surface of the substrate by moving the reaction bath toward the front surface of the substrate, which is supported by the support-heat unit, and that can detach the opening from the front surface of the substrate by moving the reaction bath away from the front surface of the substrate are provided. | 2013-08-29 |
20130224896 | MICRO-ELECTRO-MECHANICAL SYSTEM TILTABLE LENS - A tiltable micro-electro-mechanical (MEMS) system lens comprises a microscopic lens located on a front surface of a semiconductor-on-insulator (SOI) substrate and a semiconductor rim surrounding the periphery of the microscopic lens. Two horizontal semiconductor beams located at different heights are provided within a top semiconductor layer. The microscopic lens may be tilted by applying an electrical bias between the lens rim and one of the two semiconductor beams, thereby altering the path of an optical beam through the microscopic lens. An array of tiltable microscopic lenses may be employed to form a composite lens having a variable focal length may be formed. A design structure for such a tiltable MEMS lens is also provided. | 2013-08-29 |
20130224897 | LIGHT TRANSMISSION MEMBER, IMAGE PICKUP DEVICE, AND METHOD OF MANUFACTURING SAME - A method of forming a light transmission member includes a plurality of processes to form a plurality of sections of the light transmission member. Notably, after a first class process to form light transmission portions having narrow-band light transmission properties in a first class section group, a second class process is performed to form light transmission portions in a second class section group, and a fourth class process is performed to form light transmission portions having wide-band light transmission properties in a first section. | 2013-08-29 |
20130224898 | COMPOSITIONS AND METHODS FOR TEXTURING POLYCRYSTALLINE SILICON WAFERS - Compositions and methods for chemical texturing a surface of a polycrystalline silicon wafer to be used in the manufacture of solar cells provide increased efficiency in the manufacture and operation of solar cells. The compositions and methods disclosed herein include first and second components, wherein the first component is a UKON etch composition, including a hydrofluoric acid/nitric acid mixture and water, while the second component includes a silicon wafer texturing enhancer (SWTE). | 2013-08-29 |
20130224899 | ENHANCING EFFICIENCY IN SOLAR CELLS BY ADJUSTING DEPOSITION POWER - Methods for forming a photovoltaic device include adjusting a deposition power for depositing a buffer layer including germanium on a transparent electrode. The deposition power is configured to improve device efficiency. A p-type layer is formed on the buffer layer. An intrinsic layer and an n-type layer are formed over the p-type layer. | 2013-08-29 |
20130224900 | SOLAR CELL MADE IN A SINGLE PROCESSING CHAMBER - Methods for forming a photovoltaic device include depositing a p-type layer on a substrate and cleaning the p-type layer by exposing a surface of the p-type layer to a plasma treatment to react with contaminants. An intrinsic layer is formed on the p-type layer, and an n-type layer is formed on the intrinsic layer. | 2013-08-29 |
20130224901 | Production Line to Fabricate CIGS Thin Film Solar Cells via Roll-to-Roll Processes - An industrial production line is presented to fabricate CIGS thin film solar cells on continuous flexible substrates in roll-to-roll processes. It provides an entire solution including procedures and related equipments from starting blank substrates to completed solar cells that can be used to fabricate solar modules. This production line contains some core apparatuses, such as a modular electroplating system to deposit CIGS materials, a modular thermal reactor to annealing the CIGS films, and a chemical bath deposition reactor to coat CdS buffer layer, are recently invented by the present inventor. The present production line can be conveniently used to prepare the CIGS thin film solar cells with high efficiency but low cost. | 2013-08-29 |
20130224902 | METHOD OF MANUFACTURING PHOTOVOLTAIC CELL - Provided is a method for manufacturing a photovoltaic cell in which a light absorption layer is formed by promoting chalcogenation. The method includes providing a microporous member, arranging an object on a first side of the microporous member, and arranging a chalcogen source on a second side of the microporous member opposite to the first side, heating the chalcogen source, transmitting a liquefied or evaporated portion of the heated chalcogen source through the microporous member, and exposing the object to the liquefied or evaporated portion of the heated chalcogen source that has passed through the microporous member | 2013-08-29 |
20130224903 | SYSTEMS AND METHODS FOR SOLAR CELLS WITH CIS AND CIGS FILMS MADE BY REACTING EVAPORATED COPPER CHLORIDES WITH SELENIUM - Systems and methods for solar cells with CIS and CIGS films made by reacting evaporated copper chlorides with selenium are provided. In one embodiment, a method for fabricating a thin film device comprises: providing a semiconductor film comprising indium (In) and selenium (Se) upon a substrate; heating the substrate and the semiconductor film to a desired temperature; and performing a mass transport through vapor transport of a copper chloride vapor and se vapor to the semiconductor film within a reaction chamber. | 2013-08-29 |
20130224904 | METHOD FOR FABRICATING THIN-FILM PHOTOVOLTAIC DEVICES - Described are an apparatus and a method for depositing a thin film on a web. The method includes depositing a first layer of a composite metal onto a web. A first selenium layer is deposited onto the first layer and the web is heated to selenize the first layer. Subsequently, a second layer of the composite metal is deposited onto the selenized first layer and a second selenium layer is deposited onto the second layer. The web is then heated to selenize the second layer. The composition of each composite metal layer can be varied to achieve desired bandgap gradients and other film properties. Segregation of gallium and indium is substantially reduced or eliminated because each incremental layer is selenized before the next incremental layer is deposited. The method can be implemented in production systems to deposit CIGS films on metal and plastic foils. | 2013-08-29 |
20130224905 | SILVER PASTE AND USE THEREOF IN THE PRODUCTION OF SOLAR CELLS - A silver paste comprising particulate silver, at least one glass frit, and an organic vehicle, wherein the particulate silver includes 10 to 100 wt-% of spherically-shaped silver particles, based on the total weight of the particulate silver, wherein the spherically-shaped silver particles have an average particle size in the range of 1 to 3 μm, a crystallite size in the range of 40 to 60 nm and a smooth particle surface. | 2013-08-29 |
20130224906 | METHOD AND DEVICE FOR PRODUCING A METALLIC CONTACT STRUCTURE FOR MAKING ELECTRICAL CONTACT WITH A PHOTOVOLTAIC SOLAR CELL - A method for producing a metallic contact structure for making electrical contact with a photovoltaic solar cell, wherein, in order to create the contact structure, a paste, which contains metal particles, is applied to a surface of a carrier substrate via at least one dispensing opening, wherein the dispensing opening and the carrier substrate are moved in relation to one another during the dispensing of the paste. The paste is circulated in a circulating region, and in each case a part of the paste is branched off out of the circulating region at a plurality of branching points and each branching point is assigned at least one dispensing opening, via which the paste branched off at the branching point is applied to the surface of the carrier substrate, wherein the paste flows through a flow path having a length of less than 1 cm in each case between being branched off out of the circulating region and being dispensed from the dispensing opening assigned to the branching point. A device for producing a metallic contact structure for making electrical contact with a photovoltaic solar cell is also provided. | 2013-08-29 |
20130224907 | METHODS OF MANUFACTURING PHOTOVOLTAIC ELECTRODES - A photovoltaic electrode is made by the following steps: (a) depositing on a substrate a dispersion comprising powdered semiconductor particles in a dispersion medium; (b) removing the majority of the dispersion medium to leave the powdered semiconductor particles in a deposition layer on the substrate; (c) creating a plasma using microwave energy excitation; (d) exposing the deposition layer to said microwave-excited plasma for a sufficient time to sinter the nanoparticles thereby adhering them to the substrate; and (e) absorbing a dye into said sintered deposition layer. The electrode thus obtained exhibits improved performance relative to conventional sintered electrodes. | 2013-08-29 |
20130224908 | METHOD OF MANUFACTURING PRAM USING LASER INTERFERENCE LITHOGRAPHY - A method of manufacturing a phase-change random access memory includes: sequentially depositing an insulating layer, a first electrode layer, a phase change material layer, and a transfer material layer on a substrate; forming an array pattern in the transfer material layer using a laser interference lithography process; forming a metal layer on the transfer material layer having the array pattern formed; forming a second electrode layer by removing the transfer material layer; and forming a phase change layer by etching the phase change material layer using the second electrode layer as a mask. Accordingly, the manufacturing process of the phase-change random access memory may achieve an increase in speed and may be simplified. | 2013-08-29 |
20130224909 | PROCESS OF FORMING THROUGH-SILICON VIA STRUCTURE - In a process, an opening is formed to extend from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A metal silicide layer is formed on at least one portion of the metal seed layer. A metal layer is formed on the metal silicide layer and the metal seed layer to fill the opening. | 2013-08-29 |
20130224910 | METHOD FOR CHIP PACKAGE - Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming on the metal bonding pad a sub-ball metal electrode, using a selective formation process; forming a protective layer on the wafer in a region not including the sub-ball metal electrode, with the protective layer covering the cutting trail; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The present invention can prevent metal in the cutting trail from being affected during the production of the sub-ball metal electrode, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield. | 2013-08-29 |
20130224911 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region. | 2013-08-29 |
20130224912 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate; a semiconductor element installed on the substrate so that a surface formed with an electrode is directed to the substrate; a chip capacitor installed on the substrate; and a conductive material covering a rear surface opposite to the surface of the semiconductor element and joining to one terminal electrode of the chip capacitor. | 2013-08-29 |
20130224913 | UNDERFILL MATERIAL AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SAME - Provided is an underfill material which enables a semiconductor chip to be mounted at a low pressure, and a method for manufacturing a semiconductor device by using the underfill material. The method comprises: a semiconductor chip mounting step configured to mount a semiconductor chip having a solder bump on a substrate via an underfill film including a film forming resin having a weight average molecular weight of not more than 30000 g/mol and a molecular weight distribution of not more than 2.0, an epoxy resin, and an epoxy curing agent; and a reflow step configured to solder-bond the semiconductor chip and the substrate by a reflow furnace. The film forming resin of the underfill material has a weight average molecular weight of not more than 30000 g/mol and a molecular weight distribution of not more than 2.0, and accordingly, the viscosity at the time of heat melting can be reduced, and a semiconductor chip can be mounted at a low pressure. | 2013-08-29 |
20130224914 | METHOD FOR PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer. | 2013-08-29 |
20130224915 | GATE-ALL AROUND SEMICONDUCTOR NANOWIRE FETs ON BULK SEMICONDUCTOR WAFERS - Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate. | 2013-08-29 |
20130224916 | HAFNIUM TANTALUM TITANIUM OXIDE FILMS - Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition. | 2013-08-29 |
20130224917 | Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistor (DCFS MOSFET) and Method to Fabricate the Same - Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction. By storing charge in the two independent conducting floating spacers, DCFS MOSFET can have two independent sets of threshold voltages associated with the source junctions. | 2013-08-29 |
20130224918 | NON-VOLATILE STORAGE HAVING A CONNECTED SOURCE AND WELL - A non-volatile storage device is disclosed that includes a set of connected non-volatile storage elements formed on a well, a bit line contact positioned in the well, a source line contact positioned in the well, a bit line that is connected to the bit line contact, and a source line that is connected to the source line contact and the well. | 2013-08-29 |
20130224919 | METHOD FOR MAKING GATE-OXIDE WITH STEP-GRADED THICKNESS IN TRENCHED DMOS DEVICE FOR REDUCED GATE-TO-DRAIN CAPACITANCE - A method for making gate-oxide with step-graded thickness (S-G GOX) in a trenched DMOS device is proposed. First, a substrate is provided and a silicon oxide-silicon nitride-silicon oxide (ONO) protective composite layer is formed atop. Second, an upper interim trench (UIT), an upper trench protection wall (UTPW) and a lower interim trench (LIT) are created into the substrate. Third, the substrate material surrounding the LIT is shaped and oxidized into a desired thick-oxide-layer of thickness T | 2013-08-29 |
20130224920 | SEMICONDUCTOR DEVICE INCLUDING METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS AND METHODS OF FABRICATING THE SAME - A method of fabricating a semiconductor device may include patterning a substrate to form trenches, forming a sacrificial layer to cover inner surfaces of the trenches, the sacrificial layer having a single-layered structure, forming sacrificial patterns by isotropically etching the sacrificial layer such that the sacrificial layer remains on bottom surfaces of the trenches, forming lightly doped regions in sidewalls of the trenches using the sacrificial patterns as an ion mask, removing the sacrificial patterns, and sequentially forming a gate insulating layer and a gate electrode layer in the trenches. | 2013-08-29 |
20130224921 | LATERAL TRENCH TRANSISTOR, AS WELL AS A METHOD FOR ITS PRODUCTION - A method for production of doped semiconductor regions in a semiconductor body of a lateral trench transistor includes forming a trench in the semiconductor body and introducing dopants into at least one area of the semiconductor body that is adjacent to the trench, by carrying out a process in which dopants enter the at least one area through inner walls of the trench. | 2013-08-29 |
20130224922 | UMOS Semiconductor Devices Formed by Low Temperature Processing - UMOS (U-shaped trench MOSFET) semiconductor devices that have been formed using low temperature processes are described. The source region of the UMOS structure can be formed before the etch processes that are used to create the trench, allowing low-temperature materials to be incorporated into the semiconductor device from the creation of the gate oxide layer oxidation forward. Thus, the source drive-in and activation processing that are typically performed after the trench etch can be eliminated. The resulting UMOS structures contain a trench structure with both a gate insulting layer comprising a low temperature dielectric material and a gate conductor comprising a low temperature conductive material. Forming the source region before the trench etch can reduce the problems resulting from high temperature processes, and can reduce auto doping, improve threshold voltage control, reduce void creation, and enable incorporation of materials such as silicides that cannot survive high temperature processing. Other embodiments are described. | 2013-08-29 |
20130224923 | STACKED NON-VOLATILE MEMORY WITH SILICON CARBIDE-BASED AMORPHOUS SILICON THIN FILM TRANSISTORS - A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer. | 2013-08-29 |
20130224924 | PAD-LESS GATE-ALL AROUND SEMICONDUCTOR NANOWIRE FETS ON BULK SEMICONDUCTOR WAFERS - A non-planar semiconductor device is provided including at least one semiconductor nanowire suspended above a semiconductor oxide layer present within a portion of a bulk semiconductor substrate. The semiconductor oxide layer has a topmost surface that is coplanar with a topmost surface of the bulk semiconductor substrate. A gate surrounds a portion of the at least one suspended semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate. The source region is in direct contact with an exposed end portion of the at least one suspended semiconductor nanowire, and the drain region is in direct contact with another exposed end portion of the at least one suspended semiconductor nanowire. The source and drain regions have an epitaxial relationship with the exposed end portions of the suspended semiconductor nanowire. | 2013-08-29 |
20130224925 | Method of Manufacturing a Semiconductor Device - Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer. | 2013-08-29 |
20130224926 | PENETRATING IMPLANT FOR FORMING A SEMICONDUCTOR DEVICE - A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack. | 2013-08-29 |
20130224927 | METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH NARROW, METAL FILLED OPENINGS - Methods are provided for fabricating an integrated circuit that includes metal filled narrow openings. In accordance with one embodiment a method includes forming a dummy gate overlying a semiconductor substrate and subsequently removing the dummy gate to form a narrow opening. A layer of high dielectric constant insulator and a layer of work function-determining material are deposited overlying the semiconductor substrate. The layer of work function-determining material is exposed to a nitrogen ambient in a first chamber. A layer of titanium is deposited into the narrow opening in the first chamber in the presence of the nitrogen ambient to cause the first portion of the layer of titanium to be nitrided. The deposition of titanium continues, and the remaining portion of the layer of titanium is deposited as substantially pure titanium. Aluminum is deposited overlying the layer of titanium to fill the narrow opening and to form a gate electrode. | 2013-08-29 |
20130224928 | MEMORY DEVICE HAVING AN INTEGRATED TWO-TERMINAL CURRENT LIMITING RESISTOR - A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices. | 2013-08-29 |
20130224929 | METHOD OF FORMING A CONTACT AND METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING THE SAME - Provided are a method of forming a contact and a method of manufacturing a phase change memory device using the same. The method of forming a contact includes forming on a substrate an insulating layer pattern having first sidewalls extending in a first direction and second sidewalls extending in a second direction perpendicular to the first direction and which together delimit contact holes, forming semiconductor patterns in lower parts of the contact holes, forming isolation spacers on the semiconductor pattern and side surfaces of the first sidewalls to expose portions of the semiconductor patterns, and etching the exposed portions of the semiconductor patterns using the isolation spacers as a mask to divide the semiconductor patterns into a plurality of finer semiconductor patterns. | 2013-08-29 |
20130224930 | METHOD FOR MANUFACTURING VARIABLE RESISTANCE ELEMENT - A variable resistance element manufacturing method includes: forming a conductive plug in an interlayer insulating film on a substrate; planarizing an upper surface of the insulating film such that an upper part of the conductive plug protrudes from an upper surface of the insulating film by removing (i) a depression in the insulating film formed around the conductive plug and (ii) a depression in the insulating film formed across a plurality of conductive plugs; forming, on the insulating film and the plug, a lower electrode layer electrically connected to the plug; planarizing an upper surface of the lower electrode layer to remove a protruding part on the upper surface of the lower electrode layer; forming, on the lower electrode layer, a variable resistance layer; forming an upper electrode layer on the variable resistance layer; and forming a lower electrode, the variable resistance layer, and an upper electrode layer. | 2013-08-29 |
20130224931 | NONVOLATILE MEMORY DEVICE MANUFACTURING METHOD - A method of manufacturing a nonvolatile memory device that is a variable resistance nonvolatile memory device, which has good consistency with a dual damascene process that is suitable for the formation of fine copper lines and which enables large capacity and high integration. This method includes: forming a variable resistance element, a contact hole and a line groove; and forming a current steering layer of a bidirectional diode element above interlayer insulating layers and a variable resistance layer to cover the line groove without covering a bottom surface of the contact hole. | 2013-08-29 |
20130224932 | ADHESIVE SHEET, DICING TAPE INTEGRATED TYPE ADHESIVE SHEET, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - The invention provides an adhesive sheet which can be stuck to a wafer at low temperatures of 100° C. or below, which is soft to the extent that it can be handled at room temperature, and which can be cut simultaneously with a wafer under usual cutting conditions; a dicing tape integrated type adhesive sheet formed by lamination of the adhesive sheet and a dicing tape; and a method of producing a semiconductor device using them. In order to achieve this object, the invention is characterized by specifying the breaking strength, breaking elongation, and elastic modulus of the adhesive sheet in particular numerical ranges. | 2013-08-29 |
20130224933 | Programmable Poly Fuse Using a P-N Junction Breakdown - According to one exemplary embodiment, a programmable poly fuse includes a P type resistive poly segment forming a P-N junction with an adjacent N type resistive poly segment. The programmable poly fuse further includes a P side silicided poly line contiguous with the P type resistive poly segment and coupled to a P side terminal of the poly fuse. The programmable poly fuse further includes an N side silicided poly line contiguous with the N type resistive poly segment and coupled to an N side terminal of the poly fuse. During a normal operating mode, a voltage less than or equal to approximately 2.5 volts is applied to the N side terminal of the programmable poly fuse. A voltage higher than approximately 3.5 volts is required at the N side terminal of the poly fuse to break down the P-N junction. | 2013-08-29 |
20130224934 | NANOTUBE SOLUTION TREATED WITH MOLECULAR ADDITIVE, NANOTUBE FILM HAVING ENHANCED ADHESION PROPERTY, AND METHODS FOR FORMING THE NANOTUBE SOLUTION AND THE NANOTUBE FILM - The present disclosure provides a nanotube solution being treated with a molecular additive, a nanotube film having enhanced adhesion property due to the treatment of the molecular additive, and methods for forming the nanotube solution and the nanotube film. The nanotube solution includes a liquid medium, nanotubes in the liquid medium, and a molecular additive in the liquid medium, wherein the molecular additive includes molecules that provide source elements for forming a group IV oxide within the nanotube solution. The molecular additive can introduce silicon (Si) and/or germanium (Ge) in the liquid medium, such that nominal silicon and/or germanium concentrations of the nanotube solution ranges from about 5 ppm to about 60 ppm. | 2013-08-29 |
20130224935 | OPTICAL INPUT/OUTPUT DEVICE FOR PHOTO-ELECTRIC INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING SAME - A photo-electric integrated circuit device comprises an on-die optical input/output device. The on-die optical input/output device comprises a substrate having a trench, a lower cladding layer disposed in the trench and having an upper surface lower than an upper surface of the substrate, and a core disposed on the lower cladding layer at a distance from sidewalls of the trench and having an upper surface at substantially the same level as the upper surface of the substrate. | 2013-08-29 |
20130224936 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - Methods of manufacturing a semiconductor device are provided. The method includes constructing and arranging a semiconductor substrate to include a first active region and a second active region and forming mold patterns on the semiconductor substrate. The mold patterns have openings that expose a top surface of the semiconductor substrate. A plurality of first semiconductor fins are formed in openings at the first active region and a plurality of second semiconductor fins in openings at the second active region and selectively recessing top surfaces of the mold patterns. A recessed depth of the mold patterns on the first active region is different than a recessed depth of the mold patterns on the second active region. A gate electrode is formed over the first and second semiconductor fins. A distance between a first semiconductor fin of the plurality of first semiconductor fins and a second semiconductor fin of the plurality of second semiconductor fins adjacent the first semiconductor fin is greater than a distance between two or more first semiconductor fins of the plurality of first semiconductor fins that are adjacent each other. | 2013-08-29 |
20130224937 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Semiconductor layer forming gas is introduced into a reaction chamber, and the gas generates a plasma discharge, so that a semiconductor layer is formed. In addition to the gas, impurity gas is introduced into the chamber, and first conductivity type layer forming gas including the semiconductor layer forming gas and the impurity gas generates a plasma discharge, so that a first conductivity type layer of a first conductivity type is formed so as to cover the semiconductor layer. In the step of forming the first conductivity type layer, a composition set value of gas supplied to the chamber is shifted from a composition of the semiconductor layer forming gas to a composition of the first conductivity type layer forming gas in a state where a pressure in the chamber is not reduced to ultimate vacuum even after a plasma discharge processing for forming the semiconductor layer is terminated. | 2013-08-29 |
20130224938 | PASSIVATION LAYER FOR WORKPIECES FORMED FROM A POLYMER - Methods of forming a passivation layer on a workpiece are disclosed. These methods utilize a SiC forming polymer to form the passivation layer. In addition, while the polymer is being heated to form SiC, a second result, such as annealing of the underlying workpiece, or firing of the metal contacts is achieved. For example, the workpiece may be implanted prior to coating it with the polymer. When the workpiece is heated, SiC is formed and the workpiece is annealed. In another embodiment, a workpiece is coating with the SiC forming polymer and metal pattern is applied to the polymer. The firing of workpiece causes the metal contacts to form and also forms SiC on the workpiece. | 2013-08-29 |
20130224939 | REPLACEMENT GATE ELECTRODE WITH MULTI-THICKNESS CONDUCTIVE METALLIC NITRIDE LAYERS - Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV. | 2013-08-29 |
20130224940 | WORK FUNCTION ADJUSTMENT WITH THE IMPLANT OF LANTHANIDES - Semiconductor devices and fabrication methods are provided, in which fully silicided gates are provided. A lanthanide series metal is implanted into the gate electrode layer prior to silicidation and diffuses into the gate dielectric during an activation anneal. This process and resultant structure provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting transistor. | 2013-08-29 |
20130224941 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×10 | 2013-08-29 |
20130224942 | Methods of Fabricating Semiconductor Devices and Structures Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the workpiece. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the workpiece comprising an NMOS FET of a CMOS device and a second transistor in the second region of the workpiece comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage. | 2013-08-29 |
20130224943 | Memory Device Structure and Method - A system and method for manufacturing a memory device is provided. A preferred embodiment comprises manufacturing a flash memory device with a tunneling layer. The tunneling layer is formed by introducing a bonding agent into the dielectric material to bond with and reduce the number of dangling bonds that would otherwise be present. Further embodiments include initiating the formation of the tunneling layer without the bonding agent and then introducing a bonding agent containing precursor and also include a reduced concentration region formed in the tunneling layer adjacent to a substrate. | 2013-08-29 |
20130224944 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING TAILORED CHAMFERED GATE LINER PROFILES - Methods for fabricating integrated circuits using tailored chamfered gate liner profiles are provided. In an exemplary embodiment, a method for fabricating an integrated circuit includes forming a dummy gate electrode overlying a semiconductor substrate and forming a liner on sidewalls of the dummy gate electrode. A dielectric material is deposited overlying the dummy gate electrode, the liner, and the substrate. The dummy gate electrode is exposed by chemical mechanical planarization. A portion of the dummy gate electrode is removed and the liner is isotropically etched such that it has a chamfered surface. A remainder of the dummy gate electrode is removed to form an opening that is filled with a metal. | 2013-08-29 |
20130224945 | METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS - One illustrative method disclosed herein includes forming a plurality of spaced-apart trenches in a semiconducting substrate to thereby define a fin structure for the device, forming a local isolation region within each of the trenches, forming a sacrificial gate structure on the fin structure, wherein the sacrificial gate structure comprises at least a sacrificial gate electrode, and forming a layer of insulating material above the fin structure and within the trench above the local isolation region. In this example, the method further includes performing at least one etching process to remove the sacrificial gate structure to thereby define a gate cavity, after removing the sacrificial gate structure, performing at least one etching process to form a recess in the local isolation region, and forming a replacement gate structure that is positioned in the recess in the local isolation region and in the gate cavity. | 2013-08-29 |
20130224946 | Passivated Copper Chip Pads - A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels. | 2013-08-29 |
20130224947 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. | 2013-08-29 |
20130224948 | METHODS FOR DEPOSITION OF TUNGSTEN IN THE FABRICATION OF AN INTEGRATED CIRCUIT - A method for fabricating an integrated circuit includes providing a semiconductor wafer comprising a hole etched therein, depositing a first layer comprising tungsten onto the semiconductor wafer and into the hole therein, thereby filling the hole with the first layer, and etching the first layer from the semiconductor wafer, wherein etching the first layer results in the formation of a divot above the first layer within the hole. The method may further include depositing a second layer comprising tungsten onto the semiconductor wafer and into the divot formed above the first layer within the hole and polishing the second layer from the semiconductor wafer, wherein polishing the second layer does not remove the second layer deposited into the divot. | 2013-08-29 |
20130224949 | FABRICATION METHOD FOR IMPROVING SURFACE PLANARITY AFTER TUNGSTEN CHEMICAL MECHANICAL POLISHING - A fabrication method for improving surface planarity after tungsten chemical mechanical polishing (W-CMP) is disclosed. The method forms contact holes and dummy patterns by performing two respective photolithography-and-etching processes to ensure that the dummy patterns have a depth smaller than that of the contact holes. Then the method fills tungsten into the contact holes and dummy patterns and removes the redundant tungsten by a W-CMP process. With such a method, difference of wiring density between areas can be reduced by the dummy patterns, and hence a better surface planarity of the contact hole layer can be achieved. Besides, as the dummy patterns are formed in a pre-metal dielectric layer and their depth is well controlled, tungsten filled in the dummy patterns will not contact with the device area below the pre-metal dielectric layer, and thus will not affect the performance of the device. | 2013-08-29 |
20130224950 | METHOD TO ALTER SILICIDE PROPERTIES USING GCIB TREATMENT - A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region. | 2013-08-29 |
20130224951 | TEMPLATE AND SUBSTRATE PROCESSING METHOD - A template for feeding a processing solution to predetermined positions of a substrate has multiple opening portions formed in positions on a front surface corresponding to the predetermined positions, flow channels penetrating from the opening portions to a back surface in a thickness direction for flowing a processing solution, first hydrophilic regions set to be hydrophilic around the opening portions on the front surface, and second hydrophilic regions set to be hydrophilic on inner surfaces of flow channels. The first hydrophilic regions are formed in positions corresponding to hydrophilic patterns set to be hydrophilic around the predetermined positions on a substrate surface. | 2013-08-29 |
20130224952 | Curved Wafer Processing on Method and Apparatus - An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like. | 2013-08-29 |
20130224953 | ABATEMENT AND STRIP PROCESS CHAMBER IN A LOAD LOCK CONFIGURATION - Embodiments of the present invention a load lock chamber including two or more isolated chamber volumes, wherein one chamber volume is configured for processing a substrate and another chamber volume is configured to provide cooling to a substrate. One embodiment of the present invention provides a load lock chamber having at least two isolated chamber volumes formed in a chamber body assembly. The at least two isolated chamber volumes may be vertically stacked. A first chamber volume may be used to process a substrate disposed therein using reactive species. A second chamber volume may include a cooled substrate support. | 2013-08-29 |
20130224954 | SILICON CARBIDE SINGLE CRYSTAL SUBSTRATE - A silicon carbide single crystal substrate is disclosed, wherein a density of first adhered particles attached onto one surface of the substrate and having a height of 100 nm or more is one particle/cm | 2013-08-29 |
20130224955 | METHOD FOR POLISHING ALUMINUM/COPPER AND TITANIUM IN DAMASCENE STRUCTURES - The invention provides compositions and methods for planarizing or polishing a substrate. The composition comprises an abrasive consisting of alumina particles optionally treated with a polymer, an α-hydroxycarboxylic acid, an oxidizing agent that oxidizes at least one metal, polyacrylic acid, optionally, a calcium-containing compound, optionally, a biocide, optionally, a pH adjusting agent, and water. The method uses the composition to chemically-mechanically polish a substrate. | 2013-08-29 |
20130224956 | SUBSTRATE TREATMENT APPARATUS AND SUBSTRATE TREATMENT METHOD - A substrate treatment apparatus is used for treating a major surface of a substrate with a chemical liquid. The substrate treatment apparatus includes: a substrate holding unit which holds the substrate; a chemical liquid supplying unit having a chemical liquid nozzle which supplies the chemical liquid onto the major surface of the substrate held by the substrate holding unit; a heater having an infrared lamp to be located in opposed relation to the major surface of the substrate held by the substrate holding unit to heat the chemical liquid supplied onto the major surface of the substrate by irradiation with infrared radiation emitted from the infrared lamp, the heater having a smaller diameter than the substrate; and a heater moving unit which moves the heater along the major surface of the substrate held by the substrate holding unit. | 2013-08-29 |
20130224957 | SILICON-CONTAINING RESIST UNDERLAYER FILM FORMING COMPOSITION HAVING FLUORINE-BASED ADDITIVE - A resist underlayer film forming composition for lithography includes: as a component (I), a fluorine-containing highly branched polymer obtained by polymerizing a monomer A having two or more radical polymerizable double bonds in the molecule thereof, a monomer B having a fluoroalkyl group and at least one radical polymerizable double bond in the molecule thereof, and a monomer D having a silicon atom-containing organic group and at least one radical polymerizable double bond in the molecule thereof, in the presence of a polymerization initiator C in a content of 5% by mole or more and 200% by mole or less, based on the total mole of the monomer A, the monomer B, and the monomer D; and as a component (II), a hydrolyzable silane compound, a hydrolysis product thereof, a hydrolysis-condensation product thereof, or a silicon-containing compound that is a combination of these compounds. | 2013-08-29 |
20130224958 | THROUGH HOLE FORMING METHOD - Provided are a method of forming a through hole, which can inhibit misalignment between central axes of holes in both surfaces of a substrate, which is free from metal contamination, and which inhibits notching so as to improve the dimensional accuracy, the method including: preparing a silicon substrate; preparing a supporting substrate for supporting the silicon substrate; fixing the silicon substrate and the supporting substrate to form a composite substrate; and carrying out dry etching to the composite substrate from a silicon substrate side of the composite substrate toward a supporting substrate side of the composite substrate to form a through hole in the silicon substrate, in which the supporting substrate in the preparing a supporting substrate has a hole formed at a region corresponding to a region of the through hole to be formed in the silicon substrate, on a surface of the supporting substrate facing the silicon substrate. | 2013-08-29 |
20130224959 | Ta-TaN SELECTIVE REMOVAL PROCESS FOR INTEGRATED DEVICE FABRICATION - Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor. | 2013-08-29 |
20130224960 | METHODS FOR ETCHING OXIDE LAYERS USING PROCESS GAS PULSING - Methods for etching an oxide layer disposed on a substrate through a patterned layer defining one or more features to be etched into the oxide layer are provided herein. In some embodiments, a method for etching an oxide layer disposed on a substrate through a patterned layer defining one or more features to be etched into the oxide layer may include: etching the oxide layer through the patterned layer using a process gas comprising a polymer forming gas and an oxygen containing gas to form the one or more features in the oxide layer; and pulsing at least one of the polymer forming gas or the oxygen containing gas for at least a portion of etching the oxide layer to control a dimension of the one or more features. | 2013-08-29 |
20130224961 | PLASMA TUNING RODS IN MICROWAVE RESONATOR PLASMA SOURCES - A resonator system is provided with one or more resonant cavities configured to couple electromagnetic (EM) energy in a desired EM wave mode to plasma by generating resonant microwave energy in a resonant cavity adjacent the plasma. The resonator system can be coupled to a process chamber using one or more interface and isolation assemblies, and each resonant cavity can have a plurality of plasma tuning rods coupled thereto. The plasma tuning rods can be configured to couple the EM-energy from the resonant cavities to the process space within the process chamber. | 2013-08-29 |
20130224962 | NON-CONTACT SUBSTRATE PROCESSING - Embodiments of the present invention provide apparatus and methods for supporting, positioning or rotating a semiconductor substrate during processing. One embodiment of the present invention provides a method for processing a substrate comprising positioning the substrate on a substrate receiving surface of a susceptor, and rotating the susceptor and the substrate by delivering flow of fluid from one or more rotating ports. | 2013-08-29 |
20130224963 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor manufacturing apparatus includes a substrate stage, a transfer unit, and a control unit. A substrate is settable on the substrate stage. The transfer unit is configured to transfer a pattern having an uneven configuration onto a major surface of the substrate by attachably and removably holding a template. The pattern is provided in the transfer surface. The control unit is configured to acquire information relating to a number of foreign objects on the major surface prior to the transferring of the pattern. The control unit adds the number for a plurality of the substrates including the pattern transferred by the transfer unit. The control unit causes the transfer unit not to implement the transferring of the pattern in the case where the sum has reached the upper limit. | 2013-08-29 |
20130224964 | Method for Forming Dielectric Film Containing Si-C bonds by Atomic Layer Deposition Using Precursor Containing Si-C-Si bond - A method of forming a dielectric film having Si—C bonds on a semiconductor substrate by atomic layer deposition (ALD), includes: (i) adsorbing a precursor on a surface of a substrate; (ii) reacting the adsorbed precursor and a reactant gas on the surface; and (iii) repeating steps (i) and (ii) to form a dielectric film having at least Si—C bonds on the substrate. The precursor has a Si—C—Si bond in its molecule, and the reactant gas is oxygen-free and halogen-free and is constituted by at least a rare gas. | 2013-08-29 |
20130224965 | SEMICONDUCTOR MANUFACTURING APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor manufacturing apparatus, which forms a metal film, and which has the following parts: a processing chamber that carries out the processing of a substrate set inside it, a gas feeding part that feeds the feed gas of the metal film and a plasma generating gas into the processing chamber, a plasma generating part that generates the plasma of the plasma generating gas, and a bias generating part that causes the ions generated by the plasma generating part to impact on the substrate. | 2013-08-29 |
20130224966 | COMPOSITE DIELECTRIC MATERIAL DOPED WITH RARE EARTH METAL OXIDE AND MANUFACTURING METHOD THEREOF - A composite dielectric material doped with rare earth metal oxide and a manufacturing method thereof are provided. The composite dielectric material is doped with nano-crystalline rare metal oxide which is embedded in silicon dioxide glass matrix, and the composite dielectric material of the nano-crystalline rare metal oxide and the silicon dioxide glass matrix is synthesized by the manufacturing method using sol-gel route. The dielectric value of the glass composite dielectric material is greater than that of pure rare metal oxide or that of silicon dioxide. In presence of magnetic field, the dielectric value of the composite dielectric material is substantially enhanced compared with that of the composite dielectric material at zero field. | 2013-08-29 |
20130224967 | HEAT TREATMENT APPARATUS HEATING SUBSTRATE BY IRRADIATION WITH LIGHT - A capacitor, a coil, a flash lamp, and a switching element such as an IGBT are connected in series. A controller outputs a pulse signal to the gate of the switching element. A waveform setter sets the waveform of the pulse signal, based on the contents of input from an input unit. With electrical charge accumulated in the capacitor, a pulse signal is output to the gate of the switching element so that the flash lamp emits light intermittently. A change in the waveform of the pulse signal applied to the switching element will change the waveform of current flowing through the flash lamp and, accordingly, the form of light emission, thereby resulting in a change in the temperature profile for a semiconductor wafer. | 2013-08-29 |
20130224968 | ELECTRICAL SWIVEL DESIGN - High voltage swivel ( | 2013-08-29 |
20130224969 | CHARGE INLET - A charge inlet connectable to a power supplying plug that charges a vehicle battery includes a power supplying plug fitting unit connected to the power supplying plug. A vehicle body connector fitting unit is arranged integrally with the power supplying plug fitting unit. The vehicle body connector fitting unit is connected to a vehicle body connector extending from the battery. The charge inlet includes a direct connection type connector that allows for direct connection of the vehicle body connector to the vehicle body connector fitting unit. | 2013-08-29 |
20130224970 | INTEGRATED CIRCUIT SOCKET SYSTEM WITH CONFIGURABLE STRUCTURES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit socket system includes: forming a retainer plate having a pinhole extending through the retainer plate; forming a base plate having a connector hole extending through the base plate, the connector hole aligned with the pinhole; inserting a compressible pin having a lower probe end through the connector hole and the pinhole below the connector hole, a portion of the compressible pin in the base plate; forming a device plate having a cavity hole extending through the device plate and aligned with the an upper probe end of the compressible pin exposed in the cavity hole; and mounting a removable fastener through the device plate, the base plate, and into the retainer plate, the device plate over the base plate directly on the retainer plate and attached to one another by the removable fastener. | 2013-08-29 |
20130224971 | MODULAR CONNECTORS WITH EASY-CONNECT CAPABILITY - Modular connectors are provided that have a modular receptacle connector assembly matable with a modular plug connector assembly for connecting AC or DC power connectors and electrical signals including board-to-board and wire-to-board connection. Provided is a “pass through” modular component to facilitate connection and disconnection of only the power supply for service without disconnecting the entire system. The wire connector also may load to the main housing thus obviating the need for a panel mount. Also provided is a one-unit modular connector system with either a coplanar or a right-angle design. Furthermore, multiple AC and/or DC power supplies can be provided that utilize minimum board space. | 2013-08-29 |
20130224972 | UNIVERSAL SERIAL BUS DEVICE - Provided is a universal serial bus (USB) device including a main body in which a printed circuit board (PCB) is housed, and a USB terminal unit with at least two hinge portions rotatably connected with the main body to electrically connect with the PCB according to a rotation of the USB terminal unit. | 2013-08-29 |
20130224973 | ELECTRICAL DEVICE, IN PARTICULAR A SOCKET AND CONNECTOR, HAVING A SECONDARY LOCK, METHOD FOR MOULDING SUCH A DEVICE AND MOULD FOR PRODUCING SUCH A DEVICE - an electrical device has a first portion intended for receiving a complementary electrical lamp and a fixed connector intended for receiving power supply wires extended by at least one contact leading into said first portion, the fixed connector including a lock that is only activated when the contacts are correctly inserted in the fixed connector, the first portion, the fixed connector and the lock thereof being moulded simultaneously, the lock being is made up of a slide translatably mobile relative to the fixed connector between a retracted position permitting the insertion of contacts, and a locked position in which a shutter prevents the removal of the contacts. a method for moulding such a device and a mould for producing such a device, are also enclosed. | 2013-08-29 |
20130224974 | LEVER LOCK CONNECTOR AND CONNECTOR UNIT HAVING THAT - A connector | 2013-08-29 |
20130224975 | Lever Connector - A lever connector includes a housing, and a lever rotatably provided on the housing to be rotated in a locking direction to be disposed at a connection locking position. The lever includes support plate portions rotatably supported by both sides of the housing, each support plate portion has a protrusion portion protruding toward a side of the housing, the both sides of the housing have groove portions with which the protrusion portions of the lever at the connection locking position are engaged, each groove portion has a tapered surface inclined in a protruding direction of a protrusion portion as extending in the locking direction of the lever, and as the protrusion portions are slid along the tapered surfaces to be engaged with the tapered surfaces, respectively, the lever is applied with a rotating force in the locking direction. | 2013-08-29 |
20130224976 | FOLDABLE USB CONNECTOR - The present invention provides a foldable USB connector comprising a first folding part, a second folding part and an elastic strap, facilitates effective use, saves more space to match demand for a compact design currently, and is integrated with other relevant products to create a composite product with diversified functions and advantages such as compact structure. | 2013-08-29 |
20130224977 | UNIVERSAL ADAPTOR MOUNT FOR A DOCKING STATION - A universal adapter module supporting a plurality of different interface adapters, each of the interface adapters having a body, a plug, and a cable communicating with the plug and extended from the body; a housing having an internal cavity sized to receive therewithin the body of the adapter with an opening adjacent to one surface thereof that is sized to admit the plug therethrough, and access means for removing one interface adapter from the housing and substituting therefor a different interface adapter; and a means for urging the plug outwardly through the opening of the housing. A docking station formed of a docking tray configured for supporting a portable electronics device, the docking tray having a means for coupling the housing of the universal adapter module to a device receiver structure thereof with the opening of the adapter module positioned adjacent to an aperture formed in an interface portion thereof. | 2013-08-29 |
20130224978 | Electrical Connector - A rolled terminal ( | 2013-08-29 |
20130224979 | CONNECTOR - A connector includes an inner plate including cavities for holding terminals connected to electric wires, a cylindrical housing which accommodates therein the inner plate, and a filling material which is filled in an interior of the housing so as to surround a periphery of the inner plate. A plurality of air bleeding holes are formed in a portion of the inner plate other than portions where the cavities are provided so as to penetrate from a front side to a back side thereof. | 2013-08-29 |
20130224980 | EASY-INSTALLATION AND MAINTENANCE WATERPROOF SOCKET AND PLUG ASSEMBLY - An easy-installation and maintenance waterproof socket and plug assembly comprising a socket ( | 2013-08-29 |
20130224981 | SECURING STRUCTURE FOR FLEXIBLE PRINTED CIRCUIT - A securing structure includes a housing, and a securing member. The housing defines a receiving space and includes a base at end of the housing adjacent to the receiving space. The base includes at least one latching patch secured on the base. The securing member includes a latching portion and at least one resisting portion extended from one side of the latching portion. The latching portion detachably engages with the at least one latching patch with an end of the at least one latching patch pressing the resisting portion toward the receiving space. | 2013-08-29 |
20130224982 | MICRO SIM CARD SOCKET - The micro SIM card socket of the Present Disclosure, by manufacturing the contact terminals in a “U” shape, can resolve the problem of narrowing contact terminal installation space due to miniaturization trends, and also the problem of collision between the card front end and the contact terminals when a card is inserted; it can effectively prevent the malfunction or poor contact that can occur due to the inability of the contact terminals to firmly contact the connection terminals of the SIM card when the SIM card is inserted. | 2013-08-29 |
20130224983 | FEMALE-TYPE METAL TERMINAL FITTING - A connector provided with a female-type metal terminal fitting, includes a case portion including a bottom plate portion, first and second side plate portions, and an upper plate portion, a lance engaging portion formed at a rear end portion of the upper plate portion so as to engage with a lance, a biasing portion integrated in the case portion, a wire connecting portion provided so as to be extended to a rear side of the case portion, and a spring supporting plate portion laminated on an inner face of the upper plate portion. A rear end portion of the spring supporting plate portion is recessed toward inside of the case portion further than the rear end portion of the upper plate portion. The biasing portion is extended from the spring supporting plate portion. | 2013-08-29 |
20130224984 | LOCKING ELECTRICAL SOCKET - A locking electrical plug is disclosed having a rigid tubular housing which rotates axially around a partially enclosed cylindrical socket face. As the tubular housing rotates, internally projecting cam engages clevis pins on the socket face, which pins lock through apertures of male electrical prongs detachably inserted into jacks on the socket face. The clevis pins are disengaged from the electrical prongs as the tubular body is rotated backward, the clevis pins biased back into an open position by resilient springs. Certain embodiments of the present invention recite electrical outlet embodiments comprising a plurality of socket faces. The locking electrical socket securely retains the male end of a US 120 volt electrical plug, but may be embodied to retain the male end of a US 220 volt electrical plug or electrical plugs of various international standards. | 2013-08-29 |
20130224985 | CONNECTOR - A receiving housing is displaceable in the direction to be pushed out from the opening of a bottom panel by a connecting operation. One end of a lever can be engaged with a counterpart housing and the other end can be engaged with a rotating shaft protrusion of the bottom panel. The counterpart housing is pulled towards the receiving housing by means of the lever that pivots around a portion to be engaged with the rotating shaft protrusion of the bottom panel as a fulcrum by the displacement of the receiving housing in cooperation with the connecting operation. | 2013-08-29 |
20130224986 | CABLE CONNECTOR - A cable connector includes an insulator, signal contacts supported in the insulator, wherein the signal contacts come in contact with the cable when the cable is inserted into the insulator, a pair of lock members which are rotatable between a locked position and an unlocked position, and springs supported on the insulator, wherein the springs retain the locked position and allow rotation of the lock members to the unlocked position by elastic deformation of the springs. Each spring includes a base-plate portion supported on the insulator, an elastically deformable portion extending from the base-plate portion, an end-extending portion extending from an end of the elastically deformable portion, and an engaging portion which engages with an associated lock member to integrate the spring with the associated the lock member. | 2013-08-29 |