35th week of 2013 patent applcation highlights part 25 |
Patent application number | Title | Published |
20130221983 | SYSTEMS AND METHODS FOR PROVIDING TRANSFORMER RATINGS USING HARMONICS DATA - A method of providing transformer rating information. The method includes the steps of: (a) determining k-factors for eddy losses and stray losses related to a transformer; and (b) providing a revised rating for the transformer using the k-factors determined at step (a). | 2013-08-29 |
20130221984 | CALIBRATION UNIT FOR A MEASUREMENT DEVICE - A calibration unit for a measurement device for connecting to a connector embodied in a coaxial manner. The calibration unit provides a housing and an inner conductor, whereas the inner conductor ( | 2013-08-29 |
20130221985 | SIGNAL ACQUISITION SYSTEM HAVING REDUCED PROBE LOADING OF A DEVICE UNDER TEST - A signal acquisition system has a signal acquisition probe having probe tip circuitry coupled to a resistive center conductor signal cable. The resistive center conductor signal cable of the signal acquisition probe is coupled to a compensation system in a signal processing instrument via an input node and input circuitry in the signal processing instrument. The signal acquisition probe and the signal processing instrument have mismatched time constants at the input node with the compensation system providing pole-zero pairs for maintaining flatness over the signal acquisition system frequency bandwidth. | 2013-08-29 |
20130221986 | Method for Calibrating a Conductivity Measuring Cell - The invention relates to a method for calibrating a conductivity measuring cell located in a measurement setup for determining conductivity of a liquid medium, especially very pure water, by means of two electrodes of predetermined area arranged in the liquid medium at a predetermined separation relative to one another, supplied with an alternating voltage and having a cell constant, which is predetermined by separation and electrode area and must be calibrated. In order to be able to determine the cell constant independently of calibration standards with predetermined conductivity and/or reference measurement cells, an electrical capacitance of the measuring cell is ascertained by means of an alternating voltage placed on the electrodes in a frequency range between 1 kHz and 1 MHz, following which the cell constant is determined from the ascertained capacitance and the permittivity of the liquid medium contained in the measuring cell. | 2013-08-29 |
20130221987 | STATIC NOISE MARGIN MONITORING CIRCUIT AND METHOD - A monitoring circuit and method, wherein a voltage waveform having a linear falling edge is applied to a first node of at least one test memory cell (e.g., a plurality of test memory cells connected in parallel). The input voltage at the first node is captured when the output voltage at a second node of the test memory cell(s) rises above a high reference voltage during the falling edge. Then, a difference is determined between the input voltage as captured and either (1) the output voltage at the second node, as captured when the input voltage at the first node falls below the first reference voltage during the falling edge, or (2) a low reference voltage. This difference is proportional to the static noise margin (SNM) of the test memory cell(s) such that any changes in the difference noted with repeated monitoring are indicative of corresponding changes in the SNM. | 2013-08-29 |
20130221988 | DEVICES AND METHODS FOR TESTING FLEX CABLE SHIELDING - Methods and devices for testing flex cable shielding of a consumer electronic device are provided. In one example, a method may include applying a signal across a first portion of the flex cable shielding and a second portion of the flex cable shielding. The method may also include detecting a parameter associated with the signal. The method may include determining a health of the flex cable shielding based at least partially on the detected parameter. | 2013-08-29 |
20130221989 | DETECTING A FOREIGN BODY APPLIED TO AN INPUT MEANS USED FOR AUTHENTICATION - The apparatus for detecting a foreign object mounted in the near range of an input means used for identification and/or authentication includes at least a coupler. The coupler is arranged to supply an oscillating signal to two input terminals of an antenna for generating a standing wave, to supply the oscillating signal with a predetermined level to a detection device, and to couple out, for the detection device, a reflection signal received by the antenna. Furthermore, the coupler is arranged to detect a phase difference between the supplied oscillating signal with the predetermined level and the reflection signal that is coupled out, in order to detect the foreign object. | 2013-08-29 |
20130221990 | DETECTING A CONNECTION TYPE OF A PIN - The subject matter discloses an apparatus configured for detecting type of a connection of an electrical module to an electrical node of an electrical circuit, the apparatus comprising a pulse generator configured for generating a first pulse; and a sampling circuit configured for applying a reaction of the electrical circuit on the first pulse to provide a sampled pulse and for detecting the type of connection from the sampled pulse. The electrical module comprising a capacitor or an inductor. | 2013-08-29 |
20130221991 | USER INTERFACE HAVING UNIVERSAL SENSING ELECTRODE STRUCTURE - A universal sensor array for use with a user interface panel includes a first array of conductors separated from a second array of conductors by a dielectric substrate. Conductors of the first array cross over the conductors of the second array without touching. A control circuit detects stimuli proximate the conductors and provides respective control outputs in response to substantially simultaneous detection of stimuli proximate predetermined pairs of intersecting conductors and provides a null control output in response to detection of stimuli proximate other conductors or pairs of conductors. | 2013-08-29 |
20130221992 | Structure of Bridging Electrode - In a structure of a bridging electrode, the structure of a bridging electrode applied to a capacitive touchpad, the structure comprising: a substrate; a plurality of first electrode blocks disposed on the substrate and electrically connected together in series through a first wire; a plurality of second electrode blocks disposed on the substrate and respectively disposed on two sides of the first wire; and a bridging insulation unit, which is perpendicular to and disposed on the first wire and having a bridging groove; wherein the second electrode blocks connecting electrically together in series through the bridging insulation unit having a second wire. | 2013-08-29 |
20130221993 | FREQUENCY HOPPING ALGORITHM FOR CAPACITANCE SENSING DEVICES - Apparatuses and methods of frequency hopping algorithms are described. One method listens to a noise level on multiple electrodes of a sense network at multiple operating frequencies. The method then selects one of the frequencies with a lowest noise level for scanning the electrodes to detect a conductive object proximate to the electrodes. | 2013-08-29 |
20130221994 | MOVEMENT AND POSITION IDENTIFICATION SENSOR - Disclosed is a movement sensor that comprises a plurality of plate-type layers on which individual sensors are arranged. The layers are configured in the way set forth in the claims. | 2013-08-29 |
20130221995 | SENSE AMPLIFIER - An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device. | 2013-08-29 |
20130221996 | USER INTERACTIVE LIVING ORGANISMS - Embodiments described herein use capacitive sensing to detect human interaction with living plants. A sensing system may utilize the natural conductive paths found in an organic plant to transmit an electrical signal between the plant and a user interacting with the plant. By directly contacting the plant or coming into proximity of the plant, the user may affect the electrical signal. That is, the electrical properties of the user (e.g., the capacitance of the human body) change a measured impedance curve associated with the electrical signal. Based on this change, the sensing system detects an interaction between the user and the plant and may inform a user interaction device to provide a feedback response to the user. For example, the feedback response may be an audio or video effect that is based on the type of user interaction such as whether the user touched the plant's leaf or stem. | 2013-08-29 |
20130221997 | METHOD AND DEVICE FOR MONITORING THE INSULATION RESISTANCE IN AN UNGROUNDED ELECTRICAL NETWORK - A method and a device for monitoring the insulation resistance in an ungrounded electrical network having a constant-voltage d.c. link and at least one inverter, connected to it, for controlling an n-phase electrical consumer in an n-phase network. A voltage to be monitored, is determined during operation of the consumer, which represents a voltage fluctuation of supply voltage potentials of the constant-voltage d.c. link with respect to a reference potential. In addition, a variable characterizing an electrical frequency of the electrical consumer is determined, particularly an electrical angular speed of the electrical consumer. A first spectral amplitude of the voltage to be monitored at the n-fold electrical frequency of the electrical consumer, is compared to a first reference value, and detects a symmetrical insulation error in the constant-voltage d.c. link or the n-phased network, if the comparison yields a deviation of the first spectral amplitude from the first reference value. | 2013-08-29 |
20130221998 | CURRENT SENSOR - A current sensor includes a magnetoresistive element that has a stripe shape and that has a sensing axis in a certain direction. The magnetoresistive element includes element portions that are disposed so as to be spaced apart from each other in a longitudinal direction of the stripe shape, and permanent magnet portions, each of which is disposed between adjacent ones of the element portions. Each element portion has a layered structure including a free magnetic layer whose magnetization direction is changed with respect to an external magnetic field, a non-magnetic intermediate layer, and a ferromagnetic pinned layer whose magnetization direction is pinned. The permanent magnet portion includes a hard bias layer, and an electrode layer that is disposed so as to cover the hard bias layer. | 2013-08-29 |
20130221999 | TESTING SYSTEM AND METHOD - A testing method implemented by a testing system connected to an electronic device includes testing whether the electronic device is successfully powered on in a powering on/off test according to pre-set test parameters; detecting if the electronic device is successfully powered on in the powering on/off test; generating a pause signal when the electronic device is successfully powered on; upon receiving the pause signal, preventing from entering into testing powering off of the electronic device, controlling to test whether certain components in the electronic device can successfully perform some functions; generating a continue signal to test powering off of the electronic device after testing the certain components performing some functions; and testing whether the electronic device is successfully powered off in the powering on/off test. The testing system is also provided. | 2013-08-29 |
20130222000 | LOAD CIRCUIT FOR TESTING USB PORTS - An exemplary load circuit includes a switch unit and a current dividing circuit. The switch unit includes a number of switches. The current dividing circuit includes a number of sub-circuits. A terminal of a resistance module of each of the sub-circuits is connected to both a power terminal and a terminal of a corresponding one of the switches. The other terminal of the resistance module of each of the sub-circuits is connected to a drain of a transistor of each of the sub-circuits. A source of the transistor is connected to ground. A gate of the transistor is connected to ground, and is also connected to another terminal of the corresponding switch. | 2013-08-29 |
20130222001 | CURRENT SENSOR HAVING SELF-DIAGNOSIS FUNCTION AND SIGNAL PROCESSING CIRCUIT - There are provided a current sensor which has a self-diagnosis function and a signal processing circuit. The current sensor is provided with an offset component output circuit | 2013-08-29 |
20130222002 | CABLE WITH WIRE DISCONNECTION DETECTION FUNCTION - A cable with a wire disconnection detection function includes a detecting wire including a conductor formed by twisting a plurality of strands, and a detected wire including a conductor formed by twisting a plurality of the strands. A twist pitch of the conductor of the detecting wire is longer than that of the conductor of the detected wire. | 2013-08-29 |
20130222003 | WIRING BOARD AND PROBE CARD USING THE SAME - A wiring board and a probe card using the wiring board which respond to a demand for improving electrical reliability. | 2013-08-29 |
20130222004 | INSPECTION APPARATUS AND INSPECTION METHOD - An inspection apparatus inspects a photovoltaic cell panel in which the photo device is formed. The inspection apparatus includes: an irradiation part that irradiates the photovoltaic cell panel with pulsed light (pump light) emitted from a femtosecond laser; a detecting part that detects an electromagnetic wave pulse, which is generated from the photovoltaic cell panel according to the irradiation of the pump light; and a continuous light irradiation part that irradiates a portion, which is irradiated with the pump light in the photovoltaic cell panel, with continuous light. | 2013-08-29 |
20130222005 | CONTACT PROBE PIN - The present invention provides a contact probe pin in which a carbon film having both of conductivity and durability is formed on a base material with a tip divided, wherein Sn adherence can be reduced as much as possible to be able to maintain stable electrical contact over a long period of time, even under such circumstances that the temperature of a usage environment becomes high. The present invention relates to a contact probe pin, including a tip divided into 2 or more projections and repeatedly coming into contact with a test surface at the projection, wherein a carbon film containing a metal element is formed at least on a surface of the projection, and a radius of curvature at an apex part of the projection is 30 μm or more. | 2013-08-29 |
20130222006 | APPARATUS FOR MONITORING OPERATING PARAMETERS OF INTEGRATED CIRCUITS AND INTEGRATED CIRCUIT WITH OPERATING PARAMETER MONITORING - A device for monitoring operating parameters of integrated circuits. A signal is generated at least at one output of a comparison element by comparing switching states of input signals at the at least two inputs of the comparison element, which signal indicates that the at least one operating parameter has fallen below or has exceeded a predefined threshold. The two input signals are generated by at least two operating parameter-dependent devices, and the switching behavior thereof is subject to a time delay depending on the current value of the at least one operating parameter. A predefined time delay has a value such that when the predefined threshold of the operating parameter is exceeded, one of the input signals changes its switching state at the times predefined for the comparison element by the clock signal on the basis of the time delay. | 2013-08-29 |
20130222007 | POWER SUPPLY TEST SYSTEM - A power supply test system for testing the reliability of a power supply includes a controlling input module, a signal collecting module, a signal input module, an alarm module, and a display module. The controlling input module inputs a time signal and a test signal in the signal collecting module. The signal collecting module turns on the power supply according to the test signal. When the power supply is turned on, the power supply outputs a power on signal, the signal collecting module records the time the test starts. When the power supply breaks off, the power supply outputs a power off signal, the signal collecting module records the time the power supply breaks off and outputs an alarm signal. The alarm module receives alarm signal and alarms to indicate the test is over. The display module displays the time the test starts and the power supply breaks off. | 2013-08-29 |
20130222008 | METHOD FOR DIAGNOSING AN ELECTRICAL CIRCUIT - A method for diagnosing an electrical circuit including at least one electrical device, an actuator for the device controlled by a high side actuating switch and a low side actuating switch, and at least one additional switch not in series with any of the HS or LS switch, the method including: to each of the possible statuses of the circuit, giving a code; sequentially putting the circuit in at least some of these statuses for a given time period; during each of these periods, measuring voltage and/or current in different parts of the circuit and giving a code to the measurement; and establishing a diagnosis of correct functioning or of a malfunctioning of at least some elements of the circuit according to a pre-established correlation between the status codes and the measurement codes. | 2013-08-29 |
20130222009 | CONTROL SIGNAL GENERATION CIRCUITS, SEMICONDUCTOR MODULES, AND SEMI CONDUCTOR SYSTEMS INCLUDING THE SAME - Semiconductor modules are provided. The semiconductor module includes a first semiconductor chip configured for storing an information signal that is set in response to a command/address signal and which determines reception of an on-die termination (ODT) signal in a power down mode in response to the information signal to control activation of a first ODT circuit; and a second semiconductor chip configured for sharing and utilizing the first ODT circuit included in the first semiconductor chip. | 2013-08-29 |
20130222010 | FIELD PROGRAMMABLE GATE ARRAYS USING RESISTIVITY-SENSITIVE MEMORIES - Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane. | 2013-08-29 |
20130222011 | PROGRAMMABLE LOGIC SWITCH - One embodiment provides a programmable logic switch in which a first nonvolatile memory and a second nonvolatile memory are formed in the same well, and in which to change the first nonvolatile memory from an erased state to a written state and leave the second nonvolatile memory being in the erased state, a first write voltage is applied to a first line connected with gate electrodes of the first and second nonvolatile memories, a second write voltage is applied to a second line connected to a source in the first nonvolatile memory, and a third write voltage lower than the second write voltage is applied to a fourth line connected to a source of the second nonvolatile memory. | 2013-08-29 |
20130222012 | Programmable Logic Unit - Programmable logic units are described. A described unit includes one or more input interfaces to receive one or more input signals; logic elements that are individually programmable; one or more output interfaces to provide one or more output signals; and a programmable interconnect array that is configured to selectively form one or more interconnections within the unit based on one or more programming settings. The programmable interconnect array can be programmable to route the one or more input signals from the one or more input interfaces to at least a portion of the logic elements, programmable to route one or more intermediate signals among at least a portion of the logic elements, and programmable to route one or more signals from at least a portion of the logic elements to produce the one or more output signals via the output interface. | 2013-08-29 |
20130222013 | PHYSICAL UNCLONABLE FUNCTION CELL AND ARRAY - A function cell comprising a first field effect transistor (FET) device, a second FET device, a first node connected to a gate terminal of the first FET device and a gate terminal of the second FET device, wherein the first node is operative to receive a voltage signal from an alternating current (AC) voltage source, an amplifier portion connected to the first FET device and the second FET device, the amplifier portion operative to receive a signal from the first FET device and the second FET device, a phase comparator portion having a first input terminal connected to an output terminal of the amplifier and a second input terminal operative to receive the voltage signal from the AC voltage source, the phase comparator portion operative to output a voltage indicative of a bit of a binary value. | 2013-08-29 |
20130222014 | DIFFERENTIAL CURRENT SIGNAL CIRCUIT - A differential current signal circuit is described which includes a voltage to differential current converter circuit that generates a differential pair of current output signals in response to receiving a voltage input signal, where the differential pair of current output signals are linearly proportional to the voltage input signal within a voltage operating range from a minimum operating voltage to a maximum operating voltage. The differential pair of current output signals are linear over a wide range of voltage input signals. A correction circuit is included which eliminates voltage offsets in the voltage operating range due to process and temperature variations. The correction circuit also provides the capability to adjust the minimum operating voltage, and eliminates variations in the minimum operating voltage due to process and temperature variations. | 2013-08-29 |
20130222015 | LEVEL SHIFTERS FOR IO INTERFACES - An integrated circuit which includes a pre-driver configured to receive a first high supply voltage and to generate an input signal and at least one post-driver configured to receive at least one second high supply voltage and to receive the input signal. The at least one post-driver includes an input node configured to receive the input signal and an output node configured to output an output signal. The at least one post-driver further includes a pull-up transistor configured to be in a conductive state during an entire period of operation, and a pull-down transistor. The at least one post-driver further includes at least one diode-connected device coupled between the pull-down transistor and the output node. Each post-driver of the at least one post-driver is configured to supply the output signal having a second voltage level corresponding to a high logic level which is higher than an input voltage level. | 2013-08-29 |
20130222016 | Digital PLL Circuit and Clock Generator - A circuit according to the present invention includes: an oscillator; an divider; a time-to-digital converter comparing the phase and frequency of a reference clock signal REF from the divider with an internal clock signal and outputting digital data D | 2013-08-29 |
20130222017 | RESET DEVICE AND ELECTRONIC SYSTEM HAVING THE SAME - An electronic system is provided. The electronic system comprises a power device and a reset device. The power device provides power to the electronic system. The reset device comprises a wireless signal generator, a wireless signal receiver and a control module. The wireless signal generator generates a wireless signal. The wireless signal receiver receives the wireless signal and generates a control signal in response. The control module is electrically connected to the wireless signal receiver to activate a reset mechanism of the control module or reset the power device upon reception of the control signal from the wireless signal receiver. | 2013-08-29 |
20130222018 | ADAPTIVE CLOCK GENERATING APPARATUS AND METHOD THEREOF - An adaptive clock generating apparatus is provided. The apparatus includes a fixed frequency divider, a replica, a counter, a variable frequency divider. The adaptive clock generating apparatus generates a clock whose period varies along with changes in the critical path delay of a synchronous circuit. | 2013-08-29 |
20130222019 | SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR DEVICE, AND METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT - An semiconductor integrated circuit has a macro cell, an initial voltage setting unit to generate initial data to be set in the macro cell, and a data wiring section connected between the macro cell and the initial voltage setting unit so that the data wiring section is at a predetermined potential level. | 2013-08-29 |
20130222020 | FREQUENCY-CONTROL CIRCUITS AND SIGNAL GENERATION DEVICES USING THE SAME - A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops. | 2013-08-29 |
20130222021 | TRANSMITTING APPARATUS AND TRANSMITTING METHOD - A transmitting apparatus includes a first circuit to which a base clock and a first clock condition are input, the first circuit outputting a first enable signal based on the base clock and the first clock condition; a second circuit to which the base clock and a second clock condition are input, the second circuit outputting a second enable signal based on the base clock and the second clock condition; a first frame processing circuit receiving a first frame input signal and the first enable signal to output a first frame output signal in synchronization with the first enable signal; and a second frame processing circuit receiving a second frame input signal and the second enable signal to output a second frame output signal in synchronization with the second enable signal. | 2013-08-29 |
20130222022 | SYSTEM AND METHOD FOR OSCILLATOR FREQUENCY CONTROL - Techniques to compensate for sources of temperature and process dependent errors within an oscillator system for frequency control oscillator output clock signal. The oscillator system may include a controller and an oscillator circuit. The techniques may include generating a pair of voltages, a first of which is temperature variant, having (approximately) known temperature variations across process, and a second of which is (approximately) temperature invariant. Each voltage may be scaled by a corresponding trim factor. The scaled voltages may be combined to generate a reference voltage. The reference voltage may compensate for process and temperature dependent error sources within the oscillator system to set the oscillator output clock signal frequency. | 2013-08-29 |
20130222023 | DIGITAL PHASE LOCK LOOP AND METHOD THEREOF - An apparatus of digital phase lock loop and method are provided. In one embodiment, an apparatus comprises: an analog-to-digital converter (ADC) for converting a voltage level of an output clock into a first digital word in accordance with a timing defined by a reference clock; a first digital loop filter for receiving the first digital word and outputting a control code; a circuit to receive the reference clock and the output clock and output an offset code according to a frequency error of the output clock with respect to a frequency of the reference clock; an adder for generating an offset control code by summing the control code with the offset code; and a digitally controlled oscillator for outputting the output clock in accordance with the offset control code. | 2013-08-29 |
20130222024 | FREQUENCY GENERATING SYSTEM - A frequency generating system including a phase-locked loop (PLL) and a control signal generation unit is provided. The PLL outputs a phase-locked clock and controls a voltage-controlled oscillator (VCO) therein by using a dual-path architecture. The VCO includes a varactor. The control signal generation unit is coupled to the PLL and disposed in one of the dual paths. The control signal generation unit provides an up voltage, a down voltage, or a middle voltage as a control signal to control the VCO according to an up signal and a down signal of the PLL. The control signal generation unit provides the middle voltage in response to an electrical characteristic of the varactor to compensate the control signal. | 2013-08-29 |
20130222025 | PHASE LOCKED LOOP - A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal. | 2013-08-29 |
20130222026 | DIGITAL PHASE LOCKED LOOP - An apparatus comprises digitally controlled oscillator circuitry, feedback circuitry operatively coupled to the digitally controlled oscillator circuitry, and comparison circuitry operatively coupled to the digitally controlled oscillator circuitry and the feedback circuitry. The feedback circuitry, in response to a clock signal generated by the digitally controlled oscillator circuitry, generates a first digital value representing a detected phase of the clock signal for a given clock signal cycle. The comparison circuitry, in response to the first digital value and to a second digital value representing a reference phase, generates a phase error value. The phase error value is useable to generate a first digital control word provided to the digitally controlled oscillator circuitry for controlling a frequency associated with the clock signal. The digitally controlled oscillator circuitry further comprises adjustment circuitry capable of applying a phase adjustment to the clock signal in response to a second digital control word. | 2013-08-29 |
20130222027 | INTEGRATED CIRCUIT, MICRO-CONTROLLER UNIT, AND METHOD INCLUDING A SYNCHRONOUS SAMPLING CONTROLLER - A micro-controller unit (MCU) includes an analog-to-digital converter (ADC) including an input, a timing input, and an output. The input of the ADC is configurable to couple to an output of a peripheral module. The MCU further includes a synchronous sampling controller configured to provide a clock signal to a clock output terminal configurable to couple to a clock input of the peripheral module. The synchronous sampling controller is further configured to provide a timing signal to the timing input of the ADC to synchronize sampling of a signal at the input of the ADC to timing of the peripheral module. | 2013-08-29 |
20130222028 | METHOD AND APPARATUS FOR LOAD SWITCH CONTROLLER - A power control device can generate control signals to control operation of power sources. Additional control signals control operation of load switches that can be connected to the power sources to provide secondary sources of power. The load switches can be turned in a gradual manner at rates that depend on the power sources to which they are connected. The outputs of the load switches can be monitored for overvoltage and undervoltage conditions relative to the power sources to which they are connected. | 2013-08-29 |
20130222029 | METHOD FOR PULSE-LATCH BASED HOLD FIXING - A hold pulse latch is located in a data path between an output of a launch pulse latch and an input of a capture pulse latch. The hold pulse latch is configured to latch, and hold for the input of the capture patch, the output of the launch pulse latch in response to a hold pulse on its enable input. Optionally, at higher voltages, and frequency is high the launch pulse latch is changed to a transparent buffer mode. Optionally, the hold pulse latch is placed midway through the logic path between the launch pulse latch and the capture pulse latch. | 2013-08-29 |
20130222030 | PULSE SHIFTING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a rupture instructing pulse generation unit configured to generate a rupture instructing pulse signal in response to a fuse rupture command signal and an address; a first anti-fuse rupture unit configured to perform an operation for rupturing a first anti-fuse during an enable period of the rupture instructing pulse signal, and generate rupture information of the first anti-fuse; a pulse shifting unit configured to delay the rupture instructing pulse signal and generate a delayed rupture instructing pulse signal; and a second anti-fuse rupture unit configured to perform an operation for rupturing a second anti-fuse during an enable period of the delayed rupture instructing pulse signal, and generate rupture information of the second anti-fuse. | 2013-08-29 |
20130222031 | IMPLEMENTING POWER SAVING SELF POWERING DOWN LATCH STRUCTURE - A method and circuits for implementing power saving self powering down latch operation, and a design structure on which the subject circuit resides are provided. A master slave latch includes a virtual power supply connection. At least one connection control device is coupled between the virtual power supply connection and a voltage supply rail. A driver gate applies a power down signal driving the at least one connection control device to control the at least one connection control device during a self power down mode. The driver gate combines a self power down input signal and a latch data output signal to generate the power down signal. | 2013-08-29 |
20130222032 | ADAPTIVE CLOCK SIGNAL GENERATOR WITH NOISE IMMUNITY CAPABILITY - An adaptive clock signal generator with noise immunity capability is disclosed, including a gain amplifier for processing an analog oscillation signal to generate an amplified signal; an adjustable Schmitt trigger, coupled with the gain amplifier, for generating a triggered signal according to the amplified signal; an output buffer, coupled with the adjustable Schmitt trigger, for generating a clock signal according to the triggered signal; and a noise detector coupled with the adjustable Schmitt trigger. The noise detector detects noise components of an input signal and enlarges the hysteresis window of the adjustable Schmitt trigger as the level of detected noise increases. | 2013-08-29 |
20130222033 | Nonvolatile Latch Circuit And Logic Circuit, And Semiconductor Device Using The Same - To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided. | 2013-08-29 |
20130222034 | High Speed Pulse Shaping Technology - A circuit adapted to generate a high speed shaped pulse comprising an input adapted to receive a data signal and a control signal. A plurality of logic elements are configures to receive the data signal and the control signal and generate a plurality of output signals representative of the shaped pulse. A digital to analog converter is adapted to receive the plurality of output signals and generate a shaped pulse. | 2013-08-29 |
20130222035 | LEVEL-SHIFTING INTERFACE FOR A PROCESSOR-BASED DEVICE - An apparatus includes an integrated circuit, which includes an input terminal, a second terminal to communicate with circuitry external to the integrated circuit, a multiplexer, a level shifter and a processor. The multiplexer is adapted to selectively couple the input terminal, the level shifter and the second output terminal together. | 2013-08-29 |
20130222036 | VOLTAGE LEVEL CONVERTING CIRCUIT - A voltage level converting circuit includes: a voltage level converting block configured to convert an input signal having a first voltage level into an output signal having a second voltage level; and a boosting block connected to an input stage and an inverting input stage of the voltage level converting block, and configured to provide a negative voltage to the input stage or the inverting input stage. | 2013-08-29 |
20130222037 | VOLTAGE LEVEL SHIFTER - A voltage level shifter has an input circuit with an inverter coupled to an input node, a pull-down control transistor with a gate coupled to a first node of the inverter, and a pull-up control transistor with a gate coupled to a second node of the inverter. Sources of the pull-down and pull-up control transistors are coupled to a low voltage reference. A transient connectivity limiter (TCL) has pull-down and pull-up transistors. Two control inputs are coupled to respective first and second nodes of the inverter and path inputs are coupled to respective drains of the pull-down and pull-up control transistors. An output circuit has inputs coupled to pull-up and pull-down nodes of the TCL. During a voltage level transition at the input node, the TCL connects the pull-up node to the low voltage reference through the TCL pull-up transistor transitioning from a saturation to a sub-threshold region of operation. | 2013-08-29 |
20130222038 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a bypass circuit that forms a bypass path under a low voltage condition, and the bypass circuit includes first and second bypass MOS transistors respectively placed between drains of first and second PMOS transistors and a ground voltage terminal, each transistor having a gate to which a second power supply voltage is applied, and third and fourth bypass MOS transistors respectively placed between the first and second bypass MOS transistors and the ground voltage terminal, each transistor controlled to be ON and OFF in accordance with an input signal and a voltage condition. | 2013-08-29 |
20130222039 | INPUT BUFFER - An input buffer includes a first amplification block, a second amplification block, and a buffer block. The first amplification block is configured to be driven by an external voltage, to differentially amplify an input signal and a reference voltage in response to a bias voltage, and to subsequently generate first and second differential signals. The second amplification block is configured to be driven by an internal voltage, to differentially amplify the first and second differential signals, and to generate an output signal. The buffer block is configured to be driven by the internal voltage, to buffer the output signal, and to output an inverted output signal. | 2013-08-29 |
20130222040 | Signal Transmission Arrangement with a Transformer - A signal transmission arrangement includes a transformer with a first and a second winding. A damping circuit has an input terminal for receiving an input signal. The damping circuit is coupled to the first winding and is configured to have an electrical resistance that is dependent on the input signal. An oscillator circuit includes the second winding and is configured to provide an oscillating signal. An evaluation circuit is configured to receive the oscillating signal and to provide an output signal that is dependent on an amplitude of the oscillating signal. | 2013-08-29 |
20130222041 | HIGH FREQUENCY MIXER WITH TUNABLE DYNAMIC RANGE - A high frequency mixer with a tunable dynamic range is disclosed. One embodiment provides a mixer apparatus including multiple first transistors at an input branch that receive a differential radio frequency (RF) signal, and multiple second transistors at a second branch that receive a differential local oscillator (LO) signal. The second transistors generate an intermediate frequency (IF) differential output signal. The bias current that flows at the input branch and the output branch can be independently adjusted to allow the conversion gain, linearity, or the output noise of the mixer to be controlled. | 2013-08-29 |
20130222042 | DRIVE CIRCUIT - A drive circuit is provided with a charge pump including a capacitor. The capacitor of the charge pump is configured to be charged in the first stage and to be connected with the gate terminal of the switching device in the second stage. The charge pump is configured to be able to adjust a charging voltage charged in the capacitor according to an order signal. | 2013-08-29 |
20130222043 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In the device, a pair of transistors includes first and second transistors connected in parallel between a power-supply-line and a power-supply or between a ground-line and a ground-potential. A third transistor is connected between the power-supply-line and the power-supply or between the ground-line and the ground-potential. First to third nodes are gate nodes of the first to third transistors. A first buffer outputs a first control-signal for controlling the first transistor. A second buffer is connected between the first node and the second and third nodes to receive the first control-signal and transmit a second control-signal for controlling the second and third transistors to the second and third nodes in parallel. When power-supplying starts, the second control signal drives the second and third transistors to the conductive-state after the first control-signal controls the first transistor to be driven in an intermediate-state between the conductive-state and a shutoff-state. | 2013-08-29 |
20130222044 | POWER TRANSISTOR DRIVING CIRCUITS AND METHODS FOR SWITCHING MODE POWER SUPPLIES - A power supply controller is provided for providing a drive current to a control terminal of a power transistor in three time intervals. The controller includes control circuits configured to control the drive current in multiple stages. During a first time interval, first drive current includes a current spike for turning on the power transistor in response to a start of the control signal pulse. During a second time interval, a second drive current includes a ramping current substantially proportional to a magnitude of a current through the power transistor. During a third time interval, current flow to the power transistor is at least partially turned off before an end of the control signal pulse. | 2013-08-29 |
20130222045 | SEMICONDUCTOR POWER MODULES AND DEVICES - An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion. | 2013-08-29 |
20130222046 | MODIFIED BINARY SEARCH FOR TRANSFER FUNCTION ACTIVE REGION - This document discusses, among other things, a modified binary search configured to identify monotonic transfer function active region boundaries. The modified binary search can avoid false results outside of the active region of the monotonic transfer function. | 2013-08-29 |
20130222047 | DRIVING METHOD FOR CHARGER NOISE REJECTION IN TOUCH PANEL - A driving method for charger noise rejection in a touch panel has steps of: reading the sensing frame of the touch panel with a self-capacitance sensing mode, marking at least one first-axis sensing line having a recognizable sensing value, and driving the at least one marked first-axis sensing line with a mutual-capacitance sensing mode to acquire at least one sensing value corresponding to at least one sensing point on each one of the at least one marked first-axis sensing line. Accordingly, the charger noise is rejected in the touch panel by the driving method of the present invention. Additionally, a frame rate is further increased since the sensing lines are partially driven under the mutual-capacitance sensing mode. | 2013-08-29 |
20130222048 | POWER DEVICE - A power device possesses a built-in fuse function and can continue to normally operate after a short circuit failure. The power device includes a plurality of output cells, a plurality of bonding wires provided corresponding to the output cells, and a control terminal driving circuit. Each of the output cells includes an output transistor. First side electrodes of the output transistors are commonly coupled to a first power source. Each of second side electrodes of the output transistors is coupled to an output terminal through the corresponding bonding wire. The control terminal driving circuit supplies a drive signal to the control terminals of the individual output transistors to control the output transistors. Each of the bonding wires is designed to be fused and cut if the output transistor included in the corresponding output cell fails and is shorted. | 2013-08-29 |
20130222049 | METHODS OF CONTROLLING STANDBY MODE BODY BIASING AND SEMICONDUCTOR DEVICES USING THE METHODS - A semiconductor device includes a semiconductor element; a body bias controller configured to generate a standby mode body bias control signal in a standby mode; and a body bias voltage generator configured to receive the standby mode body bias control signal from the body bias controller, generate a standby mode body bias voltage, and apply the standby mode body bias voltage to a body of the semiconductor element. The semiconductor device is capable of retaining data stored in a semiconductor element and blocking leakage current in the standby mode by controlling a body bias voltage, thereby increasing the integration degree of the semiconductor device. | 2013-08-29 |
20130222050 | Low Voltage and High Driving Charge Pump - The present disclosure relates to a charge pump circuit having one or more voltage multiplier circuits that enable generation of an output signal having a higher output voltage. In one embodiment, the charge pump circuit comprises a NMOS transistor having a drain connected to a supply voltage and a source connected to a chain of diode connected NMOS transistors coupled in series. A first voltage multiplier circuit is configured to generate a first two-phase output signal having a maximum voltage value that is twice the supply voltage. The first two-phase output signal is applied to the gate of the NMOS transistor, forming a conductive channel between the drain and the source, thereby allowing the supply voltage to pass through the NMOS transistor without a threshold voltage drop. Therefore, degradation of the charge pump output voltage due to voltage drops of the NMOS transistor is reduced, resulting in larger output voltages. | 2013-08-29 |
20130222051 | Charge Pump Device and Driving Capability Adjustment Method Thereof - A charge pump device is disclosed. The charge pump device includes a driving stage, for generating a driving signal corresponding to a driving capability; a charge pump circuit, for generating an output voltage according to the driving signal; a comparing circuit, comprising a first comparator for comparing the output voltage and a first reference voltage to generate a first comparing result; an overload detection circuit, for generating a detection result according to at least one of the first comparing result and the output voltage; and a driving capability control circuit, coupled between the overload detection circuit and the driving stage for controlling the driving capability corresponding to the driving signal according to the detection result. | 2013-08-29 |
20130222052 | LINEAR VOLTAGE REGULATOR GENERATING SUB-REFERENCE OUTPUT VOLTAGES - A linear voltage regulator includes a pair of amplifiers. A first amplifier of the pair is used in conventional fashion to generate a regulated output voltage by controlling an impedance of a pass transistor in the linear voltage regulator, the controlling being based on a difference between a reference voltage and a voltage at a first node in a voltage divider network connected between the output terminal of the voltage regulator and a ground terminal. The second amplifier of the pair compares the regulated output voltage and a voltage at a second node in the voltage divider network, and injects a proportional current into the first node. Generation of a regulated output voltage lesser than the reference voltage is thereby enabled. | 2013-08-29 |
20130222053 | HIGH FREQUENCY SMART BUFFER - Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies. | 2013-08-29 |
20130222054 | LOW DISTORTION FILTERS - An integrated continuous-time active-RC filter comprises a set of opamp integrators with Operational Transconductance Amplifiers (OTAs). The filter further includes at least one assistant connected between the input and output of each of the integrators of the set to enhance the linearity and speed of the opamp integrators of the set. The assistant comprises a plurality of sets of transconductors connected in parallel to each other wherein each set of transconductors is formed by a pair of MOSFETs connected in series, with one MOSFET operating in the triode region and the other MOSFET operating in the saturation region. The assistant is configured to provide an assistant current to be injected into the source of each of the integrators in the set to enhance the linearity and speed of the opamp integrators of the set. | 2013-08-29 |
20130222055 | Feedback Control And Coherency Of Multiple Power Supplies In Radio Frequency Power Delivery Systems For Pulsed Mode Schemes in Thin Film Processing - A RF power supply system for delivering periodic RF power to a load. A power amplifier outputs a RF signal to the load. A sensor measures the RF signal provided to the load and outputs signals that vary in accordance with the RF signal. A first feedback loop enables control the RF signal based upon power determined in accordance with output from the sensor. A second feedback loop enables control the RF signal based upon energy measured in accordance with signals output from the sensor. Energy amplitude and duration provide control values for varying the RF signal. The control system and techniques are applicable to both pulsed RF power supplies and in various instances to continuous wave power supplies. | 2013-08-29 |
20130222056 | RF BEAMFORMING IN PHASED ARRAY APPLICATION - Exemplary embodiments are directed to a beamforming device. A device may include at least one receive path; and an amplifier coupled to an output of each receive path. The device configured to process each a signal from each receive path in at least one of a voltage domain and a current domain. | 2013-08-29 |
20130222057 | POWER SUPPLY PRE-DISTORTION - There is disclosed a method of generating a supply voltage ( | 2013-08-29 |
20130222058 | AMPLIFIER - An amplifier includes an amplifying element that amplifies an input signal; an output terminal that outputs the signal amplified by the amplifying element; a matching circuit disposed in series between the amplifying element and the output terminal, and performing impedance matching; an impedance converter disposed in series between the amplifying element and the matching circuit or between the matching circuit and the output terminal; and a first resonator and a second resonator connected at the ends of the impedance converter. | 2013-08-29 |
20130222059 | FIR/IIR FILTER PREDISTORTER FOR POWER AMPLIFIERS EXHIBITING SHORT-TERM AND/OR LONG-TERM MEMORY EFFECTS - The present disclosure generally relates to predistortion that compensates for non-linearity of a power amplifier as well as short-term and long-term memory effects of the power amplifier. In one embodiment, a transmitter includes a power amplifier that amplifies a power amplifier input signal to provide a power amplifier output signal, a predistortion sub-system that effects predistortion of the power amplifier input signal to compensate for non-linearity of the power amplifier and memory effects of the power amplifier, and a adaptation sub-system that adaptively configures the predistortion sub-system. The predistortion sub-system includes a memory-less predistortion component that compensates for the non-linearity of the power amplifier, a Finite Impulse Response (FIR) filter that compensates for short-term memory effects of the power amplifier, and an Infinite Impulse Response (IIR) filter that compensates for long-term memory effects of the power amplifier. | 2013-08-29 |
20130222060 | MUTUALLY COUPLED MATCHING NETWORK - An impedance matching circuit is disclosed. The impedance matching circuit includes two or more mutually coupled inductors. A total self inductance of the impedance matching circuit is less than a corresponding impedance matching circuit that includes inductors that are not mutually coupled. The two or more mutually coupled inductors may have known current ratios that match current ratios in the corresponding impedance matching circuit. | 2013-08-29 |
20130222061 | MULTI-OCTAVE POWER AMPLIFIER - A multi-octave power amplifier and related method provides an impedance matching unit configured to match impedances of a pair of balanced radio frequency (RF) signals applied thereto and output a pair of impedance-matched balanced RF signals, a converting unit configured to convert the pair of the impedance-matched balanced RF signals to an unbalanced RF signal and a compensation unit configured to compensate at least one rolled-off frequency component of the unbalanced RF signal and output a compensated RF signal. | 2013-08-29 |
20130222062 | EFFICIENCY IMPROVED ENVELOPE AMPLIFIER USING DUAL SWITCHING AMPLIFIERS - Provided is a hybrid envelope amplifier having improved efficiency, and more particularly, to an envelope amplifier using a dual switching amplifier and having improved efficiency in which power consumption is reduced by controlling a switching current of a switching region according to a magnitude of an envelope input signal, thereby improving efficiency compared to a conventional hybrid envelope amplifier. The envelope amplifier using a dual switching amplifier and having improved efficiency comprises a linear amplifier and a switching amplifier, wherein the switching amplifier includes two or more switching stages that are selectively operated according to a magnitude of an input signal. | 2013-08-29 |
20130222063 | Method and Apparatus for Efficient and Distortion Compensated Digital Class-D Amplifier Ternary Modulation Scheme - The present disclosure generally relates to the field of digital Class-D amplifiers and more specifically to a technique for reducing output waveforms distortion of a digital class-D amplifier implementing a ternary modulation scheme. An apparatus embodiment comprises an enlarging component for enlarging at least one pulse of a first output waveform PWM_P_TERN′ of the amplifier | 2013-08-29 |
20130222064 | Low Voltage Operation For A Power Amplifier - In one embodiment, a power amplifier may include a bridge configuration having a first pair of gain transistors to receive a first portion of a differential signal and to amplify the first portion of the differential signal to an amplified first differential signal portion and a second pair of gain transistors to receive a second portion of the differential signal and to amplify the second portion of the differential signal to an amplified second differential signal portion. This second pair of gain transistors can be configured to be enabled in a first power mode and to be disabled in a second power mode. | 2013-08-29 |
20130222065 | DOHERTY POWER AMPLIFIER APPARATUS AND POWER AMPLIFICATION METHOD - A Doherty power amplifier apparatus and a power amplification method are disclosed in the present invention. The apparatus includes an auxiliary power amplifier apparatus and a main power amplifier apparatus, wherein the auxiliary power amplifier apparatus is configured to amplify signal power by using a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device; the main power amplifier is configured to amplify signal power by using a High voltage heterojunction bipolar transistor (HVHBT) device. An HVHBT device is adopted as a main power amplifier in the present invention. By use of the present invention, a power amplification efficiency of a main power amplifier in a Doherty power amplifier may be enhanced compared with an existing Doherty power amplifier in which both a main power amplifier and an auxiliary power amplifier use LDMOS, thereby a power amplification efficiency of the whole Doherty power amplifier is substantially increased. | 2013-08-29 |
20130222066 | VOLTAGE-CONTROLLED OSCILLATOR WITH AMPLITUDE AND FREQUENCY INDEPENDENT OF PROCESS VARIATIONS AND TEMPERATURE - In one embodiment, a voltage-controlled oscillator (VCO) is provided having an output signal having a frequency responsive to a tuning signal. The VCO includes: a plurality of inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, each inverter stage including a plurality of switched-capacitor circuits configured to control a signal delay through the inverter stage response to the tuning signal so as to control the frequency of the output signal; and a bias circuit configured to generate the bias voltage responsive to a reference signal such that an amplitude of the output signal is substantially independent of the output signal frequency and depends upon the reference signal. | 2013-08-29 |
20130222067 | PHASE-LOCKED LOOP - A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal. | 2013-08-29 |
20130222068 | OSCILLATION CIRCUIT, INTEGRATED CIRCUIT, AND ABNORMALITY DETECTION METHOD - There is provided an oscillation circuit including: a main oscillation circuit that outputs a specific main clock to an internal circuit; a sub oscillation circuit that outputs a sub clock having a different frequency to the frequency of the main oscillation circuit; a first abnormality detection section that detects an abnormality according to a number of main clock cycles output from the main oscillation circuit within a predetermined period corresponding to sub clock outputs from the sub oscillation circuit; and a second abnormality detection section that detects an abnormality according to a frequency divided clock of the main clock output from the main oscillation circuit that has been frequency-divided and the sub clock output from the sub oscillation circuit. | 2013-08-29 |
20130222069 | Systems and Methods of Low Power Clocking for Sleep Mode Radios - Systems and methods of low power clocking of sleep mode radios are disclosed herein. In an example embodiment, a crystal oscillator is purposefully mistuned to achieve lower power consumption, and then synchronized using a high frequency crystal oscillator. In an alternative embodiment, the input offset voltages of the comparator in an RC oscillator are cancelled, which allows low power operation and high accuracy performance when tuned to the high frequency crystal. A lower power comparator may be used with higher input offset voltages but still achieve higher accuracy. The RC circuit is switched back and forth on opposite phases of the output, cancelling the offset voltage on the inputs of the comparator. | 2013-08-29 |
20130222070 | RECONFIGURABLE VOLTAGE CONTROLLED OSCILLATOR FOR SUPPORTING MULTI-MODE APPLICATIONS - In accordance with an embodiment of the disclosure, circuits and methods are provided for using a reconfigurable voltage controlled oscillator to support multi-mode applications. A voltage control oscillator circuit comprises a resonant circuit, a first oscillator circuitry coupled to the resonant circuit, and a second oscillator circuitry coupled to the resonant circuit. The voltage control oscillator circuit further comprises switching circuitry configured to select, based on an operating metric, one of the first oscillator circuitry and the second oscillator circuitry for providing an output voltage. | 2013-08-29 |
20130222071 | Oscillator based on a 6T SRAM for measuring the Bias Temperature Instability - The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately. | 2013-08-29 |
20130222072 | LEVEL SHIFTER, OSCILLATOR CIRCUIT USING THE SAME AND METHOD - A level shifter for a set of at least three phase-shifted signals is disclosed. The level shifter comprises an odd plural number of inverters arranged in a ring. A supply terminal of each inverter is coupled to a supply rail via a respective switching device, which is controlled by the phase-shifted signals. | 2013-08-29 |
20130222073 | Design and Control of Multi-Temperature Micro-Oven for MEMS Devices - Disclosed are microelectromechanical system (MEMS) devices and methods of using the same. In some embodiments, a MEMS device comprises a micro-oven comprising a MEMS oscillator configured to generate a reference signal. The device further comprises a control unit comprising at least one input node configured to receive a parameter set, where the parameter set comprises at least a first parameter indicative of a sensed ambient temperature, and where the control system is configured to (i) based on the parameter set, select from a plurality of pre-characterized operation temperatures an operation temperature for the MEMS oscillator, and (ii) generate a temperature-setting signal indicating the selected operation temperature. The device still further comprises a temperature control system communicatively coupled to the control unit and configured to (i) receive the temperature-setting signal and (ii) maintain the MEMS oscillator at the selected operation temperature. | 2013-08-29 |
20130222074 | OSCILLATION FREQUENCY REGULATING CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE AND OSCILLATION FREQUENCY REGULATION METHOD - There is provided an oscillation frequency regulating circuit including: a measuring section that performs measurement based on an oscillation frequency of an oscillation circuit; a comparator section that compares a measurement value measured by the measuring section against a set comparison value over a set comparison duration; a setting section that sets a comparison value selected from a plurality of comparison values of different magnitudes and that sets in the comparator section the comparison duration according to the magnitude of the selected comparison value; and a regulation section that, based on the comparison result of the comparator section, regulates the oscillation frequency of the oscillation circuit such that the oscillation frequency that is measured by the measuring section becomes a target oscillation frequency. | 2013-08-29 |
20130222075 | Methods and Apparatuses for use in Tuning Reactance in a Circuit Device - Methods and apparatuses for use in tuning reactance are described. Open loop and closed loop control for tuning of reactances are also described. Tunable inductors and/or tunable capacitors may be used in filters, resonant circuits, matching networks, and phase shifters. Ability to control inductance and/or capacitance in a circuit leads to flexibility in operation of the circuit, since the circuit may be tuned to operate under a range of different operating frequencies. | 2013-08-29 |
20130222076 | COUPLING APPARATUS FOR DIVIDING RECEIVING AND TRANSMITTING SIGNALS AND CONTROL METHOD THEREOF - The present invention is directed to a coupling apparatus for dividing a radio frequency (RE) transmitting signal and an RF receiving signal in a transceiver with a transmitting unit and a receiving unit sharing an antenna, comprising: a four-port circuit having ports | 2013-08-29 |
20130222077 | ELASTIC WAVE FILTER DEVICE - An elastic wave filter device includes first and second signal terminals, an inductor, and a ladder elastic wave filter unit. The elastic wave filter device includes an elastic wave filter chip provided with the ladder elastic wave filter unit and a wiring board. The wiring board includes a plurality of dielectric layers and a plurality of electrode layers alternately laminated. An inductor electrode and a ground electrode are arranged so as to not face each other via the dielectric layer. | 2013-08-29 |
20130222078 | EMC FILTER CIRCUIT - An EMC filter circuit ( | 2013-08-29 |
20130222079 | SURFACE ACOUSTIC WAVE DEVICE AND METHOD OF ADJUSTING LC COMPONENT OF SURFACE ACOUSTIC WAVE DEVICE - A surface acoustic wave device comprises a piezoelectric substrate ( | 2013-08-29 |
20130222080 | NON-RESONANT NODE FILTER - Various exemplary embodiments relate to a filter configured to operate in an operational frequency range. The filter may include a mainline, at least one combline resonator coupled to the mainline, an input port coupled to the mainline, and an output port coupled to the mainline. The mainline may include at least one non-resonant node. The at least one non-resonant node may be configured to resonate in a frequency range outside of the operational frequency range of the filter, and the at least one combline resonator may be configured to resonate in a frequency range within the operational frequency range of the filter. | 2013-08-29 |
20130222081 | ANTENNA FEED WITH POLARIZATION ROTATION - Various exemplary embodiments relate to an antenna feed configured to receive a signal having a wavelength. They antenna feed may include a cylindrical body and four pin groups. Each pin group may include two pins in close proximity extending across the center of the cylindrical body. One of the two pins may be rotated approximately 22.5° from the angle of the other pin. Each pin group may be spaced approximately one quarter of a wavelength away from each other, and may be rotated approximately 22.5° from the angle of the previous pin group. | 2013-08-29 |
20130222082 | EQUALIZER FOR MULTI-LEVEL EQUALIZATION - An equalizer includes a first delay module, a second delay module, a first amplitude module, a second amplitude module, and a combining unit. The first delay module receives a first signal and delays the first received signal for a preset period, and the first amplitude module transfers the first delayed signal to transmit a first weighted signal with a first peak amplitude. Similarly, the second delay module receives the first delayed signal and delays the second received signal for the preset period, and the second amplitude module transfers the second delayed signal to transmit a second weighted signal with a second peak amplitude. The combining unit combines an input signal and the first and the second weighted signals together to generate an equalized signal. | 2013-08-29 |