35th week of 2013 patent applcation highlights part 19 |
Patent application number | Title | Published |
20130221381 | ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic light emitting diode display device includes: a semiconductor layer on a substrate and including source and drain regions; a first insulating layer on the semiconductor layer; a gate electrode and a first storage electrode on the first insulating layer; a second insulating layer on the gate electrode and the first storage electrode; source and drain electrodes connected with the source and drain regions, respectively; a second storage electrode on the second insulating layer at a location corresponding to the first storage electrode; a third insulating layer on the source and drain electrodes and the second storage electrode; a first metal layer on the third insulating layer and connecting the drain electrode to an anode; and a second metal layer on the third insulating layer at a location corresponding to the second storage electrode. | 2013-08-29 |
20130221382 | MANUFACTURING LIGHT EMITTING DIODE (LED) PACKAGES - A method of manufacturing an LED package includes mounting a large panel frame/substrate (LPF/S) having a substantially square shape to a ring. The LPF/S includes a plurality of die pads and a corresponding plurality of leads arranged in a matrix pattern. Each of the die pads includes a planar chip attach surface. An LED chip is attached to the planar chip attach surface of each of the die pads. An encapsulant material is applied overlaying the LED chips and at least a part of the LPF/S. Each die pad and corresponding leads are separated from the LPF/S to form individual LED packages. The steps of attaching the LED chips and applying the encapsulant material are performed while the LPF/S is mounted to the ring. | 2013-08-29 |
20130221383 | TRANSPARENT LIGHT EMITTING DIODE PACKAGE AND FABRICATION METHOD THEROF - A light emitting diode (LED) package and a method of fabricating an LED package are provided. The LED package can include a transparent substrate and an LED arranged on the transparent substrate. A reflective layer and/or a polarizing layer can also be included. The LED may be disposed on one surface of the transparent substrate with the reflective layer and/or polarizing layer formed on an opposing surface of the transparent substrate. The fabrication method may include forming an LED on one surface of a transparent substrate by mounting a flip-chip on the transparent substrate or vapor-depositing the LED directly on the transparent substrate. A multi-package stacked structure can also be provided wherein a plurality of LED packages are stacked together unidirectionally or bidirectionally, with or without a reflective layer and/or a polarizing layer. | 2013-08-29 |
20130221384 | SEMICONDUCTOR LIGHT EMITTING ELEMENT ARRAY - A semiconductor light emitting element array contains: a support substrate; a plurality of semiconductor light emitting elements disposed on said support substrate, a pair of adjacent semiconductor light emitting elements being separated by street, each of the semiconductor light emitting elements including; a first electrode formed on the support substrate, a semiconductor lamination formed on the first electrode and including a stack of a first semiconductor layer having a first conductivity type, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer, and having a second conductivity type different from the first conductivity type, and a second electrode selectively formed on the second semiconductor layer of the semiconductor lamination; and connection member having electrical insulating property and optically propagating property, disposed to cover at least part of the street between a pair of adjacent semiconductor laminations. | 2013-08-29 |
20130221385 | LIGHT EMITTING ELEMENT AND PRODUCTION METHOD FOR SAME, PRODUCTION METHOD FOR LIGHT-EMITTING DEVICE, ILLUMINATION DEVICE, BACKLIGHT, DISPLAY DEVICE, AND DIODE - A light-emitting element includes a first conductivity type semiconductor base, a plurality of first conductivity type protrusion-shaped semiconductors formed on the semiconductor base, and a second conductivity type semiconductor layer that covers the protrusion-shaped semiconductors. | 2013-08-29 |
20130221386 | ISLANDED CARRIER FOR LIGHT EMITTING DEVICE - A low-cost conductive carrier element provides structural support to a light emitting device (LED) die, as well as electrical and thermal coupling to the LED die. A lead-frame is provided that includes at least one carrier element, the carrier element being partitioned to form distinguishable conductive regions to which the LED die is attached. When the carrier element is separated from the frame, the conductive regions are electrically isolated from each other. A dielectric may be placed between the conductive regions of the carrier element. | 2013-08-29 |
20130221387 | LIGHT EMITTING DIODE AND A MANUFACTURING METHOD THEREOF, A LIGHT EMITTING DEVICE - The present invention provides an LED and the manufacturing method thereof, and a light emitting device. The LED includes a first electrode, for connecting the LED to a negative electrode of a power supply; a substrate, located on the first electrode; and an LED die, located on the substrate; in which a plurality of contact holes are formed extending through the substrate, the diameter of upper parts of the contact holes is less than the diameter of lower parts of the contact holes, and the contact holes are filled with electrode plugs connecting the first electrode to the LED die. The light emitting device includes the LED, and further includes a susceptor and an LED mounted on the susceptor. The manufacturing method includes: forming successively an LED die and a second electrode on a substrate; patterning a backsurface of the substrate to form inverted trapezoidal contact holes which expose the LED die; and filling the contact holes with conductive material till the backface of the substrate is covered by the conductive material. The LED has a high luminous efficiency and the manufacturing method is easy to implement. | 2013-08-29 |
20130221388 | METHOD FOR MANUFACTURING GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT, GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT, LAMP, AND RETICLE - A method for manufacturing a Group III nitride semiconductor light-emitting element of the invention includes a substrate-processing process of forming a main surface including a flat surface and a convex portion | 2013-08-29 |
20130221389 | LIGHT EMITTING DEVICE AND METHOD - A light emitting device and a method of manufacturing the same are capable of enhancing brightness and color distribution characteristics on a light-exiting surface. The light emitting device can include: a substrate; a light emitting stacked body composed of a semiconductor light emitting element disposed on the substrate, a wavelength conversion layer disposed on the semiconductor light emitting element and containing phosphor particles, and a light-transmitting plate member disposed on the wavelength conversion layer; and a light-transmitting scattering member containing a scattering material and disposed on the light-transmitting plate member. | 2013-08-29 |
20130221390 | LIGHT-EMITTING DIODE CHIP - A light-emitting diode chip having a semiconductor layer sequence having an active layer that generates electromagnetic radiation, wherein the light-emitting diode chip has, on a front side, a radiation exit surface, at least regions of the light-emitting diode chip have, on a rear side opposite the radiation exit surface, a mirror layer containing silver, a protective layer containing Pt is disposed on the mirror layer, and the protective layer has a structure that covers the mirror layer only in sub-regions. | 2013-08-29 |
20130221391 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light emitting device comprising: a substrate, wherein the substrate comprising a first major surface, a second major surface opposite to the first major surface, and a sidewall wherein at least partial of the sidewall is a substantially textured surface with a depth of 10˜150 μm; and a light emitting stack layer formed on the substrate. | 2013-08-29 |
20130221392 | Optoelectronic Semiconductor Body and Method for Producing the Same - An optoelectronic semiconductor body includes a semiconductor layer sequence which has an active layer suitable for generating electromagnetic radiation, and a first and a second electrical connecting layer. The semiconductor body is provided for emitting electromagnetic radiation from a front side. The first and the second electrical connecting layer are arranged at a rear side opposite the front side and are electrically insulated from one another by means of a separating layer. The first electrical connecting layer, the second electrical connecting layer and the separating layer laterally overlap and a partial region of the second electrical connecting layer extends from the rear side through a breakthrough in the active layer in the direction of the front side. Furthermore, a method for producing such an optoelectronic semiconductor body is specified. | 2013-08-29 |
20130221393 | LIGHT EMITTING DIODE COMPONENT COMPRISING POLYSILAZANE BONDING LAYER - In one embodiment, a semiconductor component, such as a wavelength converter wafer, is described wherein the wavelength converter is bonded to an adjacent inorganic component with a cured bonding layer comprising polysilazane polymer. The wavelength converter may be a multilayer semiconductor wavelength converter or an inorganic matrix comprising embedded phosphor particles. In another embodiment, the semiconductor component is a pump LED component bonded to an adjacent component with a cured bonding layer comprising polysilazane polymer. The adjacent component may the described wavelength converter(s) or another component comprised of inorganic material(s) such as a lens or a prism. Also described are methods of making semiconductor components such as wavelength converters and LED's. | 2013-08-29 |
20130221394 | LIGHT EMITTING DIODE AND FLIP-CHIP LIGHT EMITTING DIODE PACKAGE - A light emitting diode (LED) is revealed. The LED includes a substrate, a first-type-doped layer, a light emitting layer, a second-type-doped layer, a plurality of first grooves, a second groove, an insulation layer, a first contact, and a second contact. The LED features that the second groove is connected to one end of each first groove and penetrates the second-type-doped layer and the light emitting layer to expose a part of the first-type-doped layer. The contact area between the first contact and the first-type-doped layer is increased. Therefore, the LED is worked at high current densities without heat accumulation. Moreover, the light emitting area is not reduced and the light emitting efficiency is not affected. The LED is flipped on a package substrate to form a flip-chip LED package. | 2013-08-29 |
20130221395 | OPTOELECTRONIC DEVICE - A optoelectronic device comprises a semiconductor stack layer; a first transparent conductive oxide (abbreviate as “TCO” hereinafter) layer located on the semiconductor stack layer, wherein the first TCO layer has at least one opening; and a second TCO layer covering the first TCO layer, wherein the second TCO layer is filled into the opening of the first TCO layer and contacted with the semiconductor stack layer, and one of the first TCO layer and the second TCO layer forms an ohmic contact with the semiconductor stack layer. | 2013-08-29 |
20130221396 | OBJECT HAVING INTERNAL CAVITIES, LIGHT EMITTING DIODE ASSEMBLY - An object with an internal cavity may serve as a cooling structure for a semiconductor package. The object includes a stack of form fitting bodies. The stack has a first form fitting body shaped according to the cavity with a first layer forming a partially form fitting surface, the first layer including a mixture of a first metal and an oxide of the first metal, and a second layer adjacent to the first layer. The second layer includes the first metal but less oxide of the first metal than the first layer. The stack has a second form fitting body shaped according to the cavity with a first layer forming a partially form fitting surface configured to conform to the partially form fitting surface of the first form fitting body. | 2013-08-29 |
20130221397 | LIGHT EMITTING ELEMENT STRUCTURE AND CIRCUIT OF THE SAME - A light emitting element structure and a circuit thereof are provided. The light emitting element circuit includes a driving unit and a light emitting element. The driving unit is used for generating a driving current at a light emission period. The light emitting element includes a current transferring unit and a light emitting unit. The current transferring unit is connected with the driving unit to transfer the driving current and generate a light emitting current at the light emission period. The light emitting unit is connected with the current transferring unit and emits light in response to the light emitting current. The light emitting unit is connected with the current transferring unit and emits light in response to the light emitting current. | 2013-08-29 |
20130221398 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND FABRICATION METHOD THEREOF - A semiconductor light emitting device includes a conductive substrate, a light emitting structure, a first contact layer, a conductive via and a current interruption region. The light emitting structure is disposed on the conductive substrate and includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer. The first contact layer is disposed between the conductive substrate and the first conductive semiconductor layer. The conductive via is disposed to extend from the conductive substrate to be connected to the second conductive semiconductor layer. The current interruption region is disposed in a region adjacent to the conductive via in the light emitting structure. | 2013-08-29 |
20130221399 | LIGHT EMITTING DIODE HAVING ELECTRODE PADS - Exemplary embodiments of the present invention relate to a including a substrate, a first conductive type semiconductor layer arranged on the substrate, a second conductive type semiconductor layer arranged on the first conductive type semiconductor layer, an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer, a first electrode pad electrically connected to the first conductive type semiconductor layer, a second electrode pad arranged on the second conductive type semiconductor layer, an insulation layer disposed between the second conductive type semiconductor layer and the second electrode pad, and at least one upper extension electrically connected to the second electrode pad, the at least one upper extension being electrically connected to the second conductive type semiconductor layer. | 2013-08-29 |
20130221400 | ENCAPSULATING AGENT FOR OPTICAL SEMICONDUCTOR DEVICES, AND OPTICAL SEMICONDUCTOR DEVICE USING SAME - Provided is an encapsulant for optical semiconductor devices, which is capable of enhancing the adhesion between a housing and the encapsulant when an optical semiconductor device is encapsulated in the housing, and which is also capable of enhancing the bonding reliability with respect to humidity. The encapsulant for optical semiconductor devices includes: a first organopolysiloxane having an alkenyl group bonded to a silicon atom and an aryl group bonded to a silicon atom, but not having a hydrogen atom bonded to a silicon atom; a second organopolysiloxane having a hydrogen atom bonded to a silicon atom and an aryl group bonded to a silicon atom; a catalyst for hydrosilylation reaction; and an organic compound having a titanium atom. | 2013-08-29 |
20130221401 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction. | 2013-08-29 |
20130221402 | INSULATED GATE BIPOLAR TRANSISTOR - An insulated gate bipolar transistor includes a first semiconductor layer of a first conductivity type, a first base layer of a second conductivity type, a second base layer of the second conductivity type, a first emitter layer of the first conductivity type, and a second emitter layer of the first conductivity type. The first semiconductor layer has a first surface. A first trench and a second trench extend from the first surface into the first semiconductor layer. The first gate electrode is provided on the first semiconductor layer, on the first base layer, and on the first emitter layer via a first gate insulating film in the first trench. The second gate electrode is provided on the first semiconductor layer, on the second base layer, and on the second emitter layer via a second gate insulating film in the second trench. | 2013-08-29 |
20130221403 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device and related method of manufacturing a semiconductor device that has an active region in the inner circumference of a chip with a thickness less than that of the outer circumference of the chip in which a termination structure is provided. An n field stop region, a p collector region, and a collector electrode are on the other main surface of an n | 2013-08-29 |
20130221404 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall. | 2013-08-29 |
20130221405 | APPARATUS AND METHOD FOR ELECTRONIC CIRCUIT PROTECTION - Apparatus and methods for electronic circuit protection are disclosed. In one embodiment, an apparatus comprises a well having an emitter and a collector region. The well has a doping of a first type, and the emitter and collector regions have a doping of a second type. The emitter region, well, and collector region are configured to operate as an emitter, base, and collector for a first transistor, respectively. The collector region is spaced away from the emitter region to define a spacing. A first spacer and a second spacer are positioned adjacent the well between the emitter and the collector. A conductive plate is positioned adjacent the well and between the first spacer and the second spacer, and a doping adjacent the first spacer, the second spacer, and the plate consists essentially of the first type. | 2013-08-29 |
20130221406 | Ohmic Contact to Semiconductor - A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged. | 2013-08-29 |
20130221407 | MULTI-GATE TRANSISTOR DEVICE - A multi-gate transistor device includes a substrate, a fin structure extending along a first direction formed on the substrate, a gate structure extending along a second direction formed on the substrate, a drain region having a first conductivity type formed in the fin structure, a source region having a second conductivity type formed in the fin structure, and a first pocket doped region having the first conductivity type formed in and encompassed by the source region. The first conductivity type and the second conductivity type are complementary to each other. | 2013-08-29 |
20130221408 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, PROTECTIVE ELEMENT, AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: an epitaxial substrate formed by stacking a plurality of kinds of semiconductors over one semiconductor substrate by epitaxial growth; a field effect transistor of a first conductivity type formed in a first region; a field effect transistor of a second conductivity type formed in a second region; and a protective element formed in a third region. The protective element includes: a first stacking structure formed by etching the epitaxial substrate by vertical etching that proceeds in a stacking thickness direction; and a second stacking structure formed by etching the epitaxial substrate by vertical etching that proceeds in a stacking thickness direction. The protective element has two PN junctions on a current path formed between an upper end of the first stacking structure and an upper end of the second stacking structure via a base part of the first stacking structure and the second stacking structure. | 2013-08-29 |
20130221409 | SEMICONDUCTOR DEVICES WITH 2DEG AND 2DHG - A semiconductor device comprises three semiconductor layers. The semiconductor layers are arranged to form a 2DHG and a 2DEG separated by a polarization layer. The device comprises a plurality of electrodes: first and second electrodes electrically connected to the 2DHG so that current can flow between them via the 2DHG and a third electrode electrically connected to the 2DEG so that when a positive voltage is applied to the third electrode, with respect to at least one of the other electrodes, the 2DEG and the 2DHG will be at least partially depleted. | 2013-08-29 |
20130221410 | UNIT PIXEL OF IMAGE SENSOR AND IMAGE SENSOR INCLUDING THE SAME - A unit pixel of an image sensor includes a photoelectric conversion region, an isolation region, a floating diffusion region and a transfer gate. The photoelectric conversion region is formed in a semiconductor substrate. The isolation region surrounds the photoelectric conversion region, extends substantially vertically with respect to a first surface of the semiconductor substrate, and crosses the incident side of the photoelectric conversion region so as to block leakage light and diffusion carriers. The floating diffusion region is disposed in the semiconductor substrate above the photoelectric conversion region. The transfer gate is disposed adjacent to the photoelectric conversion region and the floating diffusion region, extends substantially vertically with respect to the first surface of the semiconductor substrate, and transmits the photo-charges from the photoelectric conversion region to the floating diffusion region. | 2013-08-29 |
20130221411 | MICROMECHANICAL SENSOR APPARATUS WITH A MOVABLE GATE, AND CORRESPONDING PRODUCTION PROCESS - A micromechanical sensor apparatus has a movable gate and a field effect transistor. The field effect transistor has a drain region, a source region, an intermediate channel region with a first doping type, and a movable gate which is separated from the channel region by an intermediate space. The drain region, the source region, and the channel region are arranged in a substrate. A guard region is provided in the substrate at least on the longitudinal sides of the channel region and has a second doping type which is the same as the first doping type and has a higher doping concentration. | 2013-08-29 |
20130221412 | Device System Structure Based On Hybrid Orientation SOI and Channel Stress and Preparation Method Thereof - The present invention provides a device system structure based on hybrid orientation SOI and channel stress and a preparation method thereof. According to the preparation method provided in the present invention, first, a (100)/(110) global hybrid orientation SOI structure is prepared; then, after epitaxially growing a relaxed silicon-germanium layer and strained silicon layer sequentially on the global hybrid orientation SOI structure, an (110) epitaxial pattern window is formed; then, after epitaxially growing a (110) silicon layer and a non-relaxed silicon-germanium layer at the (110) epitaxial pattern window, a surface of the patterned hybrid orientation SOI structure is planarized; then, an isolation structure for isolating devices is formed; and finally, a P-type high-voltage device structure is prepared in a (110) substrate portion, an N-type high-voltage device structure and/or low voltage device structures are prepared in the (100) substrate portion. In this manner, a carrier mobility is improved, Rdson of a high-voltage device is reduced, and performance of devices are improved, thereby facilitating further improvement of integration and reduction of power consumption. | 2013-08-29 |
20130221413 | DIVOT-FREE PLANARIZATION DIELECTRIC LAYER FOR REPLACEMENT GATE - After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers. | 2013-08-29 |
20130221414 | Semiconductor FET and Method for Manufacturing the Same - The present invention provides a semiconductor FET and a method for manufacturing the same. The semiconductor FET may comprise: a gate wall; a fin outside the gate wall, both ends of the fin being connected with the source/drain regions on both ends of the fin; and a contact wall on both sides of the gate wall, the contact wall being connected with the source/drain regions via the underlying silicide layer, wherein an airgap is provided around the gate wall. Since an airgap is formed around the gate wall, and particularly the airgap is formed between the gate wall and the contact wall, it is possible to decrease the parasitic capacitance between the gate wall and the contact wall. As a result, the problem of excessive parasitic capacitance resulting from use of the contact wall can be effectively alleviated. | 2013-08-29 |
20130221415 | Field-Effect P-N Junction - This disclosure provides systems, methods, and apparatus related to field-effect p-n junctions. In one aspect, a device includes an ohmic contact, a semiconductor layer disposed on the ohmic contact, at least one rectifying contact disposed on the semiconductor layer, a gate including a layer disposed on the at least one rectifying contact and the semiconductor layer and a gate contact disposed on the layer. A lateral width of the rectifying contact is less than a semiconductor depletion width of the semiconductor layer. The gate contact is electrically connected to the ohmic contact to create a self-gating feedback loop that is configured to maintain a gate electric field of the gate. | 2013-08-29 |
20130221416 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND SOLID-STATE IMAGING APPARATUS - A method of manufacturing a semiconductor device includes the steps of forming a gate electrode of a transistor on an insulator layer on a surface of a semiconductor substrate, forming an isolation region by performing ion implantation of an impurity of a first conductivity type into the semiconductor substrate, forming a lightly doped drain region by performing, after forming a mask pattern including an opening portion narrower than a width of the gate electrode on an upper layer of the gate electrode of the transistor, ion implantation of an impurity of a second conductivity type near the surface of the semiconductor substrate with the mask pattern as a mask, and forming a source region and a drain region of the transistor by performing ion implantation of an impurity of the second conductivity type into the semiconductor substrate after forming the gate electrode of the transistor. | 2013-08-29 |
20130221417 | MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages. | 2013-08-29 |
20130221418 | Analog Floating-Gate Memory Manufacturing Process Implementing N-Channel and P-Channel MOS Transistors - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. | 2013-08-29 |
20130221419 | Memcapacitor Devices, Field Effect Transistor Devices, And Non-Volatile Memory Arrays - A memcapacitor device includes a pair of opposing conductive electrodes. A semiconductive material including mobile dopants within a dielectric and a mobile dopant barrier dielectric material are received between the pair of opposing conductive electrodes. The semiconductive material and the barrier dielectric material are of different composition relative one another which is at least characterized by at least one different atomic element. One of the semiconductive material and the barrier dielectric material is closer to one of the pair of electrodes than is the other of the semiconductive material and the barrier dielectric material. The other of the semiconductive material and the barrier dielectric material is closer to the other of the pair of electrodes than is the one of the semiconductive material and the barrier dielectric material. Other implementations are disclosed, including field effect transistors, memory arrays, and methods. | 2013-08-29 |
20130221420 | STRUCTURE COMPRISING A RUTHENIUM METAL MATERIAL - A method for forming a ruthenium metal layer comprises combining a ruthenium precursor with a measured amount of oxygen to form a ruthenium oxide layer. The ruthenium oxide is annealed in the presence of a hydrogen-rich gas to react the oxygen in the ruthenium oxide with hydrogen, which results in a ruthenium metal layer. By varying the oxygen flow rate during the formation of ruthenium oxide, a ruthenium metal layer having various degrees of smooth and rough textures can be formed. | 2013-08-29 |
20130221421 | STACKED-GATE NON-VOLATILE FLASH MEMORY CELL, MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A stacked-gate non-volatile flash memory cell, a memory device including the memory cell, and a manufacturing method thereof are provided. The memory cell includes a semiconductor structure and a movable switch ( | 2013-08-29 |
20130221422 | MEMORY DEVICE AND METHOD OF MANUFACTURE THEREOF - A memory device is provided with a floating gate electrode film formed in a memory cell region, a first inter-electrode insulating film formed on the floating gate electrode film, a control gate electrode film formed on the first inter-electrode insulating film, a lower conductive film formed in a peripheral circuit region, a second inter-electrode insulating film formed on the lower conductive film, an upper conductive film formed on the second inter-electrode insulating film, and a pair of contacts that is separated from each other, is connected to the lower conductive film from the upper side, and is not connected to the upper conductive film. Materials of the lower conductive film and the floating gate electrode film are the same. Materials of the second inter-electrode insulating film and the first inter-electrode insulating film are the same. Materials of the upper conductive film and the control gate electrode film are the same. | 2013-08-29 |
20130221423 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes an underlayer and a stacked body. The stacked body includes control gate layers and insulating layers. The device includes a channel body layer penetrating through the stacked body, and the control gate layers and the insulating layers are stacked in the stacking direction, a floating gate layer provided between each of the plurality of control gate layers and the channel body layer. The device includes a block insulating layer provided between each of the plurality of control gate layers and the floating gate layer, and includes a tunnel insulating layer provided between the channel body layer and the floating gate layer. A length of a boundary between the floating gate layer and the block insulating layer is shorter than a length of a boundary between the floating gate layer and the tunnel insulating layer. | 2013-08-29 |
20130221424 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is described. A stacked gate dielectric is formed over a substrate, including a first dielectric layer, a second dielectric layer and a third dielectric layer from bottom to top. A conductive layer is formed on the stacked gate dielectric and then patterned to form a gate conductor. The exposed portion of the third and the second dielectric layers are removed with a selective wet cleaning step. S/D extension regions are formed in the substrate with the gate conductor as a mask. A first spacer is formed on the sidewall of the gate conductor and a portion of the first dielectric layer exposed by the first spacer is removed. S/D regions are formed in the substrate at both sides of the first spacer. A metal silicide layer is formed on the S/D regions. | 2013-08-29 |
20130221425 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device includes a plurality of interlayer dielectric layers and conductive layers for gate electrodes alternately stacked over a substrate, a channel trench passing through the interlayer dielectric layers and the conductive layers and exposing the substrate, a charge blocking layer and a charge trap or charge storage layer formed on sidewalls of the trench, a coupling prevention layer formed at the surface of the charge trap or charge storage layer, and a tunnel insulation layer formed over the coupling prevention layer. | 2013-08-29 |
20130221426 | ELECTRIC POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers. | 2013-08-29 |
20130221427 | Semiconductor Device With Improved Robustness - A semiconductor device includes a first contact in low Ohmic contact with a source region of the device and a first portion of a body region of the device formed in an active area of the device, and a second contact in low Ohmic contact with a second portion of the body region formed in a peripheral area of the device. The minimum width of the second contact at a first surface of the device is larger than the minimum width of the first contact at the first surface so that maximum current density during commutating the semiconductor device is reduced and thus the risk of device damage during hard commutating is also reduced. | 2013-08-29 |
20130221428 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN - An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface, wherein the patterned semiconductor layer defines a first trench and a second trench that extend from the primary surface towards the substrate. The electronic device can further include a first conductive electrode and a gate electrode within the first trench. The electronic device can still further include a second conductive electrode within the second trench. The electronic device can include a source region within the patterned semiconductor layer and disposed between the first and second trenches. The electronic device can further include a body contact region within the patterned semiconductor layer and between the first and second trenches, wherein the body contact region is spaced apart from the primary surface. Processes of forming the electronic device can take advantage of forming all trenches during processing sequence. | 2013-08-29 |
20130221429 | METHOD AND APPARATUS RELATED TO A JUNCTION FIELD-EFFECT TRANSISTOR - In a general aspect, a semiconductor device can include a gate having a first trench portion disposed within a first trench of a junction field-effect transistor device, a second trench portion disposed within a second trench of the junction field-effect transistor device, and a top portion coupled to both the first trench portion and to the second trench portion. The semiconductor device can include a mesa region disposed between the first trench and the second trench, and including a single PN junction defined by an interface between a substrate dopant region having a first dopant type and a channel dopant region having a second dopant type. | 2013-08-29 |
20130221430 | NANO-TUBE MOSFET TECHNOLOGY AND DEVICES - This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches. | 2013-08-29 |
20130221431 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF - A method for manufacturing a semiconductor device includes forming a first insulating film on inner surfaces of trenches arranged in parallel in a semiconductor layer, forming a control electrode on the first insulating film, and forming a second insulating film on the control electrode, where the upper surface of the second insulating film is lower than the upper end of the first insulating film. In addition, the method includes etching the semiconductor layer to a depth near the upper end of the control electrode and forming a first semiconductor region. The method further includes forming a conductive film and then a second semiconductor region in the upper portion of the first semiconductor region by diffusion of impurities from the conductive film into the upper portion of the first semiconductor region, and forming a contact hole by etching back the conductive layer. | 2013-08-29 |
20130221432 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device having a vertical MOS transistor and a method of manufacturing the same. The vertical MOS transistor has a trench gate, a distance between a gate electrode and an N-type high concentration buried layer below the gate electrode is formed longer than that in the conventional structure, and a P-type trench bottom surface lower region ( | 2013-08-29 |
20130221433 | Vertical Semiconductor Device with Thinned Substrate - A vertical semiconductor device is formed in a semiconductor layer having a first surface, a second surface and background doping. A first doped region, doped to a conductivity type opposite that of the background, is formed at the second surface of the semiconductor layer. A second doped region of the same conductivity type as the background is formed at the second surface of the semiconductor layer, inside the first doped region. A portion of the semiconductor layer is removed at the first surface, exposing a new third surface. A third doped region is formed inside the semiconductor layer at the third surface. Electrical contact is made at least to the second doped region (via the second surface) and the third doped region (via the new third surface). In this way, vertical DMOS, IGBT, bipolar transistors, thyristors, and other types of devices can be fabricated in thinned semiconductor, or SOI layers. | 2013-08-29 |
20130221434 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SAME - It is an object to improve the breakdown voltage characteristics of a vertical semiconductor device having an opening and including a channel formed of two-dimensional electron gas in the opening. The vertical semiconductor device includes a GaN-based stacked layer | 2013-08-29 |
20130221435 | CLOSED CELL TRENCHED POWER SEMICONDUCTOR STRUCTURE - A closed cell trenched power semiconductor structure is provided. The closed cell trenched power semiconductor structure has a substrate and cells. The cells are arranged on the substrate in an array. Every cell has a body and a trenched gate. The trenched gate surrounds the body. A side wall of the trenched gate facing body has a concave. | 2013-08-29 |
20130221436 | ELECTRONIC DEVICE INCLUDING A TRENCH AND A CONDUCTIVE STRUCTURE THEREIN AND A PROCESS OF FORMING THE SAME - An electronic device can include a transistor structure, including a patterned semiconductor layer overlying a substrate and having a primary surface. The electronic device can further include first conductive structures within each of a first trench and a second trench, a gate electrode within the first trench and electrically insulated from the first conductive structure, a first insulating member disposed between the gate electrode and the first conductive structure within the first trench, and a second conductive structure within the second trench. The second conductive structure can be electrically connected to the first conductive structures and is electrically insulated from the gate electrode. The electronic device can further include a second insulating member disposed between the second conductive structure and the first conductive structure within the second trench. Processing sequences can be used that simplify formation of the features within the electronic device. | 2013-08-29 |
20130221437 | TRANSISTOR WITH MINIMIZED RESISTANCE - The present disclosure discloses a power transistor array designed to have a very low resistance. The power transistor array includes a bottom metal layer and a top metal layer. The bottom metal layer includes a plurality of strips, each corresponding to either drain or source strips, the drain and source strips being placed in parallel and alternating with each other. Further, the top metal layer, above the bottom metal layer, includes a plurality of strips. Each strip corresponds to either drain or source strips, the drain and the source strips being placed and alternating with each other. The strips of the top metal layer are oriented at angle with respect to the strips of the bottom metal layer. Moreover, the power transistor includes a plurality of bond pads on the top metal layer, and bond wires with one end attached to the corresponding bond pad. | 2013-08-29 |
20130221438 | HIGH VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR DEVICE AND LAYOUT PATTERN THEREOF - A layout pattern of a high voltage metal-oxide-semiconductor transistor device includes a first doped region having a first conductivity type, a second doped region having the first conductivity type, and an non-continuous doped region formed in between the first doped region and the second doped region. The non-continuous doped region includes a plurality of gaps formed therein. The non-continuous doped region further includes a second conductivity type complementary to the first conductivity type. | 2013-08-29 |
20130221439 | SOI WAFER AND METHOD OF MANUFACTURING THE SAME - An SOI wafer according to the present invention includes a support substrate and an insulating layer formed on the support substrate, a predetermined cavity pattern being formed on one of main surfaces of the support substrate on which the insulating layer is provided, further includes an active semiconductor layer formed on the insulating layer with the cavity pattern being closed, the active semiconductor layer not being formed in an outer peripheral portion of the support substrate, and further includes a plurality of superposition mark patterns formed in the outer peripheral portion on the one of the main surfaces of the support substrate for specifying a position of the cavity pattern. | 2013-08-29 |
20130221440 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer. | 2013-08-29 |
20130221441 | REPLACEMENT GATE ELECTRODE WITH MULTI-THICKNESS CONDUCTIVE METALLIC NITRIDE LAYERS - Gate electrodes having different work functions can be provided by providing conductive metallic nitride layers having different thicknesses in a replacement gate scheme. Upon removal of disposable gate structures and formation of a gate dielectric layer, at least one incremental thickness conductive metallic nitride layer is added within some gate cavities, while not being added in some other gate cavities. A minimum thickness conductive metallic nitride layer is subsequently added as a contiguous layer. Conductive metallic nitride layers thus formed have different thicknesses across different gate cavities. A gate fill conductive material layer is deposited, and planarization is performed to provide multiple gate electrode having different conductive metallic nitride layer thicknesses. The different thicknesses of the conductive metallic nitride layers can provide different work functions having a range of about 400 mV. | 2013-08-29 |
20130221442 | EMBEDDED POWER STAGE MODULE - One aspect of the invention pertains to an integrated circuit package with an embedded power stage. The integrated circuit package includes a first field effect transistor (FET) and a second FET that are electrically coupled with one another. The FETs are embedded in a dielectric substrate that is formed from multiple dielectric layers. The dielectric layers are laminated together with one or more foil layers that help form an electrical interconnect for the package. Various embodiments relate to method of forming the above package. | 2013-08-29 |
20130221443 | FINFETS AND METHOD OF FABRICATING THE SAME - The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a plurality of first trenches having a first width and extending downward from the substrate major surface to a first height, wherein a first space between adjacent first trenches defines a first fin; and a plurality of second trenches having a second width less than first width and extending downward from the substrate major surface to a second height greater than the first height, wherein a second space between adjacent second trenches defines a second fin. | 2013-08-29 |
20130221444 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, with gate electrodes and side walls as a mask, oblique ion implanting of the impurity is carried out for the semiconductor substrate, so that channel impurity layers having different dopant concentrations are simultaneously implanted beneath a first and a second gate electrode. | 2013-08-29 |
20130221445 | Atomic Layer Deposition Methods For Metal Gate Electrodes - Provided are devices and methods utilizing TiN and/or TaN films doped with Si, Al, Ga, Ge, In and/or Hf. Such films may be used as a high-k dielectric cap layer, PMOS work function layer, aluminum barrier layer, and/or fluorine barrier. These TiSiN, TaSiN, TiAlN, TaAlN, TiGaN, TaGaN, TiGeN, TaGeN, TiInN, TaInN, TiHfN or TaHfN films can be used where TiN and/or TaN films are traditionally used, or they may be used in conjunction with TiN and/or TaN. | 2013-08-29 |
20130221446 | SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT - Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. | 2013-08-29 |
20130221447 | FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME - Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern. | 2013-08-29 |
20130221448 | FIN PROFILE STRUCTURE AND METHOD OF MAKING SAME - A FinFET device may include a first semiconductor fin laterally adjacent a second semiconductor fin. The first semiconductor fin and the second semiconductor fin may have profiles to minimize defects and deformation. The first semiconductor fin comprises an upper portion and a lower portion. The lower portion of the first semiconductor fin may have a flared profile that is wider at the bottom than the upper portion of the first semiconductor fin. The second semiconductor fin comprises an upper portion and a lower portion. The lower portion of the second semiconductor fin may have a flared profile that is wider than the upper portion of the second semiconductor fin, but less than the lower portion of the first semiconductor fin. | 2013-08-29 |
20130221449 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING DEVICE - According to one embodiment, a manufacturing method of a semiconductor device includes forming a monolayer that includes organic compounds that contain conductive type dopants on a semiconductor layer, applying a bias voltage to the semiconductor layer, and injecting plasma inactive gas ions against the monolayer, so that conductive type dopants included in the monolayer are impacted by the ions to form the dopant layer injected with the conductive type dopants in a semiconductor layer. This manufacturing method controls the density of the conductive type dopants in the dopant layer by changing a size of functional group. | 2013-08-29 |
20130221450 | MEMS DEVICE AND METHOD OF FORMING THE SAME - A micro electro mechanical system (MEMS) device and a method of forming the same are provided. The MEMS device comprises a semiconductor substrate ( | 2013-08-29 |
20130221451 | MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS - A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack. | 2013-08-29 |
20130221452 | Semiconductor Device and Method of Forming Semiconductor Die with Active Region Responsive to External Stimulus - A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die. | 2013-08-29 |
20130221453 | Tunable MEMS Device and Method of Making a Tunable MEMS Device - A tunable MEMS device and a method of manufacturing a tunable MEMS device are disclosed. In accordance with an embodiment of the present invention, a semiconductor device comprises a substrate, a moveable electrode and a counter electrode. The moveable electrode or the counter electrode comprises a first region and a second region, wherein the first region is isolated from the second region, wherein the first region is configured to be tuned, wherein the second region is configured to provide a sensing signal or control a system, and wherein the moveable electrode and the counter electrode are mechanically connected to the substrate. | 2013-08-29 |
20130221454 | PLANAR CAVITY MEMS AND RELATED STRUCTURES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - A Micro-Electro-Mechanical System (MEMS). The MEMS includes a lower chamber with a wiring layer and an upper chamber which is connected to the lower chamber. A MEMS beam is suspended between the upper chamber and the lower chamber. A lid structure encloses the upper chamber, which is devoid of structures that interfere with a MEMS beam. The lid structure has a surface that is conformal to a sacrificial material vented from the upper chamber. | 2013-08-29 |
20130221455 | Methods for Embedding Controlled-Cavity MEMS Package in Integration Board - An embedded micro-electro-mechanical system (MEMS) ( | 2013-08-29 |
20130221456 | Capacitance Type Micro-Silicon Microphone and Method for Making the Same - A capacitance type micro-silicon microphone includes a base, a backplate and a diaphragm positioned above the backplate in a suspended manner. The base includes a top face, a bottom face and a number of sound bores recessing inwardly from the top face. Bottom sides of the sound bores are in communication with each other so as to form an upper cavity. The base defines at least one lower cavity recessing inwardly from the bottom face. The backplate is positioned above the upper cavity in a suspended manner. The lower cavity is in communication with the upper cavity so as to jointly form a back cavity of the capacitance type micro-silicon microphone. Besides, a method for fabricating the capacitance type micro-silicon microphone is also disclosed. | 2013-08-29 |
20130221457 | ASSEMBLY OF A CAPACITIVE ACOUSTIC TRANSDUCER OF THE MICROELECTROMECHANICAL TYPE AND PACKAGE THEREOF - A microelectromechanical-acoustic-transducer assembly has: a first die integrating a MEMS sensing structure having a membrane, which has a first surface in fluid communication with a front chamber and a second surface, opposite to the first surface, in fluid communication with a back chamber of the microelectromechanical acoustic transducer, is able to undergo deformation as a function of incident acoustic-pressure waves, and faces a rigid electrode so as to form a variable-capacitance capacitor; a second die, integrating an electronic reading circuit operatively coupled to the MEMS sensing structure and supplying an electrical output signal as a function of the capacitive variation; and a package, housing the first die and the second die and having a base substrate with external electrical contacts. The first and second dice are stacked in the package and directly connected together mechanically and electrically; the package delimits at least one of the front and back chambers. | 2013-08-29 |
20130221458 | SENSOR MODULE FOR ACCOMMODATING A PRESSURE SENSOR CHIP AND FOR INSTALLATION INTO A SENSOR HOUSING - In a sensor module for accommodating a pressure sensor chip and for installation into a sensor housing, a module wall is connected monolithically to the module bottom and surrounds the pressure sensor chip. Multiple connecting elements which are conducted through the module wall to the outside run straight at least in the entire outside area. Furthermore, the connecting elements are exposed on their top and bottom sides for affixing and electrically connecting at least one electrical component and for electrically integrating the sensor module into the sensor housing. In this way, a two-sided use of a sensor module having an identical external geometry and identical connectors is possible. | 2013-08-29 |
20130221459 | Engineered Magnetic Layer with Improved Perpendicular Anisotropy using Glassing Agents for Spintronic Applications - A magnetic element is disclosed wherein first and second interfaces of a free layer with a perpendicular Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to increase thermal stability in a magnetic tunnel junction (MTJ). The free layer may be a single layer or a composite and is comprised of one or more glassing agents that have a first concentration in a middle portion thereof and a second concentration less than the first concentration in regions near first and second interfaces. As a result, a CoFeB free layer, for example, selectively crystallizes along first and second interfaces but maintains an amorphous character in a middle region containing a glass agent providing the annealing temperature is less than the crystallization temperature of the middle region. The magnetic element may be part of a spintronic device or serve as a propagation medium in a domain wall motion device. | 2013-08-29 |
20130221460 | Engineered Magnetic Layer with Improved Perpendicular Anisotropy using Glassing Agents for Spintronic Applications - A magnetic element in a spintronic device or serving as a propagation medium in a domain wall motion device is disclosed wherein first and second interfaces of a free layer with a perpendicular Hk enhancing layer and tunnel barrier, respectively, produce enhanced surface perpendicular anisotropy to increase thermal stability in a magnetic tunnel junction. The free layer may be a single layer or a composite and is comprised of a glassing agent that has a first concentration in a middle portion thereof and a second concentration less than the first concentration in regions near first and second interfaces. A CoFeB free layer selectively crystallizes along first and second interfaces but maintains an amorphous character in a middle region containing a glass agent providing the annealing temperature is less than the crystallization temperature of the middle region. | 2013-08-29 |
20130221461 | Ferromagnetic Tunnel Junction Structure and Magnetoresistive Effect Device and Spintronics Device Utilizing Same - A ferromagnetic tunnel junction structure comprising a first ferromagnetic layer, a second ferromagnetic layer, and a tunnel barrier layer that is interposed between the first ferromagnetic layer and the second ferromagnetic layer, wherein the tunnel barrier layer includes a crystalline non-magnetic material having constituent elements that are similar to those of an crystalline oxide that has spinel structure as a stable phase structure; the non-magnetic material has a cubic structure having a symmetry of space group Fm-3m or F-43m in which atomic arrangement in the spinel structure is disordered; and an effective lattice constant of the cubic structure is substantially half of the lattice constant of the oxide of the spinel structure. | 2013-08-29 |
20130221462 | SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor memory device includes sequentially depositing a bottom electrode layer, a magnetic tunnel junction (MTJ) layer, a first top electrode layer, a second top electrode layer and a mask layer, etching the mask layer and forming a mask pattern, etching the second top electrode layer and the first top electrode layer by using the mask pattern as an etch barrier, etching the MTJ layer by using the mask layer and the second top electrode layer as an etch barrier, and etching the bottom electrode layer by using the first top electrode layer as an etch barrier. | 2013-08-29 |
20130221463 | SOLID-STATE IMAGING ELEMENT - According to one embodiment, a solid-state imaging element, includes a plurality of impurity regions provided with a prescribed interval, each of the impurity regions acting as a channel for transferring charges, wherein the impurity region has a trapezoid shape in which bases is perpendicularly directed to a charge transfer direction, a width of a first base of the bases at a transferring side is larger than a width of a second base of the bases at a receiving side. | 2013-08-29 |
20130221464 | REDUCED LIGHT DEGRADATION DUE TO LOW POWER DEPOSITION OF BUFFER LAYER - Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a work function that falls substantially in a middle of a barrier formed between the transparent electrode and the p-type layer to provide a greater resistance to light induced degradation. An intrinsic layer and an n-type layer are formed over the p-type layer. | 2013-08-29 |
20130221465 | IMAGE SENSORS - Image sensors include a first insulation interlayer structure on a first surface of a substrate and having a multi-layered structure. A first wiring structure is in the first insulation interlayer structure. A via contact plug extends from a second surface of the substrate and penetrates the substrate to be electrically connected to the first wiring structure. Color filters and micro lenses are stacked on the second surface in a first region of the substrate. A second insulation interlayer structure is on the second surface in a second region of the substrate. A second wiring structure is in the second insulation interlayer structure to be electrically connected to the via contact plug. A pad pattern is electrically connected to the second wiring structure and having an upper surface through which an external electrical signal is applied. Photodiodes are between the first and second wiring structures in the first region. | 2013-08-29 |
20130221466 | MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE AND SOLID-STATE IMAGING DEVICE - A manufacturing method of a solid-state imaging device includes: preparing a photoelectric conversion device; forming an insulating layer on a surface of the photoelectric conversion device; forming a wire-grid polarizer on a support base; bonding a forming surface of the wire-grid polarizer on the support base to the insulating layer on the surface of the photoelectric conversion device and removing the support base from the wire-grid polarizer. | 2013-08-29 |
20130221467 | Performance Optically Coated Semiconductor Devices and Related Methods of Manufacture - The present application disclosed various embodiments of improved performance optically coated semiconductor devices and various methods for the manufacture thereof and includes depositing a first layer of a low density, low index of refraction material on a surface of a semiconductor device, depositing a multi-layer optical coating comprising alternating layers of low density, low index of refraction materials and high density, high index of refraction materials on the coated surface of the semiconductor device, selectively ablating a portion of the alternating multi-layer optical coating to expose at least a portion of the low density first layer, and selectively ablating a portion of the first layer of low density material to expose at least a portion of the semiconductor device. | 2013-08-29 |
20130221468 | COMPACT SENSOR MODULE - A compact sensor module and methods for forming the same are disclosed herein. In some embodiments, a sensor die is mounted on a sensor substrate. A processor die can be mounted on a flexible processor substrate. In some arrangements, a thermally insulating stiffener can be disposed between the sensor substrate and the flexible processor substrate. At least one end portion of the flexible processor substrate can be bent around an edge of the stiffener to electrically couple to the sensor substrate | 2013-08-29 |
20130221469 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package including a semiconductor chip configured to include a connection terminal electrically connected to wirings for transferring signals. The semiconductor package may include a semiconductor supporting substrate configured to be bonded to the semiconductor chip and include a through-silicon via which allows the connection terminal to be opened. The connection terminal may be formed on a scribe line of a semiconductor wafer and a conductive material contacting the connection terminal may filled in the through-silicon via. | 2013-08-29 |
20130221470 | MULTI-CHIP PACKAGE FOR IMAGING SYSTEMS - A multi-chip package may include an image sensor chip, an image signal processor (ISP) chip, a cover glass, and a package substrate. The ISP chip may be placed on the substrate. The image sensor chip may be placed over the ISP chip. An adhesive film may be formed between the ISP and image sensor chips. A cover glass may be suspended above the image sensor chip. The ISP chip and the image sensor chip may be wire bonded to the substrate. The multi-chip package may be hermetically sealed using a liquid compound or a dam structure. During normal operation, the ISP chip sends control signals to the image sensor chip via a first set of wire bond members and conductive traces in the substrate while the image sensor chip sends output signals to the ISP chip via a second set of wire bond terminals and conductive traces in the substrate. | 2013-08-29 |
20130221471 | BACKSIDE ILLUMINATED IMAGE-SENSOR AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a backside-illuminated image sensor may include forming an insulating layer having a predetermined depth in an inactive region of a front side of a semiconductor substrate and forming a photodetector in an active region of a front side of the semiconductor substrate having the insulating layer. Further, the method may include stacking a support substrate on and/or over the front side of the semiconductor substrate having the photodetector. Furthermore, the method may include performing back grinding on the rear side of the semiconductor substrate by using the insulating layer as the stop point. | 2013-08-29 |
20130221472 | RANGE SENSOR AND RANGE IMAGE SENSOR - A signal charge collecting region is disposed inside a charge generating region so as to be surrounded by the charge generating region, and collects signal charges from the charge generating region. An unnecessary charge collecting region is disposed outside the charge generating region so as to surround the charge generating region, and collects unnecessary charges from the charge generating region. A transfer electrode is disposed between the signal charge collecting region and the charge generating region, and causes the signal charges from the charge generating region to flow into the signal charge collecting region in response to an input signal. An unnecessary charge collecting gate electrode is disposed between the unnecessary charge collecting region and the charge generating region, and causes the unnecessary charges from the charge generating region to flow into the unnecessary charge collecting region in response to an input signal. | 2013-08-29 |
20130221473 | PHOTOELECTRIC CONVERSION DEVICE, IMAGE PICKUP SYSTEM AND METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate. | 2013-08-29 |
20130221474 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - According to one embodiment, an image sensor includes an image-sensing element region formed by arranging a plurality of image-sensing elements on a semiconductor substrate, and a logic circuit region formed in a region different from the image-sensing element region on the substrate and including a plurality of gate patterns. Further, dummy gate patterns are formed with a constant pitch on the image-sensing element region. | 2013-08-29 |
20130221475 | SEMICONDUCTOR CERAMIC AND RESISTIVE ELEMENT - Provided is a resistive element which has excellent inrush current resistance, and can suppress heat generation in a steady state. The resistive element has an element main body of a semiconductor ceramic in which the main constituent has a structure of R1 | 2013-08-29 |
20130221476 | DEVICES AND METHODS RELATED TO ELECTROSTATIC DISCHARGE PROTECTION BENIGN TO RADIO-FREQUENCY OPERATION - Disclosed are systems, devices and methods for providing electrostatic discharge (ESD) protection for integrated circuits. In some implementations, first and second conductors with ohmic contacts on an intrinsic semiconductor region can function similar to an x-i-y type diode, where each of x and y can be n-type or p-type. Such a diode can be configured to turn on under selected conditions such as an ESD event. Such a structure can be configured so as to provide an effective ESD protection while providing little or substantially nil effect on radio-frequency (RF) operating properties of a device. | 2013-08-29 |
20130221477 | SEMICONDUCTOR DEVICE - A semiconductor device that can achieve a high-speed operation at a time of switching, and the like. The semiconductor device includes: a p-type buried layer buried within an n | 2013-08-29 |
20130221478 | METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY EMPLOYING A SPIN-ON GLASS MATERIAL OR A FLOWABLE OXIDE MATERIAL - Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices using a spin-on glass material or a flowable oxide material. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure comprised of an insulating material in at least the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench. | 2013-08-29 |
20130221479 | CMOS STRUCTURE AND METHOD OF MANUFACTURE - CMOS structures with a replacement substrate and methods of manufacture are disclosed herein. The method includes forming a device on a temporary substrate. The method further includes removing the temporary substrate. The method further includes bonding a permanent electrically insulative substrate to the device with a bonding structure. | 2013-08-29 |
20130221480 | Semiconductor Devices and Methods of Manufacture Thereof - Methods of fabricating semiconductor devices and structures thereof are disclosed. In a preferred embodiment, a method of fabricating a semiconductor device includes providing a workpiece having a plurality of trenches formed therein, forming a liner over the workpiece, and forming a layer of photosensitive material over the liner. The layer of photosensitive material is removed from over the workpiece except from over at least a portion of each of the plurality of trenches. The layer of photosensitive material is partially removed from over the workpiece, leaving a portion of the layer of photosensitive material remaining within a lower portion of the plurality of trenches over the liner. | 2013-08-29 |