35th week of 2014 patent applcation highlights part 18 |
Patent application number | Title | Published |
20140239397 | JLT (JUNCTION-LESS TRANSISTOR) DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a junction-less transistor device that includes a substrate, a buried dielectric layer having a fin structure on the substrate, a doped region formed through the buried dielectric layer in the substrate, a semiconductor layer overlying the buried dielectric layer and the doped region, a gate structure on the semiconductor layer, and source/drain regions in the semiconductor layer at opposite sides of the gate structure. The semiconductor layer includes first, second, third regions, with the second region interposed between the first and second regions and disposed underneath the gate electrode structure. The first, second, and third regions have a same doping polarity. The second region has a doping concentration less than those of the first and second regions. The second region and the doped region have opposite doping polarities. The second region has a groove in contact with a bottom portion of the gate structure. | 2014-08-28 |
20140239398 | U-SHAPED SEMICONDUCTOR STRUCTURE - A method for forming a U-shaped semiconductor device includes forming trenches in a crystalline layer and epitaxially growing a U-shaped semiconductor material along sidewalls and bottoms of the trenches. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. The U-shaped semiconductor material is supported by backfilling underneath the U-shaped semiconductor material with a dielectric material. A semiconductor device is formed with the U-shaped semiconductor material. | 2014-08-28 |
20140239399 | SEMICONDUCTOR DEVICE HAVING COMPRESSIVELY STRAINED CHANNEL REGION AND METHOD OF MAKING SAME - A semiconductor device and method making it utilize a three-dimensional channel region comprising a core of a first semiconductor material and an epitaxial covering of a second semiconductor material. The first and second semiconductor materials have respectively different lattice constants, thereby to create a strain in the epitaxial covering. The devices are formed by a gate-last process, so that the second semiconductor material is deposited only after the high temperature processes have been performed. Consequently, the lattice strain is not substantially relaxed, and the improved performance benefits of the lattice strained channel region are not compromised. | 2014-08-28 |
20140239400 | STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS - Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device. | 2014-08-28 |
20140239401 | SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION - A FinFET structure which includes: silicon fins on a semiconductor substrate, each silicon fin having two sides and a horizontal surface; a gate wrapping around at least one of the silicon fins, the gate having a first surface and an opposing second surface facing the at least one of the silicon fins; a hard mask on a top surface of the gate; a silicon nitride layer formed in each of the first and second surfaces so as to be below and in direct contact with the hard mask on the top surface of the gate; spacers on the gate and in contact with the silicon nitride layer; and epitaxially deposited silicon on the at least one of the silicon fins so as to form a raised source/drain. | 2014-08-28 |
20140239402 | FinFETs with Strained Well Regions - A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band. | 2014-08-28 |
20140239403 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first gate formed on a substrate, the first gate having a square shape. A first junction and a second junction are formed in the substrate at two opposite sides of the first gate. A third junction is formed in the substrate at one of the other two opposite sides of the first gate. | 2014-08-28 |
20140239404 | FInFET Structure and Method for Forming the Same - A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins protruding over a substrate, wherein two adjacent first fins are separated from each other by a plurality of first isolation regions and two adjacent second fins are separated from each other by a plurality of second isolation regions. The method further comprises applying a first ion implantation process to the first isolation region, wherein dopants with a first polarity type are implanted in the first isolation region, applying a second ion implantation process to the second isolation region, wherein dopants with a second polarity type are implanted in the second isolation region and recessing the first isolation regions and the second isolation regions through an etching process. | 2014-08-28 |
20140239405 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A semiconductor device using a high-k dielectric film is provided. The semiconductor device comprises a first gate insulating layer on a substrate and a first barrier layer on the first gate insulating layer, the first barrier layer having a first thickness. A first work function control layer is on the first barrier layer. A second barrier layer is present on the first work function control layer, the second barrier layer having a second thickness that is less than the first thickness. | 2014-08-28 |
20140239406 | SEMICONDUCTOR DEVICE - A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch. | 2014-08-28 |
20140239407 | REPLACEMENT METAL GATE TRANSISTOR WITH CONTROLLED THRESHOLD VOLTAGE - A method and structure for a semiconductor device includes a semiconductor substrate and an N-channel transistor and a P-channel transistor provided on the semiconductor substrate. Each of the N-channel transistor and the P-channel transistor has a gate dielectric film on the semiconductor substrate, and a gate electrode is formed on the gate dielectric. The gate electrode comprises a metal conductive layer. The oxygen concentration in the metal conductive layer for the N-channel transistor is different from that for the P-channel transistor. | 2014-08-28 |
20140239408 | SEMICONDUCTOR CHIP INCLUDING REGION HAVING CROSS-COUPLED TRANSISTOR CONFIGURATION WITH OFFSET ELECTRICAL CONNECTION AREAS ON GATE ELECTRODE FORMING CONDUCTIVE STRUCTURES AND AT LEAST TWO DIFFERENT INNER EXTENSION DISTANCES OF GATE ELECTRODE FORMING CONDUCTIVE STRUC - A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a second transistor of the first transistor type. A fourth LCS forms a GE of a second transistor of the second transistor type. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. The electrical connection areas of the first and third LCS's are offset from each other. The GE of the first transistor of the first transistor type is electrically connected to the GE of the second transistor of the second transistor type. The GE of the second transistor of the first transistor type is electrically connected to the GE of the first transistor of the second transistor type. | 2014-08-28 |
20140239409 | NON-VOLATILE ANTI-FUSE WITH CONSISTENT RUPTURE - In an embodiment of the invention, a non-volatile anti-fuse memory cell is disclosed. The memory cell consists of a programmable n-channel diode-connectable transistor. The poly-silicon gate of the transistor has two portions. One portion is doped more highly than a second portion. The transistor also has a source with two portions where one portion of the source is doped more highly than a second portion. The portion of the gate that is physically closer to the source is more lightly doped than the other portion of the poly-silicon gate. The portion of the source that is physically closer to the lightly doped portion of the poly-silicone gate is lightly doped with respect to the other portion of the source. When the transistor is programmed, a rupture in the insulator will most likely occur in the portion of the poly-silicone gate that is heavily doped. | 2014-08-28 |
20140239410 | Integrated Circuit with Standard Cells - A die includes a plurality of rows of standard cells. Each of all standard cells in the plurality of rows of standard cells includes a transistor and a source edge, wherein a source region of the transistor is adjacent to the source edge. No drain region of any transistor in the each of all standard cells is adjacent to the source region. | 2014-08-28 |
20140239411 | Through Vias and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor chip includes a device region disposed in or over a substrate, a doped region disposed in the device region, and a through via disposed in the substrate. The through via extends through the doped region. | 2014-08-28 |
20140239412 | Channel Doping Extension beyond Cell Boundaries - An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration. | 2014-08-28 |
20140239413 | POWER ELECTRONIC DEVICE - A device includes a first and second transistors integrated in first and second chips. Each chip has opposed rear and front surfaces, and further has a first conduction terminal and a control terminal on the front surface and a second conduction terminal on the rear surface. The first and second transistors are electrically connected in series by having the first conduction terminals of the first and second transistors be electrically connected. The device includes a common package enclosing the first and second chips, the common package having an insulating body with a mounting surface. A heat sink is also enclosed within the insulating body, the heat sink making electrical contact with the first conduction terminals of the first and second chips on the respective front surfaces, so that the first conduction terminals are electrically connected together through the heat sink. | 2014-08-28 |
20140239414 | FinFETs and the Methods for Forming the Same - A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A middle portion of each of the two edge fins is etched, and the center fin is not etched. A gate dielectric is formed on a top surface and sidewalls of the center fin. A gate electrode is formed over the gate dielectric. The end portions of the two edge fins and end portions of the center fin are recessed. An epitaxy is performed to form an epitaxy region, wherein an epitaxy material grown from spaces left by the end portions of the two edge fins are merged with an epitaxy material grown from a space left by the end portions of the center fin to form the epitaxy region. A source/drain region is formed in the epitaxy region. | 2014-08-28 |
20140239415 | STRESS MEMORIZATION IN RMG FINFETS - Transistors with memorized stress and methods for making such transistors. The methods include forming a transistor structure having a channel region, a source and drain region, and a gate dielectric; depositing a stressor over the channel region of the transistor structure, wherein the stressor provides a stress to the channel region; removing the stressor metal after the stress is memorized within the channel region; and depositing a work function metal over the channel region of the transistor structure, where the work function metal applies less stress to the channel region than the stress applied by the stressor. A transistor with memorized stress includes a source and drain region on a substrate; a stress-memorized channel region on the substrate that retains an externally applied stress; and a gate structure including a work function gate metal that applies less stress to the stress-memorized channel region than the externally applied stress. | 2014-08-28 |
20140239416 | Semiconductor device - A semiconductor device includes a source/drain feature in a substrate. The source/drain feature has an upper portion and a lower portion, the upper portion having a lower concentration of Ge than the lower portion. A Si-containing layer over the source/drain feature includes a metal silicide layer. | 2014-08-28 |
20140239417 | Semiconductor Device Having Electrode and Manufacturing Method Thereof - The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an electrode. An exemplary structure for a semiconductor device comprises a semiconductor substrate; an electrode over the semiconductor substrate, wherein the electrode comprises a trench in an upper portion of the electrode; and a dielectric feature in the trench. | 2014-08-28 |
20140239418 | Semiconductor Dielectric Interface and Gate Stack - A semiconductor/dielectric interface having reduced interface trap density and a method of manufacturing the interface are disclosed. In an exemplary embodiment, the method comprises receiving a substrate, the substrate containing a semiconductor; preparing a surface of the substrate; forming a termination layer bonded to the semiconductor at the surface of the substrate; and depositing a dielectric layer above the termination layer, the depositing configured to not disrupt the termination layer. The forming of the termination layer may be configured to produce the termination layer having a single layer of oxygen atoms between the substrate and the dielectric layer. | 2014-08-28 |
20140239419 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially. | 2014-08-28 |
20140239420 | SILICON NITRIDE GATE ENCAPSULATION BY IMPLANTATION - A method of forming a FinFET structure which includes forming fins on a semiconductor substrate; forming a gate wrapping around at least one of the fins, the gate having a first surface and an opposing second surface facing the fins; depositing a hard mask on a top of the gate; angle implanting nitrogen into the first and second surfaces of the gate so as to form a nitrogen-containing layer in the gate that is below and in direct contact with the hard mask on top of the gate; forming spacers on the gate and in contact with the nitrogen-containing layer; and epitaxially depositing silicon on the at least one fin so as to form a raised source/drain. Also disclosed is a FinFET structure. | 2014-08-28 |
20140239421 | SURFACE CHARGE MITIGATION LAYER FOR MEMS SENSORS - A semiconductor device includes a substrate. At least one transducer is provided on the substrate. The at least one transducer includes at least one electrically conductive circuit element. A dielectric layer is deposited onto the substrate over the at least one transducer. A surface charge mitigation layer formed of a conductive material is deposited onto the outer surface of the dielectric layer with the surface charge mitigation layer being electrically coupled to ground potential. The surface charge mitigation layer may be deposited to a thickness of 10 nm or less, and the transducer may comprise a microelectromechanical systems (MEMS) device, such as a MEMS pressure sensor. The surface charge mitigation layer may be patterned to include pores to enhance the flexibility as well as the optical properties of the mitigation layer. | 2014-08-28 |
20140239422 | ELECTRONIC DEVICE, PACKAGE, ELECTRONIC APPARATUS, AND MOVING OBJECT - A physical quantity sensor includes an IC chip and a package base mounted with the IC chip. The package base includes a first wiring layer provided with bonding pads connected to the IC chip via a bonding wire, a second wiring layer overlapping the first wiring layer in plan view, and an insulating layer provided between the first wiring layer and the second wiring layer. A contour of a wiring pattern provided on the second wiring layer (of the second wiring layer) is arranged in a position not overlapping the bonding pads in plan view. | 2014-08-28 |
20140239423 | MICROELECTROMECHANICAL SYSTEM DEVICES HAVING THROUGH SUBSTRATE VIAS AND METHODS FOR THE FABRICATION THEREOF - Methods for the fabrication of a Microelectromechanical Systems (“MEMS”) devices are provided. In one embodiment, the MEMS device fabrication method forming a via opening extending through a sacrificial layer and into a substrate over which the sacrificial layer has been formed. A body of electrically-conductive material is deposited over the sacrificial layer and into the via opening to produce an unpatterned transducer layer and a filled via in ohmic contact with the unpatterned transducer layer. The unpatterned transducer layer is then patterned to define, at least in part, a primary transducer structure. At least a portion of the sacrificial layer is removed to release at least one movable component of the primary transducer structure. A backside conductor, such as a bond pad, is then produced over a bottom surface of the substrate and electrically coupled to the filled via. | 2014-08-28 |
20140239424 | CAP BONDING STRUCTURE AND METHOD FOR BACKSIDE ABSOLUTE PRESSURE SENSORS - A pressure sensor includes a pressure sensing element having a diaphragm, a cavity, and bridge circuitry connected to the diaphragm. A top surface is formed as part of the pressure sensing element such that at least a portion of the top surface is part of the diaphragm, and the plurality of piezoresistors are located on the top surface. A cap is bonded to the top surface through the use of a plurality of layers. One of the layers is a silicon dioxide layer, another layer is a silicon nitride layer, another layer is an oxide layer, and another of the layers is a polysilicon layer. The plurality of layers provides proper bonding between the cap and the top surface of the pressure sensing element. | 2014-08-28 |
20140239425 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, a side surface arranged between the first main surface and the second main surface, and a magnetic storage device, a first magnetic shield overlaying on the first main surface, a second magnetic shield overlaying on the second main surface, and a third magnetic shield overlaying on the side surface. The first and second magnetic shields are mechanically connected via the third magnetic shield. | 2014-08-28 |
20140239426 | CURRENT SENSORS AND METHODS - Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a leadframe; a semiconductor die coupled to the leadframe; a conductor comprising a metal layer on the semiconductor die, the conductor comprising at least one bridge portion and at least two slots, a first slot having a first tip and a second slot having a second tip, a distance between the first and second tips defining a width of one of the at least one bridge portion, wherein the conductor is separated from the leadframe by at least a thickness of the semiconductor die, and the thickness is about 0.2 millimeters (mm) to about 0.7 mm; and at least one magnetic sensor element arranged on the die relative to and spaced apart from the one of the at least one bridge portion and more proximate the conductor than the leadframe. | 2014-08-28 |
20140239427 | Integrated Antenna on Interposer Substrate - Some embodiments relate to a semiconductor module comprising a low-cost integrated antenna that uses a conductive backside structure in conjunction with a ground metal layer to form a large ground plane with a small silicon area. In some embodiments, the integrated antenna structure has an excitable element that radiates electromagnetic radiation. An on-chip ground plane, located on a first side of an interposer substrate, is positioned below the excitable element. A compensation ground plane, located on an opposing side of the interposer substrate, is connected to the ground plane by one or more through-silicon vias (TSVs) that extend through the interposer substrate. The on-chip ground plane and the compensation ground collectively act to reflect the electromagnetic radiation generated by the excitable element, so that the compensation ground improves the performance of the on-chip ground plane. | 2014-08-28 |
20140239428 | CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - According to various embodiments, a chip arrangement may be provided, the chip arrangement including: a chip; an antenna structure disposed over a first side of the chip, wherein the antenna structure may include an antenna being electrically conductively coupled to the chip; and a reinforcement structure, wherein the reinforcement structure supports the chip to increase the stability of the chip arrangement. | 2014-08-28 |
20140239429 | RADIATION DETECTOR - A radiation detector has a semiconductor substrate of a first conductivity type, a plurality of semiconductor regions of a second conductivity type making junctions with the semiconductor substrate, and a plurality of electrodes joined to the corresponding semiconductor regions. The electrodes cover the corresponding semiconductor regions, when viewed from a direction perpendicular to a first principal face. The semiconductor regions include a plurality of first and second semiconductor regions in a two-dimensionally array. The first semiconductor regions arrayed in a first direction in the two dimensional array out of the plurality of first semiconductor regions are electrically connected to each other, and the second semiconductor regions arrayed in a second direction intersecting with the first direction out of the plurality of second semiconductor regions are electrically connected to each other. | 2014-08-28 |
20140239430 | SOLID-STATE IMAGING DEVICE - According to one embodiment, a photoelectric converting layer, a charge accumulating layer, and a light collecting unit are provided. The photoelectric converting layer is formed at a back surface side of a semiconductor substrate. The charge accumulating layer is formed at a front surface side of the semiconductor substrate, and accumulates charges photoelectric-converted by the photoelectric converting layer. The light collecting unit makes light incident to the back surface side of the semiconductor substrate to be collected on the photoelectric converting layer not to be incident to the charge accumulating layer. | 2014-08-28 |
20140239431 | IMAGE SENSOR AND COMPUTING SYSTEM HAVING THE SAME - An image sensor includes a light receiving element, an anti-reflection layer, a high refractive pattern, a color filter, and a micro lens. The light receiving element is formed on a semiconductor substrate to generate charges responsive to incident light. The anti-reflection layer is formed on the semiconductor substrate. The high refractive pattern is formed on the anti-reflection layer in correspondence with the light receiving element. The color filter is formed on the anti-reflection layer while covering a top surface and lateral sides of the high refractive pattern. The micro lens is formed on the color filter. The image sensor provides an image having high quality. | 2014-08-28 |
20140239432 | ENERGY CONVERSION AND STORAGE DEVICE AND MOBILE ELECTRONIC DEVICE CONTAINING SAME - An energy conversion and storage device includes an energy storage component ( | 2014-08-28 |
20140239433 | SOLID-STATE IMAGE SENSOR AND ELECTRONIC DEVICE - There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers. | 2014-08-28 |
20140239434 | SEMICONDUCTOR PACKAGE - According to example embodiments, a semiconductor package may include a first package substrate, a first semiconductor chip on the first package substrate, and a thermistor array film on the first semiconductor chip. The thermistor array film may include a variable resistive film that covers the first semiconductor chip, and an array of electrode patterns that are connected to the variable resistive film. The array of electrode patterns may be connected to at least one of the upper and lower surfaces of the variable resistive film. | 2014-08-28 |
20140239435 | SUPER-JUNCTION SCHOTTKY PIN DIODE - A semiconductor chip has an n | 2014-08-28 |
20140239436 | HIGH VOLTAGE FAST RECOVERY TRENCH DIODE - Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2014-08-28 |
20140239437 | SEMICONDUCTOR DEVICE - According to one embodiment, the semiconductor device with element isolation by DTI has a layer of the first electroconductive type formed on a substrate. The semiconductor layer of the second electroconductive type is formed on the embedding layer. The first DTI has the following structure: a trench is formed from the surface of the semiconductor layer through the first layer into the substrate and surrounds the semiconductor layer, and an insulator is formed in the trench. The second DTI is formed around the periphery of the semiconductor layer. The first electrode is connected to the first region of the semiconductor layer divided by the first DTI. The second electrode is connected to the second region of the semiconductor layer divided as mentioned previously. The first region and the second region form electrode plates and the first DTI forms the dielectric, to thereby form a capacitor. | 2014-08-28 |
20140239438 | SEMICONDUCTOR DEVICE - A number of semiconductor chips each include a first main face and a second main face opposite to the first main face. A first encapsulation layer is applied over the second main faces of the semiconductor chips. An electrical wiring layer is applied over the first main faces of the first semiconductor chips. A second encapsulation layer is applied over the electrical wiring layer. The thickness of the first encapsulation layer and the thicknesses of the first semiconductor chips is reduced. The structure can be singulated to obtain a plurality of semiconductor devices. | 2014-08-28 |
20140239439 | ELECTRICAL FUSES AND METHODS OF MAKING ELECTRICAL FUSES - A fuse, a method of making the fuse and a circuit containing the fuse. The fuse includes an electrically conductive and conformal liner on sidewalls and the bottom of a trench; a copper layer on the conformal liner, a first thickness of the copper layer over the bottom of the trench in a lower portion of the trench greater than a second thickness of the copper layer over the sidewalls of the trench in an abutting upper portion of the trench; and a dielectric material on the copper layer in the trench, the dielectric material filling remaining space in the upper portion of said trench. | 2014-08-28 |
20140239440 | Thin Beam Deposited Fuse - A back-end-of-line thin ion beam deposited fuse ( | 2014-08-28 |
20140239441 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device, includes: a first semiconductor layer having a first conductivity type; a pair of first electrodes arranged to be separated from each other in the first semiconductor layer; a second electrode provided on the first semiconductor layer between the pair of first electrodes with a dielectric film in between; and a pair of connection sections electrically connected to the pair of first electrodes, wherein one or both of the pair of first electrodes are divided into a first region and a second region, the first region and the second region being connected by a bridge section. | 2014-08-28 |
20140239442 | ELECTROLESS PLATED MATERIAL FORMED DIRECTLY ON METAL - A method for forming magnetic conductors includes forming a metal structure on a substrate. Plating surfaces are prepared on the metal structure for electroless plating by at least one of: masking surfaces of the metal structure to prevent electroless plating on masked surfaces and/or activating a surface of the metal structure. Magnetic material is electrolessly plated directly on the plating surfaces to form a metal and magnetic material structure. | 2014-08-28 |
20140239443 | ELECTROLESS PLATED MATERIAL FORMED DIRECTLY ON METAL - A method for forming magnetic conductors includes forming a metal structure on a substrate. Plating surfaces are prepared on the metal structure for electroless plating by at least one of: masking surfaces of the metal structure to prevent electroless plating on masked surfaces and/or activating a surface of the metal structure. Magnetic material is electrolessly plated directly on the plating surfaces to form a metal and magnetic material structure. | 2014-08-28 |
20140239444 | BURIED TSV'S USED FOR DECAPS - An interposer having decaps formed in blind-vias, a packaged semiconductor structure having decaps formed in blind-vias, and methods for forming the same are provided. In one embodiment, an interposer is provided that includes an interconnect layer disposed on a substrate. A plurality of through-vias are formed through the substrate in an isolated region of the substrate. At least one of the plurality of conductive vias are electrically coupled to at least one of a plurality of top wires formed in the interconnect layer. A plurality of blind-vias are formed through the substrate in a dense region of the substrate during a common etching step with the through-vias. At least one blind-via includes (a) a dielectric material lining the blind-vias, and (b) a conductive material filling the lined blind-vias and forming a decoupling capacitor. | 2014-08-28 |
20140239445 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line. | 2014-08-28 |
20140239446 | FRACTAL STRUCTURES FOR FIXED MEMS CAPACITORS - An embodiment of a fractal fixed capacitor comprises a capacitor body in a microelectromechanical system (MEMS) structure. The capacitor body has a first plate with a fractal shape separated by a horizontal distance from a second plate with a fractal shape. The first plate and the second plate are within the same plane. Such a fractal fixed capacitor further comprises a substrate above which the capacitor body is positioned. | 2014-08-28 |
20140239447 | METHODS AND APPARATUS RELATED TO CAPACITANCE REDUCTION OF A SIGNAL PORT - In one general aspect, an apparatus includes a first capacitor defined by a dielectric disposed between a bump metal and a region of a first conductivity type, and a second capacitor in series with the first capacitor and defined by a PN junction including the region of the first conductivity type and a region of a second conductivity type. The region of the first conductivity type can be configured to be coupled to a first node having a first voltage, and the region of the second conductivity type can be configured to be coupled to a second node having a second voltage different than the first voltage. | 2014-08-28 |
20140239448 | INTERDIGITATED CAPACITORS WITH A ZERO QUADRATIC VOLTAGE COEFFICIENT OF CAPACITANCE OR ZERO LINEAR TEMPERATURE COEFFICIENT OF CAPACITANCE - Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (T | 2014-08-28 |
20140239449 | THREE PRECISION RESISTORS OF DIFFERENT SHEET RESISTANCE AT SAME LEVEL - An integrated circuit contains three thin film resistors over a dielectric layer. The first resistor body includes only a bottom thin film layer and the first resistor heads include the bottom thin film layer, a middle thin film layer and a top thin film layer. The second resistor body and heads include all three thin film layers. The third resistor body does not include the middle thin film layer. The three resistors are formed using two etch masks. | 2014-08-28 |
20140239450 | GUARD STRUCTURE FOR SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING GUARD LAYOUT PATTERN FOR SEMICONDUCTOR LAYOUT PATTERN - A guard structure for a semiconductor structure is provided. The guard structure includes a first guard ring, a second guard ring and a third guard ring. The first guard ring has a first conductivity type. The second guard ring has a second conductivity type, and surrounds the first guard ring. The third guard ring has the first conductivity type, and surrounds the second guard ring, wherein the first, the second and the third guard rings are grounded. A method of forming a guard layout pattern for a semiconductor layout pattern is also provided. | 2014-08-28 |
20140239451 | Semiconductor Devices Including A Lateral Bipolar Structure And Fabrication Methods - A semiconductor device includes an emitter region, a collector region and a base region. The emitter region is implanted in a semiconductor substrate. The collector region is implanted in the semiconductor substrate. The base region is disposed between the emitter region and collector region. The base region includes no more than one LDD region and no more than one halo region. The base region contacts directly with at least one of the emitter region and the collector region. | 2014-08-28 |
20140239452 | SUBSTRATE FOR EPITAXIAL GROWTH, AND CRYSTAL LAMINATE STRUCTURE - Provided is a substrate for epitaxial growth, which enables the improvement in quality of a Ga-containing oxide layer that is formed on a β-Ga | 2014-08-28 |
20140239453 | MULTIPLE BONDING LAYERS FOR THIN-WAFER HANDLING - Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side. | 2014-08-28 |
20140239454 | WAFER EDGE PROTECTION - A semiconductor device and a method for forming a device are presented. A wafer substrate having first and second regions is provided. The second region includes an inner region of the substrate while the first region includes an outer peripheral region from an edge of the substrate towards the inner region. A protection unit is provided above the substrate. The protection unit includes a region having a total width W | 2014-08-28 |
20140239455 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR WAFER - To improve reliability of a semiconductor device obtained through a dicing step. | 2014-08-28 |
20140239456 | SEMICONDUCTOR WAFER AND ITS MANUFACTURE METHOD, AND SEMICONDUCTOR CHIP - A semiconductor wafer includes: a first semiconductor chip area formed with a semiconductor element; a second semiconductor chip area formed with a semiconductor element; and a scribe area sandwiched between said first and second semiconductor chip areas; wherein: the first semiconductor chip area includes a first metal ring surrounding the semiconductor element formed in the first semiconductor chip area; and the metal ring is constituted of a plurality of metal layers including an lower metal layer and an upper metal layer superposed upon the lower metal layer, and the upper metal layer is superposed upon the lower metal layer in such a manner that an outer side wall of the upper metal layer is flush with the outer side wall of the lower metal layer or is at an inner position of said first semiconductor chip area relative to said outer side wall of the lower metal layer. | 2014-08-28 |
20140239457 | THERMAL VIA FOR 3D INTEGRATED CIRCUITS STRUCTURES - A three dimensional integrated circuit (3D-IC) structure, method of manufacturing the same and design structure thereof are provided. The 3D-IC structure includes two chips having a dielectric layer, through substrate vias (TSVs) and pads formed on the dielectric layer. The dielectric layer is formed on a bottom surface of each chip. Pads are electrically connected to the corresponding TSVs. The chips are disposed vertically adjacent to each other. The bottom surface of a second chip faces the bottom surface of a first chip. The pads of the first chip are electrically connected to the pads of the second chip through a plurality of conductive bumps. The 3D-IC structure further includes a thermal via structure vertically disposed between the first chip and the second chip and laterally disposed between the corresponding conductive bumps. The thermal via structure has an upper portion and a lower portion. | 2014-08-28 |
20140239458 | BONDED STRUCTURE WITH ENHANCED ADHESION STRENGTH - A first bonding material layer is formed on a first substrate and a second bonding material layer is formed on a second substrate. The first and second bonding material layers include a metal. Ions are implanted into the first and second bonding material layers to induce structural damages in the in the first and second bonding material layers. The first and second substrates are bonded by forming a physical contact between the first and second bonding material layers. The structural damages in the first and second bonding material layers enhance diffusion of materials across the interface between the first and second bonding material layers to form a bonded material layer in which metal grains are present across the bonding interface, thereby providing a high adhesion strength across the first and second substrates. | 2014-08-28 |
20140239459 | METHOD FOR PRODUCING MECHANICALLY FLEXIBLE SILICON SUBSTRATE - A method for making a mechanically flexible silicon substrate is disclosed. In one embodiment, the method includes providing a silicon substrate. The method further includes forming a first etch stop layer in the silicon substrate and forming a second etch stop layer in the silicon substrate. The method also includes forming one or more trenches over the first etch stop layer and the second etch stop layer. The method further includes removing the silicon substrate between the first etch stop layer and the second etch stop layer. | 2014-08-28 |
20140239460 | Semiconductor Device Having an Insulating Layer Structure and Method of Manufacturing the Same - In a semiconductor device having an insulating layer structure and method of manufacturing the same, a substrate including a first region and a second region may be provided. A first pattern structure may be formed on the first region of the substrate. A second pattern structure may be formed on the second region of the substrate, and have a height that is greater than the height of the first pattern structure. An insulating layer structure is formed on the first and second pattern structures and includes a protrusion near an area at which the first and second regions meet each other. An upper surface of the insulating interlayer structure is higher than a top surface of the second pattern structure. The protrusion may have at least one side surface having a staircase shape. A planarized insulating interlayer may be formed without substantial damage to the infrastructure by using the insulating layer structure in accordance with example embodiments. | 2014-08-28 |
20140239461 | Oxygen Monolayer on a Semiconductor - A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si | 2014-08-28 |
20140239462 | PECVD FILMS FOR EUV LITHOGRAPHY - Provided herein are multi-layer stacks for use in extreme ultraviolet lithography tailored to achieve optimum etch contrast to shrink features and smooth the edges of features while enabling use of an optical leveling sensor with little or reduced error. The multi-layer stacks may include an atomically smooth layer with an average local roughness of less than a monolayer, and one or more underlayers, which may be between a target layer to be patterned and a photoresist. Also provided are methods of depositing multi-layer stacks for use in extreme ultraviolet lithography. | 2014-08-28 |
20140239463 | EMBEDDED CHIP PACKAGE STRUCTURE - An embedded chip package structure including a core layer, a chip, a first circuit layer and a second circuit layer is provided. The core layer includes a first surface, a second surface opposite to each other and a chip container passing through the first surface and the second surface. The chip is disposed in the chip container. The chip includes an active surface and a protrusion and a top surface of the protrusion is a part of the active surface. The first circuit layer is disposed on the first surface and electrically connected to the core layer and the chip. The first circuit layer has a through hole. The protrusion of the chip is situated within the through hole, and the top surface of the protrusion is exposed to receive an external signal. The second circuit layer is disposed on the second surface and electrically connected to the core layer. | 2014-08-28 |
20140239464 | SEMICONDUCTOR PACKAGES WITH THERMAL-ENHANCED CONFORMAL SHIELDING AND RELATED METHODS - The semiconductor package includes a substrate, a die, a first metal layer, a second metal layer and an optional seed layer. The package body at least partially encapsulates the die on the substrate. The seed layer is disposed on the package body and the first metal layer is disposed on the seed layer. The second metal layer is disposed on the first metal layer and the lateral surface of the substrate. The first metal layer and the second metal layer form an outer metal cap that provides thermal dissipation and electromagnetic interference (EMI) shielding. | 2014-08-28 |
20140239465 | SEMICONDUCTOR PACKAGE HAVING A WAVEGUIDE ANTENNA AND MANUFACTURING METHOD THEREOF - A semiconductor package comprises a substrate, a grounding layer, a encapsulant, a shielding layer, and a conductive element. The substrate includes a chip. The encapsulant encapsulates the grounding layer and the chip, wherein the encapsulant has an upper surface. The shielding layer is formed on the upper surface of the encapsulant. The conductive element surrounds a waveguide cavity and extends to the grounding layer. The grounding layer, the shielding layer and the conductive element together form a waveguide antenna. | 2014-08-28 |
20140239466 | Electronic Device - An electronic device includes a first transistor device with first contact elements, a second transistor device with second contact elements, and an electrical connection member with a first main face and a second main face opposite to the first main face. The first transistor device is disposed on the first main face of the electrical connection member and the second transistor device is disposed on the second main face of the electrical connection member. One of the first contact elements is electrically connected with one of the second contact elements by a part of the electrical connection member. | 2014-08-28 |
20140239467 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lead frame, a semiconductor chip soldered to the lead frame, and a metal bar. The metal bar is arranged inside a solder layer so as to extend along one side of the semiconductor chip. When viewed in a stacking direction of the lead frame and the semiconductor chip, the metal bar is arranged so that a part of the metal bar overlaps the semiconductor chip, and the rest of the metal bar does not overlap the semiconductor chip. Then, in a section of the metal bar in a plane perpendicular to a longitudinal direction of the metal bar, an outline of the metal bar on a side of a center of the semiconductor chip is curved so as to project on the side of the center of the semiconductor chip. | 2014-08-28 |
20140239468 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a plate electrode adapted to a plurality of chips, capable of being produced at low cost, and having high heat cycle property. A semiconductor device according to the present invention includes a plurality of semiconductor chips formed on a substrate, and a plate electrode connecting electrodes of the plurality of semiconductor chips. The plate electrode has half-cut portions formed by half-pressing and the raised sides of the half-cut portions are bonded with the electrodes of the semiconductor chips. | 2014-08-28 |
20140239469 | INFORMATION ENCODING USING WIREBONDS - A method and structure for encoding information on an integrated circuit chip. The method includes selecting a set of chip pads of the integrated circuit chip for encoding the information; encoding the information during a wirebonding process, the wirebonding process comprising forming ball bonds on chip pads of the integrated circuit chip and wedge bonds on leadframe fingers adjacent to one or more edges of the integrated circuit chip, the ball bonds and the wedge bonds connected by respective and integral wires; and wherein the information is encoded by varying one or more wirebonding parameters on each chip pad of the set of chip pads, the wirebonding parameters selected from the group consisting of the location of a ball bond, the diameter of a ball bond, both the location and diameter of a ball bond, the location of a wedge bond and combinations thereof. | 2014-08-28 |
20140239470 | RESIN PACKAGE - A resin package includes: a die pad having a main surface on which a semiconductor substrate and a matching circuit substrate is mounted; at least one lead terminal electrically connected to the semiconductor substrate and the matching circuit substrate; a thin plate fixed to at least one of the main surface of the die pad and a main surface of the at least one lead terminal; and molding resin which covers the semiconductor substrate, the matching circuit substrate, and the thin plate. | 2014-08-28 |
20140239471 | IC PACKAGE WITH STAINLESS STEEL LEADFRAME - Various aspects of the disclosure are directed to integrated circuit (IC) die leadframe packages. In accordance with one or more embodiments, a stainless steel leadframe apparatus has a polymer-based layer that adheres to both stainless steel and IC die encapsulation, with the stainless steel conducting signals/data between respective surfaces for communicating with the packaged IC die. In some embodiments, the apparatus includes the IC die adhered to the polymer-based layer via an adhesive, wire bonds coupled to the stainless steel leadframe for passing the signals/data, and an encapsulation epoxy that encapsulates the IC die and wire bonds. | 2014-08-28 |
20140239472 | DUAL-FLAG STACKED DIE PACKAGE - In one embodiment, a semiconductor package includes a first and a second die flag, wherein the first and second die flags are separated by a gap. First and second metal oxide semiconductor field effect transistor (MOSFET) die are on the first and the second die flags, respectively. A power control integrated circuit (IC) is stacked on top of at least one of the first or the second MOSFET die. A mold compound is encapsulating the power control IC, the first and second MOSFET die, and the first and second die flags. | 2014-08-28 |
20140239473 | WIRE BONDING ASSEMBLY AND METHOD - A method of wire bonding a die to a lead frame comprising mounting the die on a die attachment pad portion of a leadframe and supporting the leadframe on a support plate having a vacuum hole therein filled with porous material. | 2014-08-28 |
20140239474 | CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - In various embodiments a chip arrangement is provided, wherein the chip arrangement may include a chip and at least one foil attached to at least one side of the chip. | 2014-08-28 |
20140239475 | PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE AND FABRICATION METHODS THEREOF - A packaging substrate is disclosed, which includes: an encapsulant having opposite first and second surfaces; a plurality of conductive elements embedded in the encapsulant, wherein each of the conductive elements has a first conductive pad exposed from the first surface of the encapsulant and a second conductive pad exposed from the second surface of the encapsulant; and a protection layer formed on the second surface of the encapsulant and the second conductive pads so as to protect the second surface of the encapsulant from being scratched. | 2014-08-28 |
20140239476 | SEMICONDUCTOR DEVICE WITH INTEGRAL HEAT SINK - A packaged semiconductor device has opposing first and second main surfaces and a sidewall connecting the first and second main surfaces. A semiconductor die is embedded in the package and has a first main surface facing the first main surface of the package and an opposing second main surface facing the second main surface of the package. Conductive leads are electrically coupled to the semiconductor die, each of which is partially embedded within the package and extends outside of the package from the package sidewall. At least one tie bar is partially embedded within the package and has an exposed segment extending outside of the package from the sidewall. A portion of the exposed segment is in contact with the first main surface of the package. The tie bar forms a heat sink to dissipate heat generated by the semiconductor die. | 2014-08-28 |
20140239477 | SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME - A semiconductor package including a package substrate having a chip mounting region and a peripheral region and including a ground layer formed in the peripheral region, first solder balls on the package substrate in the chip mounting region, second solder balls on the ground layer, at least one semiconductor chip stacked on the package substrate in the chip mounting region, and a package cap covering the semiconductor chip and contacting the package substrate in the peripheral region may be provided. The package cap is electrically connected to the second solder balls. Methods of fabricating the semiconductor package are also provided. | 2014-08-28 |
20140239478 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink. | 2014-08-28 |
20140239479 | MICROELECTRONIC PACKAGE INCLUDING AN ENCAPSULATED HEAT SPREADER - A microelectronic package of the present description may include a microelectronic interposer having a first surface with an active surface of the at least one microelectronic device electrically attached to the microelectronic interposer first surface. A thermal interface material may be disposed on a back surface of the at least one microelectronic device. A heat spreader, having a first surface and an opposing second surface, may be in thermal contact by its first surface with the thermal interface material. A mold material may be disposed to encapsulate the microelectronic device, the thermal interface material, and the heat spreader, wherein the mold material abuts at least a portion of the microelectronic interposer first surface. | 2014-08-28 |
20140239480 | ELECTRONIC DEVICES ASSEMBLED WITH THERMALLY INSULATING LAYERS - Provided herein are electronic devices assembled with thermally insulating layers. | 2014-08-28 |
20140239481 | ELECTRONIC DEVICES ASSEMBLED WITH THERMALLY INSULATING LAYERS - Provided herein are electronic devices assembled with thermally insulating layers. | 2014-08-28 |
20140239482 | INTEGRATED HEAT SPREADER FOR MULTI-CHIP PACKAGES - An integrated heat spreader comprising a heat spreader frame that has a plurality of openings formed therethrough and a plurality of thermally conductive structures secured within the heat spreader frame openings. The thermally conductive structures can be formed to have various thicknesses which compensate for varying heights between at least two microelectronic devices in a multi-chip package. The thermally conductive structures can be secured in the heat spreader frame by sizing the openings and the thermally conductive structures such that the thermally conductive structures can be secured within the openings without requiring welding or adhesives. | 2014-08-28 |
20140239483 | HEAT SPREADING IN MOLDED SEMICONDUCTOR PACKAGES - A molded semiconductor package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, and one or more heat conductors in the molding compound that are thermally coupled to the substrate. Advantageously, the heat conductors are mounted in the molding compound near one or more of the corners of the die. The package may also include a lid. The heat conductors produce a more uniform distribution of heat in the substrate. The package is assembled by mounting the die on the substrate, mounting the heat conductors on the substrate and applying the molding compound to the substrate, the die, and the heat conductors mounted on the substrate. For packages that use a lid, the lid is then secured to the package and coupled to the heat conductors. | 2014-08-28 |
20140239484 | METHOD FOR FORMING SINTERED SILVER COATING FILM, BAKING APPARATUS, AND SEMICONDUCTOR DEVICE - In a method for forming a sintered silver coating film, for use as a heat spreader, on a semiconductor substrate or a semiconductor package, a coating film of an ink or paste containing silver nanoparticles is formed on one surface of the semiconductor substrate or the substrate package. Further, the coating film is sintered by heating the coating film under an atmosphere of a humidity of 30% to 50% RH (30° C.) by a ventilation oven. | 2014-08-28 |
20140239485 | WINDOW BALL GRID ARRAY (BGA) SEMICONDUCTOR PACKAGES - A semiconductor package includes a substrate having a first surface, a second surface that is opposite to the first surface, and an opening formed between the first surface of the substrate and the second surface of the substrate. One or more bonding wires electrically couple a first surface of a semiconductor die included in the semiconductor package to the first surface of the substrate through an opening of the substrate. A first electrically insulative structure is disposed to substantially fill an area between the first surface of the semiconductor die, the second surface of the substrate, and one or more interconnect bumps that electrically couple the semiconductor die to the substrate. The first electrically insulative structure substantially encapsulates the one or more bonding wires and substantially fills the opening of the substrate. | 2014-08-28 |
20140239486 | COOLING DEVICE FOR SEMICONDUCTOR MODULE, AND SEMICONDUCTOR MODULE - A cooling device for a semiconductor module supplying a coolant from outside into a water jacket and cooling a semiconductor element, includes a heat sink thermally connected to the semiconductor element; a first flow channel extending from a coolant introducing port and including a guide section having an inclined surface for guiding the coolant toward one side surface of the heat sink; a second flow channel disposed parallel to the first flow channel and extending toward a coolant discharge port; a flow velocity adjusting plate disposed in the second flow channel and formed parallel to the other side surface of the heat sink at a distance therefrom; and a third flow channel formed to communicate the first flow channel and the second flow channel. The heat sink is disposed in the third flow channel. | 2014-08-28 |
20140239487 | HEAT PIPE IN OVERMOLDED FLIP CHIP PACKAGE - The present invention is an improvement in a molded semiconductor package and the method for its manufacture. The package comprises a substrate, a semiconductor die mounted on the substrate, a molding compound encircling the die on the substrate, a lid on the molding compound, and a heat pipe extending between the semiconductor die and the lid. Preferably, the heat pipe is formed so that it encircles the die. The package is assembled by mounting the die on the substrate, applying the molding compound to the substrate while a channel is formed in the molding compound adjacent the semiconductor die, inserting a heat pipe material in the channel, and mounting the lid on the molding compound and the heat pipe material. | 2014-08-28 |
20140239488 | ELECTRONIC COMPONENT UNIT AND FIXING STRUCTURE - An electronic component unit includes a semiconductor package mounted on a front surface of a substrate, a heat sink including a pushing plate installed on the semiconductor package, a reinforcing plate disposed on a back surface of the substrate, and a plurality of fasteners that connect corner portions of the pushing plate and the reinforcing plate to each other, wherein the semiconductor package is pressed and fixed on the substrate by fastening the plurality of fasteners, and the reinforcing plate includes a base plate portion including a connection portion to which each of the plurality of fasteners is connected, and a pressing plate portion which is disposed at a planar central side of the base plate portion, and separably laminated on the base plate portion to press the back surface of the substrate. | 2014-08-28 |
20140239489 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, multiple terminals arranged in a first direction, a resin portion sealing the semiconductor chip and the terminals. The terminals are projected from a side surface of the resin portion in a second direction, and include at least one subject terminal having a first portion and a second portion. In the subject terminal, a first longitudinal end of the first portion is positioned inside of the resin portion and a second longitudinal end of the first portion is positioned outside of the resin portion, and the second portion is arranged adjacent to the first portion. Further, a length of the first portion is greater than a length of the second portion in the third direction, and a length of the first portion is smaller than a length of the second portion in the first direction. | 2014-08-28 |
20140239490 | PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF - A packaging substrate and a fabrication method thereof are disclosed. The packaging substrate includes: a substrate body having a plurality of first and second conductive pads formed on a surface thereof; a first insulating layer formed on the surface of the substrate body and having a plurality of first and second openings for respectively exposing the first and second conductive pads; a conductive layer formed on the first and second conductive pads and the first insulating layer around peripheries of the first and second conductive pads; a plurality of first and second conductive bumps formed on the conductive layer on the first and second conductive pads, respectively; a solder layer formed on the second conductive bumps; and a plurality of conductive posts formed on the first conductive bumps and having a width different from that of the first conductive bumps. The invention improves the fabrication efficiency. | 2014-08-28 |
20140239491 | MICROELECTRONIC UNIT AND PACKAGE WITH POSITIONAL REVERSAL - A semiconductor unit includes a chip having left and right columns of contacts at its front surface. Interconnect pads are provided overlying the front surface of the chip and connected to at least some of the contacts as, for example, by traces or by arrangements including wire bonds. The interconnect pads alone, or the interconnect pads and some of the contacts, provide an array of external connection elements. This array includes some reversal pairs of external connection elements in which the external connection element connected to or incorporating the right contact is disposed to the left of the external connection element incorporating or connected to the left contact. Such a unit may be used in a multi-chip. The reversed connections simplify routing, particularly where corresponding contacts of two chips are to be connected to common terminals on the package substrate. | 2014-08-28 |
20140239492 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes a first wiring substrate, a second wiring substrate positioned above the first wiring substrate, multiple connection terminals provided between the first wiring substrate and the second wiring substrate and configured to electrically connect the first wiring substrate and the second wiring substrate, an electronic component provided on at least one of the first wiring substrate and the second wiring substrate. The multiple connection terminals include a signal terminal and ground terminals provided on both sides of the signal terminal. The signal terminal and the ground terminals have side surfaces that face each other. The signal terminal and the ground terminals are adjacently arranged, so that intervals between the side surfaces of the signal terminal and the ground terminals are constant from a plan view. | 2014-08-28 |
20140239493 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - Provided is a semiconductor chip that is flip-chip mounted where an inner chip pad array and an outer chip pad array, which are arranged on an inner side and an outer side of IO cells in a staggered manner, are arranged to be spaced away from each other by a predetermined gap or greater. The predetermined gap represents a gap where one via can be arranged between an inner substrate pad array and an outer substrate pad array on a substrate which faces and is connected to the inner chip pad array and the outer chip pad array. In addition, the predetermined gap represents a gap where a plated wire is interconnected and then a resist opening for etch-back can be formed. Even in a case where a space for forming an interconnection is not present between outer substrate pad arrays, interconnection characteristics of the substrate are improved. | 2014-08-28 |
20140239494 | SEMICONDUCTOR PACKAGE STRUCTURE AND SEMICONDUCTOR PROCESS - The disclosure relates to a semiconductor bonding structure and process and a semiconductor chip. The semiconductor bonding structure includes a first pillar, a first interface, an intermediate area, a second interface and a second pillar in sequence. The first pillar, the second pillar and the intermediate area include a first metal. The first interface and the second interface include the first metal and an oxide of a second metal. The content percentage of the first metal in the first interface and the second interface is less than that of the first metal in the intermediate area. | 2014-08-28 |
20140239495 | Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP - A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed. | 2014-08-28 |
20140239496 | Semiconductor Device and Method of Forming Micro-Vias Partially Through Insulating Material Over Bump Interconnect Conductive Layer for Stress Relief - A semiconductor device has a semiconductor die and first insulating layer formed over the semiconductor die. A plurality of first micro-vias can be formed in the first insulating layer. A conductive layer is formed in the first micro-openings and over the first insulating layer. A second insulating layer is formed over the first insulating layer and conductive layer. A portion of the second insulating layer is removed to expose the conductive layer and form a plurality of second micro-openings in the second insulating layer over the conductive layer. The second micro-openings can be micro-vias, micro-via ring, or micro-via slots. Removing the portion of the second insulating layer leaves an island of the second insulating layer over the conductive layer. A bump is formed over the conductive layer. A third insulating layer is formed in the second micro-openings over the bump. The second micro-openings provide stress relief. | 2014-08-28 |