35th week of 2014 patent applcation highlights part 17 |
Patent application number | Title | Published |
20140239297 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer. | 2014-08-28 |
20140239298 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor. | 2014-08-28 |
20140239299 | Semiconductor Device, Power Circuit, And Manufacturing Method Of Semiconductor Device - The semiconductor device includes a first conductive layer over a substrate; an oxide semiconductor layer which covers the first conductive layer; a second conductive layer in a region which is not overlapped with the first conductive layer over the oxide semiconductor layer; an insulating layer which covers the oxide semiconductor layer and the second conductive layer; and a third conductive layer in a region including at least a region which is not overlapped with the first conductive layer or the second conductive layer over the insulating layer. | 2014-08-28 |
20140239300 | SEMICONDUCTOR TEST DEVICE AND METHOD FOR FABRICATING THE SAME - Semiconductor test devices and methods for fabricating the same may be provided. The semiconductor test device may include a first thermal test flip chip cell including a first heater and a first sensor, and a test substrate formed under the first thermal test flip chip cell. The first thermal test flip chip cell may include a plurality of first bumps arranged on a bottom surface of the first thermal test flip chip cell and be configured to be electrically connected to the first heater and the first sensor. The test substrate may include a first ball array arranged on a bottom surface of the test substrate in a first direction and be configured to be electrically connected to the plurality of first bumps, which are electrically connected to the first heater and the first sensor. | 2014-08-28 |
20140239301 | High Performance Surface Illuminating GeSi Photodiodes - A GeSi avalanche photodiode (APD includes an anti-reflection structure, a Ge absorption region, and a resonance cavity enhanced (RCE) reflector. The anti-reflection structure includes one or more dielectric layers and a top contact layer which is heavily doped with dopants of a first polarity. The RCE reflector includes: an intrinsic or lightly doped Si multiplication layer, a Si contact layer which is heavily doped with dopants of a second polarity opposite the first polarity, a Si cavity length compensation layer, a buried oxide (BOX) layer, and a Si substrate. | 2014-08-28 |
20140239302 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - An object is to realize a hermetically sealed package which ensures long-term airtightness inside the package by sealing using a substrate, or a sealing structure for reducing destruction caused by pressure from the outside. A frame of a semiconductor material is provided over a first substrate, which is bonded to a second substrate having a semiconductor element so that the semiconductor element is located inside the frame between the first substrate and the second substrate. The frame may be formed using, as frame members, two L-shaped semiconductor members in combination or four or more stick semiconductor members in combination. | 2014-08-28 |
20140239303 | SEMICONDUCTOR DEVICES INCLUDING WISX AND METHODS OF FABRICATION - Some embodiments include a semiconductor device having a stack structure including a plurality of alternating tiers of dielectric material and poly-silicon formed on a substrate. Such a semiconductor device may further include at least one opening having a high aspect ratio and extending into the stack structure to a level adjacent the substrate, a first poly-silicon channel formed in a lower portion of the opening adjacent the substrate, a second poly-silicon channel formed in an upper portion of the opening, and WSiX material disposed between the first poly-silicon channel and the second poly-silicon channel in the opening. The WSiX material is adjacent to the substrate, and can be used as an etch-landing layer and a conductive contact to contact both the first poly-silicon channel and the second poly-silicon channel in the opening. Other embodiments include methods of making semiconductor devices. | 2014-08-28 |
20140239304 | DISPLAY DEVICE - According to one embodiment, a display device includes a semiconductor including a first channel region, a second channel region, a source region, a drain region, a first region located between the source region and the first channel region, a second region formed between the first channel region and the second channel region, and a third region located between the drain region and the second channel region, wherein the second region has a length of 5 μm or more, which is greater than a length of each of the first region and the third region. | 2014-08-28 |
20140239305 | METHOD OF OPTIMIZING A GA-NITRIDE DEVICE MATERIAL STRUCTURE FOR A FREQUENCY MULTIPLICATION DEVICE - A preferred method of optimizing a Ga-nitride device material structure for a frequency multiplication device comprises:
| 2014-08-28 |
20140239306 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A diffusion barrier layer is disposed on top of the second III-V compound layer. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode. | 2014-08-28 |
20140239307 | REO GATE DIELECTRIC FOR III-N DEVICE ON Si SUBSTRATE - A rare earth oxide gate dielectric on III-N material grown on a silicon substrate includes a single crystal stress compensating template positioned on a silicon substrate. The stress compensating template is substantially crystal lattice matched to the surface of the silicon substrate. A GaN structure is positioned on the surface of the stress compensating template and substantially crystal lattice matched thereto. An active layer of single crystal III-N material is grown on the GaN structure and substantially crystal lattice matched thereto. A single crystal rare earth oxide dielectric layer is grown on the active layer of III-N material. | 2014-08-28 |
20140239308 | MIX DOPING OF A SEMI-INSULATING GROUP III NITRIDE - Embodiments of a semi-insulating Group III nitride and methods of fabrication thereof are disclosed. In one embodiment, a semi-insulating Group III nitride layer includes a first doped portion that is doped with a first dopant and a second doped portion that is doped with a second dopant that is different than the first dopant. The first doped portion extends to a first thickness of the semi-insulating Group III nitride layer. The second doped portion extends from approximately the first thickness of the semi-insulating Group III nitride layer to a second thickness of the semi-insulating Group III nitride layer. In one embodiment, the first dopant is Iron (Fe), and the second dopant is Carbon (C). In another embodiment, the semi-insulating Group III nitride layer is a semi-insulating Gallium Nitride (GaN) layer, the first dopant is Fe, and the second dopant is C. | 2014-08-28 |
20140239309 | Heterostructure Power Transistor With AlSiN Passivation Layer - A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts. | 2014-08-28 |
20140239310 | GROWTH SUBSTRATE, NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a method of manufacturing a light emitting device. More particularly, disclosed are a growth substrate, a nitride semiconductor device and a method of manufacturing a light emitting device. The method includes preparing a growth substrate including a metal substrate, forming a semiconductor structure including a nitride-based semiconductor on the growth substrate, providing a support structure on the semiconductor structure, and separating the growth substrate from the semiconductor structure. | 2014-08-28 |
20140239311 | SEMICONDUCTOR DEVICE - A semiconductor device includes a buffer layer, a channel layer and a barrier layer formed over a substrate, a trench penetrating through the barrier layer to reach the middle of the channel layer, and a gate electrode disposed inside the trench via a gate insulating film. The channel layer contains n-type impurities, and a region of the channel layer positioned on a buffer layer side has an n-type impurity concentration larger than a region of the channel layer positioned on a barrier layer side, and the buffer layer is made of nitride semiconductor having a band gap wider than that of the channel layer. The channel layer is made of GaN and the buffer layer is made of AlGaN. The channel layer has a channel lower layer containing n-type impurities at an intermediate concentration and a main channel layer formed thereon and containing n-type impurities at a low concentration. | 2014-08-28 |
20140239312 | Semiconductor Structure with Inhomogeneous Regions - A semiconductor layer including a plurality of inhomogeneous regions is provided. Each inhomogeneous region has one or more attributes that differ from a material forming the semiconductor layer. The inhomogeneous regions can include one or more regions configured based on radiation having a target wavelength. These regions can include transparent and/or reflective regions. The inhomogeneous regions also can include one or more regions having a higher conductivity than a conductivity of the radiation-based regions, e.g., at least ten percent higher. | 2014-08-28 |
20140239313 | LIGHT-EMITTING SEMICONDUCTOR DEVICE USING GROUP III NITROGEN COMPOUND - A method of producing a light-emitting semiconductor device of a group III nitride compound includes forming a buffer layer on a sapphire substrate, forming a Si-doped N | 2014-08-28 |
20140239314 | PHOTOCOUPLER - A photocoupler includes: a light emitting element; a first photodiode array; a second photodiode array; a third photo diode array; an enhancement-mode MOSFET; a first depletion-mode MOSFET; and a second depletion mode MOSFET. The light emitting element converts the input electrical signal into the optical signal. A drain current of the enhancement-mode MOSFET is supplied to the external load when the optical signal is ON. A drain current of the first depletion-mode MOSFET is supplied to the external load when the optical signal is OFF and a voltage passing through the second depletion-mode MOSFET switched to the ON state is supplied to the gate of the first depletion-mode MOSFET. And the drain current of the first depletion-mode MOSFET is larger than a drain current of the first depletion-mode MOSFET when a gate voltage of the first depletion-mode MOSFET is zero. | 2014-08-28 |
20140239315 | PACKAGE STRUCTURE OF OPTICAL TRANSCEIVER COMPONENT - The invention provides a package structure of optical transceiver component, comprising: a metal base; a plurality of pins, at least one optical emitting diode and/or at least one optical receiving diode; wherein the pins are provided and passed through the metal base and insulated with the metal base by using an insulating material; the optical emitting diode and the optical receiving diode are each mounted on the metal base through a sub-mount, respectively. The optical emitting diode/optical receiving diode is connected to the pins neighboring therewith by a wire directly or through the sub-mount, when set the top surface of the pins be a reference level, at least one of the top surfaces of the optical emitting diode, the optical receiving diode, and sub-mount is flush with the reference level. | 2014-08-28 |
20140239316 | LIGHT EMITTER PACKAGES AND METHODS - Light emitter packages and related methods having improved performance are disclosed. In one aspect, a light emitter package can include at least one light emitter chip disposed over a substrate or submount. In some aspects, the package can include a reflective polymeric material or polymeric reflector (sometimes referred to as a “solder mask” or “solder mask material”), a reflective material, and a conductive material disposed adjacent each other within a portion of the light emitter package. In some aspects, the reflective material can include a metallic material or metallic reflector applied to side walls of traces and/or within portions of a gap between traces prior to application of the reflective polymeric material within the gap. | 2014-08-28 |
20140239317 | DISPLAY DEVICE - A display device includes a substrate and a flexible circuit having one of its ends bonded to the substrate. The substrate comprises a pixel array. A driver integrated circuit (IC) is mounted on the flexible circuit. The flexible circuit is bonded to the substrate without protruding beyond an edge of the substrate. One end of the flexible circuit faces toward an inside of the substrate when the flexible circuit is flatly placed on or over the substrate, and the other end of the flexible circuit is bonded to the edge of the substrate. | 2014-08-28 |
20140239318 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The light emitting device including: a flexible substrate having a negative lead electrode and a positive lead electrode formed on an upper surface thereof; a light emitting element having a negative electrode and a positive electrode formed on an upper surface thereof; an insulating film formed on a side surface of the light emitting element; a wiring formed in contact with the insulating film for connecting between the negative electrode and the negative lead electrode, or between the positive electrode and the positive lead electrode. | 2014-08-28 |
20140239319 | Light Emitting Device - A light emitting device including a light emitting structure comprising a plurality of light emitting regions comprising a first semiconductor layer, an active layer and a second semiconductor layer, a first electrode unit disposed on the first semiconductor layer in one of the light emitting regions, a second electrode unit disposed on the second semiconductor layer in another of the light emitting regions, and at least one connection electrode to sequentially connect the light emitting regions in series, wherein the light emitting regions connected in series are divided into 1 | 2014-08-28 |
20140239320 | LIGHT EMITTING APPARATUS AND PRODUCTION METHOD THEREOF - A light emitting apparatus comprises an electrically insulating base member; a pair of electrically conductive pattern portions formed on an upper surface of the base member; at least one light emitting device that is electrically connected to the pair of electrically conductive pattern portions; and a resin portion that surrounds at least a side surface of the at least one light emitting device and partially covers the pair of electrically conductive pattern portions. Each of the pair of electrically conductive pattern portions extends toward a periphery of the base member from resin-covered parts of the electrically conductive pattern portions. At least the resin-covered parts of each of the electrically conductive pattern portions has at least one elongated through hole extending in a direction in which the electrically conductive pattern portions extend from the resin-covered parts, wherein the resin portion contacts the base member via the through holes. | 2014-08-28 |
20140239321 | Lighting Device, Backlight Module And Illumination Module - Various examples of a lighting device, backlight module and illumination module are described. A lighting device includes a carrier component, an LED chip, a thermistor, and a plurality of metal wires. The carrier component includes a plurality of electrodes. The LED chip and the thermistor are disposed on the carrier component and electrically coupled to each other. The plurality of metal wires form a circuit with the plurality of electrodes, the LED chip, and the thermistor. The thermistor has dimensions in chip-level scale when viewed from the top of the lighting device. A backlight module includes the aforementioned lighting device. An illumination module includes the aforementioned lighting device and a driver which is electrically coupled to the lighting device. | 2014-08-28 |
20140239322 | LIGHT EMITTING DEVICE ARRAY - Disclosed is a light emitting device array. The light emitting device array comprises a light emitting device and a body comprises first and second lead frames electrically connected to the light emitting device and a substrate on which the light emitting device package is disposed, the substrate comprises a base layer and a metal layer disposed on the base layer and electrically connected to the light emitting device package, wherein the metal layer comprises first and second electrode patterns electrically connected to the first and second lead frames and a heat dissipation pattern insulated from at least one of the first or(and) second electrode patterns, absorbing heat generated from at least one of the base layer or(and) the light emitting device package and then dissipating the heat. | 2014-08-28 |
20140239323 | Method and Apparatus for Accurate Die-to-Wafer Bonding - A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath. | 2014-08-28 |
20140239324 | GERMANIUM ELECTROLUMINESCENCE DEVICE AND FABRICATION METHOD OF THE SAME - This invention provides a germanium electroluminescence device and a fabricating method of the same for using germanium of an indirect bandgap semiconductor without modifying a bandgap as a light-emitting layer which emits a 1550 nm-wavelength light and enabling to use not only as infrared LEDs itself but also as light sources for optical communication systems. | 2014-08-28 |
20140239325 | LIGHT EMITTER COMPONENTS AND METHODS HAVING IMPROVED PERFORMANCE - Light emitter components and methods having improved performance and related methods are disclosed. In one embodiment, a light emitter component can include a submount and at least one light emitting diode (LED) chip disposed over the submount. The submount can contact at least two different sides of the at least one LED chip. In one aspect, a submount can include surface portions adapted to receive portions one or more LED chips. In one aspect, one or more LED chips can be embedded within the submount. | 2014-08-28 |
20140239326 | LIGHT EMITTING DIODE BACKLIGHT MODULE - A light emitting diode (LED) backlight module includes a transparent conductive substrate that has an electrode-bearing surface and a plurality of transparent conductive electrodes disposed on the electrode-bearing surface, an LED chip that is welded on the transparent conductive electrodes by flip-chip packaging techniques, and a reflecting member that is spaced apart from and that corresponds in position to the LED chip so as to reflect light generated from the LED chip to the transparent conductive substrate. | 2014-08-28 |
20140239327 | NANOSTRUCTURED LED - The device according to the invention comprises a nanostructured LED with a first group of nanowires protruding from a first area of a substrate and a contacting means in a second area of the substrate. Each nanowire of the first group of nanowires comprises a p-i-n-junction and a top portion of each nanowire or at least one selection of nanowires is covered with a light reflecting contact layer. The contacting means of the second area is in electrical contact with the bottom of the nanowires, the light-reflecting contact layer being in electrical contact with the contacting means of the second area via the p-i-n-junction. Thus when a voltage is applied between the contacting means of the second area and the light-reflecting contact layer, light is generated within the nanowire. On top of the light-reflecting contact layer, a first group of contact pads for flip-chip bonding can be provided, distributed and separated to equalize the voltage across the layer to reduce the average serial resistance. | 2014-08-28 |
20140239328 | LIGHT EMITTING DEVICE PACKAGE - The present application relates to a light emitting device package. The light emitting device package includes a package substrate in which a via hole is formed. An electrode layer extends to both surfaces of the package substrate after passing through the via hole. A light emitting device is arranged on the package substrate and is connected to the electrode layer. A fluorescence film includes a first part that fills at least a part of an internal space of the via hole and a second part that covers at least a part of the light emitting device. | 2014-08-28 |
20140239329 | COLOR FILTER SUBSTRATE, ELECTROOPTIC DEVICE, ELECTROOPTIC DEVICE MANUFACTURING METHOD, AND ELECTRONIC APPARATUS - A color filter substrate includes a second base material, a stopper film provided on the second base material, an insulating film including color filter grooves provided on the stopper film, and color filters provided so as to embed the color filter grooves. | 2014-08-28 |
20140239330 | OPTICAL COMMUNICATION MODULE AND METHOD FOR MAKING THE SAME - An optical communication module includes an optical semiconductor element. The element includes an optical functional region having a light receiving function or a light emitting function, a first transmission layer transmissive to light emitted from the optical functional region or light received by the optical functional region, and a wiring layer stacked on the first transmission layer and constituting a conduction path to the optical functional region. The communication module also includes a second transmission layer transmissive to the light and disposed to cover the optical semiconductor element, and a first resin member stacked on the second transmission layer. The communication module is formed with a fixing hole for fixing an optical fiber. The fixing hole includes a bottom face provided by the second transmission layer, and an opening formed in an outer surface of the first resin member. | 2014-08-28 |
20140239331 | LIGHT EMITTING DEVICE, LIGHT EMITTING ELEMENT MOUNTING METHOD, AND LIGHT EMITTING ELEMENT MOUNTER - Disclosed is a light emitting device including: a light emitting element including an LED chip and a phosphor layer provided at the light emitting side of the LED chip; and a substrate on which the light emitting element is bonded by an adhesive material. The adhesive material is an anisotropic conductive material. | 2014-08-28 |
20140239332 | LIGHT EMITTING DEVICE AND LIGHTING DEVICE INCLUDING SAME - A light emitting device includes a base that has an element mounting surface, a light emitting element that is mounted on the element mounting surface and that has maximum light intensity in a directly upward direction, and a coating member that contains a fluorescent body that is excited by light from the light emitting element, and that is constituted by a single layer that coats an upper part of the light emitting element. The fluorescent body exists at a position other than directly above the light emitting element. | 2014-08-28 |
20140239333 | LED LIGHTING SYSTEMS WITH PHOSPHOR SUBASSEMBLIES, AND/OR METHODS OF MAKING THE SAME - Certain example embodiments relate to improved lighting systems and/or methods of making the same. In certain example embodiments, a lighting system includes a glass substrate with one or more apertures. An LED or other light source is disposed at one end of the aperture such that light from the LED directed through the aperture of the glass substrate exits the opposite end of the aperture. Inner surfaces of the aperture have a mirroring material such as silver to reflect the emitted light from the LED. In certain example embodiments, a remote phosphor article or layer is disposed opposite the LED at the other end of the aperture. In certain example embodiment, a lens is disposed in the aperture, between the remote phosphor article and the LED. | 2014-08-28 |
20140239334 | PACKAGE STRUCTURE OF LIGHT EMITTING DIODE - A package structure of semiconductor light emitting element is provided. The package structure of semiconductor light emitting element includes a substrate, a light emitting element and a transparent conductive board. A first electrode and a second electrode are disposed on the substrate. The light emitting element is disposed on the substrate and between the first electrode and the second electrode. A first bonding pad and a second bonding pad are disposed on the light emitting element. The transparent conductive board has a first surface and a second surface opposite to the first surface. The second surface of the transparent conductive board is located over the light emitting element for electrically connecting the first electrode and the first bonding pad and electrically connecting the second electrode and the second bonding pad. | 2014-08-28 |
20140239335 | LIGHT-EMITTING DEVICE AND APPLICATION LIQUID - Formation of an interlayer is realized for a light-emitting device, the interlayer having properties of anticorrosion and adhesion to a silicone layer, thus preventing incidence of cracking during a baking process. The light-emitting device comprises a light-emitting element covered with the silicone layer, and the interlayer is provided between the light-emitting element and the silicone layer. The interlayer is formed of a mixture of a tri-functional polysiloxane and a tetra-functional polysiloxane. | 2014-08-28 |
20140239336 | SEMICONDUCTOR LIGHT DEVICE INCLUDING A LENS HAVING A LIGHT DEFLECTION STRUCTURE - A semiconductor lighting device may include at least one semiconductor light source and a lens, wherein the lens has a light entrance surface at the underside, said light entrance surface facing the at least one semiconductor light source, and a light exit surface at the top side, the light entrance surface has a light deflection structure in the form of a TIR structure, at which entering light can be deflected in the direction of the light exit surface by means of total internal reflection, and the lens is fitted to the semiconductor lighting device in a detachable fashion. | 2014-08-28 |
20140239337 | SUBSTRATE FOR LIGHT-EMITTING DEVICE AND LIGHT-EMITTING DEVICE THEREOF - This invention discloses a substrate for a light-emitting device and light-emitting device using the same, and the substrate comprises a sapphire substrate. The sapphire substrate comprises a surface having a plurality of cones, heights of the cones are ranged from 1.4-1.9 μm, diameters of the cones are ranged from 2.4-2.9 μm, base angles between the bottom of each of the cones and the level surface of the sapphire substrate are ranged from 40°-80°, the plurality of cones are uniformly distributed over the sapphire substrate and do not contact each other, a distance between the apexes of each two neighboring cones is ranged from 2.5-3.5 μm, a distance between the bottoms of each two neighboring cones is ranged from 0.1-0.6 μm. Further, the substrate of the light-emitting device further comprises an interlayer covering the sapphire substrate to increase the epitaxy speed and enhance the throughput subsequently. | 2014-08-28 |
20140239338 | SUBSTRATE FOR LIGHT-EMITTING DEVICE AND LIGHT-EMITTING DEVICE THEREOF - This invention discloses a substrate for a light-emitting device and light-emitting device using the same, and the substrate comprises a sapphire substrate. The sapphire substrate comprises a surface having a plurality of cones, heights of the cones are ranged from 1.6-2.1 μm, diameters of the cones are ranged from 3.4-3.9 μm, base angles between the bottom of each of the cones and the level surface of the sapphire substrate are ranged from 40°-80°, the plurality of cones are uniformly distributed over the sapphire substrate and do not contact each other, a distance between apexes of each two neighboring cones is ranged from 3.5-4.5 μm, a distance between the bottoms of each two neighboring cones is ranged from 0.1-0.6 μm. Further, the substrate of the light-emitting device further comprises an interlayer covering the sapphire substrate to increase the epitaxy speed and enhance the throughput subsequently. | 2014-08-28 |
20140239339 | A LIGHT EMITTING DEVICE COMPRISES A SAPPHIRE SUBSTRATE HAVING A PLURALITY OF OPTIMIZED CONES ON ITS SURFACE - This invention discloses a substrate for a light-emitting device and light-emitting device using the same, and the substrate comprises a sapphire substrate. The sapphire substrate comprises a surface having a plurality of cones, heights of the cones are ranged from 0.6-1.6 μm, diameters of the cones are ranged from 0.6-1.6 μm, base angles between the bottom of each of the cones and the level surface of the sapphire substrate are ranged from 40°-80°, the plurality of cones are uniformly distributed over the sapphire substrate and do not contact each other, a distance between the apexes of each two neighboring cones is ranged from 1.7-2.3 μm, a distance between the bottoms of each two neighboring cones is ranged from 0.4-1.4 μm. Further, the substrate of the light-emitting device further comprises an interlayer covering the sapphire substrate to increase the epitaxy speed and enhance the throughput subsequently. | 2014-08-28 |
20140239340 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE PACKAGE, AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - The light emitting device includes: a substrate; a first conductive-type semiconductor layer laminated on the substrate; a light emitting layer laminated on the first conductive-type semiconductor layer; a second conductive-type semiconductor layer laminated on the light emitting layer; a first ITO layer, a second ITO layer, a first metal layer and a second metal layer. The first ITO layer is laminated at a side of the first conductive-type semiconductor layer opposite to the substrate. The second ITO layer is laminated at a side of the second conductive-type semiconductor layer opposite to the substrate. The first metal layer is laminated on the first ITO layer. The second metal layer is laminated on the second ITO layer. | 2014-08-28 |
20140239341 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - The light emitting element including: a semiconductor laminate including a first layer, an active layer and a second layer; a first electrode including protrusions that penetrate the second layer and the active layer, the first electrode connected to the first layer via the protrusions; a second electrode connected to the second layer on an lower face of the second layer; and an insulation film between the protrusions and the semiconductor laminate, wherein the protrusions each include a protrusion body covered with the insulation film and a protrusion tip, an upper face and a side face of the protrusion tip being exposed from the insulation film, the first layer includes recesses arranged on an upper face of the first layer so as to sandwich first areas located above the respective the protrusions, and a distance between the recesses sandwiching the first area is larger than a width of the protrusion tip. | 2014-08-28 |
20140239342 | LED BACK END ASSEMBLY AND METHOD OF MANUFACTURING - An LED device and method of manufacture including separately coupling a thin flexible interposer and an LED die to a heat sink structure and then electrically coupling the interposer and the LED die together with a wirebond. A specifically shaped perimeter of an aperture within the interposer negates the need for a cavity or alignment markings within the heat sink structure by limiting the orientation in which the die fits within the aperture. Alternatively, an LED device and method of manufacture include coupling a rigid circuit board to an LED die such that electrical contacts of the die are electrically coupled with electrical input/output terminals of the circuit board. This die/board unit is then able to be coupled to a heat sink structure to form a portion of the device. | 2014-08-28 |
20140239343 | BI-DIRECTIONAL SILICON CONTROLLED RECTIFIER STRUCTURE - Bi-directional silicon controlled rectifier device structures and design structures, as well as fabrication methods for bi-directional silicon controlled rectifier device structures. A well of a first conductivity type is formed in a device region, which may be defined from a device layer of a semiconductor-on-insulator substrate. An anode of a first silicon controlled rectifier is formed in the first well. A cathode of a second silicon controlled rectifier is formed in the first well. The anode of the first silicon controlled rectifier has the first conductivity type. The cathode of the second silicon controlled rectifier has a second conductivity type opposite to the first conductivity type. | 2014-08-28 |
20140239344 | POWER SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a power semiconductor device, including a first conductive type drift layer; a second conductive type body layer formed on the drift layer, a second conductive type collector layer formed below the drift layer; a first gate formed by penetrating through the body layer and a portion of the drift layer, a first conductive type emitter layer formed in the body layer and formed to be spaced apart from the first gate, a second gate covering upper portions of the body layer and the emitter layer and formed as a flat type gate on the first gate, and a segregation stop layer formed between contact surfaces of the first and second gates with the body layer, the emitter layer, and the drift layer. | 2014-08-28 |
20140239345 | STRAINED TRANSISTOR INTEGRATION FOR CMOS - Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area. | 2014-08-28 |
20140239346 | MISHFET AND SCHOTTKY DEVICE INTEGRATION - A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate. | 2014-08-28 |
20140239347 | Structure and Method for Defect Passivation To Reduce Junction Leakage For FinFET Device - The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first semiconductor material; shallow trench isolation (STI) features formed in the semiconductor substrate; and a fin-like active region of a second semiconductor material epitaxy grown on the semiconductor substrate. The first semiconductor material has a first lattice constant and the second semiconductor material has a second lattice constant different from the first lattice constant. The fin-like active region further includes fluorine species. | 2014-08-28 |
20140239348 | METHODS, DEVICES, AND SYSTEMS RELATED TO FORMING SEMICONDUCTOR POWER DEVICES WITH A HANDLE SUBSTRATE - Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure. | 2014-08-28 |
20140239349 | Drain Pad Having a Reduced Termination Electric Field - In an exemplary implementation, a semiconductor device includes a drain pad on a semiconductor substrate, the drain pad being coupled to a plurality of drain fingers. The semiconductor device further includes a source pad on the semiconductor substrate, the source pad being coupled to a plurality of source fingers. The plurality of source fingers is interdigitated with the plurality of drain fingers. Furthermore, an outer corner of the drain pad has a gradual transition between adjoining sides of the drain pad. The gradual transition between the adjoining sides of the drain pad reduces a termination electric field at the outer corner of the drain pad. Furthermore, the gradual transition between the adjoining sides of the drain pad increases the breakdown voltage of the semiconductor device. | 2014-08-28 |
20140239350 | SEMICONDUCTOR DEVICE CONTAINING HEMT AND MISFET AND METHOD OF FORMING THE SAME - A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A third III-V compound layer is disposed on the second III-V compound layer is different from the second III-V compound layer in composition. A source feature and a drain feature are disposed in each of the MISFET and HEMT regions on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but above the top surface of the third III-V compound layer. | 2014-08-28 |
20140239351 | PROCESS TO ELIMINATE LAG IN PIXELS HAVING A PLASMA-DOPED PINNING LAYER - Embodiments of a process including depositing a sacrificial layer on the surface of a substrate over a photosensitive region, over the top surface of a transfer gate, and over at least the sidewall of the transfer gate closest to the photosensitive region, the sacrificial layer having a selected thickness. A layer of photoresist is deposited over the sacrificial layer, which is patterned and etched to expose the surface of the substrate over the photosensitive region and at least part of the transfer gate top surface, leaving a sacrificial spacer on the sidewall of the transfer gate closest to the photosensitive region. The substrate is plasma doped to form a pinning layer between the photosensitive region and the surface of the substrate. The spacing between the pinning layer and the sidewall of the transfer gate substantially corresponds to a thickness of the sacrificial spacer. Other embodiments are disclosed and claimed. | 2014-08-28 |
20140239352 | CMOS COMPATIBLE SILICON DIFFERENTIAL CONDENSER MICROPHONE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a CMOS compatible silicon differential condenser microphone and a method of manufacturing the same. Said microphone comprises a silicon substrate, wherein a CMOS circuitry is accommodated thereon; a first rigid conductive perforated backplate supported on the silicon substrate with an insulating layer inserted therebetween; a second rigid perforated backplate formed above the first backplate, including CMOS passivation layers and a metal layer sandwiched between the CMOS passivation layers as an electrode plate of the second plate, wherein an air gap, with a spacer forming its boundary, is provided between the opposite perforated areas of the first backplate and the second backplate; a compliant diaphragm provided between the first backplate and the second backplate, wherein a back hole is formed to be open in the silicon substrate underneath the first backplate so as to allow sound pass through, and the diaphragm and the first backplate form a first variable condenser, the diaphragm and the second backplate form a second variable condenser, and the first variable condenser and the second variable condenser form differential condensers. | 2014-08-28 |
20140239353 | METHOD FOR MEMS STRUCTURE WITH DUAL-LEVEL STRUCTURAL LAYER AND ACOUSTIC PORT - A method for fabricating a MEMS device includes depositing and patterning a first sacrificial layer onto a silicon substrate, the first sacrificial layer being partially removed leaving a first remaining oxide. Further, the method includes depositing a conductive structure layer onto the silicon substrate, the conductive structure layer making physical contact with at least a portion of the silicon substrate. Further, a second sacrificial layer is formed on top of the conductive structure layer. Patterning and etching of the silicon substrate is performed stopping at the second sacrificial layer. Additionally, the MEMS substrate is bonded to a CMOS wafer, the CMOS wafer having formed thereupon a metal layer. An electrical connection is formed between the MEMS substrate and the metal layer. | 2014-08-28 |
20140239354 | FinFETs and Methods for Forming the Same - A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric. | 2014-08-28 |
20140239355 | FIN FIELD-EFFECT TRANSISTORS AND FABRICATION METHOD THEREOF - A method is provided for fabricating a fin field-effect transistor. The method includes providing a semiconductor substrate; and forming a plurality of fins on top of the semiconductor substrate. The method also includes forming isolation structures between adjacent fins; and forming doping sidewall spacers in top portions of the isolation structures near the fins. Further, the method includes forming a punch-through stop layer at the bottom of each of the fins by thermal annealing the doping sidewall spacers; and forming a high-K metal gate on each of the fins. | 2014-08-28 |
20140239356 | SEMICONDUCTOR DEVICE - A semiconductor device concerning an embodiment is provided with a semiconductor layer, an impurity-doped layer selectively formed on the semiconductor layer, and a drain electrode formed on the impurity-doped layer. The semiconductor device is further provided with a source electrode which is formed and isolated from the drain electrode, and a gate electrode which is formed between the source electrode and the drain electrode. The semiconductor device is provided with an insulating film which is formed between the gate electrode and the drain electrode, and a shielding plate which is formed on the insulating film and is electrically connected to the source electrode. At least a part of the shielding plate is formed above an extending portion of the impurity-doped layer which extends in the direction to the gate electrode from the drain electrode. | 2014-08-28 |
20140239357 | THIN FILM TRANSISTOR ON FIBER AND MANUFACTURING METHOD OF THE SAME - Provided is a thin film transistor on fiber and a method of manufacturing the same. The thin film transistor includes a fiber; a first electrode, a second electrode and a gate electrode formed on fiber; a channel formed between the first and second electrodes; an encapsulant encapsulating the fiber, the first, second, and gate electrodes, and an upper surface of the channel; and a gate insulating layer formed in a portion of the inner area of the encapsulant. | 2014-08-28 |
20140239358 | NONPLANAR DEVICE WITH THINNED LOWER BODY PORTION AND METHOD OF FABRICATION - A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode. | 2014-08-28 |
20140239359 | SEMICONDUCTOR DEVICE - A gate electrode ( | 2014-08-28 |
20140239360 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME, AND SOLID-STATE IMAGE PICKUP DEVICE USING THE SAME - A semiconductor device, including: a gate electrode formed on a semiconductor substrate through a gate insulating film; an extension region formed in the semiconductor substrate on a source side of the gate electrode; a source region formed in the semiconductor substrate on the source side of the gate electrode through the extension region; an LDD region formed in the semiconductor substrate on a drain side of the gate electrode; and a drain region formed in the semiconductor substrate on the drain side of the gate electrode through the LDD region; wherein the extension region is formed at a higher concentration than that of the LDD region so as to be shallower than the LDD region. | 2014-08-28 |
20140239361 | METHODS AND APPARATUS FOR SUPPRESSING CROSS TALK IN CMOS IMAGE SENSORS - A CMOS image sensor with reduced crosstalk includes a semiconductor substrate formed with a plurality of photodiodes formed therein, a dielectric layer formed on the semiconductor substrate, a reflective layer formed on the dielectric layer, and an insulating layer formed on the reflective layer. A plurality of grooves is formed in the dielectric layer, the reflective layer, and the insulating layer above a corresponding photodiode. Each groove is filled with a color filter material to form a color filter above the photodiode. The image sensor also includes a planarization layer formed on the insulating layer and color filter. A microlens is formed on the planarizing layer. The light reflecting layer prevents stray light diffraction line crosstalk into an adjacent photodiode. The color filter grooves confine the target image light only through the filters in the groove window to reach the photodiode. | 2014-08-28 |
20140239362 | IMAGE SENSOR AND METHOD OF FORMING THE SAME - An image sensor includes a substrate having a first surface opposing a second surface and a plurality of pixel regions. A photoelectric converter is included in each of the pixel regions, and a gate electrode is formed on the photoelectric converter. Also, a pixel isolation region isolates adjacent pixel regions. The pixel isolation region includes a first isolation layer coupled to a channel stop region. The channel stop region may include an impurity-doped region. | 2014-08-28 |
20140239363 | CAPACITORS COMPRISING SLOT CONTACT PLUGS AND METHODS OF FORMING THE SAME - An integrated circuit includes a semiconductor substrate, and an insulation region extending from a top surface of the semiconductor substrate into the semiconductor substrate. An Inter-Layer Dielectric (ILD) is overlying the insulation region. A capacitor includes a first capacitor plate including a first slot contact plug, and a second capacitor plate including a second slot contact plug. The first and the second contact plugs include portions in the ILD. A portion of the ILD between vertical surfaces of the first slot contact plug and the second slot contact plug acts as a capacitor insulator of the capacitor. | 2014-08-28 |
20140239364 | MOS Varactor Optimized Layout and Methods - Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed. | 2014-08-28 |
20140239365 | METHOD FOR USING NANOPARTICLES TO MAKE UNIFORM DISCRETE FLOATING GATE LAYER - A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape. | 2014-08-28 |
20140239366 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - According to an embodiment, a non-volatile semiconductor storage device includes a silicon substrate including an active region isolated by an element isolation insulating film, a first insulating film formed on the active region, a charge accumulation layer formed on the first insulating film, a second insulating film formed on the charge accumulation layer, and a control gate formed on the second insulating film. A plane of the active region being in contact with the element isolation insulating film is a (100) plane or a plane inclining from the (100) plane by an inclination angle of 5° or less. | 2014-08-28 |
20140239367 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - The performances of a semiconductor device are improved. The semiconductor device has a first control gate electrode and a second control gate electrode spaced along the gate length direction, a first cap insulation film formed over the first control gate electrode, and a second cap insulation film formed over the second control gate electrode. Further, the semiconductor device has a first memory gate electrode arranged on the side of the first control gate electrode opposite to the second control gate electrode, and a second memory gate electrode arranged on the side of the second control gate electrode opposite to the first control gate electrode. The end at the top surface of the first cap insulation film on the second control gate electrode side is situated closer to the first memory gate electrode side than the side surface of the first control gate electrode on the second control gate electrode side. | 2014-08-28 |
20140239368 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a first isolation region dividing a semiconductor substrate into first regions; memory cells each including a tunnel insulating film, a charge storing layer, an interelectrode insulating film, and a control gate electrode above the first region; a second isolation region dividing the substrate into second regions in a peripheral circuit region; and a peripheral circuit transistor including a gate insulating film and a gate electrode above the second region. The first isolation region includes a first trench, a first element isolation insulating film filled in a bottom portion of the first trench, and a first gap formed between the first element isolation insulating film and the interelectrode insulating film. The second isolation region includes a second trench and a second element isolation insulating film filled in the second trench. The first and the second element isolation insulating films have different properties. | 2014-08-28 |
20140239369 | SELF-ALIGNED CHARGE-TRAPPING LAYERS FOR NON-VOLATILE DATA STORAGE, PROCESSES OF FORMING SAME, AND DEVICES CONTAINING SAME - A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device. | 2014-08-28 |
20140239370 | MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided is a memory device including a first dielectric layer, a T-shaped gate, two charge storage layers and two second dielectric layers. The first dielectric layer is disposed on a substrate. The T-shaped gate is disposed on the first dielectric layer and has an upper gate and a lower gate, wherein two gaps are present respectively at both sides of the lower gate and between the upper gate and the substrate. The charge storage layers are respectively embedded into the gaps. A second dielectric layer is disposed between each charge storage layer and the upper gate, between each charge storage layer and the lower gate and between each charge storage layer and the substrate. | 2014-08-28 |
20140239371 | FIELD EFFECT TRANSISTOR WITH SELF-ADJUSTING THRESHOLD VOLTAGE - Methods for forming field effect transistors (FETs) with improved ON/OFF current ratios in addition to short charging times and the resulting devices are disclosed. Embodiments include forming a gate oxide layer above a channel region in a substrate, forming a partial self-adjusting threshold voltage layer above a drain-side end of the gate oxide layer, and forming a gate above the partial self-adjusting threshold voltage layer and the gate oxide layer. | 2014-08-28 |
20140239372 | SPLIT GATE NON-VOLATILE MEMORY (NVM) CELL AND METHOD THEREFOR - A split gate memory structure includes a pillar of active region having a first source/drain region disposed at a first end of the pillar, a second source/drain region disposed at a second end of the pillar, opposite the first end, and a channel region between the first and second source/drain regions. The pillar has a major surface extending between first and the second ends which exposes the first source/drain region, the channel region, and the second source/drain region. A select gate is adjacent the first source/drain region and a first portion of the channel region, wherein the select gate encircles the major surface the pillar. A charge storage layer is adjacent the second source/drain region and a second portion of the channel region, wherein the charge storage layer encircles the major surface the pillar. A control gate is adjacent the charge storage layer, wherein the control gate encircles the pillar. | 2014-08-28 |
20140239373 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor memory device includes a semiconductor member, a first insulating layer provided on the semiconductor member, a TaN layer provided on the first insulating layer and containing tantalum and nitrogen, a TaSiN layer provided on the TaN layer in contact with the TaN layer and containing tantalum, silicon, and nitrogen, a second insulating layer provided on the TaSiN layer in contact with the TaSiN layer and containing oxygen, and a control electrode provided on the second insulating layer. | 2014-08-28 |
20140239374 | EMBEDDED SONOS BASED MEMORY CELLS - Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a dielectric stack on a substrate, the dielectric stack including a tunneling dielectric on the substrate and a charge-trapping layer on the tunneling dielectric; patterning the dielectric stack to form a gate stack of a NVM transistor of a memory device in a first region of the substrate while concurrently removing the dielectric stack from a second region of the substrate; and performing a gate oxidation process of a baseline CMOS process flow to thermally grow a gate oxide of a MOS transistor overlying the substrate in the second region while concurrently growing a blocking oxide overlying the charge-trapping layer. In one embodiment, Indium is implanted to form a channel of the NVM transistor. | 2014-08-28 |
20140239375 | MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction. | 2014-08-28 |
20140239376 | VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A memory device includes a plurality of channels, a plurality of first charge storage sites coupled to first sides of respective ones of the channels, and a plurality of second charge storage sites coupled to second sides of respective ones of the channels. The first charge storage sites correspond to first memory cells and the second charge storage sites coupled to second memory cells. At least one of the channels is a dummy channel not connected to a bit line, and a blocking layer is contiguously formed around the first and second charge storage sites and the channels. | 2014-08-28 |
20140239377 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - To enhance the performance of a semiconductor device. In a method for manufacturing a semiconductor device, a metal film is formed over a semiconductor substrate having an insulating film formed on a surface thereof, and then the metal film is removed in a memory cell region, whereas, in a part of a peripheral circuit region, the metal film is left. Next, a silicon film is formed over the semiconductor substrate, then the silicon film is patterned in the memory cell region, and, in the peripheral circuit region, the silicon film is left so that an outer peripheral portion of the remaining metal film is covered with the silicon film. Subsequently, in the peripheral circuit region, the silicon film, the metal film, and the insulating film are patterned for forming an insulating film portion formed of the insulating film, a metal film portion formed of the metal film, and a conductive film portion formed of the silicon film. | 2014-08-28 |
20140239378 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In an MONOS-type memory cell with a split gate structure, short circuit between a selection gate electrode and a memory gate electrode is prevented, and reliability of a semiconductor device is improved. In a MONOS memory having a selection gate electrode and a memory gate electrode that are adjacent to each other and that extend in a first direction, an upper surface of the selection gate electrode in a region except for a shunt portion at an end portion of the selection gate electrode in the first direction is covered with a cap insulating film. The memory gate electrode is terminated on the cap insulating film side with respect to a border between the cap insulating film and an upper surface of the shunt portion exposed from the cap insulating film. | 2014-08-28 |
20140239379 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH CHARGE STORAGE LAYER IN MEMORY CELL - A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7. | 2014-08-28 |
20140239380 | NAND FLASH MEMORY UNIT AND NAND FLASH MEMORY ARRAY - A NAND flash memory unit is described, including a string of memory cells connected in series, S/D regions coupled to two terminals of the string, at least one select transistor couple between a terminal of the string and an S/D region, and at least one erase transistor couple between the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells. The erase transistor is for reducing Vt-shift of the select transistor. | 2014-08-28 |
20140239381 | INSULATED GATE FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - An insulated gate field effect transistor configured to reduce the occurrence of a short-circuit fault, and a method of manufacturing the insulated gate field effect transistor are provided. A FET includes a semiconductor substrate, a gate insulator, a gate electrode, and a conductive member. The semiconductor substrate has an insulation groove that splits a channel region into a first channel region on a drain region side and a second channel region on a source region side. The conductive member is supported by a drain-side end face and a source-side end face of the insulation groove. When the temperature of the conductive member is equal to or higher than a predetermined temperature, the conductive member is cut. | 2014-08-28 |
20140239382 | HIGH FREQUENCY SWITCHING MOSFETS WITH LOW OUTPUT CAPACITANCE USING A DEPLETABLE P-SHIELD - Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2014-08-28 |
20140239383 | WAFER LEVEL CHIP SCALE PACKAGE AND PROCESS OF MANUFACTURE - Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste. | 2014-08-28 |
20140239384 | SEMICONDUCTOR DEVICE HAVING VERTICAL SURROUNDING GATE TRANSISTOR STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; and a common gate section which covers side faces of the pillars. | 2014-08-28 |
20140239385 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A Field Effect Transistor (FET) and a method of manufacturing the same are provided. The FET may include a substrate; a source and a drain, one of which is formed on a bulge formed on a top surface of the substrate, and the other of which is formed in the substrate below but laterally offset from the bulge; a gate formed at a position where the bulge and the top surface of the substrate join each other; and a gate dielectric layer formed between the gate and the bulge and also between the gate and the top surface of the substrate. The FET has a vertical configuration, where the source is disposed on top of the bulge while the drain is disposed in the substrate, that is, the source and the drain are not in one same plane. As a result, the FET may have its area significantly reduced. Therefore, it is possible to improve an integration density of an IC and thus reduce cost. | 2014-08-28 |
20140239386 | Trench Gated Power Device With Multiple Trench Width and its Fabrication Process - Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps. | 2014-08-28 |
20140239387 | MOS Transistor Structure and Method - A MOS transistor structure comprises a substrate including a bulk semiconductor region, a first gate formed in a first trench, a first drain/source region, a second drain/source region, wherein the first drain/source region and the second drain/source region are formed on opposing sides of the first gate. The MOS transistor structure further comprises a second gate formed in a second trench, a third drain/source region, wherein the third drain/source region and the second drain/source region are formed on opposing sides of the second gate and a channel region formed in the bulk semiconductor region, wherein the channel region, the first drain/source region, the second drain/source region and the third drain source region share a same polarity. | 2014-08-28 |
20140239388 | TERMINATION TRENCH FOR POWER MOSFET APPLICATIONS - Aspects of the present disclosure describe a termination structure for a power MOSFET device. A termination trench may be formed into a semiconductor material and may encircle an active area of the MOSFET. The termination trench may comprise a first and second portion of conductive material. The first and second portions of conductive material are electrically isolated from each other. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2014-08-28 |
20140239389 | SEMI CONDUCTOR DEVICE HAVING ELEVATED SOURCE AND DRAIN - Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer ( | 2014-08-28 |
20140239390 | LATERAL DEVICES CONTAINING PERMANENT CHARGE - A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region. | 2014-08-28 |
20140239391 | LDMOS WITH IMPROVED BREAKDOWN VOLTAGE - An LDMOS is formed with a field plate over the n | 2014-08-28 |
20140239392 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer ( | 2014-08-28 |
20140239393 | FINFET DEVICE AND METHOD OF MANUFACTURING SAME - A FinFET device and a method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate including a fin structure, the fin structure including a first and a second fin. The FinFET device further includes a shallow trench isolation (STI) feature disposed on the substrate and between the first and the second fins. The FinFET device further includes a gate dielectric disposed on the first and the second fins. The FinFET device further includes a gate structure disposed on the gate dielectric. The gate structure traverses the first fin, the second fin, and the STI feature between the first fin and the second fin and has a longitudinal stepped profile. | 2014-08-28 |
20140239394 | U-SHAPED SEMICONDUCTOR STRUCTURE - A method for forming a U-shaped semiconductor device includes forming trenches in a crystalline layer and epitaxially growing a U-shaped semiconductor material along sidewalls and bottoms of the trenches. The U-shaped semiconductor material is anchored, and the crystalline layer is removed. The U-shaped semiconductor material is supported by backfilling underneath the U-shaped semiconductor material with a dielectric material. A semiconductor device is formed with the U-shaped semiconductor material. | 2014-08-28 |
20140239395 | CONTACT RESISTANCE REDUCTION IN FINFETS - A method for forming contacts in a semiconductor device includes forming a plurality of substantially parallel semiconductor fins on a dielectric layer of a substrate having a gate structure formed transversely to a longitudinal axis of the fins. The fins are merged by epitaxially growing a crystalline material between the fins. A field dielectric layer is deposited over the fins and the crystalline material. Trenches that run transversely to the longitudinal axis of the fins are formed to expose the fins in the trenches. An interface layer is formed over portions of the fins exposed in the trenches. Contact lines are formed in the trenches that contact a top surface of the interface layer on the fins and at least a portion of side surfaces of the interface layer on the fins. | 2014-08-28 |
20140239396 | Metal Gate and Gate Contact Structure for FinFET - An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate dielectric, and an uninterrupted metallic feature over the liner a portion of the liner overlaying the gate dielectric, wherein the liner extends from a top surface of the uninterrupted metallic feature and covers sidewalls of the metallic feature, and wherein the gate dielectric, liner, and uninterrupted metallic feature collectively form a gate, a gate contact barrier, and a gate contact. | 2014-08-28 |