35th week of 2008 patent applcation highlights part 23 |
Patent application number | Title | Published |
20080204016 | Magnetic Resonance Apparatus and Method - Magnetic resonance apparatus is provided comprising a magnet having a first pair of coils arranged in a plane. The coils are operable in a counter-running manner when in use so as to generate a sensitive volume of magnetic field spaced apart from said plane. The magnetic field in the sensitive volume is arranged to have sufficient uniformity to enable magnetic resonance signals to be obtained from a target when located within the sensitive volume. The magnetic field direction Z is oriented to lie substantially parallel to the planes. The coils are arranged such that the sensitive volume is elongate in a direction X substantially parallel to the planes. A drive system is provided to cause relative movement between the magnet and the target so as to allow the sensitive volume to be moved with respect to the target. | 2008-08-28 |
20080204017 | MRI APPARATUS - An MRI apparatus has a gantry, a bed and a lighting unit collective including a plurality of lighting units. The gantry accommodates a static field magnet configured to generate a static field, a gradient coil configured to generate a gradient magnetic field, and an RF coil configured to transmit or receive an RF pulse as well as having an opening into which a person is inserted. The bed has a removable table-top for an inside and an outside of the opening. The lighting unit group is disposed at at least one of an inside position of the opening and an outside position from which an inside of the opening can be lighted so that the lighting units can carry out lighting such that an amount of emitting light increases bit by bit from a bedside to a counter bedside opposite to the bedside across the opening. | 2008-08-28 |
20080204018 | METHOD AND MAGNETIC RESONANCE APPARATUS FOR SETTING A SHIM TO HOMOGENIZE A MAGNETIC FIELD IN THE APPARATUS - In a method for determination or adaptation of a shim for homogenization of a magnetic field of a magnetic resonance apparatus, which magnetic field is provided for the generation of magnetic resonance exposures of a specific examination region, an automatic determination, of a computer and/or supported by an operator on an image output unit of the computer, is made of a three-dimensional volume that is relevant for the determination or adaptation of the shim and that is matched to the examination region and/or an examination protocol by selection from an arbitrary morphology set of selectable volumes (which morphology set is not limited to specific shapes) and/or by generation of an arbitrarily three-dimensional volume not limited to specific shapes. The computer then automatically calculates the shim for the determined or selected three-dimensional volume. | 2008-08-28 |
20080204019 | HIGH FIELD MAGNETIC RESONANCE IMAGING APPARATUS AND METHOD FOR OBTAINING HIGH SIGNAL-TO-NOISE BY ITS RECEIVING COIL - In a high field magnetic resonance imaging apparatus and a method for obtaining signals having a high signal-to-noise ratio with the receiving coil thereof, the apparatus has at least a basic magnet and a receiving coil, the basic magnet generating a basic magnetic field, and the receiving coil being disposed within the basic magnetic field and forming an accommodating cavity. The accommodating cavity of the receiving coil is perpendicular to the direction of the basic magnetic field and is positioned in the field of view of the apparatus. The receiving coil is a loop type coil. The apparatus can further have a bracket for fixing the receiving coil. In the method, a receiving coil is used to receive signals in a magnetic field, wherein the receiving coil is perpendicular to the direction of the magnetic field. By using the apparatus and the corresponding method since the receiving coil can have a loop type design, the signal-to-noise ratio is increased. Moreover, the receiving coil can be disposed at a position closer to the center of the field of view, so that the imaging quality is improved. | 2008-08-28 |
20080204020 | Method for Magnetic Resonance Imaging - A method of magnetic resonance imaging based on rapid acquisition by sequential excitation and refocusing is provided. The method comprises turning on a first time-encoding gradient and applying an excitation pulse in the presence of the first time-encoding gradient. The excitation pulse excites magnetization sequentially along one spatial axis. Thereafter, a first refocusing pulse is applied. A second time-encoding gradient is turned on followed by a second refocusing pulse. A third time-encoding gradient is turned on and a signal is acquired in the presence of the third time-encoding gradient. The third time-encoding gradient sums to zero with the first time-encoding gradient and the second time-encoding gradient for sequential points in space. | 2008-08-28 |
20080204021 | Flexible and Wearable Radio Frequency Coil Garments for Magnetic Resonance Imaging - A radio frequency apparatus for at least one of (i) receiving and (ii) exciting a magnetic resonance signal includes an item of clothing ( | 2008-08-28 |
20080204022 | Biological detector and method - A biological detector includes a conduit for receiving a fluid containing one or more magnetic nanoparticle-labeled, biological objects to be detected and one or more permanent magnets or electromagnet for establishing a low magnetic field in which the conduit is disposed. A microcoil is disposed proximate the conduit for energization at a frequency that permits detection by NMR spectroscopy of whether the one or more magnetically-labeled biological objects is/are present in the fluid. | 2008-08-28 |
20080204023 | MAGNETIC RESONANCE IMAGING APPARATUS FOR SCANNING THE SPINE - The present invention discloses a magnetic resonance imaging apparatus for scanning a spine, comprising a body coil for emitting signals, a patient table within the body coil and a spine coil for receiving signals, wherein said spine coil is fixed within said body coil and disposed under said patient table. Said patient table is movable within said body coil by slide rails fitted at the two sides thereof, so as to reduce the length of said spine coil. The cross section of said patient table is in an arched shape, and the cross section of said spine coil is in an arched shape which matches that of said patient table. By using the apparatus of the present invention, since the spine coil is disposed underneath the board of the patient table, the design and production of the board of the patient table are simplified, the number of radio frequency choke coils and radio frequency element units is reduced and so are the costs; also, the space for the patient is increased, so the patient's comfort is improved; and furthermore, the repeated plugging and unplugging of the spine coil, as in the prior art, are avoided so as to reduce the probability of damaging the coil. | 2008-08-28 |
20080204024 | METHOD OF REDUCING EDDY CURRENTS CAUSED BY A GRADIENT MAGNETIC FIELD IN A MAGNETIC RESONANCE SYSTEM - A method for reducing eddy currents caused by the gradient magnetic field in a magnetic resonance system employs an anti-eddy current device formed by a number of laminated metallic plates, and includes the steps of calculating the distribution of the main magnetic field of the magnetic resonance system in the anti-eddy current device, calculating the distribution of the main magnetic field and the gradient magnetic field in the anti-eddy current device, subtracting the calculated distribution of the main magnetic field in the anti-eddy current device from the calculated distribution of the main magnetic field and the gradient magnetic field in the anti-eddy current device, to obtain the distribution of the gradient magnetic field in the anti-eddy current device, and adjusting the setting of the metallic plates of the anti-eddy current device based on the distribution of the gradient magnetic field in the anti-eddy current device, so as to reduce the eddy current. The adjustment in the metallic plates of the anti-eddy current device should be such that the gradient magnetic field is parallel to or substantially parallel to the plane of the metallic plates. The metallic plates can be further divided into a number of areas, or the laminating direction of the metallic plates in different areas can be adjusted according to the specific distribution of the gradient magnetic field to obtain the optimum effect of eddy current reduction. | 2008-08-28 |
20080204025 | Tool and Method for Shimming a Magnet - The invention provides tools and methods for shimming magnets such as MRI and NMR magnets, while at field. The invention provides safe methods for shimming at field. The invention particularly provides a tool ( | 2008-08-28 |
20080204026 | NMR SPECTROMETER - An object of the present invention is to solve the bending of an NMR probe and a room temperature shim coil so that they can be positioned easily. In the NMR spectrometer including split-pair magnets and a cross bore, a high rigidity straight pipe to which an NMR probe and a room temperature shim coil are attached so as to make an integral object, is provided. The outer diameter of the straight pipe is smaller than the inner diameter of a horizontal bore into which the room temperature shim coil and the probe are inserted. After the room temperature shim coil and the NMR probe are attached to the straight pipe by bolts, respectively, the integral object is inserted into the horizontal bore (a room temperature space) of the NMR spectrometer. The room temperature shim coil and the probe may be attached to different straight pipes. | 2008-08-28 |
20080204027 | Magnetic Resonance Receive Coil with Dynamic Range Control - A radio frequency receive coil ( | 2008-08-28 |
20080204028 | MAGNETIC RESONANCE COIL SYSTEM - A magnetic resonance coil system | 2008-08-28 |
20080204029 | LED CHAIN FAILURE DETECTION - The system consists of an LED failure detection circuit to provide protection against individual LED catastrophic failure. When LED clusters are arranged in a series-parallel configuration, it is important to detect individual LED failure in order to avoid uncontrolled luminous intensity reduction and/or light uniformity degradation. The circuit compares the voltage levels on LEDs with similar position but situated in different chains. In normal conditions, the voltage levels are substantially similar to one another. In case of individual or multiple LED failure, open or shortcircuit, the circuit sends a signal to the automatic turn off circuit that initiates the lamp forced turn off sequence. | 2008-08-28 |
20080204030 | Battery tester with promotion feature - Battery maintenance equipment is provided for use in maintaining storage batteries. The battery maintenance equipment includes battery maintenance circuitry. A redemption code output is provided and configured to provide an output having a redeemable value in response to the battery maintenance circuitry. A method includes outputting a redemption code in response to usage of battery maintenance equipment. | 2008-08-28 |
20080204031 | METHOD AND APPARATUS FOR DETERMINING DETERIORATION OF SECONDARY BATTERY, AND POWER SUPPLY SYSTEM THEREWITH - A method for detecting SOC and SOH of a storage battery includes: calculating an SOC value of the storage battery with use of an SOC calculation unit based on a measured voltage value or a measured current value of the storage battery and calculating an SOH value of the storage battery with use of an SOH calculation unit based on the SOC value; further calculating a new SOC value with use of the SOC calculation unit based on the SOH value and calculating a new SOH value with use of the SOH calculation unit based on the new SOC value, these further calculations of SOC value and SOH value being repeated a prescribed n times of at least one so as to obtain an nth calculated SOC value and an nth calculated SOH value; outputting the nth calculated SOH value as an SOH output value and outputting the nth calculated SOH value as an SOC output value; and storing the SOH output value into a memory. | 2008-08-28 |
20080204032 | Electrical connector Integrity Tester - This invention provides an electric fuel pump tester that allows a technician to simulate the real-life operation of the electrical system of the vehicle, i.e., when the fuel pump is installed. The present invention provides a tester that includes a load that is similar to that of an installed fuel pump. In this manner, a technician may monitor simulated real-life operation of the vehicle's electrical system. | 2008-08-28 |
20080204033 | Integrated Circuit and Method for Monitoring and Controlling Power and for Detecting Open Load State - An integrated circuit and method for monitoring and controlling power and for identifying an open circuit state at an output port is disclosed. A minimum open circuit current value of the output port is known. A steady state current at the output port is measured for a selected number of times at selected time intervals. A subset of the steady state current values are selected and an average current value is calculated. The average current value is compared to the minimum open circuit current value (if no loads detected) or to a learned open circuit current value (if a load or trailer is detected). A possible open circuit state at the output port is reported based on the comparison. | 2008-08-28 |
20080204034 | Automated Electrical Wiring Inspection System - The present invention is directed to an electrical wiring inspection system that includes a user interface device including processor circuitry, a user interface, and a first communications interface. The first communications interface is configured to transmit configuration data related to a plurality of electrical test procedures and receive test data corresponding to a plurality of electrical parameters. A branch circuit analysis device is configured to be coupled to the user interface device via the first communications interface and at least one branch circuit by at least one test connector. The branch circuit analysis device includes processor circuitry, branch circuit test circuitry configured to perform one or more of the plurality of electrical test procedures, and a second communications interface configured to transmit and receive configuration data related to a plurality of electrical test procedures and transmit and receive test data corresponding to a plurality of electrical parameters. A panel interface device is configured to be coupled to a load center panel and the branch circuit analysis device via the second communications interface. The panel interface device includes processor circuitry and load center test circuitry configured to perform one or more of the plurality of electrical test procedures. | 2008-08-28 |
20080204035 | FAULT DETECTION CIRCUIT FOR PRINTERS WITH MULTIPLE PRINT HEADS - A fault detector apparatus for a printer having a first print head and a second print head with a plurality of print head elements in each print head is disclosed. The apparatus includes a test circuit in signal communication with all the print heads to test the plurality of print head elements. The test circuit includes a test power supply for generating a test voltage, a first resistor, a second resistor, and an analog to digital converter in signal communication with the second resistor. The first resistor is in series connection between the test power supply and the plurality of elements in the first print head. The second resistor in series connection with the test power supply, the first resistor, and the plurality of elements in the second print head. The fault detector apparatus will also work for a printer with only one print head. | 2008-08-28 |
20080204036 | Pulse-generating apparatus and a method for adjusting levels of pulses outputted from pulse-generating apparatus - A pulse-generating apparatus, comprising a pulse source, an output terminal to which pulses from the pulse source are supplied, and a measuring device for measuring the level of a pulse that will be output from the output terminal at a pre-determined time position; a pulse-generating apparatus, further comprising a device for adjusting the level of the pulse that will be output at the pre-determined time position, based on at least the measured pulse level and the reference pulse level at the pre-determined time position; and a pulse-generating apparatus, wherein the pulse source generates pulses based on at least one parameter, and the adjusting device adjusts the level of the pulse that will be output by updating the parameter, changing the amount of amplification of the amplifier of the pulse source, or changing the amount of attenuation of the attenuator of the pulse source. The parameter may include at least one of the load impedance and the pulse level. | 2008-08-28 |
20080204037 | Multilayer wiring board and method for testing the same - A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. The ceramic substrate has an internal conductor layer, which is connected to a test pad. The first conductor layer is formed, and then an electric capacitance is measured between the test pad and a wiring pattern of the first conductor layer. On the other hand, an electrical capacitance is calculated under the normal wiring pattern condition. The measured value is compared to the calculated value to determine whether the wiring pattern is good or bad. Similar measurements and comparisons are carried out for each of the second through fifth conductor layers to determine whether a three-dimensional wiring path is good or bad. As the ceramic substrate has an internal conductor layer, the electric capacitance of the wiring can be measured without an overall grounded layer in the multilayer wiring section, which is a characteristic part different from others among a variety of the multilayer wiring boards. | 2008-08-28 |
20080204038 | Multilayer wiring board and method for testing the same - A multilayer wiring board has a ceramic substrate, on which a multilayer wiring section is formed. One of the conductor layers has a grounded pattern. Each of the conductor layers has a reference pattern, which is usable as a standard in calculation of an electric capacitance. An electric capacitance is measured between the grounded pattern and the three-dimensional wiring path. On the other hand, a theoretical electrical capacitance is calculated on the basis of a reference value of electric capacitance which has been measured between the reference pattern and the grounded pattern. The measured value for the wiring path is compared to the calculated value to determine whether the three-dimensional wiring path is good or bad. As the multilayer wiring section has the reference patterns, the electric capacitance for the normal wiring path can be obtained by calculation without preparing the normal acceptable product. | 2008-08-28 |
20080204039 | Self Calibration Apparatus And Methods - The present invention is a method to allow a vector network analyzer (VNA) to self calibrate without the addition of calibration standards, e.g. a calibration kit with a network analyzer. | 2008-08-28 |
20080204040 | Systems and arrangements for determining properties of a transmission path - One disclosed method is to automate testing for transmission path impedance conditions on a circuit board. The method can include transmitting a plurality of electrical pulses on a transmission path utilizing an on-board transmitter, the electrical pulses can have a time period and the transmission path can have impedance mismatches to reflect energy of the electrical pulse back towards the on-board transmitter. After the pulse is transmitted, a voltage of the reflected energy can be compared with a reference voltage at different time intervals. A single bit can be acquired for each voltage/time sample and the bits can be sequentially stored in a shift register. The digital data that is stored in the shift register can be compared to existing data in memory to determine a quality of the transmission path of the printed circuit board. | 2008-08-28 |
20080204041 | Differential Vector Network Analyzer - A measurement and correction method provides for a complete full correction of a true-mode system using only the single ended error matrix developed for 4 port correction of single ended measurements. The degree of misalignment of the balanced sources may be determined from these measurements. | 2008-08-28 |
20080204042 | NETWORKED POWER LINE PARAMETER ANALYSIS METHOD AND SYSTEM - A method and apparatus is disclosed for determining power line parameter of a system. Specifically, there is provided a system for determining comprising a networked device including a voltage perturbation circuit coupled to a voltage source and configured to perturb the waveform of the voltage source, and a voltage measurement circuit coupled to the voltage source and configured to transmit voltage measurements of the waveform over a network and a remote monitoring unit, coupled to the network, and configured to receive the voltage measurements over the network and to calculate an incident energy using the voltage measurements. | 2008-08-28 |
20080204043 | Real-Time Assessment of Biomarkers for Disease - A system and methods, thereof, monitor biomarkers from a patient suffering from neural injury in real-time. The system comprises a quartz crystal microbalance wherein a capture molecule specific for certain biomarkers is diagnostic of the type of neural injury, location of neural injury and the degree of severity of neural injury. The system, in particular, provides real-time continuous monitoring of a patient. | 2008-08-28 |
20080204044 | Method for detecting islanding operation of a distributed generator - An exemplary method comprises the steps of introducing a reactive current reference square wave, detecting load voltage changes at every change in the reactive current reverence wave, and determining whether the detected load voltage changes exceed a predefined islanding detection threshold value, indicating a loss of mains and an islanding operation of the power generator. With the exemplary loss-of-mains detection, islanding can be detected within a shortest period of time, even if the local islands active and reactive load matches exactly the distributed generators active and reactive power generation. So even without a sudden voltage change, unintentional islanding can immediately be detected and control electronics can safely turn of the distributed power generator. | 2008-08-28 |
20080204045 | Apparatus and method for measuring the current consumption and the capacitance of a semiconductor device - A measuring apparatus is provided which has least one voltage source for providing a supply voltage for a semiconductor device to be tested, at least one first tester channel connected to the supply voltage source via a first RC element having a first resistor and a first capacitor connected in series therewith, wherein the first tester channel is adapted for the temporally resolved measurement of a charging voltage of the first capacitor. | 2008-08-28 |
20080204046 | Capacitance Measurement Apparatus and Method - A time period of an event is determined by charging a known value capacitor from a constant current source during the event. The resultant voltage on the capacitor is proportional to the event time period and may be calculated from the resultant voltage and known capacitance value. Capacitance is measured by charging a capacitor from a constant current source during a known time period. The resultant voltage on the capacitor is proportional to the capacitance thereof and may be calculated from the resultant voltage and known time period. A long time period event may be measured by charging a first capacitor at the start of the event and a second capacitor at the end of the event, while counting clock times therebetween. Delay of an event is done by charging voltages on first and second capacitors at beginning and end of event, while comparing voltages thereon with a reference voltage. | 2008-08-28 |
20080204047 | Capacitive Sensor System - The present invention relates to a capacitive sensor system provided for a moving object | 2008-08-28 |
20080204048 | Free-standing nanowire sensor and method for detecting an analyte in a fluid - A sensor device and method for detecting the presence of an analyte in a fluid solution are disclosed. The sensor device system can comprise a substrate and an array of free-standing nanowires attached to the substrate. The array can include individual free-standing nanowires wherein each of the individual free-standing nanowires have a first end and a second end. The first end can, in some embodiments, be attached to the substrate and the second end unattached to the substrate. Such individual free-standing nanowires are configured for electrical communication with other individual free-standing nanowires through the first end. A chip or computer can be electrically coupled to the array of free-standing nanowires for receiving electrical information from the array of free-standing nanowires. In some embodiments a power source can be used to send current through the nanowire array. | 2008-08-28 |
20080204049 | Microprocessor-Based Capacitance Measurement - An improved system and method of performing capacitance measurements that provides a fast digital response and a reduced output error. The capacitance measurement system includes a circuit configuration that has a variable capacitor and at least one reference capacitor connected to one another at a common node, which in turn is connected to the input of an analog-to-digital converter. The circuit configuration further includes an array of switches coupled between the variable and reference capacitors and the supply voltage, a reference voltage, and ground, respectively, The switched variable and reference capacitors are employed in conjunction with the A-to-D converter to perform, at the common node, a plurality of voltage measurements for use in generating an expression defining the capacitance of the variable capacitor, The generated expression of variable capacitance is independent of a number of specified output error sources including but not limited to a sample-and-hold capacitance, the parasitic capacitance at the input of the A-to-D converter, a sample-and-hold offset voltage, and the leakage current at the input of the A-to-D converter. | 2008-08-28 |
20080204050 | Method of Measuring Electronic Device and Measuring Apparatus - In a method for measuring an electronic device which is an object to be measured, a passive element is connected to the electronic device in parallel, and electric parameters of the electronic device are extracted by measuring an impedance of the entire circuit. | 2008-08-28 |
20080204051 | CAPACITIVE SENSOR - A capacitive sensor with at least one reference impedance and at least one measuring condenser ( | 2008-08-28 |
20080204052 | INTEGRATED CIRCUIT SYSTEM WITH MOS DEVICE - An integrated circuit system includes measuring capacitance for a base structure between a base gate and a base connector thereof, measuring capacitance for a test structure between a test gate and a test connector thereof, the test structure having the test gate, a test dielectric, and the test connector with the test dielectric extending thereunder, and determining a difference between the capacitances of the base structure and the test structure to determine parasitic capacitance for the base structure between the base gate and the base connector thereof. | 2008-08-28 |
20080204053 | CONTROL CIRCUIT FOR CLOCKED CONTROL OF AT LEAST ONE LIGHT EMITTING DIODE - A control circuit includes a clock pulse generator operable to output a pulse-frequency ratio to a constant voltage source in order to control the power output of the constant voltage source. The control circuit further includes a driver circuit for the clocked control of at least one light emitting diode (LED) to which a measurement resistor is connected in parallel. The LED is supplied with power by the constant voltage source. The LED is turned on when the power is greater than a forward power level and is turned off when the power is less than the forward power level. The driver circuit taps a measurement voltage of the measurement resistor while the LED is supplied with power less than the forward power level. The clock pulse generator varies the pulse-frequency ratio as a function of the measurement voltage of the measurement resistor. | 2008-08-28 |
20080204054 | Impedance Measurement of a Power Line - A system for obtaining an accurate, real-time determination of the characteristic impedance of a length of a power line measures the operating conditions (e.g., voltage and current) for at least two locations on the power line. These measurements are synchronized so that they represent the same instant of time. The data obtained from the synchronized measurements are fitted to a circuit model of the power line to obtain a characteristic impedance for the power line according, which can be used to increase the efficiency of the use of the power line and to perform real-time assessment of the power line. | 2008-08-28 |
20080204055 | CROSSTALK SUPPRESSION IN WIRELESS TESTING OF SEMICONDUCTOR DEVICES - An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die. | 2008-08-28 |
20080204056 | DEVICE AND METHOD FOR PERFORMING A TEST OF SEMICONDUCTOR DEVICES WITH AN OPTICAL INTERFACE - A device and method for performing a test of semiconductor devices with an optical interface. In one embodiment, the device performs a test at a semiconductor device with an integrated self test function and with an optical interface. An optical transmitter and an optical receiver provide a system configured for returning an optical emission of the semiconductor device from the optical transmitter to the optical receiver of the semiconductor device. | 2008-08-28 |
20080204057 | SYSTEM AND METHOD FOR ESTIMATION OF INTEGRATED CIRCUIT SIGNAL CHARACTERISTICS USING OPTICAL MEASUREMENTS - Systems and methods for making electrical measurements using optical emissions include positioning a sensor/photodetector to measure radiation emissions from devices to be tested. Radiation emission information is collected from the device to be tested during electrical operation. Characteristic features of the radiation emission information are determined, and differences between the characteristic features are deciphered. Based on the differences, models are employed to determine electrical properties of the device, especially operational characteristics. | 2008-08-28 |
20080204058 | Probe Storage Container, Prober Apparatus, Probe Arranging Method and Manufacturing Method of Probe Storage Container - An object of the present invention relates to an arrangement of a manufactured probe in a prober apparatus without being exposed to an atmospheric air. | 2008-08-28 |
20080204059 | Probe Tile for Probing Semiconductor Wafer - A tile used to hold one or more probes for testing a semiconductor wafer is disclosed. The tile has one or more sites for inserting one or more probes to test the semiconductor wafer. Each site has one or more holes. Each hole is coupled with a slot forming an angle. A probe is inserted into the tile from a top of the tile through the hole and seated on the slot. The probe has a probe tip. The probe top is in contact with the semiconductor wafer at one end of the slot at a bottom of the tile. The probe tip is aligned with an X and Y coordinate of a bond pad on the semiconductor wafer. | 2008-08-28 |
20080204060 | Vertical-Type Electric Contactor And Manufacture Method Thereof - A vertical-type electric contactor connected to a bump of an electric contactor is provided. The vertical-type electric contactor includes a support beam, vertically bonded with the bump, in which at least two elastic parts are spaced apart from each other; a fixed part disposed at the bottom end of the support beam for fixing the support beam; and a tip part disposed at the bottom end of the fixed part, the tip part and the fixed part being a single body. According to the vertical-type electric contactor, a reaction force generated at a tip part is effectively distributed to test electric devices without damage of the vertical-type electric contactor. | 2008-08-28 |
20080204061 | Spring loaded probe pin assembly - A method and apparatus for constructing a probe card assembly is provided. A probe pin is inserted into an aperture of an inverted socket enclosure to cause a probe pin shoulder of the probe pin to make contact with an aperture shoulder of the aperture. An upper end of the probe pin protrudes from the aperture after the probe pin shoulder makes contact with the aperture shoulder. A compressible member is inserted into the aperture to position an upper end of the compressible member to make contact with a lower portion of the probe pin. A substrate is aligned over the inverted socket enclosure so that the lower end of the compressible member is in contact with a substrate contact located on the substrate. The substrate is affixed in a non-permanent manner to the inverted socket enclosure. | 2008-08-28 |
20080204062 | Cantilever probe card - A method and apparatus for a flattened probe element wire is provided. A probe element wire comprises a beam portion and a tip portion. At least a part of the tip portion is flattened. Flattened probe element wires may have greater z-direction height strength, thereby increasing maximum probe element wire z-direction vertical force. Flattened probe element wires may also have decreased variability in the flattened probe element wire tips. A probe card assembly may comprise a substrate and a plurality of at least partially flattened probe element wires supported by the substrate. Such probe card assemblies may have an extended life and maintained within design parameters for a longer period of use. | 2008-08-28 |
20080204063 | Testable Intergrated Circuit - An integrated circuit ( | 2008-08-28 |
20080204064 | TEST SYSTEM AND HIGH VOLTAGE MEASUREMENT METHOD - Provided are a test system and a related high voltage measurement method. The method includes applying an external voltage signal to one or more of a plurality of DUTs via the shared channel, comparing the external voltage signal with a high voltage signal internally generated by the one or more DUTs and generating a corresponding comparison result, and determining a voltage level for each respective high voltage signal in accordance with the comparison result. | 2008-08-28 |
20080204065 | FAULT TOLERANT SELECTION OF DIE ON WAFER - In a functional mode, the functional core logic of a die is connected to the input and output pads and the die performs its intended function. In a bypass mode, the input and output buffers of the functional core logic are disabled and pad sites of corresponding position between a first set of opposite sides and between a second set of opposite sides are electrically connected. In bypass mode the die is transformed into a simple interconnect structure between the first sides and between the second sides. The interconnect structure includes plural conductors extending substantially parallel to one another between the first sides and further plural conductors extending substantially parallel to one another between the second sides. While in bypass mode, signals from a tester apparatus can flow through the conductors between the first sides and between the second sides to access and test a selected die on a wafer. | 2008-08-28 |
20080204066 | Automatic test equipment capable of high speed test - Automatic test equipment is capable of performing a high-speed test of semiconductor devices, with a low cost and high efficiency. The automatic test equipment (ATE) comprises: an ATE body configured to electrically test semiconductor devices; a field programmable gate array (FPGA) controlling drivers and comparators on the ATE; an accelerator connected to an output terminal of the FPGA and that doubles an operating frequency of the FPGA; and a decelerator connected to an output terminal of the FPGA and that converts an operating frequency of data transferred from the semiconductor device to the operating frequency of the FPGA. | 2008-08-28 |
20080204067 | SYNCHRONOUS SEMICONDUCTOR DEVICE, AND INSPECTION SYSTEM AND METHOD FOR THE SAME - The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit. | 2008-08-28 |
20080204068 | METHOD FOR ESTIMATING DEFECTS IN AN NPN TRANSISTOR ARRAY - A method for testing bipolar transistors in an integrated circuit includes first measuring first conductances of leakage paths between collectors and emitters of a first plurality of bipolar transistors with a known number of defects, calculating a per defect conductance value using the measured first conductances and the known number of defects to derive the linear relation. The method then measures second conductances of leakage path between collectors and emitters of a second plurality of bipolar transistors under test and having an unknown number of defects. Using the measured leakage path current from the second conductances and the linear relation, the number of defects related to the second plurality of bipolar transistors under test may be accurately determined. | 2008-08-28 |
20080204069 | Electronic Module With Organic Logic Circuit Elements - The invention relates to an electronic module having two or more organic circuit elements connected together to give a logic circuit, said organic circuit elements being made up of organic components, in particular organic field effect transistors. The logic circuit comprises at least one filter module ( | 2008-08-28 |
20080204070 | Reduced power output buffer - A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor. | 2008-08-28 |
20080204071 | On-die termination circuit, method of controlling the same, and ODT synchronous buffer - An on-die termination (ODT) circuit may include an ODT synchronous buffer and/or an ODT gate. The ODT synchronous buffer may be configured to generate a synchronous ODT command from an external ODT command in synchronization with a first clock signal delay-locked to an external clock signal. The ODT gate may be configured to generate signals for controlling ODT based on a second clock signal delay-locked to the external clock signal and the synchronous ODT command. The synchronous ODT command may be generated in a disabled period of the second clock signal. | 2008-08-28 |
20080204072 | Programmable Logic Device - The invention relates to a connector ( | 2008-08-28 |
20080204073 | REDUNDANT CONFIGURATION MEMORY SYSTEMS AND METHODS - Systems and methods are disclosed directed to techniques with respect to defective configuration memory cells. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a plurality of configuration memory cells; and at least one spare memory cell, wherein the at least one spare memory cell is adapted to store configuration data to provide to at least one defective configuration memory cell. | 2008-08-28 |
20080204074 | DEDICATED INTERFACE ARCHITECTURE FOR A HYBRID INTEGRATED CIRCUIT - An interface design for a hybrid IC that utilizes dedicated interface tracks to allow signals to interface distributively with the logic blocks of the FPGA portion providing for faster and more efficient communication between the FPGA and ASIC portions of the hybrid IC. | 2008-08-28 |
20080204075 | INTERFACING OF CIRCUITS IN AN INTEGRATED ELECTRONIC CIRCUIT - An interface having internal conductors to transfer data between a sending circuit and a receiving circuit in an integrated electronic circuit, the receiving circuit including an input buffer capable of receiving data and an output terminal for sending to the sending circuit an item of extraction information on each extraction of a data word from the input buffer, and the sending circuit including an enable circuit capable of activating an enable signal according to an item of availability information representative of the memory space available in the input buffer. The item of availability information is updated in the sending circuit on each transmission of a data word or on each receipt of the item of extraction information. | 2008-08-28 |
20080204076 | Integrated Circuit and a Method For Designing a Boundary Scan Super-Cell - A method for designing an integrated circuit, the method includes: providing an initial definition of a boundary scan register that includes identical super-cells adapted to be connected to multiple pin types; and determining the configuration of each super-cell by providing at least one pin type indication signal to each super-cell. An integrated circuit that includes a boundary scan super-cell, the boundary scan super-cell includes first circuitry adapted to be connected to at least one type of integrated circuit pin; characterized by further including a second circuitry, connected to first circuitry, wherein the second circuitry is adapted to receive at least one pin type indication signal and in response allows the boundary scan super-cell to be connected to at least one additional type of an integrated circuit pin. | 2008-08-28 |
20080204077 | LEVEL SHIFTER - A level shifter for shifting an input signal to an output signal. The level shifter includes an input buffer biased a first voltage and a ground voltage; an output buffer and a level-processing unit both biased between a second voltage and the ground voltage; and a voltage-drop unit coupled to the level-processing unit and biased between the first voltage and the second voltage. While the first voltage is in an OFF state and the second voltage is switched on, the voltage-drop unit provides an initializing voltage for the level-processing unit according to the second voltage to shift the input signal to provide the output signal. | 2008-08-28 |
20080204078 | LEVEL SHIFTER FOR PREVENTING STATIC CURRENT AND PERFORMING HIGH-SPEED LEVEL SHIFTING - A level shifter amplifies a voltage of a digital signal to a predetermined voltage and outputs the amplified signal. The level shifter is capable of preventing generation of static current, and performing high-speed level shifting by increasing the speed of charging electric charges into or discharging electric charges from an output terminal of a differential amplification circuit included in the level shifter. | 2008-08-28 |
20080204079 | Level shifting circuits for generating output signals having similar duty cycle ratios - A level shifting circuit includes a level shifting unit and an output buffer unit. The level shifting unit generates first and second output signals responsive to first and second input signals. The first and second input signals range between first and second voltage levels, and the first and second input signals are a first differential pair. The first and second output signals range between the first voltage level and a third voltage level greater than the second voltage level, and the first and second output signals are a second differential pair. The output buffer unit inverts the first and second output signals to provide third and fourth output signals, respectively. Duty ratios of the first and second output signals are determined based on delay times of the first and second input signals. | 2008-08-28 |
20080204080 | Mobile circuit robust against input voltage change - An inverting flip-flop (F/F) circuit type monostable-bistable transition logic element (MOBILE) circuit that uses resonant tunneling diodes (RTDs) and can prevent a malfunction caused by low peak-to-valley current ratio (PVCR) characteristics of the RTD includes an input data conversion circuit and an inverting F/F circuit. The input data conversion circuit receives input data and converts a logic level of the input data according to a logic level of output data of the MOBILE circuit. The inverting F/F circuit inverts a logic level of data output from the input data conversion circuit and outputs the output data. Accordingly, even when a logic level of input data changes from LOW to HIGH, the logic level of output data can be maintained HIGH in the inverting F/F type MOBILE circuit constructed using silicon semiconductor based RTDs with a small PVCR. Therefore, it is possible to enhance the performance of the inverting F/F circuit type MOBILE circuit. | 2008-08-28 |
20080204081 | Clock gated circuit - A clock gated circuit includes a clock signal receiving unit that applies a first voltage to a fighting node when the clock signal is at a first logic; a discharging unit that discharges an electric charge from the fighting node when the clock signal is transitioned from the first logic to a second logic and when the enable signal is activated; a voltage maintaining unit that maintains the fighting node at a power or ground voltage; and an output unit that inverts a logic level of the fighting node to generate the gated clock signal. A blocking unit can be included that blocks a power voltage from being provided to the fighting node by the voltage maintaining unit when discharging. A blocking transistor can be included that prevents unnecessary electric charge from inflowing into the fighting node to reduce power consumption and discharging time. | 2008-08-28 |
20080204082 | Apparatus And Method For Generating A Constant Logical Value In An Integrated Circuit - An apparatus for generating a constant logical value in an integrated circuit includes a first logic network having n outputs, the n outputs providing 2 | 2008-08-28 |
20080204083 | Voltage Comparator - Output currents from differentially connected transistors (t | 2008-08-28 |
20080204084 | LOW HEAT DISSIPATION I/O MODULE USING DIRECT DRIVE BUCK CONVERTER - A current-loop output circuit for an industrial controller provides for low power dissipation and reduced part count by driving current loads of different resistances directly from a switched voltage source. Proper filtering and design of a feedback loop allows the necessary transient response times to be obtained. | 2008-08-28 |
20080204085 | Photodetector - An I/F converter | 2008-08-28 |
20080204086 | APPARATUS FOR DRIVING SOURCE LINES AND DISPLAY APPARATUS HAVING THE SAME - An apparatus for driving source lines includes an output buffer, a first switch and a second switch. The output buffer outputs a first voltage and a second voltage having an opposite phase to the first voltage during an output interval including a first interval portion and a second interval portion. The first switch applies the first and second voltages to an m-th source line and an (m+1)-th source line respectively during the first interval portion and blocks the first and second voltages during the second interval portion. The second switch includes a plurality of switching elements, the second switch short-circuiting the m-th source line and the (m+1)-th source line during the second interval portion, wherein the m-th source line has at least two connecting portions to be electrically connected to the (m+1)-th source line. | 2008-08-28 |
20080204087 | METHOD AND CIRCUIT ARRANGEMENT CONFIGURED FOR DRIVING A FIELD-EFFECT-CONTROLLED TRANSISTOR - A method and circuit arrangement including driving a field effect controlled transistor. One embodiment provides a first load terminal, a second load terminal and a control terminal. The control terminal is driven, at least during a Miller plateau phase of the transistor, with a pulse-width-modulated control signal whose period duration is shorter than the duration of the Miller plateau phase. | 2008-08-28 |
20080204088 | HIGH-SPEED DIVIDER WITH REDUCED POWER CONSUMPTION - A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-width control circuits responsive to at least one signal having a second pulse width. The method includes selecting at least one of the plurality of pulse-width control circuits to be powered-on to generate the at least one signal. The at least one of the plurality of pulse-width control circuits includes a first pulse-width control circuit to generate a first signal having the first pulse-width, second frequency, and first phase. The first signal corresponds to a select circuit output signal having a first phase. The method includes selecting at least one other of the plurality of pulse-width control circuits to be powered-off. | 2008-08-28 |
20080204089 | Dynamic frequency dividing circuit operating within limited frequency range - A frequency dividing circuit has a master circuit and a slave circuit, and a load section in at least either one of the master and slave circuits is constructed to provide an impedance that decreases with increasing frequency. | 2008-08-28 |
20080204090 | Glitch-free clock regeneration circuit - A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector detecting an edge of the output of the meta-stability filtering circuit, a regenerated clock signal output therefrom, and a clock regeneration stage receiving an input that is the edge-detected output. | 2008-08-28 |
20080204091 | Semiconductor chip package and method for fabricating semiconductor chip - A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved. | 2008-08-28 |
20080204092 | Cicuit Arrangement, in Particular Phase-Locked Loop, as Well as Corresponding Method - In order to further develop a circuit arrangement ( | 2008-08-28 |
20080204093 | Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal - Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based on corresponding rising edges and corresponding falling edges of same-state signals operated on by the delay stages. Other circuits, systems, and methods are described. | 2008-08-28 |
20080204094 | Semiconductor memory device and method for driving the same - The present invention intends to provide a semiconductor memory device including a delay locked loop (DLL) circuit capable of generating a duty-corrected delay locked clock. A semiconductor memory device includes: a DLL circuit for generating a delay locked clock through a delay locked operation; and a duty-correction circuit for correcting a duty ratio of the delay locked clock by using the delay locked clock and a divided clock generated by dividing the delay locked clock by an even value. | 2008-08-28 |
20080204095 | METHOD AND APPARATUS FOR CONTROLLING POWER-DOWN MODE OF DELAY LOCKED LOOP - A method and apparatus for controlling a power-down mode of a delay locked loop (DLL), in which the apparatus includes a first switch unit, a DLL, and a second switch unit. The first switch unit transfers a first clock signal in response to a clock input enable signal. The DLL receives the first clock signal through the first switch unit to generate a second clock signal and is turned off by a power-down signal that is generated from the first clock signal latched by the first switch unit. The second switch unit transfers the second clock signal in response to a clock output enable signal. In a power-down mode, the clock input enable signal is deactivated in response to a clock enable signal and the clock output enable signal is deactivated after a predetermined number of clock cycles that are necessary for the latched first clock signal to be completely transferred through the delay cells of the DLL to an output terminal of the DLL. In a power-down exit mode, the power-down signal is deactivated in response to the clock enable signal and the clock input enable signal and the clock output enable signal are activated after a predetermined number of clock cycles that are necessary for the latched second clock signal to be completely transferred through the delay cells. Of the DLL to the output terminal of the DLL. | 2008-08-28 |
20080204096 | Circuit and method to convert a single ended signal to duplicated signals - A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes a buffer stage and at least one inverter stage. A second path of the two paths includes at least two inverter stages. The buffer stage has a delay matched to that of a first inverter stage of the second path. The buffer stage comprises a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series. | 2008-08-28 |
20080204097 | INVERTER BASED DUTY CYCLE CORRECTION APPARATUSES AND SYSTEMS - Apparatuses, circuits, and methods to reduce duty cycle errors are disclosed. Embodiments generally comprise buffer circuits coupled with error detection circuits and correction feedback circuits that sense duty cycles errors in output signals from the buffer circuits, generate error signals, and couple the error signals back to the inputs to correct or reduce the duty cycle errors. The error circuits may comprise active low pass filters in various embodiments, while amplifiers generally comprise inverter buffers or other simple buffers which alter or affect the input signals to the buffer circuits in order to reduce the duty cycle errors. In many system and apparatus embodiments, the error circuits comprise a resistor-capacitor circuit coupled with an inverter buffer. The error detection circuits generally function as active low pass filters and generate error signals for the feedback circuits. | 2008-08-28 |
20080204098 | Current sharing for multiphase power conversion - Current sharing scheme based on input power and/or the power efficiency for a power stage with multiple phases and/or paralleled modules is described. According to the scheme, duty cycles of different phases/modules may be adaptively adjusted until the minimum input power and/or the maximum power efficiency is achieved. For certain input voltages, the minimum input power exists at the minimum total input current. Thus, input power and/or the input current may be used as an indicator of the maximized power efficiency of the power stage and hence be used to track the optimal current sharing ratio among the multiple phases/modules. | 2008-08-28 |
20080204099 | Clock generator and clock duty cycle correction method - A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock to thereby output comparing signal; a DCC controller for outputting a DCC enable signal and a weight selection signal in response to the comparing signal and a first and a second lock state signal; a DCC mixing block for blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate a rising and a falling pre-clock signals; and a clock selector for selectively output the rising and the falling pre-clock signals in response to the weight selection signal. | 2008-08-28 |
20080204100 | Logic circuit - For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit. | 2008-08-28 |
20080204101 | Hysteresis characteristic input circuit including resistors capable of suppressing penetration current - In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input voltage. An inverter has an input connected to the connection point and an output adapted to generate an output voltage. A first switching element is connected in series to the second resistor, and a second switching element is connected in series to the second MOS transistor. The first and second switching elements are complementarily controlled by the output voltage. | 2008-08-28 |
20080204102 | METHOD TO REGULATE PROPAGATION DELAY OF CAPACITIVELY COUPLED PARALLEL LINES - Capacitive coupling between adjacent parallel lines in an integrated circuit is made more uniform and allows for better timing control of the lines through the use of inverters placed on one or both of the adjacent interconnect lines. By staggering the placement of inverters along adjacent lines, constructive and destructive coupling terms between the lines are balanced out. The propagation delay through the inverter is made less than the propagation delay through one half of the line length of the corresponding line. | 2008-08-28 |
20080204103 | Clock skew controller and integrated circuit including the same - A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output clock output from the first clock mesh and a second output clock output from the second clock mesh, a pulse width detector adapted to generate a digital signal corresponding to a pulse width of the pulse signal, and a clock delay adjuster adapted to delay one of the first and second clocks by a time corresponding to the digital signal | 2008-08-28 |
20080204104 | Clocking architecture in stacked and bonded dice - A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem with a clock signal generator. The distribution die is electrically connected through an interface technology, such as microbumps, to route the clock signals to the functional circuits on a separate functional die. Alternatively, the distribution die could be electrically connected to more than one die at a time, using vias through the distribution die to route the clock signals to the different die. This separate distribution die reduces the coupling between lines and also helps to prevent signal skew as the signal moves through the distribution network. | 2008-08-28 |
20080204105 | Power supply device, signal output apparatus and power supply method - A power supply device capable of suitably reducing a loss even in a case where power is supplied to an output device which outputs a high-frequency signal, a signal output apparatus in which a loss is suitably reduced, and a power supply method capable of suitably reducing a loss. The power supply device has a power supply section which supplies a power supply voltage to an output device which is supplied with the power supply voltage and outputs an output signal, and a voltage control section which controls the power supply section so that the power supply voltage follows the envelope of the output signal from the output device. | 2008-08-28 |
20080204106 | SIGNAL ADJUSTMENT TECHNIQUES - An apparatus includes a filter module, an amplification module, and an adjustment signal source. The filter module generates a filtered signal based on a received signal. This filtered signal has a level shift corresponding to a difference between a direct current (DC) level of the filtered signal and a DC level of the received signal. From the filtered signal and an adjustment signal, the amplification module generates an amplified signal. The adjustment signal, which is provided by the adjustment signal source, may control (e.g., diminish) an effect of the level shift on a DC level of the amplified signal. | 2008-08-28 |
20080204107 | MOS RESISTANCE CONTROLLING DEVICE AND MOS ATTENUATOR - A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N−1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors. | 2008-08-28 |
20080204108 | DE-EMPHASIS SYSTEM AND METHOD FOR COUPLING DIGITAL SIGNALS THROUGH CAPACITIVELY LOADED LINES - A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal. | 2008-08-28 |
20080204109 | High-performance level shifter - A level shifter is presented that allows fast switching while requiring low power. In accordance with some embodiments of the invention, the level shifter is a two stage level shifting circuit with p-channel and n-channel transistors biased so as to limit the potential between the source to gate or drain to gate of any of the transistors. Pull-up transistors are placed in a transition state so that spikes resulting from an increasing or decreasing input voltage turn on or off the pull up transistors to assist in the switching. | 2008-08-28 |
20080204110 | LEVEL SHIFT CIRCUIT - A level shift circuit for converting a first signal level into a second signal level, includes a load circuit connected to the second power supply voltage, a first high voltage-resistant transistor in which a drain is connected to the load circuit, and a predetermined constant voltage is applied to a gate, a source voltage control circuit controls a voltage level of the source of the first high voltage-resistant transistor in accordance with an input signal at the first signal level, and has a second low voltage-resistant transistor, and an output terminal which is connected between the drain of the first high voltage-resistant transistor and the load circuit for outputting an output signal at the second signal level. A gate insulating film of the low voltage-resistant transistor has a voltage resistance lower than that of a gate insulating film of the high voltage-resistant transistor. | 2008-08-28 |
20080204111 | HIGH-IMPEDANCE LEVEL-SHIFTING AMPLIFIER CAPABLE OF HANDLING INPUT SIGNALS WITH A VOLTAGE MAGNITUDE THAT EXCEEDS A SUPPLY VOLTAGE - A level-shifting amplifier is provided for level-shifting an input signal with a voltage magnitude that exceeds a supply voltage of the amplifier. In operation, the amplifier has an input impedance of greater than 100 MOhms. | 2008-08-28 |
20080204112 | MoCA-COMPLIANT MULTIPLEXING DEVICE - A multiplexing device complies with Multimedia over Coax Alliance (MoCA) specifications, and includes a circuit board disposed in a casing, first and second adapters disposed on the circuit board and adapted to be connected between an input end and an output end, and a shielding component. The first adapter includes a first low pass filter connected in series to a first high pass filter. The second adapter includes a second low pass filter connected in series to a second high pass filter. The shielding component is disposed on the circuit board between the first and second low pass filters, and has a height greater than that of the first and second adapters such that electromagnetic energy emitted by the first and second adapters is blocked to reduce undesired coupling between signals in the first and second adapters. | 2008-08-28 |
20080204113 | Ultra fine pitch I/O design for microchips - A microchip includes at least one I/O area surrounding at least one core circuit area. The I/O area further includes a first I/O cell having at least one first post-driver device connected to a first I/O pad; a second I/O cell having at least one second post-driver device connected to a second I/O pad; and an electrostatic discharge (ESD) cluster shared by the first I/O cell and the second I/O cell for protecting the same against ESD current during an ESD event, thereby reducing a total width of the first I/O cell and the second I/O cell. | 2008-08-28 |
20080204114 | TRANSMISSION GATE SWITCH, SYSTEM USING THE SAME, AND DATA INPUT/OUTPUT METHOD THEREOF - A transmission gate switch includes a switching unit to conduct a switching operation between first and second nodes in response to a switching signal, and an isolation unit to prevent the switching unit from being turned on by a negative swing of the first or second node while the switching unit is being turned off. | 2008-08-28 |
20080204115 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME, AND POWER CONVERSION APPARATUS INCORPORATING THIS SEMICONDUCTOR DEVICE - The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement of the steady loss of the wide-gap bipolar semiconductor element corresponding to the decrement of the built-in voltage lowering depending on the temperature rising of the wide-gap bipolar semiconductor element is larger than the increment of the steady loss corresponding to the increment of the ON resistance increasing depending on the temperature rising. | 2008-08-28 |