35th week of 2008 patent applcation highlights part 17 |
Patent application number | Title | Published |
20080203416 | SURFACE MOUNTING TYPE LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - This invention provides a surface mounting type light emitting diode excellent in heat radiation performance, reliability and productivity. The surface mounting type light emitting diode includes a metallic base member, a semiconductor light emitting element having a bottom face fixedly bonded to a top face of the base member, and a metallic reflector joined to the top face of the base member with a heat conduction type adhesive sheet interposed therebetween, to surround the semiconductor light emitting element. Heat generated from the semiconductor light emitting element is transferred to the reflector via the base member and the heat conduction type adhesive sheet, and then is radiated to the outside. The metallic reflector can efficiently radiate the heat to the outside. The cutting margin provided for the reflector facilitates a dicing process, which improves productivity. | 2008-08-28 |
20080203417 | SURFACE MOUNTING TYPE LIGHT EMITTING DIODE AND METHOD FOR MANUFACTURING THE SAME - This invention provides a surface mounting type light emitting diode excellent in heat radiation performance, reliability and productivity. The surface mounting type light emitting diode includes an insulating base member, a semiconductor light emitting element having a bottom face fixedly bonded to a top face of the base member, and a metallic reflector joined to the top face of the base member with a heat conduction type adhesive sheet interposed therebetween, to surround the semiconductor light emitting element. Heat generated from the semiconductor light emitting element is transferred to the reflector via the base member and the heat conduction type adhesive sheet, and then is radiated to the outside. The metallic reflector can efficiently radiate the heat to the outside. The cutting margin provided for the reflector facilitates a dicing process, which improves productivity. | 2008-08-28 |
20080203418 | Semiconductor Device - A semiconductor device comprises an active layer having a quantum well structure, the active layer including a well layer and a barrier layer and being sandwiched by a first conductivity type layer and a second conductivity type layer, wherein a first barrier layer is provided on side of the first conductivity type layer in the active layer and a second barrier layer is provided on the side of the second conductivity type layer in the active layer, at least one well layer is sandwiched thereby, and the second barrier layer has a band gap energy lower than that of the first barrier layer in the form of asymmetric barrier layer structure, where the second conductivity type layer preferably includes a carrier confinement layer having a band gap energy higher than that of the first barrier layer, resulting in a reverse structure in each of conductivity type layer in respect to the asymmetric structure of the active layer to provide a waveguide structure having excellent crystallinity and device characteristics in the nitride semiconductor light emitting device operating at a wavelength of 380 nm or shorter. | 2008-08-28 |
20080203419 | Semiconductor Light Emitting Apparatus - A semiconductor light emitting apparatus can be configured to reduce color variations and intensity variations with a simple configuration. The semiconductor light emitting apparatus can include a substrate having conductive members including chip mounting areas and electrode areas, a plurality of semiconductor light emitting device chips mounted in the chip mounting areas on the substrate, a reflector formed on this substrate so as to surround the semiconductor light emitting device chips, and a fluorescent material and a light diffusing material arranged distributedly inside this reflector. The semiconductor light emitting apparatus can be configured so that the semiconductor light emitting device chips emit light only from their top surfaces, and a first light transmitting resin containing the fluorescent material is applied only to the top surfaces of the semiconductor light emitting device chips. | 2008-08-28 |
20080203420 | Collective Substrate, Semiconductor Element Mount, Semiconductor Device, Imaging Device, Light Emitting Diode Component and Light Emitting Diode - A collective substrate ( | 2008-08-28 |
20080203421 | Structured Substrate For a Led - A substrate ( | 2008-08-28 |
20080203422 | Structure of light emitting diode and method to assemble thereof - A structure of a light emitting diode is provided. The light emitting diode comprises a light emitting diode die; two conductive frames electronically and respectively connecting to the cathode and anode of the light emitting diode die, and two substrates. Each conductive frame has a fixing hole and each substrate has a protrusive pillar. The upper opening of the fixing hole is broader than the bottom opening. The protrusive pillar is inserted into the fixing hole and the shape of the protrusive pillar is deformed for fitting and binding with the fixing hole. | 2008-08-28 |
20080203423 | LIGHT-EMITTING DIODE - A light-emitting diode is provided which includes: a sheet-like substrate; a pair of electrode patterns formed to wrap round and cover substantially entire upper and lower surfaces of the substrate, said pair of electrode patterns comprising an upper electrode portion, a lower electrode portion and a side electrode portion; a light-emitting element mounted on at least one of the electrode patterns; and a translucent sealing resin body that seals the light-emitting element. The pair of electrode patterns are separated by spaces formed therebetween, and substantially the entire surfaces of the substrate, except the spaces, are covered with the electrode patterns. | 2008-08-28 |
20080203424 | DIODE AND APPLICATIONS THEREOF - A diode with low substrate current leakage and suitable for BiCMOS process technology. A buried layer is formed on a semiconductor substrate. A connection region and well contact the buried layer. Isolation regions are adjacent to two sides of the buried layer, each deeper than the buried layer. The isolation regions and the buried layer isolate the connection zone and the well from the substrate. The first doped region in the well is a first electrode. The well and the connection region are electrically connected, acting as a second electrode. | 2008-08-28 |
20080203425 | Phototransistors, Methods of Making Phototransistors, and Methods of Detecting Light - A phototransistor ( | 2008-08-28 |
20080203426 | HETEROJUNCTION SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A metamorphic buffer layer is formed on a semi-insulating substrate by an epitaxial growth method, a collector layer, a base layer, an emitter layer and an emitter cap layer are sequentially laminated on the metamorphic buffer layer, and a collector electrode is provided in contact with an upper layer of the metamorphic buffer layer. The metamorphic buffer layer is doped with an impurity, in a concentration equivalent to or higher than that in a conventional sub-collector layer, by an impurity doping process during crystal growth so that the metamorphic buffer layer will be able to play the role of guiding the collector current to the collector electrode. Since the sub-collector layer, which is often formed of a ternary mixed crystal or the like having a high thermal resistance, can be omitted, the heat generated in the semiconductor device can be rapidly released into the substrate. | 2008-08-28 |
20080203427 | SEMICONDUCTOR DEVICE HAVING A STRAINED SEMICONDUCTOR ALLOY CONCENTRATION PROFILE - A new technique enables providing a stress-inducing alloy having a highly stress-inducing region and a region which is processable by standard processing steps suitable for use in a commercial high volume semiconductor device manufacturing environment. The regions may be formed by a growth process with a varying composition of the growing material or by other methods such as ion implantation. The highly stress-inducing region near the channel region of a transistor may be covered with an appropriate cover. | 2008-08-28 |
20080203428 | MOS TRANSISTORS HAVING RECESSED CHANNEL REGIONS AND METHODS OF FABRICATING THE SAME - A MOS transistor having a recessed channel region is provided. A MOS transistor includes a source region and a drain region disposed in an active region of a semiconductor substrate and spaced apart from each other. A gate trench structure is disposed in the active region between the source and drain regions. A gate electrode is disposed in the gate trench structure. A gate dielectric layer is interposed between the gate trench structure and the gate electrode. A semiconductor region is disposed between the gate trench structure and the gate dielectric layer. The semiconductor region is formed of a different material from the active region. A method of fabricating the MOS transistor having a recessed channel region is also provided. | 2008-08-28 |
20080203429 | Semiconductor Device and a Method of Manufacturing the Same - In a semiconductor device with a shared contact, a gate electrode is formed via a gate insulating film on a semiconductor substrate and a sidewall insulating film is formed on both side faces of the gate electrode. At least one of the surface parts of the semiconductor substrate adjacent to both sides of the gate electrode is removed beyond the lower part of the sidewall insulating film and to the underside of the gate electrode. Then, the gate insulating film exposed in the remove part is removed. An impurity-doped semiconductor layer is formed in the part where the semiconductor substrate and the gate insulating film have been removed. | 2008-08-28 |
20080203430 | ENHANCEMENT MODE INSULATED GATE HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR - Aspects of the present invention provide an enhancement mode (E-mode) insulated gate (IG) double heterostructure field-effect transistor (DHFET) having low power consumption at zero gate bias, low gate currents, and/or high reliability. An E-mode HFET in accordance with an embodiment of the invention includes: top and bottom barrier layers; and a channel layer sandwiched between the bottom and the top barrier layers, wherein the bottom and top barrier layers have a larger bandgap than the channel layer, and wherein polarization charges of the bottom barrier layer deplete the channel layer and polarization charges of the top barrier layer induce carriers in the channel layer; and wherein a total polarization charge in the bottom barrier layer is larger than a total polarization charge in the top barrier layer such that the channel layer is substantially depleted at zero gate bias. | 2008-08-28 |
20080203431 | GaN-BASED NITRIC OXIDE SENSORS AND METHODS OF MAKING AND USING THE SAME - GaN-based heterojunction field effect transistor (HFET) sensors are provided with engineered, functional surfaces that act as pseudo-gates, modifying the drain current upon analyte capture. In some embodiments, devices for sensing nitric oxide (NO) species in a NO-containing fluid are provided which comprise a semiconductor structure that includes a pair of separated GaN layers and an AlGaN layer interposed between and in contact with the GaN layers. Source and drain contact regions are formed on one of the GaN layers, and an exposed GaN gate region is formed between the source and drain contact regions for contact with the NO-containing fluid. The semiconductor structure most preferably is formed on a suitable substrate (e.g., SiC). An insulating layer may be provided so as to cover the semiconductor structure. The insulating layer will have a window formed therein so as to maintain exposure of the GaN gate region and thereby allow the gate region to contact the NO-containing fluid. Electrical contact pads are preferably provided in some embodiments so as to be in electrical contact with the source and drain contact regions, respectively. Electrical leads may thus be connected to the contact pads. According to other embodiments, the NO detection device will include a metalloporphyrin adsorbed on the GaN gate region. | 2008-08-28 |
20080203432 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A transistor including a gate insulation layer, a gate, and source/drain regions, the transistor comprising a semiconductor layer formed under the gate insulation layer for use as a channel region in a substrate, wherein the semiconductor layer is formed of a material having a lower bandgap than silicon. | 2008-08-28 |
20080203433 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A high electron mobility transistor includes first, second and third compound semiconductor layers. The second compound semiconductor layer has a first interface with the first compound semiconductor layer. The third compound semiconductor layer is disposed over the first compound semiconductor layer. The third compound semiconductor layer has at least one of lower crystallinity and relaxed crystal structure as compared to the second compound semiconductor layer. The gate electrode is disposed over the third compound semiconductor layer. Source and drain electrodes are disposed over the second compound semiconductor layer. The two-dimensional carrier gas layer is generated in the first compound semiconductor layer. The two-dimensional carrier gas layer is adjacent to the first interface. The two-dimensional carrier gas layer either is absent under the third compound semiconductor layer or is reduced in at least one of thickens and carrier gas concentration under the third compound semiconductor layer. | 2008-08-28 |
20080203434 | Semiconductor Device with a Bipolar Transistor and Method of Manufacturing Such a Device - The invention relates to a semiconductor device ( | 2008-08-28 |
20080203435 | Semiconductor device having elongated electrostatic protection element along long side of semiconductor chip - An electrostatic protection element is disposed commonly to a plurality of output circuits along a long side of an output circuit region. More preferably, the electrostatic protection element should be disposed between a Pch region and an Nch region of an output circuit. | 2008-08-28 |
20080203436 | Semiconductor device and layout method of decoupling capacitor thereof - A semiconductor device and a layout method of a decoupling capacitor thereof are disclosed. The semiconductor device includes a main power/ground voltage voltage supplying line arranged in a first direction; a plurality of decoupling capacitor cells to reduce power noise generated by the power voltage and the ground voltage in the first direction and in a second direction; a plurality of sub power voltage supplying lines arranged in the second direction in a border of the plurality of decoupling capacitor cells; and a plurality of sub ground voltage supplying lines arranged in a net form in the border of the plurality of decoupling capacitor cells, wherein the plurality of decoupling capacitor cells have a first active region arranged to receive the ground voltage and the second active region disposed to receive the power voltage and to avoid a region where an inversion is formed in the decoupling capacitor. | 2008-08-28 |
20080203437 | Semiconductor integrated circuit device with reduced leakage current - The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data. | 2008-08-28 |
20080203438 | DEMULTIPLEXERS USING TRANSISTORS FOR ACCESSING MEMORY CELL ARRAYS - A demultiplexer using transistors for accessing memory cell arrays. The demultiplexer includes (a) a substrate; (b) 2 | 2008-08-28 |
20080203439 | Semiconductor integrated circuit having plural transistors - A layout for placing a circuit having a plurality of transistors in a small-width region. A search section inputs data on a circuit and searches for a set of routes formed so that passage through a transistor occurs only one time and so that the combination of routes covers the entire circuit network. An extraction section extracts a set of routes having the smallest number of routes. A width determination section determines the layout width from source and drain electrodes, the region between the source and drain electrodes, the region between adjacent pairs of the transistors not combined into a common electrode, the number of transistors, and the smallest number of routes. A layout determination section forms a layout in which the source, drain and gate electrodes of the transistor included in the circuit are placed in a small-width region. | 2008-08-28 |
20080203440 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE FABRICATED THEREBY - A method of fabricating a semiconductor device having a pair of shallow silicided source and drain junctions with minimal leakage is disclosed. The semiconductor device typically has a MISFET structure with NiSi regions partially making up the source and drain regions. The fabrication method includes the steps of providing silicon surfaces having Si{110} crystal planes on both sides of this gate electrode and forming a plurality of nickel silicide (NiSi) regions, each having a rectangular planar shape whose shorter sides being equal or less than 0.5 μm in length and running along a Si<100> direction. | 2008-08-28 |
20080203441 | SiC semiconductor device and method for manufacturing the same - A SiC semiconductor device having a MOS structure includes: a SiC substrate; a channel region providing a current path; first and second impurity regions on upstream and downstream sides of the current path, respectively; and a gate on the channel region through the gate insulating film. The channel region for flowing current between the first and second impurity regions is controlled by a voltage applied to the gate. An interface between the channel region and the gate insulating film has a hydrogen concentration equal to or greater than 4.7×10 | 2008-08-28 |
20080203442 | HYBRID ORIENTATION SOI SUBSTRATES, AND METHOD FOR FORMING THE SAME - The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility. | 2008-08-28 |
20080203443 | Independently-Double-Gated Transistor Memory (IDGM) - Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F | 2008-08-28 |
20080203444 | Multi-finger transistor and method of manufacturing the same - A multi-finger transistor and method of manufacturing the same are provided. The multi-finger transistor includes two active regions, a multi-finger gate, a plurality of source regions and a plurality of drain regions. The two active regions are defined in a unit cell of a substrate. The multi-finger gate includes a plurality of gate fingers formed in the two active regions and a gate connector between the two active regions. The gate connector connects the gate fingers to each other. The source regions are formed in first portions of the two active regions adjacent to the gate fingers. The drain regions are formed in second portions of the two active regions adjacent to the gate fingers. | 2008-08-28 |
20080203445 | Three-Dimensional Cascaded Power Distribution in a Semiconductor Device - An IC structure having reduced power loss and/or noise includes two or more active semiconductor regions stacked in a substantially vertical dimension, each active semiconductor region including an active layer. The IC structure further includes two or more voltage supply planes, each of the voltage supply planes corresponding to a respective one of the active layers. | 2008-08-28 |
20080203446 | COMPOSITE CONTACT FOR SEMICONDUCTOR DEVICE - A composite contact for a semiconductor device is provided. The composite contact includes a DC conducting electrode that is attached to a semiconductor layer in the device, and a capacitive electrode that is partially over the DC conducting electrode and extends beyond the DC conducting electrode. The composite contact provides a combined resistive-capacitive coupling to the semiconductor layer. As a result, a contact impedance is reduced when the corresponding semiconductor device is operated at high frequencies. | 2008-08-28 |
20080203447 | LOW-TEMPERATURE ELECTRICALLY ACTIVATED GATE ELECTRODE AND METHOD OF FABRICATING SAME - A gate electrode structure is provided, which includes, from bottom to top, an optional, yet preferred metallic layer, a Ge rich-containing layer and a Si rich-containing layer. The sidewalls of the Ge rich-containing layer include a surface passivation layer. The inventive gate electrode structure serves as a low-temperature electrically activated gate electrode of a MOSFET in which the materials thereof as well as the method of fabricating the same are compatible with existing MOSFET fabrication techniques. The inventive gate electrode structure is electrically activated at low processing temperatures (on the order of less than 750° C.). Additionally, the inventive gate electrode structure also minimizes gate-depletion effects, does not contaminate a standard MOS fabrication facility and has sufficiently low reactivity of the exposed surfaces that renders such a gate electrode structure compatible with conventional MOSFET processing steps. | 2008-08-28 |
20080203448 | STRESSED DIELECTRIC DEVICES AND METHODS OF FABRICATING SAME - A structure and a method of making the structure. The structure includes a field effect transistor including: a first and a second source/drain formed in a silicon substrate, the first and second source/drains spaced apart and separated by a channel region in the substrate; a gate dielectric on a top surface of the substrate over the channel region; and an electrically conductive gate on a top surface of the gate dielectric; and a dielectric pillar of a first dielectric material over the gate; and a dielectric layer of a second dielectric material over the first and second source/drains, sidewalls of the dielectric pillar in direct physical contact with the dielectric layer, the dielectric pillar having no internal stress or an internal stress different from an internal stress of the dielectric layer. | 2008-08-28 |
20080203449 | SOURCE/DRAIN STRESSOR AND METHOD THEREFOR - A method for forming a semiconductor device is provided. The method includes forming a gate structure overlying a substrate. The method further includes forming a sidewall spacer adjacent to the gate structure. The method further includes performing an angled implant in a direction of a source side of the semiconductor device. The method further includes annealing the semiconductor device. The method further includes forming recesses adjacent opposite ends of the sidewall spacer in the substrate to expose a first type of semiconductor material. The method further includes epitaxially growing a second type of semiconductor material in the recesses, wherein the second type of semiconductor material has a lattice constant different from a lattice constant of the first type of semiconductor material to create stress in a channel region of the semiconductor device. | 2008-08-28 |
20080203450 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGE PICKUP SYSTEM USING PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus includes: a first interlayer insulation film disposed on a semiconductor substrate; a first plug disposed in a first hole in the first interlayer insulation film, and serving to electrically connect between a plurality of active regions disposed in the semiconductor substrate, between gate electrodes of a plurality of MOS transistors, or between the active region and the gate electrode of the MOS transistor, not through the wiring of the wiring layer; and a second plug disposed in a second hole in the first interlayer insulation film, the second plug being electrically connected to the active region, wherein a wiring arranged over the second plug and closest to the second plug is electrically connected to the second plug, and the wiring electrically connected to the second plug forms a portion of dual damascene structure. By such a structure, incidence efficiency of light onto a photoelectric conversion element can be improved. | 2008-08-28 |
20080203451 | CMOS image sensor and method for fabricating the same - A CMOS image sensor and a method for fabricating the same are provided, in which an N type region of a photodiode is prevented from adjoining a device isolation film and a dark current is reduced. The CMOS image sensor includes an interlayer dielectric film formed between a gate poly and a power line, a contact formed in the interlayer dielectric film, and an epitaxial layer connected with the contact and formed only in a blue photodiode region. | 2008-08-28 |
20080203452 | CMOS IMAGE SENSORS INCLUDING BACKSIDE ILLUMINATION STRUCTURE AND METHOD OF MANUFACTURING IMAGE SENSOR - An image sensor having a backside illumination structure can include a photo diode unit in a first wafer, where the photo diode unit includes photo diodes and transfer gate transistors coupled to respective ones of the photo diodes. A wiring line unit can be included on a second wafer that is bonded to the photo diode unit, where the wiring line unit includes wiring lines and transistors configured to process signals provided by the photo diode unit and configured to control the photo diode unit. A supporting substrate is bonded to the wiring line unit and a filter unit is located under the first wafer. | 2008-08-28 |
20080203453 | SEMICONDUCTOR STRUCTURES AND MEMORY DEVICE CONSTRUCTIONS - The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions. | 2008-08-28 |
20080203454 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide a semiconductor device having a memory element, and which is manufactured by a simplified manufacturing process. A method of manufacturing a semiconductor device includes, forming a first insulating film to cover a first semiconductor film and a second semiconductor film; forming a first conductive film and a second conductive film over the first semiconductor film and the second semiconductor film, respectively, with the first insulating film interposed therebetween; forming a second insulating film to cover the first conductive film; forming a third conductive film selectively over the first conductive film which is formed over the first semiconductor film, with the second insulating film interposed therebetween, and doping the first semiconductor film with an impurity element with the third conductive film serving as a mask and doping the second semiconductor film with the impurity element through the second conductive film. | 2008-08-28 |
20080203455 | SEMICONDUCTOR DEVICE EMPLOYING TRANSISTOR HAVING RECESSED CHANNEL REGION AND METHOD OF FABRICATING THE SAME - A semiconductor device employing a transistor having a recessed channel region and a method of fabricating the same is disclosed. A semiconductor substrate has an active region. A trench structure is defined within the active region. The trench structure includes an upper trench region adjacent to a surface of the active region, a lower trench region and a buffer trench region interposed between the upper trench region and the lower trench region. A width of the lower trench region may be greater than a width of the upper trench region. An inner wall of the trench structure may include a convex region interposed between the upper trench region and the buffer trench region and another convex region interposed between the buffer trench region and the lower trench region. A gate electrode is disposed in the trench structure. A gate dielectric layer is interposed between the gate electrode and the trench structure. | 2008-08-28 |
20080203456 | Dynamic random access memory devices and methods of forming the same - Dynamic random access memory (DRAM) devices include first node pads and second node pads alternately arranged in a first direction on a substrate to form a first pad column. A width of the second node pads in a second direction, perpendicular to the first direction, is greater than a width of the first node pads in the second direction. Storage electrodes are electrically connected to the first node pads and the second node pads. Bit line pads may be arranged in the first direction on the substrate to form a second pad column. The second pad column is adjacent the first pad column and displaced therefrom in the second direction. | 2008-08-28 |
20080203457 | FAST SWITCHING POWER INSULATED GATE SEMICONDUCTOR DEVICE - An insulated gate semiconductor device ( | 2008-08-28 |
20080203458 | Semiconductor Memory Device and Method of Fabricating the Same - This patent relates to a semiconductor memory device and a method of fabricating the same. The semiconductor memory device may include a semiconductor substrate in which a tunnel insulating layer, and a first conductive layer. At least a portion of the semiconductor substrate is removed to form a trench. A first insulating layer may be formed on an internal surface of the trench. A shield layer may be made of a conductive material is formed on the first insulating layer. A second insulating layer may be formed on the shield layer and is configured to gap fill the trench. | 2008-08-28 |
20080203459 | Method of manufacturing a semiconductor device and semiconductor device - A carrier is structured with isolation regions in a precise fashion. First structures and second structures are formed above a carrier. At least one of the second structures is removed selectively with respect to the first structures. At least one recess in the carrier is formed according to the structure thus obtained. An embodiment of a semiconductor device that may be produced in this way is provided with at least one insulating striplike region and/or a plurality of insulating regions that are arranged at distances from one another along a line. | 2008-08-28 |
20080203460 | MANUFACTURING METHOD FOR A NANOCRYSTAL BASED DEVICE COVERED WITH A LAYER OF NITRIDE DEPOSITED BY CVD - The invention relates to a manufacturing method for a structure comprising semi-conductor material nanocrystals on a dielectric material substrate by chemical vapour deposition (CVD), the nanocrystals being covered by a layer of semi-conductor material nitride. The method comprises a step for forming stable nuclei on the substrate by CVD from a first gaseous precursor of the nuclei; a step of nanocrystal growth from stable nuclei by CVD from a second gaseous precursor; and a step for forming a layer of semi-conductor material nitride on the nanocrystals. The method is characterised in that the passivation step is carried out by selective and stoichiometric CVD of semi-conductor material nitride only on the nanocrystals from a mixture of the second and a third gaseous precursor selected to cause selective and stoichiometric deposition of the nitride only on said nanocrystals, wherein steps for forming the nuclei, forming the nanocrystals and passivation are carried out inside a same, single chamber. | 2008-08-28 |
20080203461 | GATE STRUCTURE OF NAND FLASH MEMORY HAVING INSULATORS EACH FILLED WITH BETWEEN GATE ELECTRODES OF ADJACENT MEMORY CELLS AND MANUFACTURING METHOD THEREOF - A semiconductor device includes first and second gate electrodes arranged adjacent to each other, an oxide film formed between the first and second gate electrodes, and a nitride film formed on control gates and upper surfaces and sidewalls of the oxide film. Each of the first and second gate electrodes has a stacked gate structure which has a first insulating film, charge storage layer, second insulating film and control gate stacked on a semiconductor substrate. The uppermost surface of the oxide film is set higher than the uppermost surface of the control gate. | 2008-08-28 |
20080203462 | Finfet-Based Non-Volatile Memory Device - A non-volatile memory device on a substrate layer ( | 2008-08-28 |
20080203463 | Non-Volatile Memory with Erase Gate on Isolation Zones - The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate ( | 2008-08-28 |
20080203464 | ELECTRICALLY ALTERABLE NON-VOLATILE MEMORY AND ARRAY - A memory device, array and method of arranging where the memory device includes a memory cell region including a plurality of memory cells. Each memory cell includes a source, a drain and a channel between the source and the drain, a channel dielectric, a charge storage region and an electrically alterable conductor-material system in proximity to the charge storage region. Cell lines extend among the memory cells. A connection region is provided for electrically coupling contacts and one or more of the cell lines. A non-memory region has embedded logic. Memory cells are arrayed at a cell pitch, with cell lines extending from cell to cell and arrayed substantially at the cell pitch, and with contacts arrayed substantially at the cell pitch forming a high density memory device. | 2008-08-28 |
20080203465 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor device including the steps of forming a flash memory cell provided with a floating gate, an intermediate insulating film, and a control gate, forming first and second impurity diffusion regions, thermally oxidizing surfaces of a silicon substrate and the floating gate, etching a tunnel insulating film in a partial region through a window of a resist pattern; forming a metal silicide layer on the first impurity diffusion region in the partial region, forming an interlayer insulating film covering the flash memory cell, and forming, in a first hole of the interlayer insulating film, a conductive plug connected to the metal silicide layer. | 2008-08-28 |
20080203466 | METHOD OF MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, AND A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - For enhancing the high performance of a non-volatile semiconductor memory device having an MONOS type transistor, a non-volatile semiconductor memory device is provided with MONOS type transistors having improved performance in which the memory cell of an MONOS non-volatile memory comprises a control transistor and a memory transistor. A control gate of the control transistor comprises an n-type polycrystal silicon film and is formed over a gate insulative film comprising a silicon oxide film. A memory gate of the memory transistor comprises an n-type polycrystal silicon film and is disposed on one of the side walls of the control gate. The memory gate comprises a doped polycrystal silicon film with a sheet resistance lower than that of the control gate comprising a polycrystal silicon film formed by ion implantation of impurities to the undoped silicon film. | 2008-08-28 |
20080203467 | NROM FLASH MEMORY DEVICES ON ULTRATHIN SILICON - An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top. | 2008-08-28 |
20080203468 | FinFET with Reduced Gate to Fin Overlay Sensitivity - Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure. | 2008-08-28 |
20080203469 | INTEGRATED CIRCUIT INCLUDING AN ARRAY OF MEMORY CELLS HAVING DUAL GATE TRANSISTORS - An integrated circuit including an array of memory cells having dual gate transistors with curved current flow, and method for operation and fabrication is disclosed. In one embodiment, in a substrate an array of transistors is formed for selecting one of a plurality of memory cells by selecting a pair of adjacent word lines and a bit line. For minimizing the area of a memory cell and reducing complexity in production an array of dual gate transistors having a curved current flow is disclosed, wherein a small portion of a current is allowed to flow through adjacent memory cells. | 2008-08-28 |
20080203470 | Lateral compensation component - A transistor is provided which includes a lateral compensation component. The lateral compensation component includes a plurality of n (or n−) layer/p (or p−) layer pairs, wherein adjacent ones of said pairs are separated by one of an insulator region and/or an intrinsic silicon region. | 2008-08-28 |
20080203471 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING NITRIDE SEMICONDUCTOR DEVICE - The nitride semiconductor device includes: a nitride semiconductor structure comprising an n-type first layer, a p-type second layer, and an n-type third layer, the nitride semiconductor structure comprising a mesa structure having a lateral surface which forms a wall surface extending from the first, second, to third layers; a gate insulating film formed on the wall surface of the mesa structure; a gate electrode formed as facing the wall surface in the second layer; a drain electrode electrically connected to the first layer; and a source electrode electrically connected to the third layer, the nitride semiconductor structure having a high dislocation region and a low dislocation region arranged along a direction parallel to a principal surface of lamination of the nitride semiconductor structure, a dislocation density of the low dislocation region being lower than that of the high dislocation region, the mesa structure being formed in the low dislocation region. | 2008-08-28 |
20080203472 | LATERAL MOSFET AND MANUFACTURING METHOD THEREOF - A lateral MOSFET according to the present invention has a trench gate structure having a cross sectional shape spreading toward an open end. | 2008-08-28 |
20080203473 | Lateral Field-Effect Transistor Having an Insulated Trench Gate Electrode - A field-effect transistor having cells ( | 2008-08-28 |
20080203474 | Semiconductor device having offset spacer and method of forming the same - A method of forming a semiconductor device having an offset spacer may include forming a gate electrode on a semiconductor substrate. An etch stop layer including a nitride may be formed on the entire surface of the semiconductor substrate having the gate electrode. First spacers may be formed on the sidewalls of the gate electrode. The first spacers may be formed of a material layer having an etch selectivity with respect to the etch stop layer. The etch stop layer may be exposed on the semiconductor substrate on both sides of the gate electrode. Lightly-doped drain (LDD) regions may be formed in the semiconductor substrate using the gate electrode and the first spacers as an ion implantation mask. Second spacers may be formed on the first spacers. Accordingly, a semiconductor device having an offset spacer may be provided. | 2008-08-28 |
20080203475 | Semiconductor device and method of fabricating the same - An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region. | 2008-08-28 |
20080203476 | Semiconductor Device Having Strip-Shaped Channel And Method For Manufacturing Such A Device - The invention relates to a semiconductor device ( | 2008-08-28 |
20080203477 | SEMICONDUCTOR DEVICE - Plural kinds of thin film transistors having different film thicknesses of semiconductor layers are provided over a substrate having an insulating surface. A channel formation region of semiconductor layer in a thin film transistor for which high speed operation is required is made thinner than a channel formation region of a semiconductor layer of a thin film transistor for which high withstand voltage is required. A gate insulating layer of the thin film transistor for which high speed operation is required may be thinner than a gate insulating layer of the thin film transistor for which high withstand voltage is required. | 2008-08-28 |
20080203478 | High Frequency Switch With Low Loss, Low Harmonics, And Improved Linearity Performance - A switch element includes a field effect transistor (FET) structure formed on a substrate, the FET structure having a drain, a gate and a source, the drain having a drain capacitance, the gate having a gate capacitance, the source having a source capacitance and an electrical connection to couple the drain capacitance, gate capacitance and the source capacitance to the substrate. | 2008-08-28 |
20080203479 | SEMICONDUCTOR DEVICE - In a PMOS transistor, the source-drain region is divided into four parts along the gate width and has an arrangement of four independent source regions and an arrangement of four independent drain regions. A partial trench isolation insulating film is arranged in contact with the whole of the opposed surfaces between the four source regions in such a manner that the channel region formed under the gate electrode is divided across the channel length. A body-tied region containing N-type impurities relatively high in concentration is arranged in contact with the side surface of the source region opposite to the gate electrode, and the potential of the body region is fixed through the well region from the body-tied region. | 2008-08-28 |
20080203480 | INTEGRATED CIRCUIT USING A SUPERJUNCTION SEMICONDUCTOR DEVICE - In an embodiment, an apparatus includes a source region, a gate region and a drain region supported by a substrate, and a drift region including a plurality of vertically extending n-wells and p-wells to couple the gate region and the drain region of a transistor, wherein the plurality of n-wells and p-wells are formed in alternating longitudinal rows to form a superjunction drift region longitudinally extending between the gate region and the drain region of the transistor. | 2008-08-28 |
20080203481 | NONVOLATILE SEMICONDUCTOR MEMORY AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer. | 2008-08-28 |
20080203482 | Transistors having gate pattern for self-alignment with channel impurity diffusion region in active region and methods of forming the same - A transistor having a gate pattern suitable for self-alignment with a channel impurity diffusion region in an active region includes an active region and an isolation layer disposed in a semiconductor substrate. The isolation layer is formed to define the active region. An insulating layer covering the active region and the isolation layer is disposed. The insulating layer has a channel-induced hole on the active region. A channel impurity diffusion region and a gate trench are formed in the active region to be aligned with the channel-induced hole. The insulating layer is removed from the semiconductor substrate. A gate pattern is disposed in the gate trench to overlap the channel impurity diffusion region. | 2008-08-28 |
20080203483 | SEMICONDUCTOR DEVICE INCLUDING A RECESSED-CHANNEL-ARRAY MISFET - A semiconductor device includes RCA MISFETs formed in active regions of a semiconductor substrate, the active regions being defined by shallow-trench-isolation (STI) structure. The top surface of the insulating film is flush with the top surface of the active regions. The gate electrode of each MISFET includes a first portion at extends over the top surface of the insulating film of the STI structure, and a second portion embedded in a gate trench formed in the active region. | 2008-08-28 |
20080203484 | FIELD EFFECT TRANSISTOR ARRANGEMENT AND METHOD OF PRODUCING A FIELD EFFECT TRANSISTOR ARRANGEMENT - A field effect transistor arrangement and a fabrication method thereof. The field effect transistor arrangement includes: a substrate having a first crystal surface orientation; a first layer formed above at least a first portion of the substrate, the first layer having a second crystal surface orientation different from the first crystal surface orientation; a second layer formed above at least a second portion of the substrate and adjacent to the first layer, the second layer having the first crystal surface orientation; a first buried oxide layer formed between the first layer and the substrate; a second buried oxide layer formed between the second layer and the substrate; a first field effect transistor formed in or on the first layer, the first field effect transistor having a first conductivity type; and a second field effect transistor formed in or on the second layer, the second field effect transistor having a second conductivity type different from the first conductivity type. | 2008-08-28 |
20080203485 | STRAINED METAL GATE STRUCTURE FOR CMOS DEVICES WITH IMPROVED CHANNEL MOBILITY AND METHODS OF FORMING THE SAME - A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the substrate and a second metal layer formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate. | 2008-08-28 |
20080203486 | METHOD FOR DIFFERENTIAL SPACER REMOVAL BY WET CHEMICAL ETCH PROCESS AND DEVICE WITH DIFFERENTIAL SPACER STRUCTURE - By removing an outer spacer of a transistor element, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, employing a wet chemical etch process, it is possible to position a stressed contact liner layer more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region, without affecting circuit elements in the P-type regions. | 2008-08-28 |
20080203487 | FIELD EFFECT TRANSISTOR HAVING AN INTERLAYER DIELECTRIC MATERIAL HAVING INCREASED INTRINSIC STRESS - By providing a highly stressed interlayer dielectric material, the performance of at least one type of transistor may be increased due to an enhanced strain-inducing mechanism. For instance, by providing a highly compressive silicon dioxide of approximately 400 Mega Pascal and more as an interlayer dielectric material, the drive current of the P-channel transistors may be increased by 2% and more while not unduly affecting the performance of the N-channel transistors. | 2008-08-28 |
20080203488 | CMOS semiconductor device and method of fabricating the same - Example embodiments provide a complementary metal-oxide semiconductor (CMOS) semiconductor device and a method of fabricating the CMOS semiconductor device. The CMOS semiconductor device may include gates in the nMOS and pMOS areas, polycrystalline silicon (poly-Si) capping layers, metal nitride layers underneath the poly-Si capping layers, and a gate insulating layer underneath the gate. The metal nitride layers of the nMOS and pMOS areas may be formed of the same type of material and may have different work functions. Since a metal gate is formed of identical types of metal nitride layers, a process may be simplified, yield may be increased, and a higher-performance CMOS semiconductor device may be obtained. | 2008-08-28 |
20080203489 | Ensuring Migratability of Circuits by Masking Portions of the Circuits While Improving Performance of Other Portions of the Circuits - Mechanisms for ensuring the migratability of circuits into future technologies while minimizing fabrication costs and maintaining or improving power efficiency are provided. A mask layer is introduced to portions of the integrated circuit prior to a stress inducing layer being applied to the integrated circuit. In an exemplary embodiment, a tensile or compressive film is applied to the devices on the integrated circuit chip but is removed from those devices whose operation is to be modified. Thereafter, a tensile or compressive strain layer is applied to the devices whose film was removed. An additional mask layer may then be used to effect a halo or well implant to relax the strain on the devices not being protected by the mask layer. In this way, the current of the non-protected devices is reduced back to its original target design point. | 2008-08-28 |
20080203490 | BIPOLAR TRANSISTOR WITH RAISED EXTRINSIC SELF-ALIGNED BASE USING SELECTIVE EPITAXIAL GROWTH FOR BICMOS INTEGRATION - High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces. | 2008-08-28 |
20080203491 | RADIATION HARDENED FINFET - The embodiments of the invention provide a structure and method for a rad-hard FinFET or mesa. More specifically, a semiconductor structure is provided having at least one fin or mesa comprising a channel region on an isolation region. A doped substrate region is also provided below the fin, wherein the doped substrate region has a first polarity opposite a second polarity of the channel region. The isolation region contacts the doped substrate region. The structure further includes a gate electrode covering the channel region and at least a portion of the isolation region. The gate electrode comprises a lower portion below the channel region of the fin, wherein the lower portion of the gate electrode comprises a height that is at least one-half of a thickness of the fin. | 2008-08-28 |
20080203492 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED SUSCEPTIBILITY TO LATCH-UP AND SEMICONDUCTOR DEVICE STRUCTURES FORMED BY THE METHODS - Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression. | 2008-08-28 |
20080203493 | Semiconductor memory device and fabrication process thereof - A SRAM includes a first CMOS inverter of first and second MOS transistors connected in series, a second CMOS inverter of third and fourth MOS transistors connected in series and forming a flip-flop circuit together with the first CMOS inverter, and a polysilicon resistance element formed on a device isolation region, each of the first and third MOS transistors is formed in a device region of a first conductivity type and includes a second conductivity type drain region at an outer side of a sidewall insulation film of the gate electrode with a larger depth than a drain extension region thereof, wherein a source region is formed deeper than a drain extension region, the polysilicon gate electrode has a film thickness identical to a film thickness of the polysilicon resistance element, the source region and the polysilicon resistance element are doped with the same dopant element. | 2008-08-28 |
20080203494 | APPARATUS AND METHOD FOR REDUCING NOISE IN MIXED-SIGNAL CIRCUITS AND DIGITAL CIRCUITS - Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus ( | 2008-08-28 |
20080203495 | INTEGRATION CIRCUITS FOR REDUCING ELECTROMIGRATION EFFECT - An integrated circuit for reducing the electromigration effect. The IC includes a substrate and a power transistor which has first and second source/drain regions. The IC further includes first, second, and third electrically conductive line segments being (i) directly above the first source/drain region and (ii) electrically coupled to the first source/drain region through first contact regions and second contact regions, respectively. The first and second electrically conductive line segments (i) reside in a first interconnect layer of the integrated circuit and (ii) run in the reference direction. The IC further includes an electrically conductive line being (i) directly above the first source/drain region, (ii) electrically coupled to the first and second electrically conductive line segments through a first via and a second via, respectively, (iii) resides in a second interconnect layer of the integrated circuit, and (iv) runs in the reference direction. | 2008-08-28 |
20080203496 | SEMICONDUCTOR DEVICE - A gate electrode | 2008-08-28 |
20080203497 | Semiconductor Devices Including Assymetric Source and Drain Regions Having a Same Width and Related Methods - A semiconductor device may include an active region of a semiconductor substrate and first and second impurity regions in the active region. The active region may have a first conductivity type, the first and second impurity regions may have a second conductivity type opposite the first conductivity type, and the first and second impurity regions are spaced apart to define a channel region therebetween. A first source/drain region may be provided in the first impurity region, a second source/drain region may be provide in the second impurity region, the first and second source/drain regions may have the second conductivity type, and impurity concentrations of the first and second source/drain regions may be greater than impurity concentrations of the first and second impurity regions. Moreover, the first and second source/drain regions may have a same width in a direction perpendicular with respect to a direction between the first and second source/drain regions, and a distance between the first source/drain region and the channel region may be less than a distance between the second source/drain region and the channel region. In addition, a control gate may be provided on the channel region. Related methods are also discussed. | 2008-08-28 |
20080203498 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a semiconductor device may include a semiconductor substrate; a first gate dielectric layer provided on the semiconductor substrate, the relative dielectric constant ratio of the first gate dielectric layer being no less than 8; a second gate dielectric layer provided on the semiconductor substrate, the relative dielectric constant ratio of the second gate dielectric layer being no less than 8; a first gate electrode provided on the first gate dielectric layer and made of germanide which is a metallic compound containing a metal element of a rare earth metal; and a second gate electrode provided on the second gate dielectric layer and made of silicide which is a metallic compound containing the same metal element of a rare earth metal as the germanide in the first gate electrode. | 2008-08-28 |
20080203499 | Semiconductor device having gate insulator including high-dielectric-constant materials and manufacture method of the same - A semiconductor device includes a semiconductor substrate, an insulating layer and a conductive layer disposed on the second insulator, the insulating layer including a first insulator containing silicon and oxygen, an intermediate region containing a metal element, silicon, oxygen and nitrogen, and a second insulator containing the metal element and oxygen, wherein a concentration of the metal element in the intermediate region is higher in a region in contact with the second insulator than in a region in contact with the first insulator. | 2008-08-28 |
20080203500 | Semiconductor device and production method therefor - A semiconductor device provided with a MIS type field effect transistor comprising a silicon substrate, a gate insulating film having a high-dielectric-constant metal oxide film which is formed on the silicon substrate via a silicon containing insulating film, a silicon-containing gate electrode formed on the gate insulating film, and a sidewall including, as a constituting material, silicon oxide on a lateral face side of the gate electrode, wherein a silicon nitride film is interposed between the sidewall and at least the lateral face of the gate electrode. This semiconductor device, although having a fine structure with a small gate length, is capable of low power consumption and fast operation. | 2008-08-28 |
20080203501 | SEMICONDUCTOR DEVICE - A semiconductor device with higher reliability and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor layer overlapping with a gate electrode and having an impurity region outside a region which overlaps with the gate electrode; a first conductive layer which is provided on a side provided with the gate electrode of the semiconductor layer and partially in contact with the impurity region; an insulating layer provided over the gate electrode and the first conductive layer; and a second conductive layer which is formed in the insulating layer and in contact with the first conductive layer through an opening at least part of which overlaps with the first conductive layer. | 2008-08-28 |
20080203502 | SELF-ADDRESSABLE SELF-ASSEMBLING MICROELECTRONIC SYSTEMS AND DEVICES FOR MOLECULAR BIOLOGICAL ANALYSIS AND DIAGNOSTICS - A self-addressable, self-assembling microelectronic device is designed and fabricated to actively carry out and control multi-step and multiplex molecular biological reactions in microscopic formats. These reactions include nucleic acid hybridization, antibody/antigen reaction, diagnostics, and biopolymer synthesis. The device can be fabricated using both microlithographic and micro-machining techniques. The device can electronically control the transport and attachment of specific binding entities to specific micro-locations. The specific binding entities include molecular biological molecules such as nucleic acids and polypeptides. The device can subsequently control the transport and reaction of analytes or reactants at the addressed specific micro-locations. The device is able to concentrate analytes and reactants, remove non-specifically bound molecules, provide stringency control for DNA hybridization reactions, and improve the detection of analytes. The device can be electronically replicated. | 2008-08-28 |
20080203503 | MAGNETIC RANDOM ACCESS MEMORY - A magnetic random access memory includes a first bit line and a second bit line, a source line formed for a group having the first bit line and the second bit line, adjacent to the first bit line, and running in a first direction in which the first bit line and the second bit line run, a first magnetoresistive effect element connected to the first bit line, a second magnetoresistive effect element connected to the second bit line, a first transistor connected in series with the first magnetoresistive effect element, and a second transistor connected in series with the second magnetoresistive effect element. A first cell having the first magnetoresistive effect element and the first transistor and a second cell having the second magnetoresistive effect element and the second transistor are connected together to the source line. | 2008-08-28 |
20080203504 | Magneto-resistance transistor and method thereof - A magneto-resistance transistor including a magneto-resistant element which may function as an emitter and a passive element which may function as a collector. The base may be interposed between the passive element and the magneto-resistant element, thereby coupling the passive element with the magneto-resistant element. A magnetic field of a given strength may be applied to at least a portion of the magneto-resistant transistor, the given strength determining a resistance in the at least a portion of the magneto-resistant transistor. Thus, by adjusting the given strength of the magnetic field, the resistance may be adjusted. Therefore, different emitter current inputs may be achieved with a fixed voltage. Further, a base current may vary with a controlled variation of the emitter current input. | 2008-08-28 |
20080203505 | Magnetic random access memory with selective toggle memory cells - A toggle MTJ is disclosed that has a SAF free layer with two or more magnetic sub-layers having equal magnetic moments but different anisotropies which is achieved by selecting Ni | 2008-08-28 |
20080203506 | Capacitive Junction Modulator, Capacitive Junction And Method For Making Same - The invention concerns a capacitive junction including a region adapted to be traversed by an electromagnetic wave, and a dielectric layer interposed between two semiconductor material layers. The dielectric layer has a reduced thickness at the region, that is a thickness at the region less than its thickness at a contact of the junction. Such a junction is for instance used to form a modulator. The invention also concerns a method for making such a junction. | 2008-08-28 |
20080203507 | Image sensors for zoom lenses and fabricating methods thereof - An image sensor includes a semiconductor substrate on which a plurality of photo diodes are formed. A plurality of interlayer dielectrics are formed above the semiconductor substrate, and a plurality of metal lines are formed on each of the interlayer dielectrics. A plurality of micro lenses are formed above the uppermost one of the interlayer dielectrics. The light passing through the zoom lenses is incident on the respective micro lenses. The plurality metal lines formed on at least one of the plurality of interlayer dielectrics have the same width. | 2008-08-28 |
20080203508 | Image sensing device having protection pattern on the microlens, camera module, and method of forming the same - An image sensing device having a protection pattern formed on microlenses is provided. The device includes a plurality of photodiodes provided in a semiconductor substrate. An insulating layer having a substantially flat top surface is disposed on the photodiodes. A plurality of microlenses are provided on the insulating layer and disposed over the photodiodes. The microlenses are covered with a protection pattern. The protection pattern can be formed of an oxide-based photosensitive polymer layer or a nitride-based photosensitive polymer layer, as examples. The protection pattern can have a substantially flat top surface. | 2008-08-28 |
20080203509 | PHOTOELECTRIC CONVERSION DEVISE AND METHOD OF MANUFACTURING THE SAME - A photoelectric conversion device comprises a photoelectric conversion element disposed at a semiconductor substrate, and a multilayered wiring structure including a plurality of wiring layers disposed over the semiconductor substrate in such a manner to sandwich an interlayer insulation film therebetween. A diffusion suppressing film is disposed at least on the uppermost one of the wiring layers, the diffusion suppressing film serving to suppress diffusion of material forming the uppermost wiring layer; the diffusion suppressing film covers regions of the uppermost wiring layer and the interlayer insulation film corresponding to the photoelectric conversion element; and a lens is disposed with respect to a region of the diffusion suppressing film corresponding to the photoelectric conversion element. | 2008-08-28 |
20080203510 | OPTICAL MODULE - An optical module of the present invention includes: a semiconductor device | 2008-08-28 |
20080203511 | Sensor-type semiconductor package and method for fabricating the same - The present invention provides a sensor-type semiconductor package and a method for fabricating the same. The method includes the steps of: providing a wafer having a plurality of sensor chips for mounting the wafer on a carrier board having an insulation layer, a plurality of conductive traces, and a substrate; forming a plurality of grooves among the solder pads on the active surfaces of the adjacent sensor chips, so as to expose the conductive traces and form a metal layer in the grooves, to electrically connect to the solder pads on the active surfaces of the adjacent sensor chips and the conductive traces; disposing a transparent medium on the wafer to cover the sensing areas of the sensor chips; removing the substrate, so as to expose the conductive traces and the insulation layer; and cutting the sensor chips along the borders to form a plurality of sensor-type semiconductor packages. This can avoid the formation of slanted grooves on the non-active surface on the wafer and shift in position of the grooves due to failure to align with the cutting lines among the sensor chips, as observed in prior art. Consequently, the problems such as stress concentration and cracking are likely to occur in the contact points of the traces formed in the slanted grooves and the traces in the active surfaces. | 2008-08-28 |
20080203512 | Image sensor chip package - A chip package includes a carrier ( | 2008-08-28 |
20080203513 | Semiconductor Integrated Device Having Solid-State Image Sensor Packaged Within and Production Method for Same - A semiconductor integrated device comprises: a light-shielding film which shields at least some part of a transfer section of the semiconductor integrated device from light; a first wiring formed in the same layer as the light-shielding film, with one end connected to a pad electrode and an other end extended to a side edge of the semiconductor substrate; a second wiring arranged to go around a side face of the semiconductor substrate, and connected to the first wiring; and a sealing member which seals the solid-state image sensor. | 2008-08-28 |
20080203514 | High Performance CdxZn1-xTe X-Ray and Gamma Ray Radiation Detector and Method of Manufacture Thereof - The present invention is a radiation detector that includes a crystalline substrate formed of a II-VI compound and a first electrode covering a substantial portion of one surface of the substrate. A plurality of second, segmented electrodes is provided in spaced relation on a surface of the substrate opposite the first electrode. A passivation layer is disposed between the second electrodes on the surface of the substrate opposite the first electrode. The passivation layer can also be positioned between the substrate and one or both of the first electrode and each second electrode. The present invention is also a method of forming the radiation detector. | 2008-08-28 |
20080203515 | Photoelectric conversion device and electronic device, and method for manufacturing photoelectric conversion device - A photoelectric conversion device includes: a first substrate of which end portions are cut off so as to slope or with a groove shape; a photodiode and an amplifier circuit over the first substrate; a first electrode electrically connected to the photodiode and provided over one end portion of the first substrate; a second electrode electrically connected to the amplifier circuit and provided over an another end portion of the first substrate; and a second substrate having third and fourth electrodes thereon. The first and second electrodes are attached to the third and fourth electrodes, respectively, with a conductive material provided not only at the surfaces of the first, second, third, and fourth electrodes facing each other but also at the side surfaces of the first and second electrodes to increase the adhesiveness between a photoelectric conversion device and a member on which the photoelectric conversion device is mounted. | 2008-08-28 |