35th week of 2015 patent applcation highlights part 59 |
Patent application number | Title | Published |
20150243599 | METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPACITANCE INTERCONNECTS BY ALTERNATING RECESSED TRENCHES - Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased. | 2015-08-27 |
20150243600 | CONDUCTIVE LINE ROUTING FOR MULTI-PATTERNING TECHNOLOGY - A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns. | 2015-08-27 |
20150243601 | METHOD OFSELF-CORRECTING A POWER GRID FOR SEMICONDUCTOR STRUCTURES - Aspects of the present invention relate to a self-correcting power grid for a semiconductor structure and a method of using thereof. Various embodiments include a self-correcting power grid for a semiconductor structure. The power grid may include a plurality of interconnect layers. Each of the plurality of interconnect layers may include a plurality of metal lines, where each of the plurality of metal lines are positioned substantially parallel to one another and substantially perpendicular to a plurality of distinct metal lines in adjacent interconnect layers. Additionally the interconnect layers may include a plurality of fuses formed within each of the metal lines of the plurality of interconnect layers. In the power grid, at least one of the fuses positioned immediately adjacent to a defect included in the power grid may be configured to blow during a testing process to isolate the defect. | 2015-08-27 |
20150243602 | SPUTTER AND SURFACE MODIFICATION ETCH PROCESSING FOR METAL PATTERNING IN INTEGRATED CIRCUITS - One embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines have pitches of less than one hundred nanometers and sidewall tapers of between approximately eighty and ninety degrees. Another embodiment of an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein at least some of the plurality of conductive lines are fabricated by providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer and sputter etching the layer of conductive metal using a methanol plasma, wherein a portion of the layer of conductive metal that remains after the sputter etching forms the one or more conductive lines. | 2015-08-27 |
20150243603 | SELF REPAIRING PROCESS FOR POROUS DIELECTRIC MATERIALS - The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage. | 2015-08-27 |
20150243604 | CAP LAYERS FOR SEMICONDUCTOR DEVICES WITH SELF-ALIGNED CONTACT ELEMENTS - One method disclosed herein includes forming an etch stop layer above recessed sidewall spacers and a recessed replacement gate structure and, with the etch stop layer in position, forming a self-aligned contact that is conductively coupled to the source/drain region after forming the self-aligned contact. A device disclosed herein includes an etch stop layer that is positioned above a recessed replacement gate structure and recessed sidewall spacers, wherein the etch stop layer defines an etch stop recess that contains a layer of insulating material positioned therein. The device further includes a self-aligned contact. | 2015-08-27 |
20150243605 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark formed at a back surface of the logic chip is imaged and a shape of the recognition range is recognized, alignment of a plurality of bumps of the logic chip and a plurality of projection electrodes of the above-described memory chip is performed based on a result of the recognition, and the above-described memory chip is mounted over the logic chip. At this time, the shape of the recognition range is different from any portion of an array shape of the bumps, as a result, the recognition mark in the shape of the recognition range can be reliably recognized, and alignment of the bumps of the logic chip and the projection electrodes of the above-described memory chip is performed with high accuracy. | 2015-08-27 |
20150243606 | INTEGRATED CIRCUIT FOR GENERATING OR PROCESSING A RADIO FREQUENCY SIGNAL - An integrated circuit includes a signal line for carrying a radio frequency signal; a coupling line inductively coupled to the signal line for delivering an induced signal in dependence on the radio frequency signal; a connecting line connected to a pick-off point of the coupling line for picking off the induced signal from the coupling line; and a conductive part for shielding the coupling line against electromagnetic interference and for enhancing inductive coupling between the signal line and the coupling line. The conductive part may have a uniform flat surface facing the coupling line. The signal line may extend parallel to the surface. The coupling line may extend parallel to the signal line and may be arranged between the surface and the signal line. | 2015-08-27 |
20150243607 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE HAVING MAGNETIC SHIELD UNIT - A method of manufacturing a semiconductor package having a magnetic shield function is provided. The method includes forming cracks in a lattice structure on an active surface in which electrode terminals are formed; grinding a back surface of a wafer facing the active surface, bonding a tape on the active surface of the wafer, expanding the tape such that the wafer on the tape is divided as semiconductor chips, forming a shield layer on surfaces of the semiconductor chips and the tape, cutting the shield layer between the semiconductor chips and individualizing as each of the semiconductor chips which has a first shield pattern formed on back surface and sides, bonding the semiconductor chips on a substrate, and forming a second shield pattern on each of the active surfaces of the semiconductor chips, wherein the semiconductor chips and the substrate are physically and electrically connected by a bonding wire. | 2015-08-27 |
20150243608 | CABLE MOUNTED MODULARIZED SIGNAL CONDITIONING APPARATUS SYSTEM - A modularized signal conditioning apparatus system includes at least two slots formed in a coaxial cable. The slots are spaced apart so as to not reduce the measuring performance of the coaxial cable. Slots may be at least 40 mills from one another. In an ESD embodiment, within each slot is an ESD protection component, such as a pair of Shottky diodes coupled between the ground shell and the center conductor of the coaxial cable. Methods of producing modularized signal conditioning apparatus system are also described. | 2015-08-27 |
20150243609 | SHIELDED PACKAGE ASSEMBLIES WITH INTEGRATED CAPACITOR - Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor. | 2015-08-27 |
20150243610 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR A HIGH BANDWIDTH BOTTOM PACKAGE - A system, method, and computer program product are provided for producing a high bandwidth bottom package of a die-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer and an integrated circuit die that is coupled to the top layer of the substrate material. A first set of pads is formed on the top layer of the substrate material and a layer of dielectric material is applied on a top surface of the bottom package to cover the integrated circuit die and the first set of pads. | 2015-08-27 |
20150243611 | Wafer Bonding Process and Structure - A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method. | 2015-08-27 |
20150243612 | CHIP PARTS AND METHOD FOR MANUFACTURING THE SAME, CIRCUIT ASSEMBLY HAVING THE CHIP PARTS AND ELECTRONIC DEVICE - A chip part according to the present invention includes a substrate having a penetrating hole, a pair of electrodes formed on a front surface of the substrate and including one electrode overlapping the penetrating hole in a plan view and another electrode facing the one electrode, and an element formed on the front surface side of the substrate and electrically connected to the pair of electrodes. | 2015-08-27 |
20150243613 | Packaging Devices and Methods of Manufacture Thereof - Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad. | 2015-08-27 |
20150243614 | SEMICONDUCTOR DEVICE - A semiconductor chip and a wiring board are coupled to each other through conductor posts. The centers of conductor posts situated above openings at the outermost periphery shift from the centers of the openings in a direction away from the center of the semiconductor chip. When a region where each of the conductor posts and an insulating layer are overlapped with each other is designated as an overlapped region, the width of the overlapped region more on the inner side than the opening is smaller than the width of the overlapped region more on the outer side than the opening. Thus, while stress applied to the conductor posts is relaxed, coupling reliability between the semiconductor chip and the wiring board is retained. | 2015-08-27 |
20150243615 | Packaging Devices and Methods - A method of manufacturing a packaging device may include: forming a plurality of through-substrate vias (TSVs) in a substrate, wherein each of the plurality of TSVs has a protruding portion extending away from a major surface of the substrate. A seed layer may be forming over the protruding portions of the plurality of TSVs, and a conductive ball may be coupled to the seed layer and the protruding portion of each of the plurality of TSVs. The seed layer and the protruding portion of each of the plurality of TSVs may extend into an interior region of the conductive ball. | 2015-08-27 |
20150243616 | PACKAGES WITH SOLDER BALL REVEALED THROUGH LASER - An integrated circuit structure includes a substrate, a PPI over the substrate, a solder region over and electrically coupled to a portion of the PPI, and a molding compound molding a lower portion of the solder region therein. A top surface of the molding compound is level with or lower than a maximum-diameter plane, wherein the maximum-diameter plane is parallel to a major surface of the substrate, and the maximum-diameter of the solder region is in the maximum-diameter plane. | 2015-08-27 |
20150243617 | Method for Flip-Chip Bonding Using Copper Pillars - A bonding pad arrangement and method of bonding a flip-chip semiconductor device to a substrate using copper pillars and solder to join die pads on the flip-chip to substrate pads on the substrate. Each substrate pad has an offset from a respective die pad at specific temperature, the offset for each of the substrate pads is substantially the same, and the offset is determined as a function of the size of the flip-chip device, a difference between a solidification temperature of the solder and the specific temperature, and a difference between a coefficient of thermal expansion of the flip-chip device and a coefficient of thermal expansion of the substrate. Alternatively, the offset for each of the substrate pads is the above-determined offset scaled as a function of a distance the respective die pad is from the centroid of the device. | 2015-08-27 |
20150243618 | REDUCING THERMAL ENERGY TRANSFER DURING CHIP-JOIN PROCESSING - Embodiments of the present invention provide a semiconductor structure and method to reduce thermal energy transfer during chip-join processing. In certain embodiments, the semiconductor structure comprises a thermal insulating element formed under a first conductor. The semiconductor structure also comprises a solder bump formed over the first conductor. The semiconductor structure further comprises a second conductor formed on a side of the thermal insulating element and in electrical communication with the first conductor and a third conductor. The third conductor is formed to be in thermal or electrical communication with the thermal insulating element. The thermal insulating element includes thermal insulating material and the thermal insulating element is structured to reduce thermal energy transfer during a chip-join process from the solder bump to a metal level included in the semiconductor structure. | 2015-08-27 |
20150243619 | CONDUCTIVE BUMP, SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR PACKAGE USING THE SAME - A conductive bump includes a step member formed to form a step on a portion of a connection pad; and a conductive member formed on the connection pad and the step member and having an inclined surface which is inclined with respect to the connection pad. | 2015-08-27 |
20150243620 | SUBSTRATE AND PACKAGE STRUCTURE - According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area. | 2015-08-27 |
20150243621 | EMBEDDED DIE BALL GRID ARRAY PACKAGE - A method of assembling a semiconductor package includes attaching a semiconductor die to a frame having a strip or panel form. The semiconductor die has at least one stud bump. The die and the stud bump are covered with a first encapsulation material, and then at least a portion of the stud bump is exposed. At least one die conductive member is formed on the first encapsulation material and electrically coupled to the stud bump. The die conductive member is covered with a second encapsulation material, and then at least a portion of the die conductive member is exposed. At least one grid array conductive member is formed on the second encapsulation material and electrically coupled to the die conductive member. Finally, at least one solder ball is attached to the at least one grid array conductive member. | 2015-08-27 |
20150243622 | PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME - A package includes a first work piece with a metal trace on a surface of the first work piece, wherein the metal trace has a first axis, wherein the first work piece is rigid, and an entirety of the metal trace is on the first work piece. The package further includes a second work piece with a plurality of elongated bumps, wherein at least one of the plurality of elongated metal bumps has a second axis and at least another of the plurality of elongated metal bumps has a third axis, wherein the second and the third axes are not the same and the second axis is at a non-zero angle from the first axis, wherein the plurality of elongated bumps are electrically connected to the metal trace. | 2015-08-27 |
20150243623 | SEMICONDUCTOR DEVICE GRID ARRAY PACKAGE - A grid array assembly is formed from an electrical insulating material with embedded solder deposits. A first portion of each of the solder deposits is exposed on a first surface of the insulating material and a second portion of each of the solder deposits is exposed on an opposite surface of the insulating material. A semiconductor die is mounted to the first surface of the insulating material and electrodes of the die are connected to the solder deposits with bond wires. The die, bond wires, and the first surface of the insulating material then are covered with a protective encapsulating material. | 2015-08-27 |
20150243624 | MICROELECTRONIC PACKAGES WITH NANOPARTICLE JOINING - A method of making an assembly includes the steps of applying metallic nanoparticles to exposed surfaces of conductive elements of either of or both of a first component and a second component, juxtaposing the conductive elements of the first component with the conductive elements of the second component with the metallic nanoparticles disposed therebetween, and elevating a temperature at least at interfaces of the juxtaposed conductive elements to a joining temperature at which the metallic nanoparticles cause metallurgical joints to form between the juxtaposed conductive elements. The conductive elements of either of or both of the first component and the second component can include substantially rigid posts having top surfaces projecting a height above the surface of the respective component and edge surfaces extending at substantial angles away from the top surfaces thereof. | 2015-08-27 |
20150243625 | JOINING A CHIP TO A SUBSTRATE WITH SOLDER ALLOYS HAVING DIFFERENT REFLOW TEMPERATURES - A method including forming a first solder bump on a chip, the first solder bump made of a first alloy, and forming a second solder bump on a chip, the second solder bump made of a second alloy, where the first alloy has a different alloy concentration and is different from the second alloy. | 2015-08-27 |
20150243626 | ANISOTROPIC CONDUCTIVE FILM, METHOD FOR PRODUCING ANISOTROPIC CONDUCTIVE FILM, METHOD FOR PRODUCING CONNECTION BODY, AND CONNECTION METHOD - To reduce substrate warp occurring after connection an anisotropic conductive film is used. An anisotropic conductive film has: a first insulating adhesive layer; a second insulating adhesive layer; and a conductive particle-containing layer sandwiched by the first insulating adhesive layer and the second insulating adhesive layer and having conductive particles contained in an insulating adhesive, wherein air bubbles are contained between the conductive particle-containing layer and the first insulating adhesive layer, and, the conductive particle-containing layer, a portion thereof below the conductive particles and in contact with the second insulating adhesive layer has a lower degree of cure than other portions thereof. | 2015-08-27 |
20150243627 | WIRE-BONDING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a wire-bonding apparatus ( | 2015-08-27 |
20150243628 | Manufacturing Method of Device Embedded Substrate and Device Embedded Substrate Manufactured by this Method - The present invention provides a manufacturing method of a device embedded substrate, including: forming a bonding layer of an insulation material on a metal layer formed on a support plate; and mounting an electric or electronic device on the bonding layer, wherein the device is formed of a device main body and a protruding terminal; the bonding layer includes a first bonding body bonded with the metal layer and a second bonding body bonded with the device; the first bonding body is formed along the outer edge of the device; the second bonding body is formed in an area equal or smaller than the area defined by the outer edge of the terminal; and, in the bonding layer forming step, the second bonding body is formed on the first bonding body after the first bonding body is cured. | 2015-08-27 |
20150243629 | Methods for Wafer Bonding, and for Nucleating Bonding Nanophases - Substrates may be bonded according to a method comprising contacting a first bonding surface of a first substrate with a second bonding surface of a second substrate to form an assembly, and compressing the assembly in the presence of an oxidizing atmosphere under suitable conditions to form a bonding layer between the first and second surfaces, wherein the first bonding surface comprises a polarized surface layer; the second bonding surface comprises a hydrophilic surface layer; the first and second bonding surfaces are different. | 2015-08-27 |
20150243630 | DIE STACKING APPARATUS AND METHOD - Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device. | 2015-08-27 |
20150243631 | MULTIPLE DIE IN A FACE DOWN PACKAGE - A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements. | 2015-08-27 |
20150243632 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR STACKED MODULE STRUCTURE, STACKED MODULE STRUCTURE AND METHOD OF MANUFACTURING SAME - A semiconductor device, having an insulating substrate; a semiconductor element which is mounted on one main surface of the insulating substrate via adhesive, with an element circuit surface of the semiconductor element facing upwards; a first insulating material layer which seals the element circuit surface of the semiconductor element and the insulating substrate peripheral thereto; a first metal thin film wire layer which is provided on the first insulating material layer (A) and a portion of which is exposed to an external surface; a first insulating material layer (B) which is provided on the first metal thin film wire layer; a second insulating material layer which is provided on a main surface of the insulating substrate where the semiconductor element is not mounted; and a second metal thin film wire layer which is provided inside the second insulating material layer. | 2015-08-27 |
20150243633 | LASER MARKING IN PACKAGES - A package includes a device die, a first plurality of redistribution lines underlying the device die, a second plurality of redistribution lines overlying the device die, and a metal pad in a same metal layer as the second plurality of redistribution lines. A laser mark is in a dielectric layer that is overlying the metal pad. The laser mark overlaps the metal pad. | 2015-08-27 |
20150243634 | SEMICONDUCTOR DEVICE - A semiconductor device includes an operation circuit formed on a top surface of a semiconductor substrate, a memory array formed over the operation circuit, an inner pad group formed on an intermediate layer between the operation circuit and the memory array and coupled to the operation circuit, a first outer pad group formed on a bottom surface of the semiconductor substrate, and a wiring structure passing through the semiconductor substrate, and coupling the inner pad group to the first outer pad group. | 2015-08-27 |
20150243635 | STACKED MICROELECTRONIC PACKAGES HAVING SIDEWALL CONDUCTORS AND METHODS FOR THE FABRICATION THEREOF - Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors. | 2015-08-27 |
20150243636 | Packaged Semiconductor Devices and Packaging Methods - Packaged semiconductor devices and packaging methods are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and through-vias disposed in a molding compound. A first redistribution layer (RDL) is disposed over a first side of the through-vias, the integrated circuit die, and the molding compound. A second RDL is disposed over a second side of the through-vias, the integrated circuit die, and the molding compound. Contact pads are disposed over the second RDL. An insulating material of the second RDL includes a recess around a perimeter of one of the contact pads. | 2015-08-27 |
20150243637 | SEMICONDUCTOR DEVICES HAVING THROUGH-VIAS AND METHODS FOR FABRICATING THE SAME - A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed. | 2015-08-27 |
20150243638 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor chip, a package that surrounds the semiconductor chip, a first electrode terminal of which an upper end portion is aligned with and exposed at an upper surface of the package or protrudes from the upper surface of the package on an upper side of the package, and of which a lower end portion is aligned with and exposed at a lower surface of the package, or protrudes from the lower surface of the package on a lower side of the package, and a second electrode terminal of which an upper end portion is aligned with and exposed at the upper surface of the package, or protrudes from the upper surface of the package on the upper side of the package, and of which a lower end portion is aligned with and exposed at the lower surface of the package or protrudes from the lower surface of the package on the lower side of the package. | 2015-08-27 |
20150243639 | INTEGRATED PASSIVE FLIP CHIP PACKAGE - A method for packaging integrated circuit die such that each package includes die with integrated passive components mounted to either the back surface, the active surface or both the back and active surfaces of the die. | 2015-08-27 |
20150243640 | SEMICONDUCTOR DEVICE - A semiconductor device includes an insulating substrate having a first conductive pattern on a first insulating substrate; a first semiconductor element having one surface fixed to the first conductive pattern; a printed circuit board having a conductive layer on a second insulating substrate and a plurality of metal pins fixed to the conductive layer; and a third insulating substrate. A portion of pins constituting the metal pins is fixed to other surface of the first semiconductor element, and the printed circuit board with the metal pins is sandwiched between the insulating substrate having the first conductive pattern and the third insulating substrate. | 2015-08-27 |
20150243641 | INTEGRATED CIRCUIT PACKAGE - A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe. | 2015-08-27 |
20150243642 | Packages and Methods for Forming the Same - A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size. | 2015-08-27 |
20150243643 | 3D IC WITH SERIAL GATE MOS DEVICE, AND METHOD OF MAKING THE 3D IC - A die stack comprises a first integrated circuit (IC) die having at least a first device comprising a first source, a first drain and a first gate electrode above a first channel region between the first source and the first drain. A second IC die has at least a second device comprising a second source, a second drain and a second gate electrode above a second channel region between the second source and the second drain. The second gate electrode is connected to the first gate electrode by a path including a first through substrate via (TSV), the second drain connected to the first source by a path including a second TSV. | 2015-08-27 |
20150243644 | Z-CONNECTION USING ELECTROLESS PLATING - In one embodiment, an assembly includes a substrate having a substrate conductor and a contact at a first surface and a terminal at a second surface for electrically interconnecting the assembly with a component external to the assembly, at least one of the substrate conductor or the contact being electrically connected with the terminal; a first element having a first surface facing the first surface of the substrate and having a first conductor at the first surface and a second conductor at a second surface, an interconnect structure extending through the first element electrically connecting the first and second conductors; an adhesive layer bonding the first surfaces of the first element and the substrate, at least portions of the first conductor and the substrate conductor being disposed beyond an edge of the adhesive layer; and a continuous electroless plated metal region extending between the first conductor and the substrate conductor. | 2015-08-27 |
20150243645 | Semiconductor Device Arrangement with a First Semiconductor Device and with a Plurality of Second Semiconductor Devices - Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device. | 2015-08-27 |
20150243646 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC APPLIANCE USING THE SAME - Provided is a semiconductor integrated circuit device including: an output buffer circuit having a P channel transistor connected between a first power supply terminal and a signal terminal; a potential control circuit that supplies potential from the first power supply terminal or the signal terminal to a back gate of the P channel transistor according to the potential of the signal terminal; a first protection diode having an anode connected to the signal terminal; a common discharge line connected to a cathode of the first protection diode; an electrostatic discharge protection circuit connected between the common discharge line and a second power supply terminal; and a second protection diode having an anode connected to the second power supply terminal and a cathode connected to the signal terminal. | 2015-08-27 |
20150243647 | DRIVER CIRCUIT, METHOD OF MANUFACTURING THE DRIVER CIRCUIT, AND DISPLAY DEVICE INCLUDING THE DRIVER CIRCUIT - Provided are a driver circuit which suppresses damage of a semiconductor element due to ESD in a manufacturing process, a method of manufacturing the driver circuit. Further provided are a driver circuit provided with a protection circuit with low leakage current, and a method of manufacturing the driver circuit. By providing a protection circuit in a driver circuit to be electrically connected to a semiconductor element in the driver circuit, and by forming, at the same time, a transistor which serves as the semiconductor element in the driver circuit and a transistor included in the protection circuit in the driver circuit, damage of the semiconductor element due to ESD is suppressed in the process of manufacturing the driver circuit. Further, by using an oxide semiconductor film for the transistor included in the protection circuit in the driver circuit, leakage current in the protection circuit is reduced. | 2015-08-27 |
20150243648 | QUANTUM WELL-MODULATED BIPOLAR JUNCTION TRANSISTOR - A semiconductor device includes a quantum well-modulated bipolar junction transistor (QW-modulated BJT) having a base with an area for a modulatable quantum well in the base. The QW-modulated BJT includes a quantum well (QW) control node which is capable of modulating a quantity and level of energy levels of the quantum well. A recombination site abuts the area for the quantum well with a contact area of at least 25 square nanometers. The semiconductor device may be operated by providing a reference node such as ground to the emitter and a power source to the collector. A bias voltage is provided to the gate to form the quantum well and a signal voltage is provided to the gate, so that the collector current includes a component which varies with the signal. | 2015-08-27 |
20150243649 | Power Transistor Die with Capacitively Coupled Bond Pad - A power transistor die includes a transistor formed in a semiconductor body. The transistor has a gate terminal, an output terminal and a third terminal. The gate terminal controls a conduction channel between the output terminal and the third terminal. The power transistor die further includes a structured first metal layer disposed on and insulated from the semiconductor body. The structured first metal layer is connected to the output terminal of the transistor. The power transistor die also includes a first bond pad disposed on and insulated from the semiconductor body. The first bond pad forms an output terminal of the power transistor die and is capacitively coupled to the structured first metal layer so as to form a series capacitance between the output terminal of the transistor and the first bond pad. A power semiconductor package including the power transistor die is also provided. | 2015-08-27 |
20150243650 | SEMICONDUCTOR DEVICE WITH RESISTANCE CIRCUIT - A semiconductor device includes a resistance circuit and an insulated gate field effect transistor. The resistance circuit includes a resistance element having a first thin film arranged on an isolation oxide film provided on a surface of a semiconductor substrate, a second thin film of silicon nitride formed on the first thin film so as to be wider than the resistance element, an intermediate insulating film formed on the second thin film, a contact hole passing through the second thin film and being provided in the intermediate insulating film at a depth reaching the first thin film, and a metal wiring formed in the contact hole. The insulated gate field effect transistor is provided in a region of the semiconductor substrate surrounded by the isolation oxide film. | 2015-08-27 |
20150243651 | VERY PLANAR GATE CUT POST REPLACEMENT GATE PROCESS - A semiconductor structure with improved gate planarity and method of fabrication are provided. In a replacement gate scheme, an array of sacrificial gate structures of substantially uniform pitch and spacing formed over a semiconductor substrate is removed and replaced with functional gate structures. Portions of functional gate structures that are accounted as extraneous features in a circuit design are subsequently removed and the removed portions of the functional gate structures are filled with a dielectric material. Because the functional gate structures of substantially uniform pitch and spacing are formed before removal of unwanted portions of the functional gate structures, the chemical mechanical polishing process can be accomplished uniformly across the semiconductor substrate. The functional gate structures thus formed have a substantially uniform height across the substrate. | 2015-08-27 |
20150243652 | INTEGRATION METHOD FOR FABRICATION OF METAL GATE BASED MULTIPLE THRESHOLD VOLTAGE DEVICES AND CIRCUITS - In one aspect there is set forth herein a semiconductor device having a first field effect transistor formed in a substrate structure, and a second field effect transistor formed in the substrate structure. The first field effect transistor can include a first substrate structure doping, a first gate stack, and a first threshold voltage. The second field effect transistor can include the first substrate structure doping, a second gate stack different from the first gate stack, and a second threshold voltage different from the first threshold voltage. | 2015-08-27 |
20150243653 | Shallow Trench Isolation Structure - A semiconductor device includes a semiconductor substrate, an active region and a trench isolation. The active region is formed in the semiconductor substrate. The trench isolation is disposed adjacent to the active region. The trench isolation includes a lower portion and an upper portion. The upper portion is located on the lower portion. The upper portion has a width gradually decreased from a junction between the upper portion and the lower portion toward a top of the trench isolation. In a method for fabricating the semiconductor device, at first, the semiconductor substrate is etched to form a trench in the semiconductor substrate. Then, an insulator fills the trench to form the trench isolation. Thereafter, the gate structure is formed on the semiconductor substrate. Then, the semiconductor substrate is etched to form a recess adjacent to the trench isolation. Thereafter, at least one doped epitaxial layer grows in the recess. | 2015-08-27 |
20150243654 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a method for manufacturing a semiconductor structure, which comprises: a) forming gate lines extending along one direction on a substrate; b) forming a photoresist layer that covers the semiconductor structure; patterning the photoresist layer to form openings that span over the gate lines: c) implanting ions into the gate lines, such that the gate lines are insulated at the openings. The present invention enables the gate lines to maintain complete shape at formation of electrically isolated gates, which will not cause defects that exist in the prior art when forming a dielectric layers at subsequent steps, thereby guaranteeing performance of semiconductor devices. Additionally, the present invention further provides a semiconductor structure manufactured according to the method provided by the present invention. | 2015-08-27 |
20150243655 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first region and at least one second region. The at least one first region includes at least one first device oriented in a first direction. The at least one second region includes at least one second device oriented in a second direction. The second direction is different than the first direction. | 2015-08-27 |
20150243656 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode. | 2015-08-27 |
20150243657 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PACKAGE USING THE SAME - A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, an interlayer dielectric, an inter-source layer, an inter-source plug, an inter-drain layer, an inter-drain plug, an inter-gate layer, and an inter-gate plug. The active layer is made of III-V group semiconductors. The source electrode, the drain electrode, and the gate electrode are disposed on the active layer. The gate electrode is disposed between the source electrode and the drain electrode. The interlayer dielectric covers the source electrode, the drain electrode, and the gate electrode. The inter-source layer, the inter-drain layer, and the inter-gate layer are disposed on the interlayer dielectric. The inter-source plug is electrically connected to the source electrode and the inter-source layer. The inter-drain plug is electrically connected to the drain electrode and the inter-drain layer. The inter-gate plug is electrically connected to the gate electrode and the inter-gate layer. | 2015-08-27 |
20150243658 | INTEGRATED CIRCUITS WITH VARYING GATE STRUCTURES AND FABRICATION METHODS - Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s). | 2015-08-27 |
20150243659 | STRUCTURES AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES USING FIN STRUCTURES - A shallow trench isolation (STI) structure is formed on a substrate. Part of the STI structure is removed to form a first fin structure and a second fin structure extending above a support structure on the substrate. A first part of the STI structure is located between the first fin structure and the second fin structure and has a first top surface higher than an interface between the first fin structure and the support structure. A second part of the STI structure is located adjacent to the first fin structure and has a second top surface lower than the interface between the first fin structure and the support structure. An etching process is performed to remove part of the first fin structure and the second fin structure. Part of the support structure adjacent to the second part of the STI structure is removed during the etching process. | 2015-08-27 |
20150243660 | CMOS STRUCTURE HAVING LOW RESISTANCE CONTACTS AND FABRICATION METHOD - A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide. | 2015-08-27 |
20150243661 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor. | 2015-08-27 |
20150243662 | Low Threshold Voltage and Inversion Oxide Thickness Scaling for a High-K Metal Gate P-Type MOSFET - A semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T | 2015-08-27 |
20150243663 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND DEVICE MANUFACTURED USING THE SAME - A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a dual silicide approach of the embodiment, a substrate having a first area with plural first metal gates and a second area with plural second metal gates is provided, wherein the adjacent first metal gates and the adjacent second metal gates are separated by an insulation. A dielectric layer is formed on the first and second metal gates and the insulation. The dielectric layer and the insulation at the first area are patterned by a first mask to form a plurality of first openings. Then, a first silicide is formed at the first openings. The dielectric layer and the insulation at the second area are patterned by a second mask to form a plurality of second openings. Then, a second silicide is formed at the second openings. | 2015-08-27 |
20150243664 | INTEGRATED JUNCTION AND JUNCTIONLESS NANOTRANSISTORS - Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor. | 2015-08-27 |
20150243665 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a technology which improves the manufacturing yield of a semiconductor device including a contact plug. After a contact plug ( | 2015-08-27 |
20150243666 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including first and second semiconductor pillars formed on a surface of a semiconductor substrate and aligning in a first direction; a first interconnect extending in a second direction intersecting with the first direction and provided between the first and second semiconductor pillars; and a first contact pad located over the first interconnect, the first contact pad being in contact with and electrically connected to the first semiconductor pillar at a side surface thereof, while being electrically isolated from the second semiconductor pillar. | 2015-08-27 |
20150243667 | Structure and Method for FinFET SRAM - Provided is an embedded FinFET SRAM structure and methods of making the same. The embedded FinFET SRAM structure includes an array of SRAM cells. The SRAM cells have a first pitch in a first direction and a second pitch in a second direction orthogonal to the first direction. The first and second pitches are configured so as to align fin active lines and gate features of the SRAM cells with those of peripheral logic circuits. A layout of the SRAM structure includes three layers, wherein a first layer defines mandrel patterns for forming fins, a second layer defines a first cut pattern for removing dummy fins, and a third layer defines a second cut pattern for shortening fin ends. The three layers collectively define fin active lines of the SRAM structure. | 2015-08-27 |
20150243668 | NON-VOLATILE MEMORY DEVICE - The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power consumption, without receiving an influence of deterioration of a selection transistor connected in series to the memory transistor. A memory cell | 2015-08-27 |
20150243669 | MEMORY DEVICE - Provided is a memory device including a control gate, floating gates, an inter-gate insulating layer and a select gate. The control gate is disposed on a substrate. The floating gates are disposed between the control gate and the substrate, wherein a width of each floating gate is greater than a width of the control gate. The inter-gate insulating layer is disposed between the control gate and each of the floating gates. The select gate is disposed on the substrate adjacent to the control gate. | 2015-08-27 |
20150243670 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING ELEMENT ISOLATING REGION OF TRENCH TYPE - Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion. | 2015-08-27 |
20150243671 | METHODS FOR FORMING A STRING OF MEMORY CELLS AND APPARATUSES HAVING A VERTICAL STRING OF MEMORY CELLS INCLUDING METAL - A method for forming a string of memory cells, a memory device having a string of memory cells, and a system are disclosed. The string of memory cells can include a string of planar memory cells formed as recesses in each of a plurality of control gate material formed as a vertical stack of alternating insulator and control gate material. The recesses can be lined with a dielectric material and filled with a floating gate material. Metal nano-particles can be formed on a surface of the floating gate material and/or infused into the floating gate material. | 2015-08-27 |
20150243672 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a stacked structure having alternately stacked conductive patterns and interlayer insulating patterns, a through-hole passing through the stacked structure, a channel pattern formed in the through-hole and protruding from an inside of the through hole over the through-hole, and a capping conductive pattern formed to be in contact with the protruded channel pattern and have a width greater than the through-hole. | 2015-08-27 |
20150243673 | SEMICONDUCTOR DEVICE - Provided are a semiconductor device. The semiconductor device includes a memory block including a drain select line, word lines, and a source select line, which are spaced apart from one another and stacked in a direction perpendicular to a semiconductor substrate; and a peripheral circuit including a switching device connected to a bit line, which is disposed under a vertical channel layer vertically passing through the drain select line, the word lines, and the source select line. | 2015-08-27 |
20150243674 | HIGH ASPECT RATIO ETCHING METHOD - A plurality of layers of a first conductive material is etched to define a first plurality of stacks of conductive strips between a first plurality of trenches, where a stack has a width greater than two times a target width. A first memory layer is formed on side surfaces of conductive strips in the first plurality of trenches, and a first layer of a second conductive material is formed over the first memory layer. The first plurality of stacks is etched to define a second plurality of stacks of conductive strips between a second plurality of trenches, wherein a stack has a width equal to the target width. A second memory layer is formed on side surfaces of conductive strips in the second plurality of trenches, and a second layer of the second conductive material is formed over the second memory layer. | 2015-08-27 |
20150243675 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer. | 2015-08-27 |
20150243676 | DISPLAY DEVICE - A display device includes a first substrate including a display area and a non-display area, the display area including a pixel including a first electrode, a light emission layer, and a second electrode; a sealing member facing the first substrate; and a first conducting member in the display area, the first conducting member being coupled to the first electrode, where the sealing member includes: a first conductive layer coupled to the first conducting member; an insulating layer on the first conductive layer; and a second conductive layer on the insulating layer, the second conductive layer being coupled to the second electrode. | 2015-08-27 |
20150243677 | TFT and Manufacturing Method Thereof, Array Substrate and Display Device - The present invention provides a thin film transistor. An active layer of the thin film transistor comprises a plurality of active semiconductor sub-layers and a plurality of insulation sub-layers, which are stacked alternately. A source and a drain of the thin film transistor are electrically connected to the plurality of active semiconductor sub-layers. Correspondingly, the present invention further provides a method for manufacturing a thin film transistor, and an array substrate. The present invention can effectively increase channel current of the active layer in a thin film transistor, and solves the problem of small channel current resulted from low carrier mobility of the active layer. | 2015-08-27 |
20150243678 | Semiconductor Device and Electronic Device - To provide a novel shift register. Transistors | 2015-08-27 |
20150243679 | Display Device - A display device in which the current load of wirings are distributed and display variations due to voltage drop are suppressed. An active matrix display device of the invention comprises a first current input terminal, a second current input terminal, and a plurality of current supply lines extending parallel to each other. Each current supply line is connected to a plurality of driving transistors in a line. One end of each current supply line is connected to the first current input terminal via a first wiring intersecting with the current supply lines, and the other end thereof is connected to the second current input terminal via a second wiring intersecting with the current supply lines. Accordingly, a current is supplied to each current supply line from both the first and the second current input terminals. The first and the second current input terminals are provided separately from each other. | 2015-08-27 |
20150243680 | THIN FILM TRANSISTOR DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - A thin film transistor array panel includes: a first gate line extending in a first direction; a second gate line extending in the first direction; a data line extending in a different second direction; a first common signal distribution line including a plurality of first branches connected to each other, wherein the first branches extend in the second direction and intersect under or over with the first gate line and the second gate line. The first branches are connected to receive an electrostatic offset voltage of polarity opposite to that of data line voltages supplied on the data line. A column of pixel-electrodes are sandwiched between the data line and one of the first branches. | 2015-08-27 |
20150243681 | ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME, AND DISPLAY DEVICE - Disclosed is method of manufacturing an array substrate, including steps of: forming a thin film transistor on a substrate through a patterning process; and on the substrate on which the thin film transistor has been formed, forming an organic transparent insulation layer including a first via hole and a first transparent electrode layer disposed above the organic transparent insulation layer and including a second via hole through one patterning process, wherein the centers of the first via hole and the second via hole coincide with each other in a thickness direction of the substrate, and a projection of the first via hole on the substrate is within a projection of the second via hole on the substrate. | 2015-08-27 |
20150243682 | THIN FILM TRANSISTOR AND THIN FILM TRANSISTOR ARRAY - A thin film transistor based on carbon nanotubes comprises a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconductor layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The semiconductor layer includes a number of semiconductor fragments, each of the number of semiconductor fragments includes multilayer semiconductor molecular layers, and a quantity of layers of the number of semiconductor molecular layers ranges from about 1 to about 20. | 2015-08-27 |
20150243683 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - Provided are a thin film transistor substrate and a display using the same. A display includes: a first thin film transistor, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer being disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer, and an etch-stopper layer disposed on the oxide semiconductor layer. | 2015-08-27 |
20150243684 | DISPLAY PANEL AND DISPLAY DEVICE - A display panel includes a TFT substrate, an opposite substrate and a display layer. A TFT of the TFT substrate has a drain. A first insulating layer has a first sub-layer and a second sub-layer disposed on the drain sequentially. The first sub-layer has a first opening with a first width. The second sub-layer has a second opening with a second width on the first opening. The first and second openings form a first via, and the second width is greater than the first width. A passivation layer is disposed on the first insulating layer. A second insulating layer is disposed on the passivation layer. A pixel electrode layer is disposed on the second insulating layer and disposed in the first via to connect the drain. The display layer is disposed between the TFT substrate and the opposite substrate. | 2015-08-27 |
20150243685 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - Provided are a thin film transistor substrate and a display using the same. A thin film transistor substrate includes: a substrate, a first thin film transistor disposed at a first area of the substrate, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor disposed at a second area of the substrate, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, a nitride layer disposed on an area of the substrate, other than the second area, the nitride layer covering the first gate electrode, and an oxide layer disposed: over the first gate electrode and the second gate electrode, and under the oxide semiconductor layer. | 2015-08-27 |
20150243686 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate. A thin film transistor substrate includes a substrate; a first thin film transistor disposed on the substrate, the first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode over the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor disposed on the substrate, the second thin film transistor including a second gate electrode, an oxide semiconductor layer over the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed over the first gate electrode and the second gate electrode and under the oxide semiconductor layer. | 2015-08-27 |
20150243687 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - Provided are a thin film transistor substrate and a display using the same. A thin film transistor substrate includes: a substrate, a first thin film transistor disposed on the substrate, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor disposed on the substrate, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer being disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer, and an etch-stopper layer disposed on the oxide semiconductor layer. | 2015-08-27 |
20150243688 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - Provided are a thin film transistor substrate and a display using the same. A display includes: a first area, a second area, a first thin film transistor disposed at the first area, the first thin film transistor including: a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode, a second thin film transistor disposed at the second area, the second thin film transistor including: a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode, a nitride layer on an area of the display device, other than the second area, the nitride layer covering the first gate electrode, and an oxide layer disposed over the first gate electrode and the second gate electrode. | 2015-08-27 |
20150243689 | THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY USING THE SAME - The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate, and a display using the same. A display includes a first thin film transistor including a poly crystalline semiconductor layer, a first gate electrode on the poly crystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor including a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer. | 2015-08-27 |
20150243690 | METHOD FOR MAKING THIN FILM TRANSISTOR ARRAY - A method for making thin film transistor array includes following steps. A gate electrode is formed on a surface of the insulating substrate. An insulating layer is deposited on the insulating substrate to cover the gate electrode. A carbon nanotube layer is applied on the insulating layer. A number of source electrodes and a number of drain electrodes opposite with each other is formed by patterning the carbon nanotube layer. A semiconductor layer is formed by coating a semiconductor fragments suspension on the insulating layer, wherein the semiconductor layer comprises a number of semiconductor fragments located between the number of source electrodes and the number of drain electrodes. | 2015-08-27 |
20150243691 | THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - The present invention discloses a thin-film transistor array substrate and a manufacturing method thereof. The method includes steps of using a first multi-tone adjustment mask to form a gate electrode and a common electrode after depositing a first transparent conductive layer and a first metallic layer on a substrate; depositing a gate-insulating layer and a semiconductor layer and then using a first mask to retain a part of the semiconductor layer that is on a top of the gate electrode; depositing a second transparent conductive layer and a second metallic layer, and using a second multi-tone adjustment mask to form a source electrode, a drain electrode and a pixel electrode. | 2015-08-27 |
20150243692 | X-Y ADDRESS TYPE SOLID STATE IMAGE PICKUP DEVICE AND METHOD OF PRODUCING THE SAME - In an X-Y address type solid state image pickup device represented by a CMOS image sensor, a back side light reception type pixel structure is adopted in which a wiring layer is provided on one side of a silicon layer including photo-diodes formed therein. and visible light is taken in from the other side of the silicon layer, namely, from the side (back side) opposite to the wiring layer. wiring can be made without taking a light-receiving surface into account, and the degree of freedom in wiring for the pixels is enhanced. | 2015-08-27 |
20150243693 | CMOS Image Sensors Including Vertical Transistor and Methods of Fabricating the Same - Provided is a complementary metal-oxide-semiconductor (CMOS) image sensor. The CMOS image sensor can include a substrate having a first device isolation layer defining and dividing a first active region and a second active region, a photodiode disposed in the substrate and can be configured to vertically overlap the first device isolation layer, a transfer gate electrode can be disposed in the first active region and can be configured to vertically overlap the photodiode, and a floating diffusion region can be in the first active region. The transfer gate electrode can be buried in the substrate. | 2015-08-27 |
20150243694 | Image Sensors Having Deep Trenches Including Negative Charge Material and Methods of Fabricating the Same - Image sensors are provided including a substrate defining a plurality of pixel regions, the substrate having a first surface and a second surface opposite the first surface. The second surface of the substrate is configured to receive light incident thereon and the substrate defines a deep trench extending from the second surface of the substrate toward the first surface substrate and separating the plurality of pixel regions from each other. In each of the plurality of pixel regions of the substrate, a photoelectric conversion region is provided. A gate electrode is provided on the photoelectric conversion region and a negative fixed charge layer covering the second surface of the substrate and at least a portion of a sidewall of the deep trench is also provided. The image sensors further include a shallow device isolation layer on the first surface of the substrate. The shallow device isolation layer defines an active region in each of the pixel regions and the negative fixed charge layer contacts the shallow device isolation layer. | 2015-08-27 |
20150243695 | IMAGING SYSTEMS WITH ACTIVATION MECHANISMS - An imaging system may be used to image a fluid sample containing particles. The imaging system may include a fluid channel that receives the fluid sample and a reactive agent that selectively attaches to target particles in the fluid sample. An activation mechanism may be operated to trigger a chemical reaction between the fluid sample and the reactive agent. The imaging system may include an image sensor integrated circuit and image sensor pixels to capture a detectable effect of the chemical reaction. The image sensor integrated circuit may be synchronized to the activation mechanism such that it captures an image of the fluid sample after the chemical reaction is triggered by the activation mechanism. | 2015-08-27 |
20150243696 | IMAGE SENSOR DEVICE WITH LIGHT BLOCKING STRUCTURE - The disclosure provides an image sensor device and a manufacturing method. The image sensor device includes a semiconductor substrate and a light sensing region in the semiconductor substrate. The image sensor device also includes a light blocking structure in the semiconductor substrate and adjacent to the light sensing region. A sidewall of the light blocking structure is a curved surface. | 2015-08-27 |
20150243697 | IMAGE SENSOR DEVICE AND METHOD FOR FORMING THE SAME - Embodiments of the disclosure provide an image sensor device. The image sensor device includes a semiconductor substrate. The semiconductor substrate has a front surface, a back surface opposite to the front surface, a light-sensing region close to the front surface, and a trench adjacent to the light-sensing region. The image sensor device includes a reflective layer positioned on an inner wall of the trench, wherein the reflective layer has a light reflectivity ranging from about 70% to about 100%. | 2015-08-27 |
20150243698 | COMPRESSIVE SENSING IMAGING SYSTEM - The present disclosure relates to a compressive sensing imaging system which may include a compressive sensing optic (CSO) that includes a plurality of compressive sensing elements (CSEs), a fiber optic bundle (FOB) that includes a plurality of fiber optic elements (FOEs) and a sensor that includes a plurality of optical sensing elements (OSEs). Each CSE is configured to capture a respective random CSE optical sample related to a respective portion of a scene and to provide the respective CSE optical sample to the FOB. Each FOE is configured to integrate one or more accepted scene optical samples to produce an associated compressed optical sample and each scene optical sample corresponds to at least a portion of a respective CSE optical sample. Each FOE is further configured to provide the associated compressed optical sample to the sensor. Each OSE is configured to integrate one or more received sensor optical samples. | 2015-08-27 |