35th week of 2015 patent applcation highlights part 56 |
Patent application number | Title | Published |
20150243299 | Method and Device for Voice Activity Detection - In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus for voice activity detection (VAD). The VAD comprises creating a signal indicative of a primary VAD decision and determining hangover addition. The determination on hangover addition is made in dependence of a short term activity measure and/or a long term activity measure. A signal indicative of a final VAD decision is then created. | 2015-08-27 |
20150243300 | Voice Activity Detector for Audio Signals - According to one aspect, a method for detecting voice activity is disclosed, the method including receiving a frame of an input audio signal, the input audio signal having an sample rate; dividing the frame into a plurality of subbands based on the sample rate, the plurality of subbands including at least a lowest subband and a highest subband; filtering the lowest subband with a moving average filter to reduce an energy of the lowest subband; estimating a noise level for each of the plurality of subbands; calculating a signal to noise ratio value for each of the plurality of subbands; and determining a speech activity level of the frame based on an average of the calculated signal to noise ratio values and a weighted average of an energy of each of the plurality of subbands. Other aspects include audio decoders that decode audio that was encoded using the methods described herein. | 2015-08-27 |
20150243301 | READ HEAD WITH MULTIPLE READER STACKS - A read head includes a bottom shield and a bottom isolation layer that electrically isolates the bottom shield. The read head includes left and right reader stacks having respective bottom layers disposed on at least a portion of the bottom isolation layer. The left and right reader stacks are cross-track adjacent to one another. The read head also includes left and right bottom contacts electrically coupled to respective left and right bottom layers. A top shield is configured as a common top contact electrically coupled to respective top layers of the left and right reader stacks. | 2015-08-27 |
20150243302 | READ HEAD WITH MULTIPLE READER STACKS - A read head includes a bottom shield configured as a bottom electrical contact. A bottom reader stack is disposed on and electrically coupled to the bottom shield. A middle electrical contact is electrically coupled to a top layer of the bottom reader stack. A top reader stack is disposed on the bottom reader stack. A bottom layer of the top reader stack electrically coupled to the middle electrical contact. A top shield is configured as a top electrical contact. The top shield is disposed on and electrically coupled to the top reader stack. | 2015-08-27 |
20150243303 | Magnetic Storage Medium Comprised of Magnetic Nanoparticles Contained Within Nanotubes - A magnetic storage medium is formed of magnetic nanoparticles that are encapsulated within nanotubes (e.g., carbon nanotubes). | 2015-08-27 |
20150243304 | METHOD TO MAKE INTERFEROMETRIC TAPER WAVEGUIDE FOR HAMR LIGHT DELIVERY - A method for making an interferometric taper waveguide (I-TWG) with high critical dimension uniformity and small line edge roughness for a heat assisted magnetic recording (HAMR) head, wherein the method includes creating an I-TWG film stack with two hard mask layers on top of an I-TWG core layer sandwiched between two cladding layers, defining a photoresist pattern over the I-TWG film stack using deep ultraviolet lithography, transferring the pattern to the first hard mask layer using reactive ion etching (RIE), forming a temporary I-TWG pattern on the second hard mask layer using RIE, transferring the temporary pattern to the I-TWG core using RIE, refilling the cladding layer, and planarizing using chemical mechanical planarization (CMP). | 2015-08-27 |
20150243305 | READER WITH DECOUPLED MAGNETIC SEED LAYER - An apparatus comprising a base shield, a sensor stack, and a base seed layer separating the base shield from the sensor stack. The base seed layer has a base coupled seed section that is coupled with the base shield, and a base uncoupled seed section that is uncoupled with the base shield, wherein the base uncoupled seed section covers a base window surrounding the sensor stack. | 2015-08-27 |
20150243306 | Magnetic Pole Self-Annealing with Current Injection in Perpendicular Magnetic Recording (PMR) - A main pole structure is selectively annealed by attaching a lead to a back side thereof and electrically connecting a lead to a front end of a narrow pole tip portion such that when a first current passes between the leads there is resistive heating that raises the temperature in the narrow pole tip to 250° C. to 400° C. As a result, defects and stress level are reduced in the narrow pole tip portion without substantially increasing a temperature in adjacent regions including the read head. Annealing may be performed with a partially completed main pole structure or with a completely fabricated write head. Leads may be removed or left in place after annealing is finished. The extent of annealing may be determined by calculating a difference between resistance measurements taken before and after annealing. | 2015-08-27 |
20150243307 | MAGNETORESISTIVE SENSOR - In accordance with one implementation of the described technology, an apparatus comprises a sensor structure including a top shield which includes a top shield synthetic antiferromagnetic layer and a bottom shield including a bottom shield synthetic antiferromagnetic layer, wherein the bottom synthetic antiferromagnetic shield layer acts as a seed layer structure. | 2015-08-27 |
20150243308 | MAGNETIC RECORDING AND REPRODUCING DEVICE - According to one embodiment, a magnetic recording and reproducing device includes magnetic recording medium and a magnetic head. The magnetic recording medium includes a first surface. A plurality of bits is provided in the first surface. Each of the bits has a direction of magnetization corresponding to recorded information. The magnetic head includes a reproducing unit. The reproducing unit senses the direction of magnetization. The reproducing unit includes a first shield, a second shield, a first magnetic layer, a second magnetic layer, a third magnetic layer, a fourth magnetic layer, an intermediate layer, a first nonmagnetic layer, and a second nonmagnetic layer. The first and the second nonmagnetic layers include at least one selected from ruthenium, copper, and tantalum. A distance between the first shield and the second shield is not less than 3 times and not more than 7 times a length of each of the bits. | 2015-08-27 |
20150243309 | HEAD GIMBAL ASSEMBLY AND DISK DEVICE WITH THE SAME - According to an embodiment, a head gimbal assembly includes a support plate, a wiring member, a magnetic head and drive members. A gimbal portion of the wiring member includes a thin metallic plate including a tongue portion mounted with a magnetic head, a proximal end portion fixed to the support plate, support projections, and link portions, an insulating layer including first bridge portions extending from the proximal end portion to the tongue portion, and second bridge portions extending from the proximal end portion to middle portions of the first bridges, and a conducive layer including signal wirings extending to the tongue portion through the second and first bridge portions, and reinforcement wiring portions. The drive members are provided at the first bridge portions. | 2015-08-27 |
20150243310 | Systems and Methods for Multi-Head Separation Determination - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for determining a down track distance between two or more read heads on a read/write head assembly. | 2015-08-27 |
20150243311 | Systems and Methods for Synchronization Hand Shaking in a Storage Device - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for reporting a synchronization indication and for applying a synchronization window. As an example, a system is discussed that includes: a head assembly including a first read head and a second read head; a down track distance calculation circuit operable to calculate a down track distance between the first read head and the second read head; and a synchronization mark detection circuit. The synchronization mark detection circuit is operable to: assert a synchronization mark window based at a location based at least in part on the down track distance; query a first data set derived from the first read head for a synchronization mark occurring within the synchronization mark window; and query a second data set derived from the second read head for the synchronization mark occurring within the synchronization mark window. | 2015-08-27 |
20150243312 | CLOCK ACCURACY DETERMINING METHOD AND CLOCK ACCURACY DETERMINING DEVICE - According to one embodiment, when a timing error between a signal read back from a multi-spiral pattern pre-recorded on a magnetic disc and an SSW clock generated at a read/write channel is set as an SSW clock following error, SSW clock accuracy is determined based on results of comparison between SSW clock following errors read from two different points in each of spiral patterns constituting the multi-spiral pattern. | 2015-08-27 |
20150243313 | COMPENSATING FOR VOICE COIL MOTOR AND MICROACTUATOR DISTURBANCE IN A HARD DRIVE - In response to positioning a read/write head of a hard drive, a voice coil motor (VCM) input signal is applied to a voice coil motor and a microactuator (PZT) input signal is applied to a microactuator. A position signal is determined in response to positioning the read/write head. A PZT component is decoupled from the position signal to determine an estimated VCM response. The estimated VCM response used to determine an estimated VCM disturbance. A VCM component is decoupled from the position signal to determine an estimated PZT response. The estimated PZT response used to determine an estimated PZT disturbance. The VCM input signal and the PZT input signal are modified respectively to compensate for the estimated VCM disturbance and the estimated PZT disturbance. | 2015-08-27 |
20150243314 | TAPE HEAD WITH THERMAL TAPE-HEAD DISTANCE SENSOR - Tape head with thermal tape-head distance sensor to reduce the distance between the tape and the head to allow an increase in areal density. A tape head designed for reading and/or writing to a tape, including: a tape bearing surface shaped to form an air bearing when moving the tape with respect to the tape bearing surface; a thermal tape-head distance sensor circuit adapted to sense heat dissipated at the level of the tape bearing surface by the tape and thereby sense a distance between the tape bearing surface and the tape; and tape-head distance control means connected to the thermal tape-head distance sensor circuit to receive a signal provided by the tape-head distance sensor circuit and configured to alter the distance according to a signal received from the tape-head distance sensor circuit. This invention is further directed to a method of tape-head distance control for the above tape head. | 2015-08-27 |
20150243315 | Magnetic Recording Device - A magnetic recording device includes: a magnetic recording medium containing a plurality of recording layers; a magnetic recording head for conducting magnetic writing of information in the magnetic recording medium; and a magnetic reproducing head for conducting magnetic reading out of the information from the magnetic recording medium; wherein the magnetic recording head includes a high frequency oscillator for magnetically assisting the magnetic writing of the information so as to change a magnetization of at least one of the plurality of recording layers of the magnetic recording medium, thereby recording a plurality of information different from one another in the magnetic recording medium commensurate with a total amount of magnetization of the plurality of recording layers. | 2015-08-27 |
20150243316 | STORAGE SYSTEM AND CONTROL APPARATUS - A storage system includes a storage apparatus, a control apparatus, and a host apparatus. The storage apparatus includes a recording medium. The control apparatus includes a detection unit and a control unit. The detection unit detects whether a recording medium loaded in the storage apparatus is a stand-alone-only recording medium that is used in a stand-alone mode. When the recording medium is the stand-alone-only recording medium, the control unit registers a physical volume of the stand-alone-only recording medium as a logical volume and automatically switches the operation mode of the control apparatus to the stand-alone mode. | 2015-08-27 |
20150243317 | DYNAMICALLY CONTROLLING TAPE VELOCITY - A maximum velocity is dynamically determined during a tape drive operation to obtain a statistical standard deviation of a position error signal (PES) that yields an amount of stopwrite (SW) operations that avoids backhitching. The tape velocity is adjusted to the maximum velocity. | 2015-08-27 |
20150243318 | LIBRARY APPARATUS AND METHOD OF READING INFORMATION OF RECORDING MEDIUM - A library apparatus, includes: a plurality of cells in each of which a cartridge-type recording medium is attachably and detachably accommodated; a robot including a hand configured to handle the recording medium; and an information reading unit which is attachably and detachably accommodated in the cells and includes a plurality of readers configured to read information of the recording medium, wherein when the information reading unit is pulled into a portion of the hand, the plurality of readers project to be capable of reading the information of the recording medium. | 2015-08-27 |
20150243319 | Hard Disk Drive Disk Separator Plate Construction - Improving track following performance and reliability in a hard disk drive involves the use of disk separator plates positioned between adjacent recording disks, where a disk separator plate is made of stamped metal with plastic over-molded mounting portions coupled to the metal, thereby reducing the reliability risks associated with the use of fiber-filled materials. | 2015-08-27 |
20150243320 | ACCESSING PROTECTED CONTENT ON AN OPTICAL DISC - Embodiments for validating an optical disc storing protected content are provided. In one example, a method comprises receiving the optical disc in an optical disc drive, detecting with a signal detector a signal while the optical disc is at rest, spinning the optical disc, determining, with the signal detector, one or more of an electrical and magnetic effect on the signal resulting from the spinning of the optical disc, and validating the optical disc if the one or more of the electrical and magnetic effect meets a predetermined condition. | 2015-08-27 |
20150243321 | Reading Data from Hard Disks Having Reduced Preambles - An exemplary hard disk (HD) track has a full overhead section followed by user sections interleaved with intervening partial overhead sections that are too short for an HD drive (HDD) to attain sufficient timing lock using only one partial overhead section, but long enough for the drive to attain sufficient timing lock using multiple partial overhead sections to read user data from the user section immediately following the partial overhead section where sufficient timing lock is attained. The drive begins, but does not finish, attaining timing lock based on the first partial overhead section, but the drive does finish attaining timing lock based on the last partial overhead section. The drive can also read user data in subsequent user sections by maintaining or re-attaining sufficient timing lock using each successive partial overhead section. Increased user data storage is achieved without significantly impacting average latency of HDD read sessions compared to conventional HD drives. | 2015-08-27 |
20150243322 | Systems and Methods for Multi-Head Servo Data Processing - Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for processing servo data using two or more sensing heads. | 2015-08-27 |
20150243323 | System and Method for Identifying Failing Drives or Media in Media Library - Embodiments of methods and systems comprise identifying failing media and/or drives for a media library. Error data can be collected from media libraries. For each tape exhibiting an error rate of interest, a determination can be made whether the tape would still have been of interest had it not been loaded in certain drives. This information can be analyzed to identify failing drives or tapes. | 2015-08-27 |
20150243324 | IMAGE SEQUENCE ENHANCEMENT AND MOTION PICTURE PROJECT MANAGEMENT SYSTEM - The system enables conversion of black and white images to color images and/or two-dimensional images into three-dimensional images based on adding color and/or depth to images using masks for regions in the images, as well as reshaping of masks to cover objects that have moved and changed shape as the objects move in a sequence of images. Also, includes motion picture project management system for reviewers, coordinators and artists. Artists utilize image analysis and image enhancement and computer graphics processing for example to convert two-dimensional images into three-dimensional images or otherwise create or alter motion pictures. Enables the efficient management of projects related to motion pictures to enable enterprises to manage assets, control costs, predict budgets and profit margins, reduce archival storage and otherwise provide displays tailored to specific roles to increase worker efficiency. | 2015-08-27 |
20150243325 | AUTOMATIC GENERATION OF COMPILATION VIDEOS - Embodiments described herein include systems and methods for automatically creating compilation videos from an original video based on metadata associated with the original video. For example, a method for creating a compilation video may include determining a relevance score for video frames in an original video; selecting a plurality of relevant video frames from the original video based on the relevance score; selecting a plurality of video clips from the original video based on the relevance scores of the video frames; and creating a compilation video from the plurality of video clips. Each of the plurality of video clips, for example, may include at least one relevant video frame from the plurality of relevant video frames. | 2015-08-27 |
20150243326 | AUTOMATIC GENERATION OF COMPILATION VIDEOS - Embodiments described herein include systems and methods for automatically creating compilation videos from an original video based on metadata associated with the original video. For example, a method for creating a compilation video may include determining a relevance score for video frames in an original video; selecting a plurality of relevant video frames from the original video based on the relevance score; selecting a plurality of video clips from the original video based on the relevance scores of the video frames; and creating a compilation video from the plurality of video clips. Each of the plurality of video clips, for example, may include at least one relevant video frame from the plurality of relevant video frames. | 2015-08-27 |
20150243327 | INFORMATION PROCESSING METHOD AND ELECTRONIC APPARATUS - The present invention discloses an information processing method applied in an electronic apparatus, and the method includes deciding whether a first condition is satisfied when the electronic apparatus plays the first data; switching from a first moment of the first data to a second moment of the first data if result of decision indicates that the first condition is satisfied, the second moment and the first moment constituting a first time interval; deciding whether a second condition is satisfied; switching a third moment of the first data to a fourth moment of the first data if result of decision indicates that the second condition is satisfied, the fourth moment and the third moment constituting the second time interval; wherein the first condition is the same as the second condition, and the first time interval is different from the second time interval. | 2015-08-27 |
20150243328 | Content Output Device And Program - At the time of device starting or channel switching in a content output device, even when buffering of a sufficiently large size is performed in order to address multimedia processing at the time of start of a device and content switching, slow reproduction in which video and audio are synchronized with each other can be performed without keeping a user waiting for a long time, and at an arbitrary reproduction rate with the extent of not giving the user feeling of unnaturalness. The broadcasting reception unit initializes the delay amount to a predetermined start value, then gradually increases it with lapse of time, and stops the increase when the delay amount reaches a predetermined end value. Video and audio are synchronously and slowly reproduced at a reproduction rate decided by an increment per unit time of the delay amount. | 2015-08-27 |
20150243329 | PLAYBACK OF CONTENT PRE-DELIVERED TO A USER DEVICE - Systems and methods for displaying content pre-delivered to a user device, playing back content pre-delivered to a user device, and/or pre-delivering content to a user device during concurrent content playback, are described. In some embodiments, the systems and methods include or interact with a mobile application that displays descriptions of content available for playback via the mobile application along with indicators that represent a state of delivery (e.g., a state of pre-delivery) for the content items. | 2015-08-27 |
20150243330 | ELECTRONIC DEVICE - An electronic device includes a housing with a carrier therein. The carrier includes a recess with a restricting portion therein. An access unit is disposed in the recess. An elastic member is connected to the access unit and engaged with the restricting portion to restrict the access unit in the recess. A fixed member is connected to the access unit. A movable member is movably disposed on the carrier, including a first contact portion and a second contact portion. When an external force is exerted on the movable member along a first direction, the first contact portion pushes the elastic member along the first direction to deform and separate from the restricting portion, and the second contact portion pushes the fixed member to move along a second direction perpendicular to the first direction, such that the access unit can be removed from the housing. | 2015-08-27 |
20150243331 | Discrete Three-Dimensional Vertical Memory Comprising Off-Die Voltage Generator - The present invention discloses a discrete three-dimensional vertical memory (3D-M | 2015-08-27 |
20150243332 | SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE - A semiconductor device with a small cell area and excellent data read/write capability is achieved. In the semiconductor device, a wiring for writing data is provided, and a first transistor with a low off-state current is turned on to supply data to a gate of a second transistor and is turned off so that electric charge corresponding to data is retained. Moreover, a wiring for reading data is provided, and a third transistor is turned on so that data is read out in accordance with the on/off state of the second transistor retaining the electric charge. With this configuration, data write and data read are achieved in the same cycle. | 2015-08-27 |
20150243333 | DETERMINING A STATE OF A CELL STRUCTURE - A method is suggested for determining a state of a cell structure, wherein the cell structure includes several memory cells, the method includes: (i) detecting a first condition in a predetermined number of memory cells; and (ii) determining the state of the cell structure by assigning a second condition to the memory cells that do not show the first condition. | 2015-08-27 |
20150243334 | High Density Magnetic Random Access Memory - A method for writing to a magnetic memory comprising: providing a plurality of magnetic tunnel junctions arranged into columns and rows, applying a first current to a first conductive line coupled to a row of magnetic tunnel junctions at their ends adjacent to a free ferromagnetic layer to produce a bias magnetic field; and applying a second current to a second conductive line electrically coupled to a column of magnetic tunnel junctions at their ends adjacent to a pinned ferromagnetic layer to produce a spin momentum transfer in the free ferromagnetic layer of a first magnetic tunnel junction disposed at a first intersection region formed by the first conductive line and the second conductive line; wherein a joint effect of the first and second currents applied simultaneously reverses a magnetization direction of the free ferromagnetic layer of the first magnetic tunnel junction. Other embodiments of the magnetic memory are disclosed. | 2015-08-27 |
20150243335 | WRITE OPERATIONS IN SPIN TRANSFER TORQUE MEMORY - In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state. | 2015-08-27 |
20150243336 | Decreased Switching Current in Spin-Transfer Torque Memory - Switching current in Spin-Transfer Torque Memory (STTM) can be decreased. A magnetic memory cell is driven with a first pulse on a write line of the memory cell to heat the cell. The cell is then driven with a second pulse on the write line to set the state of the cell. | 2015-08-27 |
20150243337 | METHOD OF WRITING TO A SPIN TORQUE MAGNETIC RANDOM ACCESS MEMORY - A method includes sampling magnetic bits, applying a write current pulse to the magnetic bits to set them to a first logic state, resampling the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. A read or write operation may be received after initiation of writing back magnetic bits having the second state, where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling. | 2015-08-27 |
20150243338 | MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME - A memory device includes a memory cell array, an intensively accessed row detection circuit, and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The intensively accessed row detection circuit generates an intensively accessed row address indicating an intensively accessed memory cell row among the plurality of memory cell rows based on an accumulated access time for each of the plurality of memory cell rows. The refresh control unit preferentially refreshes neighboring memory cell rows adjacent to the intensively accessed memory cell row indicated by the intensively accessed row address when receiving the intensively accessed row address from the intensively accessed row detection unit. The memory device effectively reduces a rate of data loss. | 2015-08-27 |
20150243339 | APPARATUSES AND METHODS FOR SELECTIVE ROW REFRESHES - Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells. | 2015-08-27 |
20150243340 | INCREASED REFRESH INTERVAL AND ENERGY EFFICIENCY IN A DRAM - Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected a number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM. | 2015-08-27 |
20150243341 | VOLTAGE REGULATOR - A voltage regulator includes an amplifier, an output stage coupled with the amplifier, at least one back-bias circuit, and an output end coupled with the output stage and with the amplifier. The output stage includes at least one transistor having a bulk and a drain. The at least one back-bias circuit is coupled with the bulk of the at least one transistor. The output end is configured to be coupled with a memory array and with an output end of another voltage regulator. The back-bias circuit is configured to reduce a contention current between the voltage regulator and the other voltage regulator during a standby mode. | 2015-08-27 |
20150243342 | Memory Systems and Methods for Dynamically Phase Adjusting a Write Strobe and Data to Account for Receive-Clock Drift - A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift. | 2015-08-27 |
20150243343 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 2015-08-27 |
20150243344 | METHOD FOR CLOCK CONTROL IN DYNAMIC RANDOM ACCESS MEMORY DEVICES - A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry. | 2015-08-27 |
20150243345 | MEMORY MODULE AND MEMORY SYSTEM INCLUDING THE SAME - A memory module may include m memory devices. Each of the m memory devices may be divided into n regions each region including a plurality of rows corresponding to row addresses, where m and n are integers equal to or greater than 2. An address detector included in each of the m memory devices, wherein for each of the address detectors, the address detector may be configured to count a number of accesses to a particular row address included in one region of each of the m memory devices during a predetermined time period, and be configured to output a detect signal when the number of the counted accesses reaches a reference value. Each of the max-count address generators may be configured to count a number of accesses for a set of row addresses different from the sets of row addresses for which the other max-count address generators count accesses. | 2015-08-27 |
20150243346 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED WORD LINES - Disclosed herein is a semiconductor device that includes: a memory cell array including sub-word lines, bit lines and memory cells arranged at intersections of the sub-word lines and the bit lines; a plurality of sub-word drivers each drives an associated one of the sub-word lines; and a plurality of main word drivers each supplies a main word signal having one of a selected-level potential and an unselected-level potential to an associated one of the sub-word drivers. Each of the sub-word drivers drives the associated one of the sub-word lines to an active level when an associated one of the main word signals has the selected-level potential, and drives the associated one of the sub-word lines to an inactive level when the associated one of the main word signals has the unselected-level potential. The unselected-level potential of the main word signals is variable depending on an operation mode. | 2015-08-27 |
20150243347 | SEMICONDUCTOR DEVICE PREVENTING MULTIWORD STATE - To prevent a multiword state in which a plurality of word lines are active in a same memory bank, the semiconductor device includes a plurality of memory chips commonly receiving an access command, in which each of the plurality of memory chips are provided with a control circuit ignoring an new access command when the bank address information in the new access command is the same as the bank address information for the specified memory bank even if the new access command received before reading/writing data from/to the specified memory bank of the selected memory chip is completed contains chip selection information selecting another memory chip. | 2015-08-27 |
20150243348 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a word line, four or more bit lines, three or more MIS transistors having gate nodes thereof connected to the word line, the N-th (N: positive integer) one of the MIS transistors having two source/drain nodes thereof connected to the N-th and N+1-th ones of the bit lines, respectively, a sense circuit having two nodes and configured to amplify a difference between potentials of the two nodes, and a switch circuit configured to electrically couple the N-th and N+2-th ones of the bit lines to the two nodes of the sense circuit, respectively, and to electrically couple the N+1-th one of the bit lines to a fixed potential, for any numerical number N selected to detect single-bit data stored in the N-th and N+1-th ones of the MIS transistors. | 2015-08-27 |
20150243349 | AMPLIFIER - A circuit includes a plurality of first circuits, a selection circuit, and a second circuit. The selection circuit is configured to selectively couple a first circuit of the plurality of first circuits with the second circuit. The first circuit includes a first data line and a second data line; and a pair of cross-coupled transistors of a first type coupled with the first data line and the second data line. The second circuit includes a first switching circuit and a second switching circuit; and a pair of cross coupled transistors of a second type different from the first type. The pair of cross-coupled transistors of the first circuit and the pair of cross-coupled transistors of the second circuit are configured as part of a sense amplifier when the first switching circuit and the second switching circuit are turned on. | 2015-08-27 |
20150243350 | NOVEL SENSE AMPLIFIER SCHEME - A sense amplifier circuit includes a pair of data lines, a pair of inverters, and a data line charging circuit. Each of the inverters is connected to a respective one of the data lines. The data line charging circuit includes a transistor. The transistor has a source/drain terminal connected to one of the data lines and a gate terminal connected to the other of the data lines. | 2015-08-27 |
20150243351 | THRESHOLD VOLTAGE COMPENSATION IN A MEMORY - Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed “aggressor” memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. | 2015-08-27 |
20150243352 | NONVOLATILE MEMORY DEVICE HAVING RESISTIVE MEMORY CELL AND METHOD SENSING DATA IN SAME - A method of sensing multi-bit data stored in a resistive memory cell includes; determining a resistive value range for the memory cell by performing a first read operation using a first read voltage and a first reference current, determining whether the multi-bit data stored in the resistive memory cell has a first program state, upon determining that the multi-bit data stored does not have the first program state, selecting a second read voltage different from the first read voltage in response to the resistive value range of the resistive memory cell, and using the second read voltage to again determine whether the multi-bit data stored in the resistive memory cell has the first program state. | 2015-08-27 |
20150243353 | NONVOLATILE MEMORY DEVICE HAVING VARIABLE RESISTANCE MEMORY CELLS AND A METHOD OF RESETTING SAME - A method of resetting a variable resistance memory cell in a nonvolatile memory device includes; programming the memory cell to a set state using a corresponding compliance current, and then programming the memory cell to a reset state by pre-reading the variable resistance memory cell to determine its resistance and resetting the memory cell using a variable reset voltage determined in response to the determined resistance. | 2015-08-27 |
20150243354 | DISTRIBUTED CASCODE CURRENT SOURCE FOR RRAM SET CURRENT LIMITATION - In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant current mode during an access operation of a memory cell. An array control circuitry may be coupled to the memory cell array, and configured to control the constant current mode and supply an associated select bias voltage to the word line select transistor. | 2015-08-27 |
20150243355 | VARIABLE RESISTANCE MEMORY DEVICE AND RELATED PROGRAMMING METHOD DESIGNED TO REDUCE PEAK CURRENT - A method is provided for programming a nonvolatile memory device comprising a variable resistance memory cell connected to a bitline and a wordline. The method comprises precharging the bitline to a first bias voltage, precharging the wordline to a second bias voltage, wherein a voltage difference between the first bias voltage and the second bias voltage is less than a threshold voltage of the memory cell, and applying a first write voltage to the bitline and a second write voltage to the wordline in response to a select signal, wherein a voltage difference between the first write voltage and the second write voltage is greater than the threshold voltage. | 2015-08-27 |
20150243356 | HIGH THROUGHPUT PROGRAMMING SYSTEM AND METHOD FOR A PHASE CHANGE NON-VOLATILE MEMORY DEVICE - A phase change non-volatile memory device has a memory array with a plurality of memory cells arranged in rows and columns, a column decoder and a row decoder designed to select columns, and, respectively, rows of the memory array during operations of programming of corresponding memory cells. A control logic, coupled to the column decoder and the row decoder, is designed to execute a sequential programming command, to control the column decoder and row decoder to select one column of the memory array and execute sequential programming operations on a desired block of memory cells belonging to contiguous selected rows of the selected column. | 2015-08-27 |
20150243357 | Independent Ordering of Independent Threads - In an embodiment, a method for managing access to memory includes receiving requests for access to a memory from one or more devices, each particular request associated with one of a plurality of virtual channels. A tag is assigned to each request received. Each tag assigned is added to a linked list associated with the corresponding virtual channel. Each request received with the assigned tag is transmitted to the memory. Responses to the requests are received from the memory, each response having an associated tag, and the responses received are sent to the one or more devices based on the corresponding linked list and the corresponding tag. | 2015-08-27 |
20150243358 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells. | 2015-08-27 |
20150243359 | METHOD AND DEVICE FOR PROCESSING AN ERASE COUNTER - A embodiment relates to a method for processing an erase counter comprising erase counter fields, the method comprising the steps of (i) determining an unused erase counter field; (ii) writing a selection code and an address information in the unused erase counter field, wherein the selection code and the address information are combined to determine at least one physical address of a memory. | 2015-08-27 |
20150243360 | METHOD, APPARATUS AND DEVICE FOR DATA PROCESSING - A method for data processing is suggested including: (i) transforming electrical variables for each cell of a data bit of a memory into a time domain; and (ii) determining a predetermined state by comparing the transformed electrical variables of at least two data bits. | 2015-08-27 |
20150243361 | EEPROM PROGRAMMING - A method of programming an EEPROM, including: a first mode where a writing into cells is performed under a first voltage; and a second mode where the writing is performed under a second voltage smaller than the first one. | 2015-08-27 |
20150243362 | TIMED MULTIPLEX SENSING - Methods for determining memory cell states during a read operation using a detection scheme that reduces the area of detection circuitry for detecting the states of the memory cells by time multiplexing the use of portions of the detection circuitry are described. The read operation may include a precharge phase, a sensing phase, and a detection phase. In some embodiments, a first bit line and a second bit line may be precharged to a read voltage in parallel, and then sensing and/or detection of selected memory cells corresponding with the first bit line and the second bit line may be performed serially using the same detection circuitry by time multiplexing the use of the detection circuitry. In some cases, the time multiplexed detection circuitry may be used for detecting two or more states corresponding with two or more memory cells being sensed during a read operation. | 2015-08-27 |
20150243363 | ADJUSTING LOG LIKELIHOOD RATIO VALUES TO COMPENSATE MISPLACEMENT OF READ VOLTAGES - An apparatus having a circuit and an interface to a nonvolatile memory is disclosed. The circuit is configured to (i) perform one or more attempts of a soft-decision decode of data stored in the nonvolatile memory, where soft-decision decode uses a plurality of log likelihood ratio values stored in a table, (ii) generate one or more adjusted log likelihood ratio values by adding a constant value to one or more of the log likelihood ratio values in response to a failure to decode the data using the log likelihood ratio values and (iii) re-decode the data using the adjusted log likelihood ratio values. | 2015-08-27 |
20150243364 | APPARATUSES AND METHODS INCLUDING MEMORY ARRAY DATA LINE SELECTION - Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. Other embodiments including additional apparatus and methods are described. | 2015-08-27 |
20150243365 | ANTIFUSE WITH BYPASS DIODE AND METHOD THEREOF - The embodiments described herein provide antifuse devices and methods that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes an antifuse, a first diode coupled with the antifuse in a parallel combination, and a second diode coupled in series with the parallel combination. In such an embodiment the first diode effectively provides a bypass current path that can reduce the voltage across the antifuse when other antifuses are being programmed. As such, these embodiments can provide improved ability to tolerate programming voltages without damage or impairment of reliability. | 2015-08-27 |
20150243366 | ONE TIME PROGRAMMABLE MEMORY CELL AND METHOD FOR PROGRAMING AND READING A MEMORY ARRAY COMPRISING THE SAME - The present invention provides a one time programmable (OTP) memory cell including a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal, a first source terminal, and two first source/drain extension areas respectively coupled to the first drain terminal and the first source terminal. The following gate transistor has a second gate terminal, a second drain terminal, a second source terminal coupled to the first drain terminal, and two second source/drain extension areas respectively coupled to the second drain terminal and the second source terminal. The antifuse varactor has a third gate terminal, a third drain terminal, a third source terminal coupled to the second drain terminal, and a third source/drain extension area coupled with the third drain terminal and the third source terminal for shorting the third drain terminal and the third source terminal. | 2015-08-27 |
20150243367 | SHIFT REGISTER UNIT CIRCUIT, SHIFT REGISTER, ARRAY SUBSTRATE AND DISPLAY DEVICE - There are provided a shift register unit circuit, a shift register, an array substrate and a display device. The shift register unit circuit comprises: an input module configured to receive an input signal and output the input signal to a pulling-up node; an output module configured to receive the input signal and output a driving signal under a control of a first clock signal; a pulling-down module configured to pull down a potential at the pulling-up node and a signal output terminal under a control of a pulling-down node; a pulling-down control module configured to pull down the pulling-down node under a control of the input signal and pull up the pulling-down node under a control of a second clock signal; and a resetting module configured to reset the potential at the pulling-up node and the signal output terminal under a control of a resetting signal. A relatively small number of thin film transistors are used to suppress interference noise in the circuit, which saves wiring space and reduces the area occupied by the shift register unit circuit, so as to realize the narrow frame of the liquid crystal display using the shift register. | 2015-08-27 |
20150243368 | High-Speed Address Fault Detection Using Split Address ROM - High-speed address fault detection is described that uses a split address ROM (read only memory) for address fault detection in split array memory systems. In one aspect, a disclosed embodiment includes separate arrays of memory cells having a plurality of wordlines and being configured to be accessed based upon a wordline address. Two or more separate address ROMs are also provided with each address ROM being associated with a different one of the separate arrays and being configured to provide outputs based upon only a portion of the wordline address. Detection logic is coupled to the outputs from the address ROMs and is configured to provide one or more fault indicator outputs to indicate whether an address fault associated with the wordline address has occurred. The outputs form the address ROMs can also be used for wordline continuity fault detection. Other embodiments are also described. | 2015-08-27 |
20150243369 | TESTING MEMORY DEVICES WITH PARALLEL PROCESSING OPERATIONS - An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably. | 2015-08-27 |
20150243370 | TESTING MEMORY DEVICES WITH DISTRIBUTED PROCESSING OPERATIONS - ATE performs testing of memory devices with distributed processing operations. A redundancy analysis (RA) system has a first test site processor (TSP), operable for controlling a testing routine over multiple DUTs and analyzing redundancy data returned from a first of the DUTs. The RA has at least a second TSP, operable for analyzing redundancy data returned from a second of the DUTs. The RA may have one or more additional TSPs, each operable for analyzing redundancy data returned from an additional DUT. Controlling the testing routine includes directing the RA in each of the first and second (and any of the additional) TSPs. | 2015-08-27 |
20150243371 | CIRCUIT BOARD HAVING BYPASS PAD - An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided. | 2015-08-27 |
20150243372 | SYSTEMATIC MITIGATION OF MEMORY ERRORS - A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system. | 2015-08-27 |
20150243373 | KERNEL MASKING OF DRAM DEFECTS - Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold. | 2015-08-27 |
20150243374 | DEVICE AND METHOD FOR REPAIRING MEMORY CELL AND MEMORY SYSTEM INCLUDING THE DEVICE - Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device. | 2015-08-27 |
20150243375 | SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF - A semiconductor memory device includes a memory cell array including a plurality of memory cells and a plurality of redundancy memory cells, a fuse array to be programmed with information of a defective memory cell among the memory cells of the memory cell array, and a control unit suitable for setting up a program operation section for programming the fuse array in response to an external command, wherein when the control unit sets up the program operation section, the control unit sets up a refresh operation section for refreshing the memory cell array, which is terminated before the program operation section ends without overlapping with the program operation section. | 2015-08-27 |
20150243376 | MOLTEN SALT FISSION REACTOR - A plant and a modular fission reactor including a sealed reaction module. The sealed reaction module includes a core reactor vessel filled with molten salt and fuel and a moderator and reflector positioned inside the vessel housing, the moderator and reflector forming an active region in which fission occurs. The plant may include a power module and a heat exchanger that extracts heat from the reaction module and communicates the extracted heat to the power module. A second heat exchanger may extracts heat from the first heat exchanger and communicates the heat to the power module. The core reactor vessel may comprise at least one spare fuel container coupled to the reactor vessel and/or a chemistry module coupled to the reactor vessel. | 2015-08-27 |
20150243377 | COMPACT NUCLEAR REACTOR - A pressurized water nuclear reactor (PWR) includes a once through steam generator (OTSG) disposed in a generally cylindrical pressure vessel and a divider plate spaced apart from the open end of a central riser. A sealing portion of the pressure vessel and the divider plate define an integral pressurizer volume that is separated by the divider plate from the remaining interior volume of the pressure vessel. An internal control rod drive mechanism (CRDM) has all mechanical and electromagnetomotive components including at least a motor and a lead screw disposed inside the pressure vessel. Optionally CRDM units are staggered at two or more different levels such that no two neighboring CRDM units are at the same level. Internal primary coolant pumps have all mechanical and electromagnetomotive components including at least a motor and at least one impeller disposed inside the pressure vessel. Optionally, the pumps and/or CRDM are arranged below the OTSG | 2015-08-27 |
20150243378 | SHEATHED, ANNULAR METAL NUCLEAR FUEL - A sheathed, annular metal fuel system is described. A metal fuel pin system is described that includes an annular metal nuclear fuel alloy. A sheath may surround the metal nuclear fuel alloy, and a cladding may surround the sheath. A gas plenum may also be present. Mold arrangements and methods of fabrication of the sheathed, annular metal fuel are also described. | 2015-08-27 |
20150243379 | Nuclear plant with a containment shell and with a pressure relief system - A nuclear plant has a containment shell and a pressure relief line passing out of the containment shell and sealed by a shut-off valve, and through which a pressure relief flow can flow during relief operation, such that it is configured for particularly reliable management of critical scenarios where there is a considerable pressure increase within the containment shell at the same time as the release of hydrogen and/or carbon monoxide. A gas flow treatment device is provided upstream from the respective pressure relief line, and contains a flow duct and has a lower inflow opening and an upper inflow/outflow opening. Catalytic elements for eliminating hydrogen and/or carbon monoxide are arranged in the flow duct above the lower inflow opening. During a critical fault, the flow duct is flowed through from bottom to top by a gas mixture present in the containment shell by the principle of natural convection. | 2015-08-27 |
20150243380 | NUCLEAR REACTOR MODULE - A method of constructing a nuclear reactor module includes providing formwork defining a chamber in which is mounted a nuclear reactor comprising a nuclear reactor pressure vessel configured to contain nuclear fuel when in use, the formwork being housed within a containment structure configured to contain an internal pressure generated by an escape of coolant from a reactor coolant circuit. The method further includes filling one or more voids within the formwork with concrete through at least one concrete supply pipe that extends from outside of the containment structure, through the containment structure, and to the formwork; and venting the one or more voids within the formwork through one or more vent pipes, thereby forming a concrete support structure for the nuclear reactor. | 2015-08-27 |
20150243381 | DEVICE FOR CLOSING A DRIVE CASING PIPE - The invention relates to a device for closing a pipe opening, opening upwards, of a drive casing pipe accommodating the control rod drive of a boiling water reactor, said device comprising a closure plug with a plug housing, opening downwards, a sealing element guided axially so as to be movable within the plug housing, which element has a sealing face providing a sealing contact with an annular counter face defining the pipe opening, a locking element provided to fix the plug housing on the drive casing pipe, and a spring, which is supported by the upper end thereof on the plug housing and by the lower end thereof on the sealing element and holds said element in a lower end position. | 2015-08-27 |
20150243382 | PASSIVE CONTAINMENT AIR COOLING DEVICE AND SYSTEM WITH ISOLATED PRESSURE BOUNDARY - Provided is a passive containment air cooling device with an isolated pressure boundary, including a heat exchanger positioned inside and outside a containment, penetrating through an outer wall of the containment to be connected to the containment through a pipe and thus form a closed loop, and including a coolant, an air induction duct circulating air outside the heat exchanger, and a cooled air exhaust unit formed in the air induction duct to increase cooling efficiency of the heat exchanger. | 2015-08-27 |
20150243383 | WATER-AIR COMBINED PASSIVE FEED WATER COOLING APPARATUS AND SYSTEM - Disclosed herein is a water-air combined passive feed water cooling apparatus including a water cooling heat exchanger connected to the inside of a containment building to cool down heat of a steam generator using a water cooling method, a cooling tank including the water cooling heat exchanger therein and storing cooling water condensing main steam generated by the steam generator, an evaporative steam pipe connected to the cooling tank, the evaporative steam pipe, into which steam of the cooling water generated by the water cooling heat exchanger in the cooling tank flows, an air cooling heat exchanger connected to the evaporative steam pipe and cooling down and liquefying the steam flowing into the evaporative steam pipe, and a condensed water collecting pipe for refilling the cooling tank with the steam liquefied by the air cooling heat exchanger. | 2015-08-27 |
20150243384 | COOLING WATER SUPPLY TANK HAVING HEAT MIXING PREVENTION FUNCTION AND PASSIVE HIGH-PRESSURE SAFETY INJECTION SYSTEM AND METHOD USING THE SAME - A passive high-pressure safety injection system includes a compressor which generates high-temperature and high-pressure steam, a cooling water supply tank which supplies cooling water using the compressed steam, a nuclear reactor which receives the cooling water so that the nuclear reactor is maintained in a cooled state, and an internal circulation prevention structure which is provided in the cooling water supply tank and prevents the cooling water from circulating in the cooling water supply tank. | 2015-08-27 |
20150243385 | PASSIVELY-COOLED SPENT NUCLEAR FUEL POOL SYSTEM AND METHOD THEREFOR - A passively-cooled spent nuclear fuel pool system and method therefor. In one embodiment, the invention can be a passively-cooled spent nuclear fuel pool system comprising: a spent nuclear fuel pool comprising a body of liquid water having a surface level, at least one spent nuclear fuel rod submerged in the body of liquid water that heats the body of liquid water; a lid covering the spent nuclear fuel pool to create a hermetically sealed vapor space between the surface level of the body of liquid water and the lid; and a passive heat exchange sub-system fluidly coupled to the vapor space, the passive heat exchange sub-system configured to: (1) receive water vapor from the vapor space; (2) remove thermal energy from the received water vapor, thereby condensing the water vapor to form a condensed water vapor; and (3) return the condensed water vapor to the body of liquid water. | 2015-08-27 |
20150243386 | PUBLIC ACCEPTABLE SIMPLE WATER-COOLED REACTOR SYSTEM FOR GENERATING ELECTRICITY - The present invention relates to a public acceptable simple water-cooled reactor system for generating electricity and, more particularly, to a public acceptable simple water-cooled reactor system for generating electricity, which includes: a water-cooled reactor that uses water as a coolant and a moderator and generates thermal energy through nuclear fission; a power conversion system that is connected to the water-cooled reactor so as to indirectly receive the thermal energy generated by the reactor core of the water-cooled reactor via a heat exchanger in a containment and generate electricity; a in-containment refueling water storage tank that is used when the water-cooled reactor is refueled with a nuclear fuel; and a containment that surrounds the entire reactor system including the water-cooled reactor and the in-containment refueling water storage tank. | 2015-08-27 |
20150243387 | PHOTOCATALYST INJECTION METHOD AND PHOTOCATALYST INJECTION SYSTEM - A photocatalyst injection system including: a reactor primary system coolant collection section collecting a reactor primary system coolant containing a noble metal or noble metal ion from a reactor primary system; a photocatalyst addition section adding a photocatalyst to the collected reactor primary system coolant; an ultraviolet irradiation section irradiating, with ultraviolet rays, the coolant to which the photocatalyst has been added for producing, in the coolant, a noble metal-carrying photocatalyst in which the noble metal is carried on a surface of the photocatalyst; and a noble metal-carrying photocatalyst injection section injecting the coolant containing the noble metal-carrying photocatalyst into the reactor primary system. | 2015-08-27 |
20150243388 | NUCLEAR STEAM SUPPLY SYSTEM - A nuclear steam supply system having a start-up sub-system for heating a primary coolant. In one embodiment, the invention can be a nuclear steam supply system comprising: a reactor vessel having an internal cavity, a reactor core comprising nuclear fuel disposed within the internal cavity; a steam generating vessel fluidly coupled to the reactor vessel; a primary coolant loop formed within the reactor vessel and the steam generating vessel, a primary coolant in the primary coolant loop; and a start-up sub-system fluidly coupled to the primary coolant loop, the start-up sub-system configured to: (1) receive a portion of the primary coolant from the primary coolant loop; (2) heat the portion of the primary coolant to form a heated portion of the primary coolant; and (3) inject the heated portion of the primary coolant into the primary coolant loop. | 2015-08-27 |
20150243389 | PRESSURIZED WATER REACTOR WITH UPPER VESSEL SECTION PROVIDING BOTH PRESSURE AND FLOW CONTROL - A pressurized water reactor (PWR) includes a vertical cylindrical pressure vessel having a lower portion containing a nuclear reactor core and a vessel head defining an integral pressurizer. A reactor coolant pump (RCP) mounted on the vessel head includes an impeller inside the pressure vessel, a pump motor outside the pressure vessel, and a vertical drive shaft connecting the motor and impeller. The drive shaft does not pass through the integral pressurizer. The drive shaft passes through a vessel penetration of the pressure vessel that is at least large enough for the impeller to pass through. | 2015-08-27 |
20150243390 | SYSTEM FOR STORAGE AND TRANSPORTATION OF SPENT NUCLEAR FUEL - A concrete storage module ( | 2015-08-27 |
20150243391 | SYSTEM, METHOD AND APPARATUS FOR PROVIDING ADDITIONAL RADIATION SHIELDING TO HIGH LEVEL RADIOACTIVE MATERIALS - A system, method and apparatus for providing radiation shielding to a ventilated cask for holding high level radioactive materials. In one aspect, the tubular shell is positioned to circumferentially surround the cask so that an annular gap exists between the tubular shell and a sidewall of the cask. The tubular shell includes a first air flow inlet and a second air flow inlet. An air flow barrier is placed within the annular gap, separating the annular gap into a first chamber and a second chamber. A first air flow into the first air flow inlet passes through the first chamber and into the inlet vent of the cask, a second air flow into the second air flow inlet passes through the second chamber and to an opening at the top end of the tubular shell, and the air flow barrier prohibits cross-flow of air between the first and second chambers. | 2015-08-27 |
20150243392 | INSTALLATION COMPRISING A GLOVE BOX AND A GLOVE CHANGE DEVICE INCORPORATING MONITORING OF THE GLOVE CHANGE - Installation comprising at least one glove box ( | 2015-08-27 |
20150243393 | METHOD AND DEVICE FOR LIMITING THE DEGASSING OF TRITIATED WASTE ISSUED FROM THE NUCLEAR INDUSTRY - A method and device for limiting the degassing of tritiated waste issued from the nuclear industry are provided. The method reduces an amount of generated tritiated hydrogen (T | 2015-08-27 |
20150243394 | COMPOSITION AND PROCESS FOR PROCESSING RADIOACTIVE WASTE FOR SHIPMENT AND STORAGE - A process for encapsulating a radioactive object to render the object suitable for shipment and/or storage, and including the steps of preparing a plastic material, causing the plastic material to react with a foaming agent, generating a foaming plastic, encapsulating the radioactive object in the foaming plastic, and allowing the foaming plastic to solidify around the radioactive object to form an impervious coating. | 2015-08-27 |
20150243395 | Techniques for On-Demand Production of Medical Isotopes Such as Mo-99/Tc-99m and Radioactive Iodine Isotopes Including I-131 - A system for radioisotope production uses fast-neutron-caused fission of depleted or naturally occurring uranium targets in an irradiation chamber. Fast fission can be enhanced by having neutrons encountering the target undergo scattering or reflection to increase each neutron's probability of causing fission (n, f) reactions in U-238. The U-238 can be deployed as one or more layers sandwiched between layers of neutron-reflecting material, or as rods surrounded by neutron-reflecting material. The gaseous fission products can be withdrawn from the irradiation chamber on a continuous basis, and the radioactive iodine isotopes (including I-131) extracted. | 2015-08-27 |
20150243396 | Techniques for On-Demand Production of Medical Isotopes Such as Mo-99/Tc-99m and Radioactive Iodine Isotopes Including I-131 - A system for radioisotope production uses fast-neutron-caused fission of depleted or naturally occurring uranium targets in an irradiation chamber. Fast fission can be enhanced by having neutrons encountering the target undergo scattering or reflection to increase each neutron's probability of causing fission (n, f) reactions in U-238. The U-238 can be deployed as one or more layers sandwiched between layers of neutron-reflecting material, or as rods surrounded by neutron-reflecting material. The gaseous fission products can be withdrawn from the irradiation chamber on a continuous basis, and the radioactive iodine isotopes (including I-131) extracted. | 2015-08-27 |
20150243397 | X-RAY INTERFEROMETRIC IMAGING SYSTEM - An x-ray interferometric imaging system in which the x-ray source comprises a target having a plurality of structured coherent sub-sources of x-rays embedded in a thermally conducting substrate. The system additionally comprises a beam-splitting grating G | 2015-08-27 |
20150243398 | X-RAY GRID STRUCTURE AND X-RAY APPARATUS INCLUDING THE SAME - An X-ray grid structure is configured to be detachably attached to an X-ray detector and includes an X-ray grid configured to selectively transmit X-rays; and holders fixed along an outer edge of the X-ray grid, wherein at least one of the holders includes an elastic material and is configured to be bendable in a direction crossing an attachment direction, which is a direction of attaching the X-ray detector to the X-ray grid. | 2015-08-27 |