35th week of 2009 patent applcation highlights part 19 |
Patent application number | Title | Published |
20090212787 | MALFUNCTION DETECTING CIRCUIT AND MALFUNCTION DETECTING METHOD FOR DETECTING MALFUNCTION OF CURRENT-SENSING RESISTOR, AND POWER CONVERTING SYSTEM APPLYING THE MALFUNCTION DETECTING CIRCUIT - A malfunction detecting circuit for detecting malfunction of a current sensing resistor includes a reference-voltage generating circuit and a comparing circuit, wherein the reference-voltage generating circuit is utilized to generate a reference voltage signal varying with the on time period of a power switch of a power converting system. The comparing circuit compares a sensing voltage signal corresponding to a current flowing through the current sensing resistor with the reference voltage signal to generate a comparing result indicating whether the malfunction occurs. | 2009-08-27 |
20090212788 | Conductivity Counter - A conductivity counter and method of determining conductivity of a fluid sample are disclosed. The counter is suitable for high-speed, accurate counting of discrete events or items, such as cancer cells, passing through a fluid sample cell. A variable frequency current source is used to supply an excitation current to a sample cell connected in parallel with an inductance or the electrical equivalence of an inductance. This configuration can be accurately modeled as a parallel RLC circuit when the system is operated at a stable frequency. The current source frequency is tuned to the resonance frequency of the equivalent RLC circuit, which effectively eliminates the capacitive and inductive components of the impedance, leaving only purely resistive components. The output of the equivalent RLC circuit is connected to a high input impedance buffer amplifier and then to a phase sensitive detector, which detects the phase shift resulting from the equivalent RLC circuit. The output is filtered and a differencing amplifier is used to zero out the output signal due to the system components and the sample cell buffer solution prior to taking active readings. The remaining output signal is due to perturbations in the fluid sample, such as passing cancer cells. This output is sent to a high-gain output amplifier and then supplied to a suitable signal processing device or system, such as a computer. | 2009-08-27 |
20090212789 | MODIFIED TDR METHOD AND APPARATUS FOR SUSPENDED SOLID CONCENTRATION MEASUREMENT - This invention utilizes the principle of time domain reflectometry (TDR) to develop an improved apparatus and method for suspended solid concentration (SSC) measurement. The apparatus comprises a TDR sensing waveguide for stably determining an electromagnetic-wave (EM-wave) travel time and a temperature sensor. The TDR sensing waveguide and the temperature sensor are submerged in a suspension to detect the EM-wave travel time and the temperature. A temperature-corrected relationship between EM-wave travel time and SSC is found and used to estimate the SSC. Although TDR has been used for measuring soil moisture content and high SSC, its accuracy is not satisfactory for typical SSC monitoring. The present invention improves the accuracy of TDR in SSC measurement by providing the apparatus and method disclosed herein, which are not affected by an electrical conductivity of the suspension and particle sizes of suspended solids therein, and therefore meet the requirements of general engineering applications and environmental monitoring. | 2009-08-27 |
20090212790 | METHOD OF ESTIMATING CHANNEL BANDWIDTH FROM A TIME DOMAIN REFLECTOMETER (TDR) MEASUREMENT - Bandwidth of a test channel is determined from a single port Time Domain Reflectometer (TDR) measurement with the channel terminated in a short or an open circuit. Bandwidth is estimated by: (1) making a TDR measurement of a channel terminated in a short or open circuit; (2) determining a maximum slope of the reflection from the TDR measurement; (2) calculating an interpolated rise or fall time, for example by taking 80% of the applied voltage between the 10% and 90% points, and then dividing the applied voltage by the maximum slope determined; (3) dividing the overall interpolated rise time by the square root of two to account for the TDR signal proceeding through the channel twice; (4) removing the contribution of rise time from measurement equipment; and (5) completing calculation of channel bandwidth using a formula to relate bandwidth to rise time, such as: bandwidth=0.35/rise time. | 2009-08-27 |
20090212791 | Method for determining the electrical resistance of an electrical supply lead to sensor elements and a sensor arrangement - The invention relates to a method for determining the electrical resistance of an electrical supply lead to sensor elements and concerns a sensor arrangement. The sensor elements are interconnected to form a sensor arrangement, and the electrical total resistance of the supply lead to the sensor elements is determined by effecting a measurement involving an electrical component. The electrical total resistance of the supply lead to the sensor elements is compared to a reference value, whereby the reference value is the value of the electrical total resistance of a reference component of the circuit arrangement and of its electrical leads. The reference value is also determined by effecting a measurement. | 2009-08-27 |
20090212792 | Inspection Method and Inspection Apparatus - There is established an easier inspection method with which it is not required to set up probes on wires. Also, there is provided an inspection apparatus using this inspection method. With the inspection apparatus or inspection method, primary coils of an inspection substrate and secondary coils of a device substrate are superimposed on each other so that a certain space is maintained therebetween. An AC signal is inputted into the primary coils, thereby generating an electromotive force in each secondary coil by electromagnetic induction. Then, each circuit provided on the device substrate is driven using the electromotive force and information possessed by an electromagnetic wave or electric field generated in this circuit is monitored, thereby detecting each defective spot. | 2009-08-27 |
20090212793 | STRUCTURES FOR TESTING AND LOCATING DEFECTS IN INTEGRATED CIRCUITS - A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices. | 2009-08-27 |
20090212794 | TEST KEY FOR SEMICONDUCTOR STRUCTURE - A test key for a semiconductor structure is provided for in-line defecting defects of the contact. The test key is disposed on a scribe line of a wafer substrate, and includes conductive structures and contacts under test. The conductive structures are electrically connected with the substrate and the contacts under test are not electrically connected with the substrate. The conductive structures and the contacts under test are regularly arranged in array. When an electronic beam is utilized to perform in-line monitoring, the normal contacts under test will be shown as bright dots and the bright dots are regularly arranged in the array; any contact under test with defect will be shown as a dark dot which results in an irregular arrangement of the bright dots. | 2009-08-27 |
20090212795 | Probe card with segmented substrate - A probe card for testing of semiconductor dice is provided. The probe card includes a mounting plate and a plurality of substrate segments supported by the mounting plate. | 2009-08-27 |
20090212796 | DEVICE, SYSTEM AND METHOD FOR TESTING AND ANALYZING INTEGRATED CIRCUITS - This invention relates to a semiconductor device for testing and analyzing integrated circuits ( | 2009-08-27 |
20090212797 | Probe card - The present invention provides a probe card that is easily assembled and maintained and configured to prevent the controlled level of a space transformer from changing due to various causes such as a thermal deformation during a test process. The probe card includes an installation member where probe tips are provided and a printed circuit hoard (PCB) disposed on the installation member. A reinforcement member is fixed to a top surface of the PCB, and a contact member is disposed between the PCB and the reinforcement member. The contact member and the installation member are fixed by means of a connect member inserted into an insert hole formed at the PCB, and a control bolt provided for controlling the level of the installation member is inserted into control holes formed at the installation member, the PCB, and the reinforcement member sequentially in a bottom-to-top direction. Due to a convex-up top surface of the contact member, the contact member continues to contact the reinforcement member even though the installation member and the contact member are inclined while controlling the level of the installation member. | 2009-08-27 |
20090212798 | PROBE CARD, MANUFACTURING METHOD OF PROBE CARD, SEMICONDUCTOR INSPECTION APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A silicon substrate is used as a mold, and thin films such as metal films and polyimide films are sequentially stacked on the silicon substrate by using photolithography techniques, thereby forming a probe sheet having contact terminals having a pyramidal shape or a truncated pyramidal shape disposed at distal ends of cantilever beam structures. A fixing substrate is further fixed to the probe sheet, and then, the formed probe sheet is sequentially stacked and formed on the silicon substrate, the substrate is fixed, and the silicon substrate and predetermined polyimide films are removed by etching, thereby forming the group of contact terminals with the cantilever beam structures at a time. | 2009-08-27 |
20090212799 | METHODS AND APPARATUS THAT SELECTIVELY USE OR BYPASS A REMOTE PIN ELECTRONICS BLOCK TO TEST AT LEAST ONE DEVICE UNDER TEST - In one embodiment, apparatus for testing at least one device under test (DUT) includes a tester input/output (I/O) node, a DUT I/O node, a remote pin electronics block, a bypass circuit, and a control system. The remote pin electronics block provides a test function and is coupled between the tester I/O node and the DUT I/O node. The bypass circuit is coupled between the tester I/O node and the DUT I/O node and provides a signal bypass path between the tester I/O node and the DUT I/O node. The signal bypass path bypasses the test function provided by the remote pin electronics block. The control system is configured to enable and disable the bypass circuit. Methods for using this and other related apparatus to test one or more DUTs are also disclosed. | 2009-08-27 |
20090212800 | ELECTRICAL CONNECTING APPARATUS - The object of the present invention is to prevent an operator from touching electronic elements arranged on an upper surface of a probe assembly of an electrical connecting apparatus at the time of carrying the electrical connecting apparatus and to restrict bowing of the probe assembly caused by the temperature difference between the upper surface and the lower surface of the probe assembly. An electrical connecting apparatus | 2009-08-27 |
20090212801 | METHOD OF MAKING HIGH-FREQUENCY PROBE, PROBE CARD USING THE HIGH-FREQUENCY PROBE - A high frequency probe preparation method for making a high frequency probe for high frequency testing to assure signal integrity by means of making a sleeve assembly subject to the size of a predetermined bare needle and then sleeving bare needle by the sleeve assembly to form a high-frequency probe is disclosed to include the steps of: a) providing an insulated tube, and b) forming a conducting layer on the outer surface of the insulated tube which having a metal layer for grounding. The insulated tube and the conducting layer constitute the sleeve assembly. The metal layer is formed by means of physical deposition, chemical deposition, mixture of physical and chemical deposition or electrochemical deposition. | 2009-08-27 |
20090212802 | Test system with high frequency interposer - An interposer with a conductive housing is disclosed. Conductive members pass through insulators positioned in openings in the conductive housing. The conductive housing may be grounded, providing a closely spaced ground structure for signal conductors passing through the conductive housing and therefore providing a desirable impedance to signals carried by the conductive members. Such an interposer may be used in a test system to couple high speed signals between instruments that generate or measure test signals and devices under test. | 2009-08-27 |
20090212803 | PROBE APPARATUS, PROBING METHOD, AND STORAGE MEDIUM - A probe apparatus is capable of being scaled-down and reducing a manufacturing cost thereof in a probe apparatus having a plurality of probe apparatus main bodies. A loader unit for transferring a wafer between carriers accommodating therein wafers and the probe apparatus main bodies includes: an upper camera for imaging the arrangement of chips to be inspected of the wafer; a lower camera for imaging probe needles; an X-Y-Θ stage for moving the position of the wafer W in a horizontal direction and a second loader mechanism for moving the wafer in a vertical direction. Accordingly, a fine alignment of the wafer is performed by the loader unit to adjust the position of the wafer. | 2009-08-27 |
20090212804 | NEEDLE TRACE TRANSFER MEMBER AND PROBE APPARATUS - A needle trace transfer member to which needle traces of probes are transferred is installed at a movable mounting table to align the probes before electrical characteristics of a target object on the mounting table are inspected by bringing the probes into electrical contact with the target object. The needle trace transfer member is made of a shape memory polymer transformed reversibly and rapidly between a glass state with a high modulus elasticity and a rubber state with a low modulus of elasticity near its glass transition temperature. The glass transition temperature is set to a temperature close to a set temperature of the mounting table. The shape memory polymer is mainly made of polyurethane-based resin. | 2009-08-27 |
20090212805 | PROBE OF VERTICAL PROBE CARD - A probe of a vertical probe card is disclosed. The probe has a probe tip and a surface region extended from the probe tip about 1-10 mil. The surface region is coated with a nano-film of high electro-conductive nano-material, and the thickness of the nano-film is about 1-20 nm. The nano-film of the probe can efficiently provide excellent no-clean property and higher electro-conductivity for lowering contact force and elongating usage lifetime of the probe of vertical probe card. Accordingly the yield of wafer testing can be improved, the frequency of cleaning probe can be lowered, and the total testing cost can be reduced. | 2009-08-27 |
20090212806 | System for Making Contact Between a Transmit/Receive Module and a Testing Device - A system for making electrical contact between a transmit/receive module and a testing device for the transmission of high-frequency signals includes a mechanically guided, frame-shaped contacting unit having a plurality of contact elements for contacting the TR module. The contacting unit surrounds the T/R module and is positioned relative to the T/R module such that the contact with the T/R module is established in one operation via the contact elements. A line substrate, which is arranged on the contacting unit and electrically connected with it, is constructed as a shielded triplate line by which the high-frequency signals can be conducted to the testing device. | 2009-08-27 |
20090212807 | PROBE OF CANTILEVER PROBE CARD - A probe of a cantilever probe card (Epoxy probe card) is disclosed. The probe has a tip and a surface region extended from the tip of the probe about 5-10 mil is coated with a nano-film of high electro-conductive nanomaterial. The thickness of the nano-film is about 1-20 nm. Through the coating process, the nano-film coated on the probe of the cantilever probe card can efficiently provide the excellent advantages of no-clean, stable electro-conductivity, minimum overdrive force and longer usage lifetime for the probe of cantilever probe card. Accordingly, the yield of wafer testing can be improved and the frequency of cleaning the probe can be decreased. Furthermore, the total testing cost can be reduced. | 2009-08-27 |
20090212808 | ELECTRO-OPTICAL DEVICE AND ELECTRONIC APPARATUS - An electro-optical device includes a test circuit for testing drive of a plurality of pixel units and a plurality of test terminals that output inputted signals to the test circuit or that output signals inputted from the test circuit. The test terminals including a first test terminal input with a high frequency signal with a frequency higher than a frequency of a signal output from a second terminal. A third test terminal is interposed between the first test terminal and the second test terminal. | 2009-08-27 |
20090212809 | DEVICE TEST AND DEBUG USING POWER AND GROUND TERMINALS - The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals. | 2009-08-27 |
20090212810 | ISOLATION CIRCUIT - The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor configured for connection to a supply voltage via a first terminal; a register connected to the first transistor; a second transistor in parallel with a resistor, wherein the second transistor is configured for connection to the first terminal, with a gate of the second transistor configured for connection to an output of the register; and wherein the second transistor is configured for connection to a second terminal, the second transistor having a state that depends on a status of the register. | 2009-08-27 |
20090212811 | Semiconductor device and method for testing the same - A method for testing a semiconductor device having plural transmitting (TX) circuits and plural receiving (RX) circuits at a low cost and in a short time. The semiconductor device includes two or more pairs of transmitting and receiving circuits. Each of the transmitting circuits converts parallel data to serial data and transmits the converted serial data to external while each of the receiving circuits receives serial data from external and converts the received serial data to parallel data. Furthermore, the semiconductor device includes a device that enables two or more selected pairs of transmitting and receiving circuits to be connected serially and alternately. The semiconductor device can be configured so that the serially connected transmitting or receiving circuit in the first stage inputs a test signal to be compared with a signal output from the serially connected receiving or transmitting circuit in the last stage. | 2009-08-27 |
20090212812 | Multi-chip package semiconductor device and method of detecting a failure thereof - A semiconductor chip may include at least one power supply pad for receiving an external power voltage, at least one input/output pad, an internal function block that may be configured to operate based on a power voltage to at least one of receive and transmit a signal through the input/output pad, and a mode set circuit that may enable or disable the power voltage by a mode set signal in an individual chip test mode. | 2009-08-27 |
20090212813 | ELECTRONIC DEVICE BOARD LEVEL SECURITY - A system may include a printed circuit board, a first component located on the printed circuit board, the first component having a first unique identifier and a processor located on the printed circuit board, the processor including a one time programming section. The processor may acquire the first unique identifier from the first component and store the first unique identifier in the one time programming section during the first time initialization. Upon subsequent initializations, the processor may acquire the first unique identifier from the first component and compare the first unique identifier to the stored first unique identifier. The processor may allow the subsequent initializations to proceed if the first unique identifier matches the stored first unique. The processor may disallow the subsequent initializations from proceeding if the first unique identifier does not match the stored first unique identifier. | 2009-08-27 |
20090212814 | Deliberate Destruction of Integrated Circuits - A method is provided for intentionally permanently disabling a target device. The target device comprises an integrated circuit having one or more electronic devices, where the target device is disabled by destroying at least one or more electronic devices. The method comprises charging at least one capacitor in an integrated circuit disabling device, detecting when at least one capacitor is charged, and selecting at least one target signal path associated with the target device for disabling. The method further includes connecting the integrated circuit disabling device to the target signal path and rapidly discharging at least one capacitor to the selected target signal path. The discharging step may apply a high energy impulse to destroy the one or more electronic devices of the target device. | 2009-08-27 |
20090212815 | TRIPLE LATCH FLIP FLOP SYSTEM AND METHOD - A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch. | 2009-08-27 |
20090212816 | Impedance adjustment circuit - Disclosed is an impedance adjustment circuit including a comparator and a resistor control circuit. The comparator compares the resistance value of an external resistor and that of a replica resistor that forms a replica of a terminal resistor. The resistor control circuit includes a replica resistor control counter, a resistor-under-adjustment control signal holding circuit and a monitor circuit. The replica resistor control counter counts up and down based on the comparison result by the comparator to output a control signal to the replica resistor. The resistor-under-adjustment control signal holding circuit holds a control signal that is delivered to the terminal resistor. The monitor circuit receives the state of the counter and an output of the retention circuit and, in case the difference between the count state of the replica resistor control counter and an output of the resistor-under-adjustment control signal holding circuit is within a preset range, delivers the output of the resistor-under-adjustment control signal holding circuit as an input to the resistor-under-adjustment control signal holding circuit. | 2009-08-27 |
20090212817 | Configuration information writing apparatus, configuration information writing method and computer program product - A configuration information writing apparatus for writing configuration information defining a logical configuration of a logic circuit device into the logic circuit device to change the logical configuration thereof, the apparatus comprising: a difference extracting unit that acquires plural pieces of configuration information and extracts differences between each of the acquired plural pieces of configuration information; a differential relation generating unit that generates a differential relation indicating a relation of the differences between each of the plural pieces of configuration information based on the differences extracted by the difference extracting unit; and an order information generating unit that generates order information specifying an order of writing the configuration information from the relation of the differences indicated by the differential relation generated by the differential relation generating unit. | 2009-08-27 |
20090212818 | Integrated circuit design method for improved testability - An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a flipflop-replaced netlist from the netlist. In classifying the flipflops, a flipflop which is connected to an input terminal of the macro directly or through an input-side logic cone and operated on the same clock signal as the macro is classified as a control type, and a flipflop which has a data output connected to an input terminal of the macro directly or through the input-side logic cone and operated on a different clock signal is classified as a hold type. In the flipflop-replaced netlist, the flipflop classified as the control type is replaced with a control flipflop which is configurable to toggle a data output thereof in synchronization with the clock signal by configuring a control input separately provided a data input thereof, and the flipflop classified as the hold type is replaced with a first hold flipflop which is configurable to hold data so that the data hold therein is unchanged. | 2009-08-27 |
20090212819 | METHOD AND SYSTEM FOR CHANGING CIRCUITS IN AN INTEGRATED CIRCUIT - A method for modifying an integrated circuit and integrated circuits are provided. The method includes: providing an integrated circuit design comprising a plurality of circuit books having a first threshold voltage; and replacing at least one of the plurality of circuit books with at least one gate array book having a second threshold voltage that is lower than the first threshold voltage. | 2009-08-27 |
20090212820 | DECODER CIRCUIT, DECODING METHOD, OUTPUT CIRCUIT, ELECTRO-OPTICAL DEVICE, AND ELECTRONIC INSTRUMENT - A decoder circuit comprises: first decoder section that decodes an m-bit address signal portion of an (m+n)-bit address signal; and a second decoder section that decodes an n-bit address signal portion of the (m+n)-bit address signal, the first decoder section including a first AND operation circuit section that outputs signals that indicate a decoding result of the m-bit address signal portion, and a second AND operation circuit section that outputs signals that indicate a decoding result of part of the m-bit address signal portion, and the second decoder section including a third AND operation circuit section that outputs signals that indicate a decoding result of the n-bit address signal portion, and a fourth AND operation circuit section that outputs signals that indicate a decoding result of part of the n-bit address signal portion. | 2009-08-27 |
20090212821 | BULK INPUT CURRENT SWITCH LOGIC CIRCUIT - A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed bit a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current. | 2009-08-27 |
20090212822 | BULK INPUT CURRENT SWITCH LOGIC CIRCUIT - A current switch logic circuit is disclosed. The circuit includes a current sense amplifier formed by a first transistor to a fifth transistor, and a logic tree. The logic tree is used to generate a first current and a second current. The current sense amplifier generates a first output signal and a second output signal according to the first current and the second current. | 2009-08-27 |
20090212823 | Low Jitter CMOS to CML Converter - The present invention provides a low jitter CMOS to CML converter, including: a differential circuit including differential pair transistors, a pair of loads and a biased transistor, each differential transistor of the differential pair transistors having an input terminal, an output terminal and a connection terminal. With the current compensation device, an additional current path may be provided for the current of the biased transistor which is used as a constant current source when the differential transistors are turned off, so that the peak tail current in the biased transistor current may be eliminated. Thus, the problem caused by the tail current that the common mode output voltages of the converter is unstable and has a high jitter may be solved. | 2009-08-27 |
20090212824 | Method and Apparatus for Automatic Optimal Sampling Phase Detection - A system for determining an optimal sampling phase is provided. The system includes a plurality of analog to digital converters, each receiving an analog signal and a clock phase signal and generating an output. A clock generator receives a reference clock and generates a plurality of clock phase signals. A sampling phase system receives the plurality of outputs of the analog to digital converters and generates an optimal sampling phase. | 2009-08-27 |
20090212825 | HIGH SPEED COMPARATOR - A comparator comprises a differential amplifier (T | 2009-08-27 |
20090212826 | HYSTERESIS COMPARATOR - Disclosed herein is a hysteresis comparator for performing a binarization determination with respect to an input signal having a consecutively varying voltage level based on two threshold voltages having different voltage levels and generating an output signal based on a result of the determination. The hysteresis comparator includes a top peak detector for detecting a top peak of the input signal and generating a top peak detect voltage based on the detected top peak, a bottom peak detector for detecting a bottom peak of the input signal and generating a bottom peak detect voltage based on the detected bottom peak, a threshold voltage generator for generating the first and second threshold voltages within a range between a voltage level of the top peak detect voltage and a voltage level of the bottom peak detect voltage, and a voltage comparison circuit for comparing the voltage level of the input signal with the voltage levels of the first and second threshold voltages to perform the binarization determination with respect to the input signal, and generating the output signal based on the determination result. | 2009-08-27 |
20090212827 | Correlated double sampling circuit - A correlated double sampling circuit includes a first capacitor and a comparator. The first capacitor may be configured to receive a ramp signal via a first end. The comparator may be configured to receive the ramp signal and an output signal of a unit pixel circuit via a differential amplifier included in the comparator. The comparator may be also be configured to compare the output signal with the ramp signal and may be configured to directly receive the output signal of the unit pixel circuit at a first input terminal of the differential amplifier. A second input terminal of the differential amplifier is connected to a second end of the first capacitor. | 2009-08-27 |
20090212828 | Load Driving Circuit - To provide a load drive circuit that has a satisfactory phase characteristic and can be realized as a low-price LSI chip. A series circuit of nonlinear resistive elements (P | 2009-08-27 |
20090212829 | LINE DRIVER ARCHITECTURE FOR 10/100/1000 BASE-T ETHERNET - A multimode line driver circuit is provided having improved performance. The multimode line driver comprises at least first and second driver circuits that, when “active,” respectively transmit data using first and second modes. The multimode line driver further comprises a circuit arrangement including a voltage regulator and an associated set of switches. In operation, at least some of the switches are coupled to the second driver circuit and are turned on when the first driver circuit is active. The voltage regulator supplies a direct current to at least some of the turned-on switches in order to decrease a common mode voltage at the second driver circuit while the first driver circuit transmits data using the first mode. As such, components of the second driver circuit can be powered off while the first driver circuit is active, thus reducing power consumption in the first mode. | 2009-08-27 |
20090212830 | BUFFER DEVICE FOR SWITCHED CAPACITANCE CIRCUIT - An integrated buffer device for a switched capacitance circuit having a buffer with an output for an output voltage dependent upon an input voltage that can be supplied by a source to the buffer device; a capacitive switching component that can be switched between a first and second condition and connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; the capacitive switching component provided with a terminal having an associated stray capacitance; a charging and discharging device configured to pre-charge the stray capacitance at a reference voltage before taking up the second condition and to pre-discharge the stray capacitance before taking up the first condition. | 2009-08-27 |
20090212831 | IMAGE FORMING APPARATUS - An image forming apparatus including plural capacitive loads, with one terminal of each of the capacitive loads being connected to a common electrode and with each of the capacitive loads being charged/discharged on the basis of image data, and a first and second drive circuits is provided. The first drive circuit includes plural charge/discharge controllers that are individually connected to other terminals of the capacitive loads and individually control the charging and discharging of the capacitive loads and first and second electrical power wires that are connected to the charge/discharge controllers and charge and discharge the capacitive loads via the charge/discharge controllers. The second drive circuit is connected to each of the first and second electrical power wires and adjusts charge resistance and discharge resistance in response to control of the charge/discharge controllers. | 2009-08-27 |
20090212832 | LOAD CAPACITY DRIVING CIRCUIT - The present invention provides a load capacity driving circuit that is inexpensive and has a high driving capability. When an input signal changes to low potential, gate voltage of an output stage of an amplifying circuit increases, an NMOS transistor MNO turns on, and an NMOS transistor MN | 2009-08-27 |
20090212833 | Frequency divider circuit - Disclosed is a frequency divider including first to fifth FFs(flip-flops), each of which receives a common clock signal and samples and outputs an input signal responsive to an effective edge of the clock, an output signal of the 1st FF being supplied to the 2nd FF, a first logic gate which receives an output signal of the 2nd FF and a first control signal and outputs the output signal of the 2nd FF, when the first control signal is of a first value, and outputs a predetermined value, when the first control signal is of a second value, the output signal of the first logic gate being supplied to an input of the 3rd FF; a second logic gate which receives an output signal of the 1st FF and a second control signal and outputs an output signal of the 1st FF, when the second control signal is of the first value and outputs the predetermined value, when the second control signal is of the second value, the output signal of the second logic gate being supplied to the 4th FF; and a third logic gate which receives an output signal of the 3rd FF and an output signal of the 4th FF and outputs an output signal of a first value, when both inputs thereof are of a second value, the output signal of the third logic gate being supplied to an input of the 5th FF, an output signal of the 5th FF being fed back to an input of the 1st FF. | 2009-08-27 |
20090212834 | SEQUENCING CONTROL CIRCUIT - A sequencing control circuit includes an electronic component configured for controlling a signal output to a motherboard, and input voltages being input to the sequencing control circuit. The input voltages are connected to an input terminal of the electronic component. The electronic component includes a preset threshold and input voltage requirements. The electric component is configured such that only when all of the required input voltages rise to their peak values and the voltage of the input terminal of the electronic component reaches the threshold. The electronic component is triggered, and an output terminal of the electronic component outputs a high level signal to the motherboard. | 2009-08-27 |
20090212835 | DELTA-SIGMA MODULATOR CLOCK DITHERING IN A FRACTIONAL-N PHASE-LOCKED LOOP - The clock signal supplied to the delta-sigma modulator in a fractional-N phase-locked loop is dithered. In one example, the PLL includes a novel programmable clock dithering circuit. The programmable clock dithering circuit is controllable via a serial bus to dither the phase of the clock signal in a selected one of several ways. If the clock signal is dithered in a first way (pseudo-random phase dithering), then the power of digital noise generated by the delta-sigma modulator is spread over a frequency band, thereby reducing the degree to which the noise interferes with other circuitry. If the clock signal is dithered in a second way (rotational phase dithering), then the power of digital noise is frequency shifted such that the degree to which the noise interferes with the other circuitry is reduced. The programmable clock dithering circuit can be controlled in other ways. For example, dithering can be programmably disabled. | 2009-08-27 |
20090212836 | FRAME PULSE SIGNAL LATCH CIRCUIT AND PHASE ADJUSTMENT METHOD - A frame pulse signal latch circuit has: a pulse-width expanding unit which outputs a frame pulse signal FPIN having a pulse width longer than a m-clock cycle; a phase adjustment unit which generates a phase-adjusted output clock CLK′; a flip-flop which latches the frame pulse signal FPIN; a racing detection unit which generates signals, which are shifted by one to m clocks with respect to a frame pulse signal FPOUT, and detects a racing state based on a result of an AND operation of the frame pulse signal FPOUT and the clock-shifted signals; and a control unit which sequentially selects and directs different phase adjustment amounts to the phase adjustment unit, determines an optimal phase adjustment amount based on a worst phase adjustment amount of the case in which the racing state is detected, and gives a direction about the optimal phase adjustment amount to the phase adjustment unit. | 2009-08-27 |
20090212837 | Circuit, apparatus and method of transmitting signal - A circuit includes a first wiring to transmit a first signal, an alteration element to adjust a delay amount being added to the first wiring, and a shield element to shield the alteration element from a second wiring, the second wiring transmitting a second signal. | 2009-08-27 |
20090212838 | Delay Circuit Having Long Delay Time and Semiconductor Device Comprising the Same - A delay circuit has a long delay time and a semiconductor device includes the delay circuit. The delay circuit includes an inverter circuit unit having at least one inverter. Each of the inverters includes a first transistor connected to a supply voltage and a second transistor connected to a ground voltage. The inverter circuit unit receives a first signal and outputs a second signal by delaying the first signal. At least one capacitor unit is connected to an input terminal of the inverter such that a loading capacitance of the inverter circuit unit is increased. | 2009-08-27 |
20090212839 | CIRCUIT FOR SETTLING DC OFFSET IN DIRECT CONVERSION RECEIVER - The present invention discloses a circuit for settling DC offset and controlling RC time-constant in a direct conversion receiver. The circuit includes a variable resistive unit for providing a continuously or non-continuously variable resistance in the direct conversion receiver. The variable resistive unit can provide the variable resistance by utilizing a controllable transistor or a plurality of resistors. Accordingly, the variable resistive unit can be coupled to a capacitor for constituting a high pass filter, which is capable of rapidly settling DC offset in a direct conversion receiver. | 2009-08-27 |
20090212840 | DC CURRENT REDUCTION CIRCUIT - A DC current reduction circuit of the present invention that reduces a DC component in an output current of a current output element in which an AC current and a DC current are superimposed includes a low-pass filter for extracting a current component of a frequency lower than a cutoff frequency from the output current and a reduction unit that reduces the extracted current component from the output current. The low-pass filter has a frequency changing unit that changes the cutoff frequency from higher to lower as a continuous function over time. | 2009-08-27 |
20090212841 | LEVEL SHIFT CIRCUIT AND METHOD FOR THE SAME - The present invention discloses a level shift circuit which comprises: an input driver circuit; a capacitor having a first end electrically connected with the output of the input driver circuit; an output driver circuit electrically connected with a second end of the capacitor; and a feedback latch circuit electrically connected between the output of the output driver circuit and the second end of the capacitor, for maintaining the voltage level at the second end of the capacitor. | 2009-08-27 |
20090212842 | Level Shifter with Memory Interfacing Two Supply Domains - A level-shifter circuit configured to transfer data between two voltage supply domains may eliminate crowbar current while simultaneously providing a valid output signal. The level-shifter circuit may transfer a data signal between the two voltage domains using a latch that is capable of maintaining its output level—based on the destination supply rail—to correspond to the same state to which the level of the input signal—based on the originating supply rail—corresponds, even when the originating supply is decreased to a zero-volt state, or to a voltage equivalent to a low state. During normal operation, when both power supplies are available, the signal at the output of the latch, and hence at the output of the level-shifter circuit may toggle to always track the input signal. Thus, the level of the signal at the output of the level-shifter may always represent the same state (e.g. binary value) as the level of the input signal, during normal operation and also when the originating power supply is powered down. | 2009-08-27 |
20090212843 | SEMICONDUCTOR DEVICE ARRANGEMENT AND METHOD - A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor. | 2009-08-27 |
20090212844 | Information Handling System Port Security - A port securing module includes a power gate that is operable to be coupled in series to a power source and to a load. A resistor is coupled in parallel to the power gate. An operational amplifier includes an inverting input and a non-inverting input that couple the operational amplifier in parallel to each of the power gate and the resistor. The operational amplifier also includes an output that is operable to indicate whether a load is coupled to the power gate and, if a load is coupled to the power gate, supply a voltage to activate the power gate such that power is supplied to the load. | 2009-08-27 |
20090212845 | High Voltage Control Switch - A high voltage control switch including a voltage controller and a control switch is provided. The high voltage control switch splits the control switching of high voltages into two ranges. The voltage controller determines the on and off voltages appropriate for the application based on the range the input signal is in. The control switch then outputs the appropriate voltages determined by the voltage controller based on a logic input. As such, the high voltage control switch provides fast and reliable operation for high voltage switching applications. | 2009-08-27 |
20090212846 | Insulated gate field effect transistors - A field transistor is divided into a number of cells ( | 2009-08-27 |
20090212847 | SYSTEM AND METHOD FOR SENSOR THERMAL DRIFT OFFSET COMPENSATION - A system and method for compensating for thermal drift. A temperature is measured in a meter as a temperature voltage. The temperature voltage is converted to a digital signal. The digital signal is processed to generate an offset voltage in response to the digital signal. The offset voltage is applied as an input to an amplifier. The amplifier receives as a second input a gauge voltage. An output is generated from the meter that corrects the gauge voltage using the offset voltage to compensate for thermal drift. | 2009-08-27 |
20090212848 | Power supply unit for mobile workstation and method - A power supply unit for a mobile computerized device includes a housing having a handle, a battery positioned within the housing, and a detector configured to detect user interaction with the handle. The power supply unit may comprise a removable power supply unit for a mobile computerized device, having a detector generating a signal in response to detecting user interaction with the handle. | 2009-08-27 |
20090212849 | CAPACITIVE MOISTURE INDEPENDENT CRUSH PROTECTION - A protective arrangement for preventing parts of the body from being trapped between at least two mutually relatively moveable parts including at least one strip which is associated with at least one part. There are provided in the strip at least two mutually spaced conductive elements extending in the longitudinal direction of the strip. An electronic sensor system serves to produce an output signal for a capacitance that is adapted to vary as a result of external influences. Due to the fact that at least one first conductive element sends out a signal which is received by at least one second conductive element due to the capacitive effect of the first conductive element and that the second conductive element is at substantially the same electrical potential as the first conductive element and likewise sends out the received signal, there is provided a capacitive crush protection arrangement which does not react to splashes of water or the formation of dew or frost. | 2009-08-27 |
20090212850 | Method and Circuit for Implementing Efuse Resistance Screening - A method and circuit for implementing eFuse resistance screening, and a design structure on which the subject circuit resides are provided. An eFuse is sensed using a first reference resistor. Responsive to the eFuse being sensed as blown with the first reference resistor, the eFuse is sensed using a second reference resistor having a higher resistance than the first reference resistor. Responsive to the eFuse being sensed as unblown with the second reference resistor, the eFuse is recorded as poorly blown. Reliability concerns are identified quickly and accurately without being required to measure the resistance of the eFuse. | 2009-08-27 |
20090212851 | POWER SUPPLY UNIT - High-accuracy overcurrent detection is performed, while a loss resulting from the current detection is significantly reduced. A switch section outputs the voltage between the both terminals of a current detection resistor using an AND signal between an output signal from a hysteresis comparator and an output signal from a pre-driver. The voltage is filtered by an electrostatic capacitor element and a resistor, and inputted to a comparator. The comparator makes a comparison between the signals inputted to the two input terminals thereof, and outputs the result of the comparison to a digital filter. When an overcurrent begins to flow in a power supply unit, the levels of the voltages inputted to the two input terminals of the comparator are inverted so that the comparator outputs an inversion signal to the digital filter. The digital filter outputs a detection signal to an overcurrent detection circuit when an arbitrary time has elapsed. | 2009-08-27 |
20090212852 | POWER SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY - A power supply circuit outputs different set potentials in response to control signals, wherein a voltage detecting circuit changes levels of a first reference potential and a second reference potential in response to inputs of control signals, and a clock generating circuit increases a frequency of the frequency divided clock signal when the levels of the first reference potential and the second reference potential are greatly changed in response to the inputs of the control signals. | 2009-08-27 |
20090212853 | APPARATUS FOR SUPPLYING POWER IN SEMICONDUCTOR INTEGRATED CIRCUIT AND INPUT IMPEDANCE CONTROL METHOD OF THE SAME - An apparatus for supplying power in a semiconductor integrated circuit includes a plurality of power lines, each supplying external power to an interior of the semiconductor integrated circuit, and at least one decoupling capacitor set connected to the plurality of power lines and having a resistance value configured to be variable according to a bias voltage. | 2009-08-27 |
20090212854 | Asymmetric Segmented Channel Transistors - Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. | 2009-08-27 |
20090212855 | FEEDBACK TECHNIQUE AND FILTER AND METHOD - An example filter includes a differential amplifier and a resistor string coupled between output terminals of the differential amplifier. The resistor string may generate a common mode sense voltage and an intermediate voltage at an intermediate node. A feedback resistor is coupled between the intermediate node of the resistor string and an input terminal of the differential amplifier, and a feedback capacitor is coupled between a differential output terminal of the amplifier and the differential input terminal. Applying feedback in this manner may reduce area and power requirements of the filter to achieve selected frequency and gain performance. | 2009-08-27 |
20090212856 | ANALOG AMPLIFIER HAVING DC OFFSET CANCELLATION CIRCUIT AND METHOD OF OFFSET CANCELLATION FOR ANALOG AMPLIFIERS - An amplifier having DC offset compensation includes at least one input node and a pair of differential output nodes, a biasing circuit coupled to the input node; and a plurality of current sources. Selected ones of said current sources are coupled to the input node to adjust a DC voltage at the input node to provide DC offset compensation for the amplifier | 2009-08-27 |
20090212857 | DC Self-Biased Vacuum Tube Differential Amplifier With Grid-to-Cathode Over-Voltage Protection - A single stage differential amplifier is disclosed as comprising a pair of vacuum tube triodes for amplifying two input signals and generating two output signals. The differential amplifier has DC self-biasing ability and grid-to-cathode over-voltage protection for directly coupling from the outputs of another differential amplifier. By possessing these unique features, this differential amplifier becomes an important building block in forming a balanced amplifier by cascading multi differential amplifiers in a directly coupled fashion. | 2009-08-27 |
20090212858 | Integrated Doherty type amplifier arrangement with high power efficiency - The present invention relates to an integrated Doherty type amplifier arrangement and an amplifying method for such an arrangement, wherein a lumped element hybrid power divider ( | 2009-08-27 |
20090212859 | AMPLIFIER CIRCUIT AND METHODS OF OPERATION THEREOF - A signal amplifying circuit and associated methods and apparatuses, the circuit comprising: a signal path extending from an input terminal to an output terminal, a gain controller arranged to control the gain applied along the signal path in response to a control signal; an output stage within the signal path for generating the output signal, the output stage having a gain that is substantially independent of its supply voltage, and a variable voltage power supply comprising a charge pump for providing positive and negative output voltages, the charge pump comprising a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of the states so as to generate positive and negative output voltages together spanning a voltage approximately equal to the input voltage. | 2009-08-27 |
20090212860 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT - An integrated circuit device includes an amplifier circuit that includes first to Nth amplifiers that are cascaded and receives an input signal, an A/D converter that performs an A/D conversion process on a signal amplified by the amplifier circuit, first to Nth D/A converters that are provided corresponding to the first to Nth amplifiers and used to perform an offset adjustment of the first to Nth amplifiers, and a control circuit that sets an offset adjustment of the first to Nth amplifiers using the first to Nth D/A converters and a gain adjustment of the first to Nth amplifiers. | 2009-08-27 |
20090212861 | LOW NOISE AMPLIFIER - A low noise amplifier is provided. The low noise amplifier includes: a low noise amplifying unit amplifying an input signal; a harmonic and noise generating unit disposed in an input terminal of the low noise amplifying unit, for generating a compensating signal for compensating for an intermodulation distortion signal and a thermal noise signal of the input signal to the low noise amplifying unit; and a load unit outputting the amplified input signal generated by the low noise amplifying unit. | 2009-08-27 |
20090212862 | OP-AMP CIRCUIT AND OP-AMP CIRCUIT DRIVING METHOD - The present invention is to provide a CMOS op-amp circuit, an op-amp circuit and an op-amp circuit control method that can increase operating speed when the op-amp circuit stabilizes to a steady state after release of a power down state. During power down, a voltage is applied to a node N | 2009-08-27 |
20090212863 | POWER AMPLIFIER - In the power amplifier of the invention, at a start of power amplification by an amplifier transistor | 2009-08-27 |
20090212864 | PREAMPLIFIER FOR RECEIVER AND METHOD THEREOF - A preamplifier used in a receiver is provided. The preamplifier comprises an input circuit and an output circuit. The input circuit receives an input differential voltage pair, pulls it down when the common voltage of the input differential voltage pair is higher than a reference voltage. The output circuit receives the input differential voltage pair outputted from the input circuit to pull high or low an output voltage accordingly. | 2009-08-27 |
20090212865 | Differential Audio Amplifier - A differential audio amplification apparatus with common mode rejection is shown, having a first input current path ( | 2009-08-27 |
20090212866 | CLASS AB AMPLIFIER - An amplifier is disclosed. An input transistor receives an input voltage. An impedance unit is coupled to a first electrode of the input transistor. A current source is coupled to a second electrode of the input transistor. A push-pull output circuit comprises a PMOS transistor and a NMOS transistor electrically connected in series to output an output voltage. The first electrode of the input transistor is coupled to a control terminal of the NMOS transistor. A level shifting unit is coupled between the first electrode of the input transistor and the push-pull output circuit, for shifting a voltage of the first electrode of the input transistor and providing a shifted voltage corresponding to the voltage of the first electrode of the input transistor to the control terminal of the PMOS transistor. | 2009-08-27 |
20090212867 | INTEGRATED CIRCUIT DEVICE AND ELECTRONIC INSTRUMENT - An integrated circuit device includes an amplifier circuit that receives an input signal and performs an offset adjustment corresponding to a DC offset of the input signal and a gain adjustment corresponding to an amplitude of the input signal, a filter that is provided in a subsequent stage of the amplifier circuit, a cut-off frequency of the filter being variably set corresponding to a frequency band of the input signal, an A/D converter that is provided in a subsequent stage of the filter and performs an A/D conversion process on a signal amplified by the amplifier circuit, and a control circuit that sets an offset adjustment of the amplifier circuit, a gain adjustment of the amplifier circuit, and the cut-off frequency of the filter. | 2009-08-27 |
20090212868 | LOW POWER COMSUMPTION, LOW NOISE AND HIGH POWER GAIN DISTRIBUTED AMPLIFERS FOR COMMUNICATION SYSTEMS - Provided is a distributed amplifier in communication systems, including: an input transmission line; an output transmission line; an input impedance match and an output impedance match, for providing termination of the input transmission line and the output transmission line, respectively and for preventing signal reflection in the input transmission line and the output transmission line, respectively; multi-stage Gm cells with common mode feedback, the input transmission line being coupled to the output transmission line by the transconductance of the Gm cells; and an input gate bias circuit, for providing bias for the multi-stage Gm cells. In at least one of the Gm cells, one inverter performs V/I conversion while other inverters provide negative resistance to control common mode of output voltage and to enhance DC gain of the Gm cell. Due to common mode feedback, no output gate bias is needed. | 2009-08-27 |
20090212869 | DISTRIBUTED AMPLIFIER WITH NEGATIVE FEEDBACK - A distributed amplifier may include an input transmission line for receiving on an input end an input signal, and an output transmission line for outputting on an output end an output signal. A plurality of amplifier stages may be coupled between intermediate positions on the input and output lines. Feedback impedance may negatively feed back a signal on the output end of the output line to a second end of the input line spaced from the first end of the input line. | 2009-08-27 |
20090212870 | CASCODE-CASCADE POWER AMPLIFIER ASSEMBLY - A cascode-cascade power amplifier assembly is provided. Which includes a first common-source amplifier, a second common-source amplifier, a phase shift matching network coupled to the first common-source amplifier and the second common-source amplifier for providing a 90-degree phase shift and allowing less than 50% of the output power of the first common-source amplifier to be transmitted to the second common-source amplifier, a common-gate amplifier which forms a series circuit arrangement with the first-common source amplifier and a parallel circuit arrangement with the second common-source amplifier, and an equivalent quarter-wave or three-quarter wave circuit which forms a series circuit arrangement with the common-gate amplifier and a parallel circuit arrangement with the second common-source amplifier. According to the present invention, the first common-source amplifier and the common-gate amplifier form a cascode main amplifier, while the first common-source amplifier and the second common-source amplifier form a cascade auxiliary amplifier. | 2009-08-27 |
20090212871 | MULTI-PLANAR SOLID STATE AMPLIFIER - A solid state power amplifier (SSPA) system may include a radio frequency (RF) input, an RF waveguide split block, multiple monolithic microwave integrated circuit (MMIC) power amplifier modules, and/or a heat spreader. The power amplifier modules and RF waveguide may be distributed about the heat spreader in different planes. Furthermore, the power amplifier modules may be located on opposite sides of the heat spreader and nonplanar to the waveguide split block. A method for dissipating heat within an SSPA may include receiving an RF signal in a first plane, amplifying the RF signal in another plane, and combining the RF signal in yet another plane. | 2009-08-27 |
20090212872 | Wideband Active Balun Using Darlington Pair - An active balun with Darlington pairs obtains a wideband operation. With differential output signals, a size of the active balun is minimized. The present invention can be applied to a transceiver. With a wideband amplitude match and 180° out of phase, the performance of the transceiver is improved by the present invention for a few wide applications. | 2009-08-27 |
20090212873 | Semiconductor device - Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits. | 2009-08-27 |
20090212874 | OSCILLATOR DEVICE - An oscillator device having an oscillation system including an oscillator and a resilient supporting member, a driving member configured to supply a driving force to the oscillation system based on a driving signal, a detecting member configured to detect at least an oscillation amplitude of the oscillator, a driving amplitude control unit configured to control at least a driving amplitude of the driving signal, and a driving frequency control unit configured to control a driving frequency of the driving signal to be supplied to the driving member, wherein, in a state in which the driving amplitude control unit controls the driving amplitude of a driving signal so that the oscillation amplitude to be detected becomes equal to a target value, and on the basis of information including driving frequencies in different driving states being driven with driving signals of these driving frequencies as well as the controlled driving amplitude, the driving frequency control unit acquires, as a resonance frequency of the oscillation system, a driving frequency with which the driving amplitude of the driving signal becomes minimal. | 2009-08-27 |
20090212875 | Oscillator based on thermal diffusion - An oscillator device for generating an oscillator signal, includes a heater arrangement, a first switching element, a temperature sensor, signal process means, and voltage controlled oscillator; an output of the temperature sensor being connected to an input of the signal processing means, and an output of the signal processing means being connected to an input of the voltage controlled oscillator. The first switching element is arranged for receiving the oscillator signal from the voltage controlled oscillator and for providing a heater drive signal to either a first heater element or a second heater element of the heater arrangement based on the oscillator signal. The signal processing means comprise a synchronous demodulator. | 2009-08-27 |
20090212876 | OSCILLATOR CONTROLLING APPARATUS - An oscillation controlling apparatus has a digitally-controlled oscillator configured to output an oscillating signal with an oscillation frequency according to an oscillator adjustment signal, and include a variable current source which supplies operation current based on an operation current control signal, a phase difference calculating unit configured to calculate a phase difference between the oscillating signal and a reference signal to output a phase difference signal, a filter configured to smooth a difference between a phase instruction signal setting the oscillation frequency of the digitally-controlled oscillator and the phase difference signal to output the oscillator adjustment signal, and a controlling unit configured to obtain the oscillator adjustment signal, output the operation current control signal so as to vary a value of the operation current, extract the value of the operation current at which the oscillator adjustment signal becomes the maximum value, and output the operation current control signal so that the operation current supplied by the variable current source becomes the extracted value. | 2009-08-27 |
20090212877 | MEMS OSCILLATOR - Provided is a MEMS oscillation circuit which performs temperature compensation of a MEMS resonator with a simple circuit, which is mild so that an output clock does not have jitter, and which makes the range of fluctuations of a reference frequency from a reference value equivalent to a range of digital processing. The MEMS oscillator includes a MEMS resonator, a temperature measurement unit for measuring a temperature and outputting a detected voltage corresponding to the temperature, and a bias voltage control circuit for applying the MEMS resonator with a bias voltage which changes the resonant frequency of the MEMS resonator in a manner opposite to a change of the resonant frequency of the MEMS resonator due to temperature change correspondingly to the detected voltage. | 2009-08-27 |
20090212878 | Oven-controlled crystal oscillator - An oven-controlled crystal oscillator includes a circuit board, a crystal unit surface-mounted on the circuit board, and a temperature control circuit that maintains operating temperature of the crystal unit constant. The temperature control circuit includes a heating resistor, a power transistor that supplies power to a heating resistor, and a temperature sensitive resistor that detects temperature of the crystal unit. The heating resistor is formed, as a film resistor, on a surface of the circuit board in an area thereof in which the crystal unit is located. The temperature sensitive resistor is provided on the circuit board as a film resistor. | 2009-08-27 |
20090212879 | METHOD AND SYSTEM FOR A BALUN EMBEDDED IN AN INTEGRATED CIRCUIT PACKAGE - Methods and systems for a balun embedded in an integrated circuit package are disclosed and may include a multi-layer package bonded to an integrated circuit. The multi-layer package may include an integrated balun which may be enabled to process RF signals received from and/or communicated to an antenna. The integrated circuit may be flip-chip bonded to the multi-layer package. The balun may include ferromagnetic layers integrated in the multi-layer package, and may be bypassed via bypass switches integrated in the multi-layer package. The switches integrated in the multi-layer package may include MEMS switches. The balun may be bypassed via bypass switches in the integrated circuit. The switches in the integrated circuit may include CMOS switches. The balun may be impedance matched to the integrated circuit via surface mount devices, which may be coupled to the multi-layer package. | 2009-08-27 |
20090212880 | Electrical Circuit Comprising a Differential Signal Path and Component with Such a Circuit - The invention relates to an electrical circuit that includes a first signal path having differential partial paths. An interface circuit arranged in the first signal path suppresses the common-mode signals in a blocking region of the signal path, but essentially does not influence differential signal parts. | 2009-08-27 |
20090212881 | COAXIAL-TO-MICROSTRIP TRANSITIONS AND MANUFACTURING METHODS - Coaxial-to-microstrip transitions may include a microstrip line and coaxial-line assembly. The microstrip line includes a first dielectric having an aperture, a conductive strip disposed on one primary face of the first dielectric, and a ground plane disposed on the opposite primary face of the first dielectric. The coaxial-line assembly includes an outer conductor and an inner conductor. In some examples, the ground plane extends between the outer conductor and the inner conductor on a first side of the coaxial-line assembly proximate the conductive strip and an aperture cross section extends beyond the outer conductor on a second side of the coaxial-line assembly distal the conductive strip. In some examples, the ground plane has a non-circular aperture. In some examples, the outer conductor encloses an area that is less than an area of the aperture. In some examples, the enclosed area has a width that is less than a corresponding width of the first aperture. | 2009-08-27 |
20090212882 | TRANSMIT/RECEIVE UNIT, AND METHODS AND APPARATUS FOR TRANSMITTING SIGNALS BETWEEN TRANSMIT/RECEIVE UNITS - In one embodiment, apparatus for transmitting and receiving data includes a transmission line network having at least three input/output terminals; at least three transmit/receive units, respectively coupled to the at least three input/output terminals; and a control system. The control system is configured to, depending on a desired direction of data flow over the transmission line network, i) dynamically place each of the transmit/receive units in a transmit mode or a receive mode, and ii) dynamically enable and disable an active termination of each transmit/receive unit. Methods for using this and other related apparatus to transmit and receive data over a transmission line network are also disclosed. | 2009-08-27 |
20090212883 | FEEDTHROUGH FILTER AND ELECTRICAL MULTI-LAYER COMPONENT - A feedthrough filter includes a base plate having a first contact surface and a second contact surface. The first contact surface and the second contact surface are galvanically connected. The first contact surface is on an upper side of the base plate and the second contact surface is on an underside of the base plate. The base plate has an opening. An electrical feedthrough passes through the opening, is soldered to the second contact surface, and is not soldered to the first contact surface. A least one electrical component includes an external contact that is soldered to first contact surface. | 2009-08-27 |
20090212884 | NANOTUBE DEVICE - A device comprising a nanotube configured as a resonator, a source electrode, a gate electrode, a drain electrode and at least one impeding element, wherein the at least one impeding element is configured to minimize energy loss due to a contact resistance between at least the source electrode and the nanotube. | 2009-08-27 |
20090212885 | RESONATOR AND BANDPASS FILTER HAVING OVERLAY ELECTROMAGNETIC BANDGAP (EBG) STRUCTURE, AND METHOD OF MANUFACTURING THE RESONATOR - Provided is an Electromagnetic Bandgap (EBG) structure, particularly, a resonator and a bandpass filter having an overlay EBG structure, and a method of manufacturing the resonator. The resonator is manufactured by forming a transmission line and ground plates on a substrate, arranging a plurality of reflector units at regular intervals along the longitudinal direction of the transmission line, and removing at least one reflector among the plurality of reflectors, thus forming a common resonating mode. Therefore, since reflector units constructing capacitance components are separated from a substrate, it is possible to prevent electromagnetic waves from leaking out of the substrate and ensure a high Q characteristic in a high frequency environment due to a resonating unit formed between the reflector units. | 2009-08-27 |
20090212886 | DUAL-BAND BANDPASS RESONATOR AND DUAL-BAND BANDPASS FILTER - A dual-band bandpass filter according to the present invention includes a plurality of dual-band bandpass resonators. The dual-band bandpass resonator includes a central conductor having a central axis aligned with an input/output direction, a pair of grounding conductors, a central conductor short-circuit part and a pair of stub conductors that are formed on a surface of a dielectric substrate. The pair of grounding conductors are disposed on the opposite sides of the central conductor with a space interposed therebetween. The central conductor short-circuit part short-circuits the pair of grounding conductors, and one end of the central conductor is connected to the central conductor short-circuit part. The pair of stub conductors are disposed in the spaces on the opposite sides of the central conductor symmetrically with respect to the central axis of the central conductor, extend at least partially parallel with the central conductor and are connected to the central conductor short-circuit part at one ends thereof. | 2009-08-27 |