35th week of 2009 patent applcation highlights part 14 |
Patent application number | Title | Published |
20090212287 | THIN FILM TRANSISTOR AND METHOD FOR FORMING THE SAME - A thin film transistor (TFT) and the method of forming the same is provided. The method of forming the TFT on a surface of a substrate, includes the steps of: forming a gate electrode; deposing a gate dielectric on the gate electrode; forming a nanocrystalline silicon (nc-Si) layer and an amorphous silicon (a-Si:H) layer above the gate dielectric, so that the thickness of the nc-Si layer is less than 30 nm thereby reducing off-current; and forming a source/drain electrode. The TFT includes: a gate electrode on a substrate, a gate dielectric on the gate electrode; a nc-Si layer having a thickness less than 30 nm, thereby reducing off-current; an a-Si:H layer; and a source/drain electrode. | 2009-08-27 |
20090212288 | THIN FILM TRANSISTOR, DISPLAY DEVICE INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE DISPLAY DEVICE - A display device including the thin film transistor, and a method of manufacturing the display device are provided. The thin film transistor comprising a first gate electrode, a second gate electrode formed on the first gate electrode, a first semiconductor formed on the first gate electrode and including a polycrystalline semiconductor, a second semiconductor formed on the second gate electrode and including an amorphous semiconductor. | 2009-08-27 |
20090212289 | THIN FILM TRANSISTOR AND METHOD FOR FABRICATING SAME - A method for forming a thin film transistor on a substrate is disclosed. A gate electrode and a gate insulation layer are disposed on a surface of the substrate. A deposition process is performed by utilizing hydrogen diluted silane to form a silicon-contained thin film on the gate insulation layer first. A hydrogen plasma etching process is thereafter performed. The deposition process and the etching process are repeated for at least one time to form an interface layer. Finally, an amorphous silicon layer, n+ doped Si layers, a source electrode, and a drain electrode are formed on the interface layer. | 2009-08-27 |
20090212290 | DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A display panel includes; a lower gate line, a lower data line disposed substantially perpendicular to the lower gate line, a thin film transistor (“TFT”) connected to the lower gate line and the lower data line, an insulating layer disposed on the lower gate line, the lower data line, and the TFT and having a plurality of trenches exposing the lower gate line and the lower data line, an upper gate line disposed in the trench on the lower gate line, an upper data line disposed in the trench on the lower data line, and a pixel electrode connected to the TFT. | 2009-08-27 |
20090212291 | Transparent Thin Film Transistor and Image Display Unit - An embodiment of the present invention is an transparent thin film transistor which has an substantially transparent substrate, a gate line made of a thin film of a substantially transparent conductive material, a substantially transparent gate insulating film, a substantially transparent semiconductor active layer, a source line made of a thin film of a metal material and a drain electrode made of a thin film of a substantially transparent conductive material. In addition, the source line and the drain electrode are formed apart from each other and sandwich the substantially transparent semiconductor active layer. Moreover, at least any one of the thin film of the gate line and the thin film of the source line is stacked with a thin film of a metal material. | 2009-08-27 |
20090212292 | Layer-selective laser ablation patterning - A method of fabricating an organic electronic device is provided. The organic electronic device has a structure including an upper conductive layer and an underlying layer immediately beneath said upper conducting layer and having at least one solution process able semiconducting layer. The upper conducting layer preferably has a thickness of between 10 nm and 200 nm. The method includes patterning said upper conductive layer of said structure by: laser ablating said upper conductive layer using a pulsed laser to remove regions of upper conductive layer from said underlying layer for said patterning; and wherein said laser ablating uses a single pulse of said laser to substantially completely remove a said region of said upper conductive layer to expose said underlying layer beneath | 2009-08-27 |
20090212293 | Semiconductor device and method for fabricating the same - A semiconductor device, comprising a substrate, a semiconductive layer and a gate electrode is provided. The semiconductive layer having a crystallization promoting material is formed over the substrate. The semiconductive layer has a channel region, a first doped region and a second doped region. The first doped region has a donor and an acceptor, and the second doped region has a dopant which is selected from one of the donor and the acceptor. The second doped region is disposed between the first doped region and the channel region. The gate electrode is insulated from the channel region. | 2009-08-27 |
20090212294 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. | 2009-08-27 |
20090212295 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and method of fabricating the same, which forms a contact hole, a via hole or a via contact hole with multiple profiles with various taper angles. The semiconductor device includes a substrate, a thin film transistor formed on the substrate and having a semiconductor layer, a gate insulating layer, a gate electrode, and an interlayer dielectric, and a contact hole penetrating the gate insulating layer and the interlayer dielectric and exposing a portion of the semiconductor layer. The contact hole has a multiple profile in which an upper portion of the contact hole has a wet etch profile and a lower portion of the contact hole has at least one of the wet etch profile and a dry etch profile. | 2009-08-27 |
20090212296 | METHOD FOR MANUFACTURING DISPLAY DEVICE - A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, a second conductive film, and a first resist mask are formed; first etching is performed to expose at least a surface of the first conductive film; second etching accompanied by side etching is performed on part of the first conductive film to form a gate electrode layer; a second resist mask is formed; third etching is performed to form a source and drain electrode layers, a source and drain regions, and a semiconductor layer; a second insulating film is formed; an opening portion is formed in the second insulating film to partially expose the source or drain electrode layer; a pixel electrode is selectively formed in the opening portion and over the second insulating film; and a supporting portion formed using the gate electrode layer is formed in a region overlapping with the opening portion. | 2009-08-27 |
20090212297 | LAMINATING SYSTEM - It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used. | 2009-08-27 |
20090212298 | Thin Film Transistor Substrate Having Nickel-Silicide Layer - Disclosed are a thin film transistor substrate of an LCD device and a method of manufacturing the same. The thin film transistor substrate includes a nickel-silicide layer formed on an insulating layer pattern including silicon and a metal layer formed on the nickel-silicide layer. Nickel is coated on the insulating layer pattern including silicon and a metal material is coated on the nickel-coated layer. After that, a heat treatment is performed at about 200 to about 350° C. to obtain the nickel-silicide layer. Since the thin film transistor substrate of the LCD device is manufactured by applying the nickel-silicide wiring, a device having low resistivity and good ohmic contact property can be obtained. | 2009-08-27 |
20090212299 | DISPLAY ELEMENT - A thin film transistor layer including a thin film transistor is formed at a liquid crystal layer side of a color filter layer on an array substrate. Since it becomes possible to form the color filter layer at a position on a relatively flat glass substrate, satisfactory characteristics of the color filter layer can be obtained. The color filter layer is unlikely to have influence on the thin film transistor layer, so that the yield can be improved. | 2009-08-27 |
20090212300 | LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - An objective is simplification of a manufacturing method of a liquid crystal display device or the like. In a manufacturing method of a thin film transistor, a stack in which a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order is formed, and the first conductive film is exposed by first etching and a pattern of the second conductive film is formed by second etching. Further, after thin film transistors are formed, a color filter layer is formed so that unevenness caused by the thin film transistors or the like is relieved; thus, the level difference of the surface where the pixel electrode layer is formed is reduced. Alternatively, a color filter layer is selectively formed utilizing the unevenness caused by thin film transistors or the like. | 2009-08-27 |
20090212301 | Double Guard Ring Edge Termination for Silicon Carbide Devices and Methods of Fabricating Silicon Carbide Devices Incorporating Same - Edge termination structures for semiconductor devices are provided including a plurality of spaced apart concentric floating guard rings in a semiconductor layer that at least partially surround a semiconductor junction. The spaced apart concentric floating guard rings have a highly doped portion and a lightly doped portion. Related methods of fabricating devices are also provided herein. | 2009-08-27 |
20090212302 | Substrate of liquid crystal device and method for manufacturing the same - A method for manufacturing a substrate of a liquid crystal display device is disclosed. The method includes forming a conductive line structure with low resistance to improve the difficulty of the resistance matching. The method can effectively reduce the resistance of the conductive line of the LCD panel to increase the transmission rate of the driving signal. Hence, the increasing yield of products can reduce the cost of manufacturing, and can meet the requirement of the large-size and high-definition thin film transistor liquid crystal display device. | 2009-08-27 |
20090212303 | Light-emitting diode matrix and method for producing a light-emitting diode matrix - A light-emitting diode matrix comprises a substrate, first and second electrodes electrically insulated from each other formed in or on the substrate, and a first organic layer on the first electrode and a second organic layer on the second electrode. The first organic layer is separated from the second organic layer by separator means. Further, the light-emitting diode matrix comprises a cap electrode with an area disposed on the first organic layer and an area disposed on the second organic layer. The areas of the cap electrode are connected in an electrically conductive way via an area of the cap electrode disposed on the separator means. | 2009-08-27 |
20090212304 | Led chip package structure with multifunctional integrated chips and a method for making the same - An LED chip package structure with multifunctional integrated chips includes a substrate unit, a light-emitting unit, a chip unit, and a package colloid unit. The light-emitting unit has a plurality of LED chips electrically arranged on the substrate unit. The chip unit is electrically arranged on the substrate unit, and the chip unit is arranged between the light-emitting unit and a power source. The package colloid unit covers the LED chips. The package colloid unit is a strip fluorescent colloid corresponding to the LED chips. | 2009-08-27 |
20090212305 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device can vary color temperatures of its emission light and have a simple and small configuration. The semiconductor light emitting device can include a substrate, electrode wiring formed on the substrate, a plurality of semiconductor light emitting elements mounted on the electrode wiring, and a wavelength conversion layer surrounding the semiconductor light emitting elements. The semiconductor light emitting elements constitute a first semiconductor light emitting element group and a second semiconductor light emitting element group. The wavelength conversion layer has a thinner portion corresponding to the first group and a thicker portion corresponding to the second group and can be differentiated by a step provided on the substrate. | 2009-08-27 |
20090212306 | DEVICE FOR AN OPTOELECTRONIC COMPONENT AND MODULE WITH AN OPTOELECTRONIC COMPONENT AND A DEVICE - An apparatus having at least one fixing element is specified, the fixing dement being provided for fixing the apparatus to a housing body of an optoelectronic device and the apparatus being designed as a mount for a separate optical element. | 2009-08-27 |
20090212307 | Light-emitting diode chip comprising a contact structure - In a luminescence diode chip having a radiation exit area ( | 2009-08-27 |
20090212308 | METHOD FOR PRODUCING AN LED CHIP AND LED CHIP - A method is disclosed in which a base body is prepared that comprises a layer sequence intended for the LED chip and suitable for emitting electromagnetic radiation. A cap layer is applied to at least one main surface of the base body. A cavity is introduced into the cap layer and is completely or partially filled with a luminescence conversion material. The luminescence conversion material comprises at least one phosphor. A method is also disclosed in which the cap layer comprises photostructurable material and at least one phosphor, such that it is able to function as a luminescence conversion material and can be photostructured directly. LED chips that are producible by means of the method are also described. | 2009-08-27 |
20090212309 | Light emitting diode package structure and a packaging method thereof - An LED package structure and an LED packaging method are disclosed. The LED package structure includes a substrate, an LED unit and a transparent holding wall. The LED unit is electrically connected and located on the surface of the substrate. The transparent holding wall that corresponds to the LED unit is formed on the surface of the substrate, and has a receiving space. The LED unit is received in the receiving space. By utilizing the transparent holding wall, the colloid is controllably received in the receiving space and uniformly spread on the surface of the LED unit and around the LED unit. Thereby, the quantity of the colloid is easily controlled, and the LED package structure has a wide lighting angle due to the light emitted from the LED unit can pass through the transparent holding wall. | 2009-08-27 |
20090212310 | SOFT LITHOGRAPHIC MOLDING OF SURFACE RELIEF OUTPUT COUPLERS FOR ORGANIC LIGHT EMITTING DIODES - The present invention provides a method and apparatus for surface relief output coupling in organic light emitting diodes is provided. The method includes forming a pattern in a surface of an elastomer ( | 2009-08-27 |
20090212311 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - The invention discloses a semiconductor light-emitting device, which includes a substrate, a first conductive type semiconductor material layer, a second conductive type semiconductor material layer, a light-emitting layer, a first electrode, a second electrode, and a plurality of bump structures. The first conductive type semiconductor material layer is formed on the substrate and has an upper surface which includes a first region and a second region distinct from the first region. The first electrode is formed on the first region. The light-emitting layer and the second conductive type semiconductor material layer are formed on the second region. The bump structures are formed on the upper surface of the first conductive type semiconductor material layer and between the first region and the second region. Each bump structure is made of ITO, SiO2, SiN, ZnO, polymide, BCB, SOG, InO, or SnO. | 2009-08-27 |
20090212312 | SEMICONDUCTOR LIGHT-EMITTING DEVICE - The invention discloses a semiconductor light-emitting device, which includes a substrate, a first conductive type semiconductor material layer, a second conductive type semiconductor material layer, a light-emitting layer, a first electrode, a second electrode, and a plurality of bump structures. The first conductive type semiconductor material layer is formed on the substrate and has an upper surface which includes a first region and a second region distinct from the first region. The first electrode is formed on the first region. The light-emitting layer and the second conductive type semiconductor material layer are formed on the second region. The bump structures are formed on the upper surface of the first conductive type semiconductor material layer and between the first region and the second region. Each bump structure is made of ITO, SiO2, SiN, ZnO, polymide, BCB, SOG, InO, or SnO. | 2009-08-27 |
20090212313 | LED Module with Application-Specific Color Setting - An LED module with a blue LED chip, over which is arranged a conversion layer, which has a luminous material mixture mixing a further proportion of greater wavelength into the blue light, so that a reddish or greenish or yellowish white light is emitted from the LED module, the emitted light of the LED module having a peak or secondary peak in the red or green or yellow range. | 2009-08-27 |
20090212314 | YELLOW EMITTING PHOSPHORS BASED ON Ce3+-DOPED ALUMINATE AND VIA SOLID SOLUTION FOR SOLID-STATE LIGHTING APPLICATIONS | 2009-08-27 |
20090212315 | SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor light emitting device is provided so that an optical axis thereof is properly set parallel with the mounting board when the device is mounted on the mounting board. The semiconductor light emitting device can have a structure in that light can be incident on the light guide plate with high efficiency and uniform introduction into the light guide plate. A multi-piece substrate can include electrodes, a plurality of semiconductor light emitting elements, and a sealing resin for sealing them simultaneously. The thus obtained integrated substrate is cut into individual semiconductor light emitting device bodies. On one of the cut end faces, which serves as a surface to be mounted onto a mounting board, a light-shielding reflective film can be coated over an area from the edge of the light emission surface of the sealing resin to at least part of the substrate. On the other cut end face, the sealing resin can be covered with a light-shielding reflective film. | 2009-08-27 |
20090212316 | Surface-mounted optoelectronic semiconductor component and method for the production thereof - A surface-mounted component, comprising an optoelectronic semiconductor chip, a molded body integrally molded onto the semiconductor chip, a mounting area formed at least in places by a surface of the molded body, at least one connection location and side areas of the component which are produced by means of singulation. | 2009-08-27 |
20090212317 | CIRCUIT BOARD FOR DIRECT FLIP CHIP ATTACHMENT - A packaging method comprises: forming a circuit board by forming a substantially continuous conductive layer on an insulating board and removing selected portions of the continuous conductive layer to define an electrically conductive trace; laser cutting the electrically conductive trace to define sub-traces electrically isolated from each other by a laser-cut gap formed by the laser cutting; and bonding a light emitting diode (LED) chip to the circuit board across or adjacent to the laser-cut gap, the bonding including operatively electrically connecting an electrode of the LED chip to one of the sub-traces without using an interposed submount. A semiconductor package comprises an LED chip flip-chip bonded to sub-traces of an electrically conductive trace of a circuit board, the sub-traces being electrically isolated from each other by a narrow gap of less than or about 100 microns. | 2009-08-27 |
20090212318 | NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A nitride-based semiconductor light-emitting device and a manufacturing method thereof are provided. The nitride-based light-emitting device includes a first conductivity type nitride-based semiconductor layer, a light-emitting layer and a second conductivity type nitride-based semiconductor layer, that are successively layered above a translucent base. A first conductivity type electrode layer is electrically connected to the first conductivity type nitride-based semiconductor layer, and a second conductivity type electrode layer is electrically connected to the second conductivity type nitride-based semiconductor layer. | 2009-08-27 |
20090212319 | GALLIUM NITRIDE-BASED COMPOUND SEMICONDUCTOR LIGHT EMITTING DEVICE - An object of the present invention is to provide a gallium nitride-based compound semiconductor light emitting device having excellent light extraction efficiency and a high emission output in which a planar shape is a rectangular shape with vertical and longitudinal sides each having a different length. | 2009-08-27 |
20090212320 | Semiconductor devices and semiconductor apparatuses including the same - Semiconductor devices and semiconductor apparatuses including the same are provided. The semiconductor devices include a body region disposed on a semiconductor substrate, gate patterns disposed on the semiconductor substrate and on opposing sides of the body region, and first and second impurity doped regions disposed on an upper surface of the body region. The gate patterns may be separated from the first and second impurity doped regions by, or greater than, a desired distance, such that the gate patterns do not to overlap the first and second impurity doped regions in a direction perpendicular to the first and second impurity doped regions. | 2009-08-27 |
20090212321 | Trench IGBT with trench gates underneath contact areas of protection diodes - A trench PT IGBT (or NPT IGBT) having clamp diodes for ESD protection and prevention of shortage among gate, emitter and collector. The clamp diodes comprise multiple back-to-back Zener Diode composed of doped regions in a polysilicon layer doped with dopant ions of a first conductivity type next to a second conductivity type disposed on an insulation layer above said semiconductor power device. Trench gates are formed underneath the contact areas of the clamp diodes as the buffer layer for prevention of shortage. | 2009-08-27 |
20090212322 | Vertical Semiconductor Device - A vertical semiconductor device includes a semiconductor body, and first and second contacts on opposite sides of the semiconductor body. A plurality of regions are formed in the semiconductor body including, in a direction from the first contact to the second contact, a first region of a first conductivity type, a second region of a second conductivity type; and a third region of the first conductivity type. The third region is electrically connected to the second contact. A semiconductor zone of the second conductivity type and increased doping density is arranged in the second region. The semiconductor zone separates a first part of the second region from a second part of the second region. The semiconductor zone has a maximum doping density exceeding about 10 | 2009-08-27 |
20090212323 | SILICON-CONTROLLED RECTIFIER (SCR) DEVICE FOR HIGH-VOLTAGE ELECTROSTATIC DISCHARGE (ESD) APPLICATIONS - A silicon-controlled rectifier (SCR) device having a high holding voltage includes a PNP transistor and an NPN transistor, each transistor having both p-type and n-type dopant regions in their respective emitter areas. The device is particularly suited to high voltage applications, as the high holding voltage provides a device which is more resistant to latchup subsequent to an electrostatic discharge event compared to devices having a low holding voltage. | 2009-08-27 |
20090212324 | HETEROJUNCTION FIELD EFFECT TRANSISTOR - An aspect of the invention provides a heterojunction field effect transistor that comprises: a base; a first GaN channel layer formed on the base; an AlN electron supply layer formed on the first GaN layer, and a second GaN cap layer formed on the AlN layer. | 2009-08-27 |
20090212325 | Hetero Field Effect Transistor and Manufacturing Method Thereof - A hetero field effect transistor includes: a main semiconductor region including a first semiconductor layer and a second semiconductor layer formed thereon to allow a generation of a two-dimensional carrier gas layer of a first conductive type on a heterojunction interface therebetween; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third semiconductor layer of a second conductive type different from the first conductive type, the third semiconductor layer being formed on the second semiconductor layer and located between the source electrode and the drain electrode; and a gate electrode formed on the third semiconductor layer. A concave portion is formed in an upper surface of the second semiconductor layer at a region immediately below the gate electrode. | 2009-08-27 |
20090212326 | Hetero Field Effect Transistor and Manufacturing Method Thereof - A hetero field effect transistor includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer to allow a generation of a two dimensional carrier gas layer of a first conductive type on a heterojunction interface between the first semiconductor layer and the second semiconductor layer; a third semiconductor layer formed on the second semiconductor layer and having an impurity introduced therein; a source electrode formed on the third semiconductor layer; a drain electrode formed on the third semiconductor layer and separated from the source electrode; a fourth semiconductor layer formed on or above the second semiconductor layer and has a second conductive type which is different from the first conductive type; and a gate electrode electrically connected on the fourth semiconductor layer. The fourth semiconductor layer is located adjacent to and surrounded by the third semiconductor layer. | 2009-08-27 |
20090212327 | STANDARD CELL LIBRARIES AND INTEGRATED CIRCUIT INCLUDING STANDARD CELLS - A standard cell library includes a first power rail, a second power rail, a third power rail, a first standard cell, and second standard cells. The first power rail extends in a first direction. The second power rail extends in the first direction, and is spaced apart from the first power rail by a predetermined spacing in a second direction perpendicular to the first direction. The third power rail extends in the first direction between the first power rail and the second power rail. The first standard cell has at least one cell having a first cell height, and is arranged between the first power rail and the second power rail. The second standard cells have at least two cells, each having a second cell height, that are in contact with each other in the second direction, and are in contact with the first standard cell in the first direction. | 2009-08-27 |
20090212328 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device is provided. The semiconductor device includes a first gate line, a second gate line, a first contact electrode, first dummy gates, a second gate pad, and a second contact electrode. The first gate line is formed on a semiconductor substrate and the second gate line of a spacer shape is formed on the sidewalls of the first gate line with a thin insulating layer interposed therebetween. The first contact electrode is vertically connected with the first gate line. The first dummy gates are formed in array spaced a predetermined interval from the first gate line on the semiconductor substrate. The second gate pad of a spacer shape is formed on the sidewalls of the first dummy gates with a thin insulating layer interposed therebetween. The second gate pad is connected to the second gate line and is also gap-filled between the first dummy gates. The second contact electrode is vertically connected with the second gate pad. | 2009-08-27 |
20090212329 | SUPER HYBRID SOI CMOS DEVICES - The present invention provides semiconductor structures comprised of stressed channels on hybrid oriented. In particular, the semiconductor structures include a first active area having a first stressed semiconductor surface layer of a first crystallographic orientation located on a surface of a buried insulating material and a second active area having a second stressed semiconductor surface layer of a second crystallographic orientation located on a surface of a dielectric material. A trench isolation region is located between the first and second active area, and the trench isolation region is partially filled with a trench dielectric material and the dielectric material that is present underneath said second stressed semiconductor surface layer. The dielectric material within the trench isolation region has lower stress compared to that is used in conventional STI process and it is laterally abuts at least the second stressed semiconductor surface layer and extends to an upper surface of the trench isolation region. | 2009-08-27 |
20090212330 | METHOD OF FABRICATING A BURIED-GATE SEMICONDUCTOR DEVICE AND CORRESPONDING INTEGRATED CIRCUIT - A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled with silicon and a metal. An annealing step is performed so as to form a silicide of said metal in the cavity. The result is a totally silicided buried gate for the semiconductor device. | 2009-08-27 |
20090212331 | SEMICONDUCTOR COMPONENT WITH SCHOTTKY ZONES IN A DRIFT ZONE - A description is given of a semiconductor component comprising a drift zone of a first conduction type and at least one Schottky metal zone arranged in the drift zone, and of a method for producing a semiconductor component. | 2009-08-27 |
20090212332 | FIELD EFFECT TRANSISTOR WITH REDUCED OVERLAP CAPACITANCE - In a first structure, a metal gate portion may be laterally recessed from a substantially vertical surface of a gate conductor thereabove. A cavity is formed between the metal gate portion and a gate spacer. In a second structure, a disposable gate portion is removed after laterally recessing a metal gate portion therebeneath and forming a dielectric layer having a surface coplanar with a top surface of the disposable gate portion. (We have to include the inner spacer without a metal recess). An inner gate spacer is formed over a periphery of the metal gate portion provide a reduced overlap capacitance. In a third structure, a thin dielectric layer is employed to form a cavity next to the metal gate portion in conjunction with the inner gate spacer to provide reduced overlap capacitance. | 2009-08-27 |
20090212333 | METHOD OF MANUFACTURING A BURIED-GATE SEMICONDUCTOR DEVICE AND CORRESPONDING INTEGRATED CIRCUIT - A semiconductor device includes a semiconductor channel region and a gate region, wherein the gate region includes at least one buried part extending under the channel region. The buried part of the gate region is formed from a cavity under the channel region. The cavity is filled with a first material. An opening is made to access the first material. In one implementation, aluminum is deposited in the opening in contact with the first material. An anneal is performed to cause the aluminum to be substituted for the first material in the cavity. In another implementation, a second material different from the first material is deposited in the opening. An anneal is performed to cause an alloy of the first and second materials to be formed in the cavity. | 2009-08-27 |
20090212334 | SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING THE SAME - Disclosed are embodiments relating to a semiconductor device and a method of manufacturing a semiconductor device that may prevent an increase of a dielectric effective constant of the IMD. In embodiments, a semiconductor device may include a substrate having a source/drain area, a gate electrode formed on the semiconductor substrate, a first inter-metal dielectric layer formed on the semiconductor substrate and having a first damascene pattern, a first barrier layer formed on the damascene pattern, a first metal line formed on the first barrier layer, and a first metal capping layer formed in the first damascene pattern. | 2009-08-27 |
20090212335 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) IMAGE SENSOR AND FABRICATING METHOD THEREOF - A method of fabricating a complementary metal-oxide-semiconductor (CMOS) image sensor is provided. First, an isolation structure is formed in a substrate with a photo-sensitive region and a transistor device region in the substrate. The transistor device region includes at least a region for forming a transfer transistor. A dielectric layer and a conductive layer are sequentially formed on the substrate. An ion implantation process is performed to implant a dopant into the substrate below the position for forming a gate of the transfer transistor and in the photo-sensitive region through the conductive layer and the dielectric layer. The conductive layer and the dielectric layer are patterned to at least form the gate structure of the transfer transistor on the transistor device region. Thereafter, a photo diode is formed in the substrate in the photo-sensitive region. | 2009-08-27 |
20090212336 | PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus includes a photoelectric conversion unit with a semiconductor region of a first conduction type, an amplifying transistor, and a contact. The contact supplies, via a semiconductor region of a second conduction type arranged along a side surface and a bottom surface of an element isolation region, a reference voltage to the semiconductor region of the second conduction-type arranged below source and drain regions of the amplifying transistor in a region below a gate electrode of the amplifying transistor. | 2009-08-27 |
20090212337 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate. | 2009-08-27 |
20090212338 | Semiconductor Constructions, And Methods Of Forming Semiconductor Constructions - Some embodiments include methods of forming semiconductor constructions. Oxide is formed over a substrate, and first material is formed over the oxide. Second material is formed over the first material. The second material may be one or both of polycrystalline and amorphous silicon. A third material is formed over the second material. A pattern is transferred through the first material, second material, third material, and oxide to form openings. Capacitors may be formed within the openings. Some embodiments include semiconductor constructions in which an oxide is over a substrate, a first material is over the oxide, and a second material containing one or both of polycrystalline and amorphous silicon is over the first material. Third, fourth and fifth materials are over the second material. An opening may extend through the oxide; and through the first, second, third, fourth and fifth materials. | 2009-08-27 |
20090212339 | Flash Memory Device and Method of Fabricating the Same - The present invention relates to flash memory devices and a method of fabricating the same. In an aspect of the present invention, the flash memory device includes trenches formed in a semiconductor substrate and having a step at their lower portion, a tunnel insulating layer formed in an active region of the semiconductor substrate, first conductive layers formed on the tunnel insulating layer, an isolation layer gap-filling between the trenches and the first conductive layers, and a second conductive layer formed on the first conductive layer and having one side partially overlapping with the isolation layers. | 2009-08-27 |
20090212340 | FLASH MEMORY DEVICES - A gate electrode line which extends in a second direction crossing a first direction on a substrate including an active region which is defined by a device isolation layer and extends in the first direction and a charge trap layer disposed between the active region and the gate electrode line, wherein a bottom surface of the gate electrode line disposed on the device isolation layer is lower than a top surface of the charge trap layer disposed on the active region and higher than a top surface of the active region. | 2009-08-27 |
20090212341 | SEMITUBULAR METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTOR - An epitaxial semiconductor layer or a stack of a silicon germanium alloy layer and an epitaxial strained silicon layer is formed on outer sidewalls of a porous silicon portion on a substrate. The porous silicon portion and any silicon germanium alloy material are removed and a semitubular epitaxial semiconductor structure in a three-walled configuration is formed. A semitubular field effect transistor comprising inner and outer gate dielectric layers, an inner gate electrode, an outer gate electrode, and source and drain regions is formed on the semitubular epitaxial semiconductor structure. The semitubular field effect transistor may operate as an SOI transistor with a tighter channel control through the inner and outer gate electrodes, or as a memory device storing electrical charges in the body region within the semitubular epitaxial semiconductor structure. | 2009-08-27 |
20090212342 | Asymmetric Single Poly NMOS Non-Volatile Memory Cell - An asymmetric non-volatile memory (NVM) cell for a CMOS IC formed by a standard CMOS process flow used to form both low voltage and high voltage transistors on a substrate. The NVM cell includes an NMOS floating gate transistor and an optional select transistor. The floating gate transistor includes an elongated floating gate having a first portion disposed over the channel region C | 2009-08-27 |
20090212343 | NON-VOLATILE TWO-TRANSISTOR PROGRAMMABLE LOGIC CELL AND ARRAY LAYOUT - A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor. | 2009-08-27 |
20090212344 | FLASH MEMORY DEVICE - Disclosed herein is a flash memory device in which the distribution of threshold voltage is significantly reduced and the durability is improved even though a floating gate has a micro- or nano-size length. It comprises a tunneling insulation film formed on a semiconductor substrate; a multilayer floating gate structure comprising a first thin storage electrode, a second thick storage electrode, and a third thin storage electrode, defined in that order on the tunneling insulation film; an interelectrode insulation film and a control electrode formed in that order on the floating gate structure; and a source/drain provided in the semiconductor substrate below the opposite sidewalls of the floating gate structure. The novel flash memory device can be readily fabricated at a high yield through a process compatible with a conventional one. | 2009-08-27 |
20090212345 | Semiconductor Device and Method for Manufacturing the Same - Disclosed herein are a semiconductor device and a method for manufacturing the same. A method of manufacturing a semiconductor device includes forming a tunnel insulating layer, a first conductive layer, a dielectric layer, a second conductive layer and a gate electrode layer on a semiconductor substrate; patterning the gate electrode layer to expose the second conductive layer; forming a protective layer on a side wall of the gate electrode layer; and etching the exposed second conductive layer, the dielectric layer, and the first conductive layer to form a gate pattern. | 2009-08-27 |
20090212346 | SEMICONDUCTOR MEMORY ELEMENT - A semiconductor memory element includes: a tunnel insulating film formed on a semiconductor substrate; a HfON charge storage film with Bevan clusters formed on the tunnel insulating film; a blocking film formed on the HfON charge storage film; and a gate electrode formed on the blocking film. | 2009-08-27 |
20090212347 | SONOS MEMORY DEVICE WITH OPTIMIZED SHALLOW TRENCH ISOLATION - Method of manufacturing a non-volatile memory device on a semiconductor substrate in a memory area, said non-volatile memory device comprising a cell stack of a first semiconductor layer, a charge trapping layer and an electrically conductive layer, the charge trapping layer being the intermediate layer between the first semiconductor layer and the electrically conductive layer, the charge trapping layer comprising at least a first insulating layer; the method comprising:—providing the substrate having the first semiconductor layer;—depositing the charge trapping layer;—depositing the electrically conductive layer; —patterning the cell stack to form at least two non-volatile memory cells, and—creating a shallow trench isolation in between said at least two non-volatile memory cells. | 2009-08-27 |
20090212348 | MIRROR BIT MEMORY DEVICE APPLYING A GATE VOLTAGE ALTERNATELY TO GATE - A semiconductor device and a method for manufacturing thereof are provided. The semiconductor device includes: an ONO film including a charge storage layer on a semiconductor substrate; a plurality of bit lines each extending inside the semiconductor substrate; a plurality of interspaces each interposed between the adjacent bit lines; a plurality of gates each provided along the bit line on the ONO film above the interspaces; and a plurality of word lines electrically coupled with the corresponding gates formed on one of the interspaces, each extending to intersect with the bit lines. The two gates adjacent with each other in a width direction of the bit line are connected to different word lines. | 2009-08-27 |
20090212349 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film. | 2009-08-27 |
20090212350 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer. | 2009-08-27 |
20090212351 | ELECTRON BLOCKING LAYERS FOR ELECTRONIC DEVICES - Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation. | 2009-08-27 |
20090212352 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor memory device has a semiconductor substrate, a plurality of word lines formed at predetermined intervals on the semiconductor substrate, each word line having a gate insulating film, a charge storage layer, a first insulating film, and a controlling gate electrode which are stacked in order, and including a metal oxide layer above the level of the gate insulating film, a second insulating film covering a side of the word line and a surface of the semiconductor substrate between the word lines, and having a film thickness of 15 nm or less, and a third insulating film formed between the word lines adjacent to each other such that a region below the level of the metal oxide layer has a cavity. | 2009-08-27 |
20090212353 | NON-VOLATILE MEMORY - A non-volatile memory includes a substrate having two openings, a stacked gate structure disposed on the substrate between the two openings, a liner disposed on a bottom of each of the two openings and parts of a sidewall of each of the two openings, a second conductive layer disposed on the liner at the bottom of each of the two openings, and a third conductive layer on the second conductive layer and the liner. The stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, and a first conductive layer. The liner has a top surface lower than that of the substrate. The second conductive layer has a top surface co-planar with that of the liner. The third conductive layer has a top surface at least co-planar with that of the substrate and lower than that of the first dielectric layer. | 2009-08-27 |
20090212354 | TRENCH MOSEFT WITH TRENCH GATES UNDERNEATH CONTACT AREAS OF ESD DIODE FOR PREVENTION OF GATE AND SOURCE SHORTATE - A trench DMOS transistor having overvoltage protection and prevention for shortage between gate and source when contact trenches are applied includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. Trench gates extend through the body region and the substrate. An insulating oxide layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer defining the Zener diode region. A plurality of cathode regions of the first conductivity type is formed in undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions. Trench gates underneath the Zener diode act as the buffer layer for prevention of shortage between gate and source. | 2009-08-27 |
20090212355 | Metal-Oxide-Semiconductor Transistor Device and Method for Making the Same - A metal-oxide-semiconductor transistor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, an oxide layer formed on the epitaxial layer, a gate structure formed on the oxide layer, and a shallow junction well formed on the two lateral sides of the gate structure including a source region and a heavy doping region. The gate structure includes a conductive layer having a gap on top of the sidewall of the conductive layer and a spacer formed on the gap. | 2009-08-27 |
20090212356 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a double-diffused metal oxide semiconductor (DMOS) transistor having a gate electrode and a drain electrode region; and a protection element protecting the gate electrode with respect to overvoltage and coupled to the DMOS transistor on a structure of one semiconductor substrate. The DMOS transistor and the protection element are included in an element integrated structure. In the device, the protection element is formed on a diffusion region, which is separately formed with respect to a diffusion region for the DMOS transistor, in the drain electrode region of the DMOS transistor. | 2009-08-27 |
20090212357 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device. A well region ( | 2009-08-27 |
20090212358 | Semiconductor device and a method of manufacturing the same - A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p | 2009-08-27 |
20090212359 | TRENCHED MOSFET WITH TRENCHED SOURCE CONTACT - A trenched MOSFET with trenched source contact, comprising: a semiconductor region, further comprising a silicon substrate, a epitaxial layer corresponding to the drain region of the trenched MOSFET, a base layer corresponding to the body region of the trenched MOSFET, and a source layer corresponding to the source region of the trenched MOSFET; an interlayer oxide film formed on the source layer; a front metal layer formed on a upper surface of the semiconductor region; a back metal layer formed on a lower surface of the semiconductor region; a plurality of trenched gates formed to reach the epitaxial layer through the source layer and the base layer, and is covered by the interlayer oxide film; and a plurality of source contact trenches formed to reach the base layer through the interlayer oxide film and the source layer, and is covered by the front metal layer; wherein the silicon substrate, the epitaxial layer, the base layer, and the source layer are stacked in sequence; and each of the source contact trenches has a lateral contact layer at a sidewall thereof. | 2009-08-27 |
20090212360 | High-Voltage Transistor and Method for its Manufacture - A high-voltage transistor is provided with a well of a first conductivity type, which is arranged in a substrate ( | 2009-08-27 |
20090212361 | Semiconductor device and method of manufacturing the same - A LOCOS offset type MOS transistor includes a MOS transistor including: a gate electrode formed on a gate oxide film, the gate oxide film being formed on a surface of a semiconductor substrate of a first conductivity type; a LOCOS oxide film and a first offset diffusion layer of a second conductivity type, which are formed on the surface of the semiconductor substrate at one of both sides and only one side of the gate electrode, a part of a region of the LOCOS oxide film, which is not an end of the LOCOS oxide film, being removed; and one of both of a source diffusion layer and a drain diffusion layer of the second conductivity type and only a drain diffusion layer of the second conductivity type is formed in the first offset diffusion layer corresponding to the region in which the LOCOS oxide film is removed. Accordingly, a semiconductor device may be provided including the MOS transistor which has a high break down voltage and ensures a proper operation even at a voltage of 50 V or higher by covering a region in which electric field accumulation is caused below the drain diffusion layer with the offset diffusion layer. | 2009-08-27 |
20090212362 | SOI FIELD EFFECT TRANSISTOR WITH A BACK GATE FOR MODULATING A FLOATING BODY - A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated. | 2009-08-27 |
20090212363 | Method for forming a one-transistor memory cell and related structure - According to one exemplary embodiment, a method for fabricating a one-transistor memory cell includes forming an opening by removing a portion of a gate stack of a silicon-on-insulator (SOI) device, where the SOI device is situated over a buried oxide layer. The method further includes forming a bottom gate of the one-transistor memory cell in a bulk substrate underlying the buried oxide layer. The method further includes forming a charge trapping region in the buried oxide layer. The charge trapping region is formed at an interface between a silicon layer underlying the gate stack and the buried oxide layer. The charge trapping region causes the one-transistor memory cell to have an increased sensing margin. The method further includes forming a top gate of the one-transistor memory cell in the opening. Also disclosed is an exemplary one-transistor memory cell fabricated utilizing the exemplary disclosed method. | 2009-08-27 |
20090212364 | Semiconductor substrates and manufacturing methods of the same - Semiconductor substrates and methods of manufacturing the same are provided. The semiconductor substrates include a substrate region, an insulation region and a floating body region. The insulation region is disposed on the substrate region. The floating body region is separated from the substrate region by the insulation region and is disposed on the insulation region. The substrate region and the floating body region are formed of materials having identical characteristics. The method of manufacturing the semiconductor substrate including forming at least one floating body pattern by etching a bulk substrate, separating the bulk substrate into a substrate region and a floating body region by etching a lower middle portion of the floating body pattern, and filling an insulating material between the floating body region and the substrate region. | 2009-08-27 |
20090212365 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a monocrystalline substrate; an inter-layer film formed on the monocrystalline substrate; a contact hole penetrating the inter-layer film and partially exposing an upper surface of the monocrystalline substrate; a sidewall formed on an inner surface of the contact hole; a plurality of first monocrystalline layers which include few defects, fill the contact hole, and cover the inter-layer film; and a plurality of second monocrystalline layers which include many defects and cover the sidewall and an upper surface of the inter-layer film so as to be sandwiched between the first monocrystalline layers and the inter-layer film. | 2009-08-27 |
20090212366 | CONTACT SCHEME FOR FINFET STRUCTURES WITH MULTIPLE FINs - A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together. | 2009-08-27 |
20090212367 | Arrangement of mosfet's for controlling same - An arrangement of a plurality of MOSFET's on a chip that includes a first terminal, a second terminal and a third terminal is provided, the arrangement having at least one first MOSFET used as a first control cell and at least one second MOSFET used as a second control cell, each MOSFET having respectively a gate terminal, a source terminal and a drain terminal. The source terminals of all the MOSFET's are connected to one another and contacting the first terminal of the chip. The drain terminal of the at least one second MOSFET, which is used as a power cell, contacts the second terminal of the chip. The gate terminals of all the MOSFET's are connected to one another and contact the third terminal of the chip. The gate terminal and the drain terminal of the at least one first MOSFET, which is used as the first control cell, are connected to one another. | 2009-08-27 |
20090212368 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device including transistors and strain layers is provided. Each transistor includes a source region and a drain region on a substrate and a gate structure on a channel region between the source region and the drain region. Lengths of the channel regions of these transistors are the same, but at least one source or drain region has a width along a channel length direction and the width is different from widths of other source or drain regions. The strain layers include first and second strain layers embedded separately at two sides of each gate structure in the substrate. A first width of each first strain layer along the channel length direction is the same, and a second width of each second strain layer along the channel length direction is the same. | 2009-08-27 |
20090212369 | Gate Effective-Workfunction Modification for CMOS - CMOS circuit structures are disclosed with the PFET and NFET devices having high-k dielectric layers consisting of the same gate insulator material, and metal gate layers consisting of the same gate metal material. The PFET device has a “p” interface control layer which is capable of shifting the effective-workfunction of the gate in the p-direction. In a representative embodiment of the invention the “p” interface control layer is aluminum oxide. The NFET device may have an “n” interface control layer. The materials of the “p” and “n” interface control layers are differing materials. The “p” and “n” interface control layers are positioned to the opposite sides of their corresponding high-k dielectric layers. Methods for fabricating the CMOS circuit structures with the oppositely positioned “p” and “n” interface control layers are also disclosed. | 2009-08-27 |
20090212370 | SEMICONDUCTOR DEVICE HAVING INSULATED GATE FIELD EFFECT TRANSISTORS AND METHOD OF FABRICATING THE SAME - A semiconductor device has a plurality of insulated gate field effect transistors on a semiconductor substrate. A SAC contact hole is formed between two gates of the insulated gate field effect transistors. A side portion of the SAC contact hole is separated from two gates of the insulated gate field effect transistors by a side wall dielectric film and a dielectric film. A polycrystalline silicon plug having a U-shaped section structure is formed in a bottom portion of the SAC contact hole. A barrier metal film is formed on the polycrystalline silicon plug. A metal plug is buried on the barrier metal film so that covering on the SAC contact hole. | 2009-08-27 |
20090212371 | SEMICONDUCTOR DEVICE FABRICATION METHOD - According to an aspect of the present invention, there is provided a method for fabricating a semiconductor device, the method including: forming a first region and a second region in a substrate; forming the high-permittivity insulating film on the substrate in the first region and in the second region; forming a nitride film on the high-permittivity insulating film in the second region; forming a cap film on the high-permittivity insulating film in the first region and on the nitride film in the second region; forming a metal film on the cap film; and performing a heating process. | 2009-08-27 |
20090212372 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate comprising an element isolation region; two gate electrodes formed in substantially parallel on the semiconductor substrate via respective gate insulating films; two channel regions each formed in regions of the semiconductor substrate under the two gate electrodes; a source/drain region formed in a region of the semiconductor substrate sandwiching the two channel regions; a first stress film formed so as to cover the semiconductor substrate and the two gate electrodes; and a second stress film formed in at least a portion of a void, the void being formed in a region between the two gate electrodes. | 2009-08-27 |
20090212373 | SEMICONDUCTOR DEVICE - A semiconductor device facilitates securing a high breakdown voltage and reducing a chip area thereof includes a low-potential gate driver circuit disposed on a semiconductor substrate, a high-breakdown-voltage junction edge-termination structure disposed in a peripheral portion of a high-potential gate driver circuit, disposed on the semiconductor substrate, for separating the low-potential gate driver circuit and the high-potential gate driver circuit from each other. A trench is disposed in the edge termination structure and between an n | 2009-08-27 |
20090212374 | SPACE EFFICIENT INTEGRATRED CIRCUIT WITH PASSIVE DEVICES - A multimodal integrated circuit (IC) is provided, comprising, first ( | 2009-08-27 |
20090212375 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance. | 2009-08-27 |
20090212376 | SEMICONDUCTOR TRANSISTORS HAVING HIGH-K GATE DIELECTRIC LAYERS AND METAL GATE ELECTRODES - A semiconductor structure and a method for forming the same. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction. | 2009-08-27 |
20090212377 | SEMICONDUCTOR INPUT CONTROL DEVICE - A force input control device suitable for high-volume applications such as cell phones, portable gaming devices and other handheld electronic devices along with other applications like medical equipment, robotics, security systems and wireless sensor networks is disclosed. The device can be one-axis or two-axis or three-axis sensitive broadening the range of applications. The device comprises a force sensor die formed within semiconductor substrate and containing a force sensor providing electrical output signal in response to applied external force, and electrical connection elements for mounting and/or wire bonding. Signal conditioning and processing integrated circuit can be integrated within some devices. A package enclosing at least a portion of the force sensor die and comprising a force-transferring element cooperated with the sensor die for transferring an external force to the force sensor die. | 2009-08-27 |
20090212378 | Method for producing a micromechanical structural element and semiconductor arrangement - The method serves for producing a micromechanical structure element ( | 2009-08-27 |
20090212379 | Semiconductor apparatus, manufacturing method for the semiconductor apparatus, and electronic information device - A semiconductor apparatus according to the present invention includes one or a plurality of pairs of a standard pattern and an offset pattern formed therein with respect to the standard pattern as manufacturing information and other information at an information writing position, which is visible from the outside, of each semiconductor chip on a wafer. | 2009-08-27 |
20090212380 | METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE - A method for manufacturing a solid-state imaging device is provided. | 2009-08-27 |
20090212381 | WAFER LEVEL PACKAGES FOR REAR-FACE ILLUMINATED SOLID STATE IMAGE SENSORS - A solid state image sensor includes a microelectronic element having a front face and a rear face remote from the front face, the rear face having a recess extending towards the front surface. A plurality of light sensing elements may be disposed adjacent to the front face so as to receive light through the part of the rear face within the recess. A solid state image sensor can include a microelectronic element having a front face and a rear face remote from the front face, a plurality of light sensing elements disposed adjacent to the front face, the light sensing elements being arranged to receive light through the rear face. Electrically conductive package contacts may directly overlie the light sensing elements and the front face and be connected to chip contacts at the front face through openings in an insulating packaging layer overlying the front face. | 2009-08-27 |
20090212382 | OPTICAL LEADLESS LEADFRAME PACKAGE - Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or translucent encapsulant formed within the first encapsulant opening and directly atop and contacting the light sensing region. A leadless leadframe or other conductive component can be coupled to a second surface of the die. The die may also have light sensitive regions that are shielded by the first encapsulant and/or stress buffer. The stress buffer can be a layer formed at the wafer stage or a dam formed at the panel stage. A customized mold is used while dispensing the first encapsulant such that the opening therethrough is properly formed. | 2009-08-27 |
20090212383 | SOLID-STATE IMAGING DEVICE, CAMERA MODULE AND ELECTRONIC EQUIPMENT MODULE - To provide a back-illuminated type solid-state imaging device capable of color separation of pixels without using a color filter, and a camera module and an electronic equipment module which incorporate the solid-state imaging device. | 2009-08-27 |
20090212384 | METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP ELEMENT, AND SOLID-STATE IMAGE PICKUP ELEMENT - Disclosed herein is a method of manufacturing a solid-state image pickup element, the method including the steps of forming a plurality of photoelectric conversion elements within a semiconductor substrate; forming a wiring layer via an insulating film on a surface of the semiconductor substrate in which surface the plurality of photoelectric conversion elements are formed; laminating a supporting substrate to a surface of the semiconductor substrate in which surface the wiring layer is formed via an adhesive; applying a pressure to the semiconductor substrate and the supporting substrate in a state of the semiconductor substrate and the supporting substrate being laminated to each other via the adhesive; and curing the adhesive by heating the adhesive to a curing temperature of the adhesive after releasing the applied pressure. | 2009-08-27 |
20090212385 | SEMICONDUCTOR DEVICE INCLUDING VANADIUM OXIDE SENSOR ELEMENT WITH RESTRICTED CURRENT DENSITY - In a semiconductor device including a semiconductor substrate and at least one sensor element made of vanadium oxide formed over the semiconductor substrate, the sensor element is designed so that a density of a current flowing through the sensor element is between 0 and 100 μA/μm2. | 2009-08-27 |
20090212386 | MEMS DEVICE AND METHOD OF MAKING SAME - A MEMS device includes a P-N device formed on a silicon pin, which is connected to a silicon sub-assembly, and where the P-N device is formed on a silicon substrate that is used to make the silicon pin before it is embedded into a first glass wafer. In one embodiment, forming the P-N device includes selectively diffusing an impurity into the silicon pin and configuring the P-N device to operate as a temperature sensor. | 2009-08-27 |