34th week of 2010 patent applcation highlights part 18 |
Patent application number | Title | Published |
20100213910 | METHOD AND APPARATUS FOR EXTERNAL CONTROL MODE STEP DOWN SWITCHING REGULATOR - A switching regulator integrated circuit (IC) is disclosed that includes a switch circuit that further includes a first switch and a second switch, a mode selector circuit controlled by external circuitry to select between a first mode and a second mode, and a control circuit. In response to a feedback signal from the switch circuit, when the first mode is selected, the control circuit toggles the first switch and the second switch ON and OFF alternately at a fixed first frequency. When a second mode is selected, the control circuit causes the second switch to turn OFF completely and the first switch to switch ON and OFF at a variable second frequency. | 2010-08-26 |
20100213911 | SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER SUPPLY DEVICE - A semiconductor integrated circuit includes: a first switching element and a second switching element that are provided in series between a first power line and a second power line; a power supply circuit that outputs a given output voltage by on/off controlling the first switching element and the second switch element; a current detection circuit that detects a current corresponding to an output load current of the power supply circuit; a switching time control circuit that controls a switching time defined by a power supply voltage and the output voltage based on a current value detected by the current detection circuit; and a switching element control circuit that controls the first switching element and the second switching element based on an output signal of the switching time control circuit. | 2010-08-26 |
20100213912 | Quick Response Power Supply Switching Device and Power Supply Network Including Such a Switch - The present invention relates to a quick response power supply switching device. It also relates to a power supply network equipped with such a switch. The electrical power supply is connected to a set of blocks, the device comprises at least one switch ( | 2010-08-26 |
20100213913 | VOLTAGE REGULATOR - Provided is a voltage regulator that is capable of improving a transient response characteristic while suppressing current consumption. A fluctuating output voltage is detected without increasing the current consumption of a differential amplifier, and a phase compensation resistor ( | 2010-08-26 |
20100213914 | CORRECTING PRE-BIAS DURING TURN-ON OF SWITCHING POWER REGULATORS - Rather than operating in asynchronous mode during turn-on ramps, a switching power regulator system may be configured to synthesize a digital waveform, which may protect against a pre-bias condition and maintain the desired ramp-up time and rate. The desired turn-on ramp may be generated digitally by counter logic, beginning with an initial value and incrementing at a programmed rate until a digital value equivalent to the desired output voltage is reached. When a pre-bias condition is not present, the output of the digital ramp generator may control a digital-to-analog converter (DAC), which may be configured to generate the reference voltage for the power regulator. To correct for a pre-bias condition, the pre-bias output of the power regulator may be measured prior to turn-on, using an analog-to-digital converter. The digital pre-bias value may be used to control the DAC until the value of the digital waveform generated by the ramp generator reaches the pre-bias value. | 2010-08-26 |
20100213915 | SEMICONDUCTOR SWITCHING DEVICE - A semiconductor switching device includes a power control part, which includes a voltage dropping chopper circuit having a first switching element and a first diode, a voltage boosting chopper circuit having a second switching element and a second diode, and an inductance. And the inductance is connected such that an unusual current caused by the arm short circuit is forced to pass through the inductance. | 2010-08-26 |
20100213916 | FREQUENCY MODULATOR AND FM TRANSMISSION CIRCUIT USING THE SAME - An input signal is input via a first resistor to an inverting input terminal of an operational amplifier. A second resistor is provided on a feedback path between an output terminal and the inverting input terminal of the operational amplifier. A control voltage Vcnt output from the operational amplifier is input to a VCO. A frequency divider frequency-divides an output signal Sout of the VCO. A phase comparator compares an output signal from the frequency divider with a reference clock signal and outputs a voltage according to a phase difference. A loop filter removes a high-frequency component of an output voltage Vcp of the phase comparator and outputs the voltage to a non-inverting input terminal of the operational amplifier. | 2010-08-26 |
20100213917 | Frequency Compensation Scheme for Stabilizing the LDO Using External NPN in HV Domain - A voltage regulator may comprise a regulator output configured to provide a regulated voltage, which may be controlled by an error amplifier based on the regulated voltage and a reference voltage. The error amplifier may control a source-follower stage to mirror a multiple of the current flowing in the source-follower stage into an internal pass device. A voltage developed by the mirror current may control an external pass device configured to deliver the load current into the regulator output. A first resistor may be configured to decouple a load capacitor coupled between the regulator output and reference ground, when the load current is below a specified value. A second resistor may be configured to create a bias current in the internal pass device even when the external pass device is close to cut-off region. A third resistor may be configured to counter the effects of negative impedance at the control terminal of the external pass device caused by the current-gain of the external pass device. A compensation capacitor and resistor may be coupled in series between the output of the error amplifier and the output of the voltage regulator to provide frequency compensation for the Miller-Effect. | 2010-08-26 |
20100213918 | Layout of a Reference Generating System - A layout of a voltage/current reference system is disclosed. A first voltage/current reference circuit (for example, a bandgap reference circuit) and a second voltage/current reference circuit are respectively laid out on either side of a substrate, such as edges or perimeter sides of the substrate. A reference voltage/current is derived by averaging respective output reference voltage/current values of the first and the second voltage/current reference circuits. Accordingly, the noise influence on the voltage/current reference system is minimized. | 2010-08-26 |
20100213919 | TEMPERATURE COMPENSATION IN INTEGRATED CIRCUIT - In an embodiment, an integrated circuit comprises a plurality of temperature sensors and a power manager coupled thereto. The temperature sensors are physically distributed over an area of the integrated circuit that is occupied by logic circuitry implementing the operations for which the integrated circuit is designed. The power manager is configured to transmit a power supply voltage request to an external power supply module, the power supply voltage request indicating a requested magnitude of the power supply voltage for the integrated circuit. The power manager is configured to modify the requested magnitude responsive to indications from each of the plurality of temperatures sensors that represent a temperature of the integrated circuit sensed by each of the plurality of temperature sensors. | 2010-08-26 |
20100213920 | POWER CONTROL CIRCUIT, METHOD OF CONTROLLING POWER CONTROL CIRCUIT, AND DLL CIRCUIT INCLUDING POWER CONTROL CIRCUIT - A power control circuit includes a check unit that receives a reference clock and generates a check signal for cyclically activating a feedback loop of a DLL circuit, a phase detecting unit that detects a phase difference between the reference clock and a feedback clock, and generates a phase difference detection signal, and a signal combining unit that generates a power cutoff signal in response to a locking completion signal, the check signal, and the phase difference detection signal. | 2010-08-26 |
20100213921 | Pre-Charging An Inverter Using An Auxiliary Winding - A transformer module includes a main primary winding coupled to a first input power source to receive a medium voltage signal, multiple main secondary windings each to couple to a power cell of a drive system, and an auxiliary primary winding coupled to a second input power source to receive a low voltage signal. The auxiliary primary winding can be spatially separated from the main windings to increase leakage inductance. The auxiliary primary winding can be active during a pre-charge operation to pre-charge the power cells. | 2010-08-26 |
20100213922 | ELECTROMAGNETIC BATH LEVEL MEASUREMENT FOR PYROMETALLURGICAL FURNANCES - In a first aspect, some embodiments of the invention provide a system for measuring the level of a plurality of phases of a conductive or semi-conductive mixture in a vessel, the system comprising: a vessel configured to hold a conductive or semi-conductive mixture including a plurality of phases, the vessel comprising a sidewall with an interior surface and an exterior surface, a plurality of antennas configured to transmit electromagnetic and/or eddy current signals into the sidewall of the vessel to impinge upon the plurality of phases in the conductive or semi-conductive mixture and to receive corresponding signals reflected from the plurality of phases in the conductive or semi-conductive mixture, the antennas situated at a plurality of different levels along the exterior surface of the vessel sidewall, wherein reflected signals are received, a transmitter module configured to generate electromagnetic and/or eddy current signals in communication with the plurality of antennas, a receiver module configured to receive electromagnetic and/or eddy current signals in communication with the plurality of antennas, a control module in communication with the transmitter module and the receiver module configured to control the operation of the transmitter module and the receiver module, and a signal analysis module in communication with the receiver module configured to process the reflected signals to determine the levels of the plurality of phases of the conductive or semi-conductive mixture within the vessel. | 2010-08-26 |
20100213923 | PROCESS FOR MEASURING PEAK VALUES AND POWER OF AN AUDIO FREQUENCY SIGNAL - The process for measuring peak and power values of an audiofrequency signal S including:
| 2010-08-26 |
20100213924 | MEASURING APPARATUS, TESTING APPARATUS AND MEASURING METHOD - Provided is a measurement apparatus that measures a characteristic of a filter, comprising a first transmission line that has the filter connected therein, the first transmission line receiving a multi-tone signal having signal components at a plurality of frequencies from an input end thereof, passing the multi-tone signal through the filter, and outputting the multi-tone signal from an output end thereof; a second transmission line that receives the multi-tone signal from an input end thereof, propagates the multi-tone signal therein, and outputs the multi-tone signal from an output end thereof; and a measuring section that calculates the characteristic of the filter based on the multi-tone signal output from the output end of the first transmission line and the multi-tone signal output from the output end of the second transmission line. | 2010-08-26 |
20100213925 | ADVANCED REAL-TIME GRID MONITORING SYSTEM AND METHOD - This invention deals with an advanced Real-time Grid Monitoring System (RTGMS) suitable for both single-phase and three-phase electric power systems. This invention provides an essential signal processing block to be used as a part of complex systems either focused on supervising and diagnosing power systems or devoted to control power processors interacting with the grid. This invention is based on a new algorithm very suitable for real-time characterization of the grid variables under distorted and unbalanced grid conditions. The main characteristic of this invention is the usage of a frequency-locked loop, based on detecting the grid frequency, for synchronizing to the grid variables. It results in a very robust system response in relation to existing technique based on the phase-angle detection since grid frequency is much more stable variable than the grid voltage/current phase-angle, mainly during grid faults. Moreover, the algorithm supporting this invention is very efficient and can be implemented in regular industrial microprocessors. These features make the RTGMS object of this invention ideal to be applied in the control of distributed generation systems (DGS), flexible AC transmission systems (FACTS), power quality conditioners (PQC) and uninterruptible power supplies (UPS). In all these systems, the fast and precise real time detection of the voltage and/or current sequence components under grid fault conditions is a crucial matter. | 2010-08-26 |
20100213926 | APPARATUS AND METHOD FOR VOLTAGE SENSING IN ELECTRICAL METERING SYSTEMS - A voltage isolation circuit. The input voltage Vin is connected to a primary winding of a transformer T | 2010-08-26 |
20100213927 | ABSOLUTE MAGNETIC POSITION ENCODER - An absolute magnetic position encoder includes a magnet carrier ( | 2010-08-26 |
20100213928 | Method and Apparatus for Detecting Rotational Movement of a Piston Rod - A piston rod position sensing system includes a cylinder and a piston rod arranged in the cylinder for movement with respect thereto. A magnetically hard layer is formed on the piston rod to provide a recording medium. A magnetic pattern is recorded in the magnetically hard layer. The magnetic pattern includes tracks recorded in the magnetically hard layer lengthwise of the piston rod. Each track comprises magnetically written regions used to identify a current position of the piston rod. The sensing system also includes a plurality of magnetic field sensors in greater number than the plurality of tracks. Each magnetic field sensor senses the magnetically written regions of one or more of the tracks while the piston rod is moving with respect to the cylinder and generates signals used for detecting rotation of the piston rod in response to the sensed magnetically written regions. | 2010-08-26 |
20100213929 | ROTOR BLADE SENSOR - A rotor blade sensor for detecting a rotor blade ( | 2010-08-26 |
20100213930 | Integrated micro actuator and lVDT for high precision position measurements - A single housing with a non-ferromagnetic piezo-driven flexure has primary and secondary coil forms of different diameters, one coaxially inside the other, integrated in the flexure. The cylinders defining the planes of the primary and secondaries do not spatially overlap. The secondary coil forms may be wound in opposite directions and wired to provide a transformer device. Movement of the primary relative to the secondaries in the direction of the central axis of the coils can be differentially detected with high precision. | 2010-08-26 |
20100213931 | DEVICE FOR DETECTING BREAKAGE OF OPEN/CLOSE TYPE WINDOW GLASS - A breakage detection device for detecting breakage of a window glass capable of opening and closing an opening of a vehicle is provided. The breakage detection device includes a clip, a magnetic sensor, a detection unit, and a determination unit. The clip is arranged at an end portion of the window glass and holds an end portion of the window glass with a force enabling the end portion of the window glass to be crushed when the window glass breaks. The magnetic sensor detects displacement of at least part of the clip when the window glass breaks. The detection unit acquires an output value of the magnetic sensor in predetermined time intervals to detect a temporal change in the output value of the magnetic sensor. The determination unit determines that the window glass is broken when the temporal change detected by the detection unit is outside a tolerable range. | 2010-08-26 |
20100213932 | MAGNETIC SENSOR CIRCUIT - Provided is a magnetic sensor circuit capable of a low-voltage operation, which comprises a Hall element and a magnetic offset cancellation circuit for the Hall element. In the magnetic sensor circuit using the Hall element, at the time of turning on transmission gates for switching connections between input terminals of an amplifier circuit in the magnetic offset cancellation circuit and electrodes of the Hall element in order to cancel a magnetic offset of the Hall element, gates of N-channel transistors in the transmission gates are set at voltages higher than a power supply voltage by a drive circuit. | 2010-08-26 |
20100213933 | MAGNETIC FIELD SENSING DEVICE - A magnetic field sensing device for determining the strength of a magnetic field, includes four magnetic tunnel junction elements or element arrays ( | 2010-08-26 |
20100213934 | HIGH MAGNETIC MOMENT PARTICLE DETECTION - A device includes a sensor surface and a pair of electrodes. The sensor surface includes a first conductive layer separated from a second conductive layer by an intermediary layer, a magnetization direction of the first conductive layer and a magnetization direction of the second conductive layer having a ground state orientation of approximately 0 degrees. An electrical resistance between the pair of electrodes is determined by a magnetic field proximate the sensor surface. | 2010-08-26 |
20100213935 | MAGNETIC DETECTION ELEMENT AND DETECTION METHOD - A magnetic detection element, comprises a core composed of a soft magnetic material, a detecting coil for detecting a magnetic field applied to the core, and an exciting coil for applying an alternating magnetic field to the core, wherein the surface of the core is divided into a first region and a second region in the longitudinal direction of the detecting coil, the first region and the second region being different in affinity for a detection object substance. | 2010-08-26 |
20100213936 | MRI SPATIAL ENCODING USING HYPERCOMPLEX NUMBERS - The disclosure relates to a method of processing a complex signal comprising acquisition of a signal in the form of complex numbers; determination on the basis of the complex signal acquired of the associated hypercomplex components, said components corresponding to at least derivatives with respect to time of the phase of the complex signal acquired; processing of the hypercomplex signal thus determined in such a way that the signal resulting from the processing comprises a greater number of components than the number of components of the signal acquired. | 2010-08-26 |
20100213937 | Magnetic Resonance Imaging Apparatus and Method - An magnetic resonance imaging apparatus includes: imaging means for dividing an object to be examined into a plurality of regions in a predetermined direction, setting images of slice positions for each of the regions so that the slice positions are continuous in each region, and imaging each of the regions while moving the object stepwise; and display means for acquiring a plurality of image data having three types of categories: the region, the slice position and the imaging sequence, and displaying the image data. | 2010-08-26 |
20100213938 | SIMULTANEOUS ACQUISITIONS OF SPIN- AND STIMULATED-ECHO PLANAR IMAGING - The disclosure provides echo planar imaging (EPI) based single-shot imaging techniques for acquiring spin-EPI (SEPI) and stimulated-EPI after a single RF excitation. In certain embodiments, the SEPI and STEPI acquired in a singleshot are used to compute a T | 2010-08-26 |
20100213939 | REMOTE BODY ARRAYS FOR HIGH-PERFORMANCE MAGNETIC RESONANCE IMAGING AND SPECTROSCOPY - In a magnetic resonance imaging apparatus and method, radio frequency signals are radiated into an examination subject and/or received from the examination subject by an array of radio frequency coils that completely encircles the examination subject, and that is located at a distance from the examination subject out of contact with the examination subject. | 2010-08-26 |
20100213940 | MAGNETIC FIELD GRADIENT GENERATING SYSTEM AND METHOD FOR REDUCING THE NOISE LEVEL IN NMR/MRI EXPERIMENTS - A magnetic field gradient generating system for a NMR system, includes at least one set of gradient coils, preferably arranged according to three axes of a spatial referential system, and a controlled power supplying unit for the gradient coils, the power supplying unit including, for each gradient coil, a converter/amplifier module, the modules being fed with pulse sequences of digital gradient data provided as word streams by an adapted gradient data generator according to a pulse program, each arrangement of a gradient coil and a converter/amplifier module forming a gradient channel. The power supplying unit also includes an automatic blanking system which scans the gradient data words sent to the [converter/amplifier] modules and, according to sensed values, selectively delivers blanking signals to be applied to the modules in order to disable the power stages of their respective amplifiers connected to the gradient coils, when no current is to be fed to the coils. | 2010-08-26 |
20100213941 | STRIPLINE ANTENNA AND ANTENNA ARRAY FOR A MAGNETIC RESONANCE DEVICE - An antenna ( | 2010-08-26 |
20100213942 | WIRED PIPE WITH WIRELESS JOINT TRANSCEIVER - A wireless transceiver for transmitting data across a pipe joint is described herein. At least some illustrative embodiments include a wireless communication apparatus including a housing configured to be positioned inside/proximate of/to an end of a drill pipe. The housing includes an antenna with at least one RF signal propagation path parallel to the axis of the housing, and an RF module (coupled to the antenna) configured to couple to a communication cable, and to provide at least part of a data retransmission function between an antenna signal and a communication cable signal. A material (transparent to RF signals within the RF module's operating range) is positioned along the circumference, and at/near an axial end, of the housing closest to the antenna. At least some RF signals, axially propagated between the antenna and a region near said axial end, traverse the radiotransparent material along the propagation path. | 2010-08-26 |
20100213943 | METHOD FOR ACCENTUATING SIGNAL FROM AHEAD OF THE BIT - A method for estimating a property of a portion of an earth formation ahead of a borehole penetrating the formation, the method includes: conveying a logging tool through the borehole; receiving one or more first signals from a previous depth of the logging tool; constructing a model of the earth formation using the one or more first signals; predicting one or more second signals from the portion of the earth formation ahead of the borehole using the model; receiving one or more third signals from the portion of the earth formation ahead of the borehole; calculating a difference between the one or more third signals and the one or more second signals; and estimating the property from the difference. | 2010-08-26 |
20100213944 | Diagnosis Device, Diagnosis Method, And Lamp Ballast Circuit Using The Same - The present invention relates a diagnosis device for detecting an end of lamp life of a lamp, a diagnosis method, and a lamp ballast circuit using the same. The diagnosis device generates a reference lamp voltage by adding a predetermined reference voltage to a distributed voltage corresponding to a lamp voltage applied to a lamp and generates an integrated lamp voltage by integrating the reference lamp voltage. The diagnosis device compares the integrated lamp voltage with a normal range that an integrated lamp voltage has when the lamp is in a normal state. | 2010-08-26 |
20100213945 | System and Method of Monitoring an Electronic Discharge Device in an Air Purification System - A method and system of remotely monitoring an operational status of electronic discharge devices in an air purification system senses emitted radiation at a location proximate the air purification system, alone or in combination with a determination of an amount of time remaining in an operational lifetime of the electronic discharge device, or an amount of power delivered to at least one of the electronic discharge devices. A determination of the operational status of at least one of the electronic discharge devices is made based on at least emitted radiation, and the status information is transmitted to a remote monitoring unit that receives the status information and displays an indicator of operational status. In one embodiment, the operational status of a UV-C germicidal lamp may be monitored using optically sensitive devices located within a purification system. | 2010-08-26 |
20100213946 | METHOD OF ESTIMATION OF THE STATE OF CHARGE OF A LEAD-ACID BATTERY - The method of estimation of the state of charge of a lead acid battery comprises measuring the open circuit voltage difference between an integrated liquid junction reference electrode and a negative battery terminal during at least one cut-off period. It further comprises determination of the sign of the current though the battery prior to cut-off and estimation of the state of charge on the basis of the open circuit voltage difference and, according to the sign of the current, respectively of a charge or a discharge calibration curve, previously determined during a calibration procedure. The cut-off period has preferably a duration of at least 5 minutes. | 2010-08-26 |
20100213947 | BATTERY ASSEMBLY WITH ENHANCED PROPERTIES - A battery assembly for use in an aircraft. The battery assembly may include a battery and a circuit configured to monitor the battery in situ. The circuit may include at least one sensor positioned to sense at least one property of the battery and a processor in communication with the sensor. The battery assembly may also include a battery housing, wherein the battery and the circuit are positioned within the battery housing. A method for evaluating a battery in an electric device. The method may include collecting operational information from the battery. The operational information may be collected without removing the battery from the electric device. The method may also include comparing the operational information to a degradation routine describing a property of the battery and calculating a capacity of the battery. | 2010-08-26 |
20100213948 | METHOD AND APPARATUS FOR DIAGNOSING A MOTOR CONTROL CIRCUIT IN A HYBRID VEHICLE - A hybrid electric vehicle (HEV) has an algorithm for executing a method for diagnosing a high-voltage (HV) fault condition aboard the HEV. The HEV includes a high-voltage (HV) battery, an auxiliary power module (APM), a power inverter module (PIM), and a three-phase motor/generator unit (MGU). A controller executes the method to thereby measure a DC output current from the HV battery, a DC inlet current into the APM, and a pair of AC phase currents in the MGU. The method further includes calculating a DC inlet current into the PIM using the AC phase currents, diagnosing the HV fault condition using the DC output currents and the DC inlet currents, and executing a control action in response to the diagnosed condition. The method can include shutting off the APM to determine whether the APM is the root cause of the HV fault condition. | 2010-08-26 |
20100213949 | Electrical Interconnect Status Monitoring System - Disclosed are advances in the arts with novel methods and apparatus for detecting faulty connections in an electrical system. Exemplary preferred embodiments include basic, ASIC, AC, DC, and RF monitoring techniques and systems for monitoring signals at one or more device loads and analyzing the monitored signals for determining fault conditions at the device loads and/or at the main transmission lines. The invention preferably provides the capability to test and monitor electrical interconnections without fully activating the host system. | 2010-08-26 |
20100213950 | SYSTEM IN PACKAGE BATCH TEST METHOD AND BATCH TEST SYSTEM THEREOF - A system in package (SIP) batch test method and an SIP batch test system are applicable to an unpartitioned circuit module having a plurality of devices under test (DUTs). The circuit module is loaded in a loading module of the batch test system after probing test and molding operations. A test module of the batch test system is electrically coupled to at least two DUTs. At least two testers provide two different signal tests. A signal transmission controller controls signal transmission paths between the testers and the test module. A test controller controls the two testers and the test module to test the electrically coupled DUTs in parallel and record test results of the DUTs in configuration data. Finally, the circuit module is partitioned, so as to classify the DUTs according to the test results. | 2010-08-26 |
20100213951 | METHOD AND SYSTEM FOR DETECTION OF TAMPERING RELATED TO REVERSE ENGINEERING - A sensor system for protecting products and technology from reverse engineering by detecting attempts to probe electronic circuitry includes a sensor electrically linked to electronic circuitry. The sensor detects interaction of probe devices with the electronic circuitry for the purpose of reverse engineering the electronic circuitry. The sensor includes an exciter and an impedance counter linked to the exciter. A count rate of the impedance counter is a function of the impedance of the electronic circuitry due to the fact that oscillation frequency generated by the exciter is also a function of the impedance of the electronic circuitry. The sensor also includes an impedance register storing the binary count value from the impedance counter, wherein after the impedance counter data is transferred into the impedance register, the data is referred to as impedance data. The sensor also includes a reference oscillator monitoring count rate of the impedance counter and a sensor evaluation system comparing the impedance value to threshold values to determine if a significant change has occurred. When changes have occurred this is indicative of abnormal behavior and may be indicative of tampering relating to the evaluation of the electronic circuit for the purpose of reverse engineering. | 2010-08-26 |
20100213952 | Methods and Apparatuses for Determining Charging Current in Electrical Power Systems - A method and apparatus are disclosed for determining a system charging current in an electrical power system having three phases, a ground, a neutral, and a neutral resistor electrically coupling the neutral to the ground. The method comprises: measuring a line voltage of each phase; measuring a line-to-neutral voltage of each phase; determining a charging capacitance of each phase based on the line voltage of each phase, the line-to-neutral voltage of each phase, a frequency of the electrical power system, and a value of the neutral resistor; determining a phase charging current for each phase of the electrical power system based on the charging capacitance of each phase, the line voltage of each phase, and the frequency of the electrical power system; and determining the system charging current based on the phase charging current for each phase. | 2010-08-26 |
20100213953 | METHODS AND APPARATUS RELATING TO FLUIDISED BEDS - A method and apparatus for producing particle density map images of fluidised particles by electrical capacitance tomography (ECT) in a fluidised bed apparatus allows for measuring online the liquid content of fluidised particles during the fluidisation process and for recalibration of the fluidised particle permittivity during fluidisation, allowing for online recalibration of an ECT system when the liquid content of particles changes, such as for fluidised bed drying or granulation processes. Recalibration measurements are made using reference electrodes positioned to measure the capacitance of the densely fluidised particles near the side walls of the fluidised bed. The electrodes of an ECT sensor array may be used to make the recalibration measurements which can be used to provide online liquid content measurement, such as moisture content, for the fluidised particles without stopping out stopping fluidisation. The liquid content information may be used for process control. The method may also be used to provide separate images for solids distribution and for total liquid distribution across a plane being imaged. | 2010-08-26 |
20100213954 | CARBON NANOTUBE ARRAY SENSOR - A carbon nanotube array sensor includes a first electrode, a second electrode, a carbon nanotube array, at least one first conductive metal layer, at least one second conductive metal layer, a first metallophilic layer, and a second metallophilic layer. The carbon nanotube array is located between the first and second electrodes. The carbon nanotube array includes a number of carbon nanotubes. Each of the carbon nanotubes includes a first end and a second end opposite to the first end. The first metallophilic layer is located on the first end of each of the carbon nanotubes and electrically connected to the first conductive metal layer. The second metallophilic layer is located on the second end of each of the carbon nanotubes and electrically connected to the second conductive metal layer. | 2010-08-26 |
20100213955 | Method and device for monitoring and detecting the coating defects of underground or underwater pipelines - The invention relates to a method and device for monitoring and detecting coating defects ( | 2010-08-26 |
20100213956 | PROBE FOR CURRENT TEST, PROBE ASSEMBLY AND PRODUCTION METHOD THEREOF - A probe for current test comprising: a probe body having a plate-like connection portion whose end face becomes a connection face to a probe board; a solder layer formed on at least one side face of said connection portion; and a guide portion formed on the connection portion, penetrating the connection portion in its thickness direction from the one side face with the solder layer formed to the other side face, and when the solder layer is melted, capable of guiding a portion thereof to the other side face. | 2010-08-26 |
20100213957 | APPARATUS FOR TESTING ELECTRONIC DEVICES - An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer. | 2010-08-26 |
20100213958 | SYSTEMS AND METHODS FOR PROVIDING A SYSTEM-ON-A-SUBSTRATE - This relates to systems and methods for providing a system-on-a-substrate. In some embodiments, the necessary components for an entire system (e.g., a processor, memory, accelerometers, I/O circuitry, or any other suitable components) can be fabricated on a single microchip in “bare die” form. The die can, for example, be coupled to suitable flash memory through a substrate and flexible printed circuit board (“flex”). In some embodiments, the flex can extend past the substrate, die, or both, to allow additional, relatively large components to be coupled to the flex. In some embodiments, the die can be coupled to the flash memory through the flex and without a substrate. In some embodiments, component test points can be placed on the flash memory side of the substrate. | 2010-08-26 |
20100213959 | Test section unit, test head and electronic device testing apparatus - A test section unit provided to a test head body includes a plurality of sockets to be attached with electronic devices to be tested and a performance board as a main substrate. All of the sockets are provided with the performance board without an intervening a socket board. | 2010-08-26 |
20100213960 | Probe Card Test Apparatus And Method - A probe card analyzer mounts on a probe card in a wafer prober and a use a fixture in the wafer probe and switch electronics in place of an ATE head. Methods of testing can confirm that probe cards are operating within their specifications over large temperature ranges and the mechanical force ranges seen in real manufacturing environments. This reduces the cost and improves the accuracy and speed of analyzing probe cards and improves diagnosing problems with probe cards. | 2010-08-26 |
20100213961 | Multi-Position Probe Circuit Tester - A circuit tester having a multi-position probe is provided. The circuit tester includes a handle with a detent assembly that allows for positioning the probe at various angles for testing a device. Once a good connection is made with the device under test, an indicator such as a light is lit or a sound is emanated. The probe may be folded into a compartment within the handle once the testing is completed. | 2010-08-26 |
20100213962 | BALLAST AND WIRING LAMP FIXTURE TESTER - Apparatus and methods for testing a light fixture power circuit are therefore provided. The light fixture power circuit may energize a fluorescent lamp by providing power at first and second power terminals. The lamp holder may include a lamp pin guide for guiding the tube's contact pins toward the first and second power terminals. The apparatus may have probes that simulate the tube's contact pins. The probes may be robotically inserted into the lamp holder in a manner that is similar to the manner in which the contact pins would be inserted. This may eliminate the requirement to use fluorescent tubes to test the light fixture power circuit. The apparatus may include circuitry for testing the impedance of the light fixture power circuit at the first and second power contacts. | 2010-08-26 |
20100213963 | SEMICONDUCTOR INTEGRATED CIRCUIT TEST METHOD - A wafer of semiconductor integrated circuits with wafer-level chip-scale packages is tested in two stages. The chip-scale packages include conductive posts extending through a sealing layer and capped by terminals. Measurements strongly affected by contact resistance are carried out before the terminals are formed, using a first probe card having probe pins that contact the ends of the conductive posts. Other measurements are carried out after the terminals are formed, using a second probe card having probe pins that contact the terminals. Accurate measurements can be made in this way even if the terminals are lead-free solder bumps with variable contact resistance. Fabrication yields are improved accordingly. | 2010-08-26 |
20100213964 | TIMER UNIT, SYSTEM, COMPUTER PROGRAM PRODUCT AND METHOD FOR TESTING A LOGIC CIRCUIT - A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit. The system has a mode control unit containing a set of instructions which is executable by the logic circuit, for switching the logic circuit from and to a test mode in which a part of the logic circuit can be subjected to a selected test by executing a selected test routine. | 2010-08-26 |
20100213965 | METHOD AND APPARATUS OF TESTING DIE TO DIE INTERCONNECTION FOR SYSTEM IN PACKAGE - Method and apparatus of testing die to die interconnection for system in package (SiP). For testing a die to die interconnection connected between two pads of two dice, an IO buffer, e.g., a bi-directional IO buffer, in one of the two dice coupled to one of the two pads is arranged. An oscillating feedback is formed between an output port and an input port of the IO buffer, such that a state, e.g., an open state, a short state or a normal state of the die to die interconnection is tested according to a timing characteristic, e.g., a frequency, of a signal of the IO buffer. | 2010-08-26 |
20100213966 | Comparator with latching function - A comparison amplification unit compares a level of a signal in a positive line with that of a signal in a negative line and latches a comparison result. An input terminal of a first inverter is connected to the positive line and an output terminal thereof is connected to the negative line. An input terminal of a second inverter is connected to the negative line and an output terminal thereof is connected to the positive line. An activation switch selectively switches between a state where the activation switch outputs a power supply voltage to the other power supply terminals of the inverters that are connected in common, such that the comparison amplification unit is inactivated, and a state where the activation switch outputs the ground voltage such that the comparison amplification is activated. The comparator outputs a signal corresponding to at least one of the signal in the positive line and the signal in the negative line at a timing after the comparison amplification unit is activated. | 2010-08-26 |
20100213967 | TEST APPARATUS - A test apparatus is configured such that two adjacent channels form a pair. Timing comparators determine the level of first output data fed from a DUT, respectively, timed in accordance with strobe signals, respectively. Clock envelope extractors extract envelopes of a clock, respectively. A clock recovery circuit recovers a strobe signal. A first main latch latches an output from the first timing comparator, timed by the first strobe signal. A first sub-latch latches the envelope of the clock, timed by the first strobe signal. An output from the sub-latch is supplied to a second main latch of the second channel. A signal dependent on the strobe signal is assigned an adjustable delay by a first delay circuit and is supplied to a clock terminal of the second main latch. | 2010-08-26 |
20100213968 | TESTING INTEGRATED CIRCUITS - A test insert for an integrated circuit according to the present invention comprises access contacts and an electrical path. Furthermore, there may be additional access contacts and a plurality of different electrical paths. The electrical path is comprised of a plurality of tracks, each track provided at a single layer of the integrated circuit and connected to the other tracks by interconnecting vias. The vias provide interlayer contacts and thus allow the tracks to be connected into a single electrical track. In one embodiment, an access contact is connected to ground; another contact is connected to a reference voltage; and connected to various points in the electrical path are transistor-resistor pairs. The transistor-resistor pairs are in connected between earth and a third access contact. If the electrical path is intact at the track connected to a transistor-resistor pair, a current can flow between contact and the respective earth of the transistor-resistor pair. By analysing the current drawn from contact it can be deduced whether the path is operational as a whole and if not, how far along the path a fault lies. This can therefore isolate a particular interconnection between layers or a particular layer as being faulty. | 2010-08-26 |
20100213969 | LIQUID CRYSTAL DISPLAY AND TEST METHOD THEREOF - A liquid crystal display includes a plurality of pixel electrodes arranged in a matrix and having first and second sub-pixel electrodes differentiated in size from each other. First and second switching elements are connected to the first and second sub-pixel electrodes, respectively. First and second gate lines are connected to the first and second switching elements, respectively. A data line is connected to the first and second switching elements to transmit a data voltage. First and second gate shorting bars are connected to the first and second gate lines, respectively. The gate lines connected to the respective sub-pixels are connected to two or four gate shorting bars to allow an array test and a visual inspection test, and to thereby detect a bridge between respective sub-pixel electrode neighbors in a simplified manner. | 2010-08-26 |
20100213970 | Semiconductor integrated circuit and method for testing the same - A semiconductor integrated circuit includes a plurality of clock gating circuits, a plurality of flip-flops to which transmission of a clock signal is controlled by a respective clock gating circuit, and a clock gating control circuit that controls an active state and an inactive state of the plurality of clock gating circuits, wherein during a test operation mode, the clock gating control circuit controlling the active state and the inactive state of the plurality of clock gating circuits according to a user logic signal, and controlling setting of an arbitrary combination of clock gating circuits to an inactive state regardless of the user logic signal. | 2010-08-26 |
20100213971 | PSEUDO-DIFFERENTIAL INTERFACING DEVICE HAVING A SWITCHING CIRCUIT - The invention relates to an interfacing device for pseudo-differential transmission through interconnections used for sending a plurality of electrical signals. The interfacing device of the invention includes signal terminals and a common terminal. A transmitting circuit receives the input signals of the transmitting circuit coming from a source. The output of the transmitting circuit delivers, when the transmitting circuit is in the activated state, voltages between one of the signal terminals and the reference terminal (ground). A receiving circuit delivers, when the receiving circuit is in the activated state, output signals of the receiving circuit determined each by the voltage between one of the signal terminals and the common terminal, to the destination. In the closed state, the common terminal switching circuit is, for the common terminal, equivalent to a voltage source delivering a constant voltage, connected in series with a passive two-terminal circuit element presenting a low impedance. | 2010-08-26 |
20100213972 | DEVICES AND METHODS FOR DRIVING A SIGNAL OFF AN INTEGRATED CIRCUIT - Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output of the differential driver circuitry is coupled to an externally-accessible output terminal of the package. The other output may be terminated off the chip, but within the package. By routing the output signal and a second complementary output through the package, crosstalk potentially caused by the output signal can be reduced. Simultaneous switching output noise may also be reduced through use of a current-steering differential driver topology. Signal symmetry may also improve, reducing inter-symbol interference. | 2010-08-26 |
20100213973 | Status holding circuit and status holding method - A status holding circuit includes status holding sections of M stages (M is an integer equal to or more than 2) connected in series. Each of the status holding sections includes: N latches (N is an integer equal to or more than 2) provided for N input signals to N input terminals, respectively; and a switch circuit configured to set a data to a j | 2010-08-26 |
20100213974 | Method and apparatus for camouflaging a printed circuit board - A method, apparatus, article of manufacture, and a memory structure for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic cells. In one embodiment, the method comprises the steps of identifying at least one gap between the plurality of interconnected functional logic cells having no functional logic therein, placing one filler cell or combination of filler cells into the identified gap and defining a routing of the placed filler cells. | 2010-08-26 |
20100213975 | COMBINED PROCESSING AND NON-VOLATILE MEMORY UNIT ARRAY - A reconfigurable logic device comprises an array of tiles interconnected through a routing network, each tile comprises both a processing unit including volatile configuration memory and a Random Access Memory unit. | 2010-08-26 |
20100213976 | Hierarchical FPGA configuration - A system for configuring programmable logic devices includes a serial data bus, a first device to fan-out data signals on the serial data bus, a second device to fan-in data signals on the serial data bus, and a control device that uses the first device and the second device to configure the serial data bus. The system configures a set of programmable logic devices by using the control device to configure the serial data bus such that the set of programmable logic devices are in communication with the serial data bus, and by sending configuration information to the set of programmable logic devices. A method for configuring programmable logic devices includes configuring a first programmable logic device such that the first programmable logic device includes signaling logic to fan-out configuration information, and using the first programmable logic device to configure at least two secondary programmable logic devices in parallel using the signaling logic to fan-out configuration information. | 2010-08-26 |
20100213977 | USERS REGISTERS IMPLEMENTED WITH ROUTING CIRCUITS IN A CONFIGURABLE IC - Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used. | 2010-08-26 |
20100213978 | LOW POWER RECONFIGURABLE CIRCUITS WITH DELAY COMPENSATION - According to one aspect of the present disclosure, a circuit includes a semiconductor device including a plurality of logic blocks and a plurality of programmable interconnects. A delay detector generates a delay signal responsive to a measured delay of an output signal, wherein the output signal is from at least one of the plurality of logic blocks. A biasing circuit responsive to the delay signal to adjust subsequent measured delays toward a predetermined value. | 2010-08-26 |
20100213979 | SEMICONDUCTOR DEVICE AND METHOD FOR LAYOUTING SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a first circuit provided between a power source voltage line and a ground line, including at least two first MOS transistors coupled in parallel and a second circuit, which is provided between the power source voltage line and the ground line, including at least two second MOS transistors coupled in series. The gate length and the gate width of the first MOS transistor are adjusted so that the first MOS transistor has a gate area allowing a first characteristic variation of the first MOS transistor to be substantially equal to a second characteristic variation of the second MOS transistor. | 2010-08-26 |
20100213980 | ARCHITECTURE FOR EFFICIENT USAGE OF IO - An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level. | 2010-08-26 |
20100213981 | DOMINO LOGIC BLOCK HAVING DATA HOLDING FUNCTION AND DOMINO LOGIC INCLUDING THE DOMINO LOGIC BLOCK - The domino logic of the general inventive concept receives a feedback signal and an input signal and outputs any one of the feedback signal and the input signal as an output signal in response to an enable signal and a clock signal. The feedback signal is an output signal of a previous cycle of a clock signal. When an enable signal is a first level, the domino logic maintains an output signal of a previous cycle instead of an input signal. According to the present general inventive concept, the domino logic having a data hold function can be embodied. | 2010-08-26 |
20100213982 | METHOD AND SYSTEM FOR DISTRIBUTING CLOCK SIGNALS ON NON MANHATTAN SEMICONDUCTOR INTEGRATED CIRCUITS - The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transforming the coordinates system such that a rotated recursive H clock signal structure is rendered. In another embodiment, a recursive Y structure is used to create a clock signal structure. The recursive Y structure may also be implemented in a rotated alignment. For clock signal redundancy, non Manhattan wiring may be used to create a clock signal mesh network. | 2010-08-26 |
20100213983 | AMPLIFIERS WITH INPUT OFFSET TRIM AND METHODS - Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed. | 2010-08-26 |
20100213984 | AUTOMATIC FREQUENCY CALIBRATION APPARATUS AND METHOD FOR A PHASE-LOCKED LOOP BASED FREQUENCY SYNTHESIZER - An automatic frequency calibration apparatus and a method thereof for a phase-locked loop based frequency synthesizer are disclosed. The apparatus includes a frequency-to-digital converter configured to convert a frequency of a VCO output signal to a first digital value, a target value setting section configured to provide a second digital value corresponding to a target frequency, and a finite state machine configured to calibrate the frequency of the VCO output signal by using the difference of the first digital value and the second digital value. Accordingly, the calibration speed and a frequency resolution of the automatic frequency calibration apparatus in a frequency synthesizer may be enhanced. | 2010-08-26 |
20100213985 | FAST COMMON MODE FEEDBACK CONTROL FOR DIFFERENTIAL DRIVER - A system and method for a fast stabilizing output buffer. A differential driver circuit is provided with an amplifier stage for receiving a differential input signal and generating a differential output based upon the input signal. The differential output has a corresponding common-mode (CM) voltage level typically based upon a value half of the power supply. A common-mode feedback buffer (CMFB) stage detects a change in the CM voltage level and recovers the CM voltage level to its desired value within a very fast settling time based upon a very high bus frequency. The CMFB stage utilizes a topology comprising only a single device. In one embodiment, this single device is a nmos transistor utilized as a transimpedance stage. Stability is provided by a circuit biasing stage and a shunting capacitor within the CMFB stage. | 2010-08-26 |
20100213986 | CLOCK BUFFER - An apparatus is provided. The apparatus comprises a first bipolar junction transistor (BJT) differential pair having a first BJT and a second BJT, a second BJT differential pair having a third BJT and a fourth BJT, a first clamp having a fifth BJT and a sixth BJT, and a second clamp having a seventh BJT and an eighth BJT. The collector and base of the third BJT are respectively coupled to the collector and base of the first BJT, and the collector and base of the fourth BJT are respectively coupled to the collector and base of the second BJT. The bases of first, second, third, and fourth BJTs receive an input clock signal. The emitters of the fifth and sixth BJTs are coupled to the collectors of the first and third BJTs, while the emitters of the seventh and eight BJTs are coupled to the collectors of the second and fourth BJTs. The bases of the fifth and seventh BJT are adapted to receive a low clamping voltage, and the bases of the sixth and eighth BJTs are adapted to receive a high clamping voltage. Additionally, the first and second clamps is coupled to the collectors of the first, second, third, and fourth BJTs. | 2010-08-26 |
20100213987 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD FOR THE SAME - A semiconductor device includes an element to be protected formed on a semiconductor substrate, a first protection transistor, and a second protection transistor. The first protection transistor is formed on a first well of a first conductivity type formed in an upper portion of a deep well of a second conductivity type. The second protection transistor is formed on a second well of the second conductivity type. A second source/drain diffusion layer is electrically connected with a third source/drain diffusion layer and at the same potential as the first well. A fourth source/drain diffusion layer is electrically connected with a second diffusion layer and at the same potential as the second well and the second diffusion layer. | 2010-08-26 |
20100213988 | DRIVING CIRCUIT OF SWITCH DEVICE - The present invention relates to a driving circuit of switch device. The present invention employs transformer isolated driving. The number of said transformers is two. The primary sides of the two transformers are connected to two driving modulators, respectively. The input terminal of a high frequency carrier signal and the input terminal of a driving signal are connected to the input terminal of a first driving modulator. The input terminal of a driving signal being connected with an inverter together with the input terminal of the high frequency carrier signal are connected to the input terminal of a second driving modulator. The first secondary side of the first transformer is connected to a power supply circuit which may provide a necessary voltage for turning on the switch device during a high level period of the driving signal. The first secondary side of a second transformer is connected to a voltage discharging circuit which may discharge a turn-on voltage of the switch device into a low level during a low level period of the driving signal. Therefore, the pair transistor amplification circuit in the existing transformer isolated driving becomes unnecessary, which provides a high driving power. In addition, employing no optical coupler isolated element makes the working life even longer. | 2010-08-26 |
20100213989 | GATE DRIVING CIRCUIT - To obtain a gate driving circuit in which rising of a constant current of a constant current circuit is fast and power saving is achieved, the gate driving circuit includes: a constant current driving circuit ( | 2010-08-26 |
20100213990 | HIGH FREQUENCY POWER SWITCHING CIRCUIT WITH ADJUSTABLE DRIVE CURRENT - A MOSFET pre-driver circuit with highly adjustable drive current for a high frequency switching power MOSFET circuit decreases the peak of the drive current and power loss of the pre-driver while maintaining power loss of the power stage so that total power loss is decreased and circuit efficiency is increased. A resistor arranged in series with a source of the MOSFET of the pre-driver circuit is provided to adjust the drive current. | 2010-08-26 |
20100213991 | DELAY-LOCKED LOOP CIRCUIT AND METHOD FOR SYNCHRONIZATION BY DELAY-LOCKED LOOP - A delay-locked loop circuit has an adjustment period setting module configured to set a rough adjustment period and a fine adjustment period, a delay time adjustment module configured to increase or decrease a delay stage by a first unit or by a second unit based on a delay stages setting value to generate a second signal by delaying a first signal, a delay module configured to generate a third signal by delaying the second signal by a predetermined time, a phase comparator configured to detect a phase difference between the first signal and the third signal, and a delay controller configured to generate the delay stages setting value based on the phase difference in order to increase or decrease the number of delay stages by the first unit when the rough adjustment period is set and to increase or decrease the number of delay stages by the second unit when the fine adjustment period is set. | 2010-08-26 |
20100213992 | Delay locked loop circuit and operation method thereof - A delay locked loop (DLL) circuit includes an analog DLL core and a digital DLL core. The analog DLL core receives an input clock signal of a first operating frequency. The digital DLL core receives an input clock signal of a second operating frequency equal to or lower than the first frequency. The analog and digital DLL cores operate selectively. The DLL core also includes a selection circuit configured to select one of the first and second DLL cores. The selection circuit may operate in response to a detection signal from a frequency detector which detects the frequency of the input clock signal. The selection circuit may also operate in response to a column address strobe writing latency signal that indicates frequency information of the input clock signal. | 2010-08-26 |
20100213993 | Phase Locked Oscillator And Radar Unit Having The Same - An error detecting unit of a phase-locked oscillator evaluates difference between a reference phase error signal output from a phase detector and a phase error signal actually output from the phase detector when a reference frequency modulation signal is output from a voltage-controlled oscillator and further detects a frequency error of the frequency modulation signal from the voltage-controlled oscillator based on a rate of change of the difference. A correction unit of the phase-locked oscillator calculates an average value of the frequency error in a predetermined section of the frequency modulation signal and corrects center frequency of the frequency modulation signal by correcting the average value to be zero, and changes the rate of change of control voltage per control step based on comparison between at least two frequency errors in one cycle of the frequency modulation signal. Thus frequency shift of the frequency modulation signal is corrected. | 2010-08-26 |
20100213994 | Charge Pump for PLL/DLL - A charge pump for use in a Phase Locked Loop/Delay Locked Loop minimizes static phase error through the use of an operational amplifier. The operational amplifier also mitigates the effects of low power supply voltage. | 2010-08-26 |
20100213995 | DELAY LOCKED LOOP CIRCUIT AND CONTROL METHOD OF THE SAME - A delay locked loop capable of preventing delay locking time from being increased, even if the operational environment fluctuates. The delay locked loop circuit includes a delay line for delaying and outputting a reference clock signal, a phase detection unit for detecting a phase difference between the reference clock signal and an output signal of the delay line and then outputting a phase detection signal and a first delay mode decision signal, a control unit for outputting a delay control signal to control the delay line according to the phase detection signal and a second delay mode decision signal, and an error decision unit for detecting an error of the first delay mode decision signal according to the delay control signal and the output signal of the delay line and outputting the second delay mode decision signal according to a result of the error detection. | 2010-08-26 |
20100213996 | CIRCUIT BREAKER - A circuit breaker having break contacts for disconnecting an electric grid or network in a predetermined manner includes a trigger unit which triggers actuation of the break contacts in response to signals received from a detector which detects aperiodic, substantially step-like changes in the amplitude of at least one electric parameter in the electric network. The trigger unit is operatively connected with the detector. The disclosed circuit breaker reduces the likelihood of a fire caused by faults in electric networks. | 2010-08-26 |
20100213997 | Interpolation Accuracy Improvement in Motion Encoder Systems, Devices and Methods - Disclosed are various embodiments of interpolation circuits for use in conjunction with motion encoders. The analog output signals provided by incremental or absolute motion encoders are provided to an interpolation circuit, which is capable of providing high interpolation factor output signals having high timing accuracy. Problems with noise spikes common to zero-hysteresis comparators typically employed in interpolation circuits are eliminated, as are problems with time delays differing between comparators that do feature hysteresis. The disclosed interpolation circuits may be implemented using CMOS processes without undue effort. | 2010-08-26 |
20100213998 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device having: a latch circuit ( | 2010-08-26 |
20100213999 | Dynamic Element Matchinig for Delay Lines - This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching. | 2010-08-26 |
20100214000 | Systems and Methods for Driving High Power Stages Using Lower Voltage Processes - In today's environment class-D amplifiers are used to provide an integrated solution for applications such as powered audio devices due to their advantages in power consumption and size over more traditional analog amplifiers. Due to power output requirements, the output stages of power drivers such as class-D amplifiers require a supply voltage in excess of the technologically allowed voltage for the switches in the output stage. A level shifter is used to ensure voltages supplied to the output switches do not exceed the technological limits. An ideal level shifter should provide the optimal voltage swing to output switches under all process, supply voltage and temperature (PVT) variations. The ideal level shifter should also provide fast transitions when the control signal changes from high to low and low to high. | 2010-08-26 |
20100214001 | Level Shift Circuit - A level shift circuit includes an inverter, a shifting circuit, a first transistor, and a second transistor. The inverter inverts an original input signal into an inverted input signal. The shifting circuit generates a control signal according to the original input signal, the inverted input signal, and a reference voltage. The first transistor has a gate, a source, and a drain, in which the gate of the first transistor receives the control signal, and the source of the first transistor is connected to a high supply voltage. The second transistor has a gate, a source, and a drain, in which the gate of the second transistor receives the inverted input signal, the drain of the second transistor is connected to the drain of the first transistor, and the source of the second transistor is connected to a ground terminal or a low supply voltage. | 2010-08-26 |
20100214002 | SIGNAL LEVEL CONVERSION CIRCUIT - A signal level conversion circuit includes three or more level shift circuits to output internal output signals upon receiving input signals, respectively. Each of the level shift circuits is formed of a common electrical element and an electrical element connected to the common electrical element. A voltage higher than that supplied to the common electrical element is supplied to the electrical element. A buffer circuit having an input tolerant function is provided in each of the common electrical elements. The internal output signals are set at lower level than the input signals by the buffer circuits, and the internal output signal outputted from one of the level shift circuits is further outputted via other level shift circuits. | 2010-08-26 |
20100214003 | Signal Transformation Arrangement and Method for Signal Transformation - A signal transformation arrangement comprises a first input tap ( | 2010-08-26 |
20100214004 | ANALOG SWITCH CIRCUIT - An analog switch circuit that includes a first field-effect transistor, a source of which is coupled to a first switch terminal, and a drain of which is coupled to a second switch terminal; a first capacitance storing electric charge; a second capacitance storing electric charge; a first switch circuit that couples the first capacitance between a direct current voltage node and a reference potential node; a second switch circuit that couples the first capacitance and the second capacitance in parallel; and a third switch circuit that couples the second capacitance between a gate and the source of the first field-effect transistor. | 2010-08-26 |
20100214005 | Power Switches Having Positive-Channel High Dielectric Constant Insulated Gate Field Effect Transistors - Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit to switch power to the functional circuit on and off. The power switch unit may include a large number of transistors coupled together. The transistors may include predominantly positive-channel, insulated gate field effect transistors, which have a gate dielectric that includes a high dielectric constant material. Power switch units having such transistors may tend to have low power consumption. In an aspect, an overdrive voltage may be applied to the gates of such transistors to further reduce power consumption. Methods of overdriving such transistors and systems including such power switch units are also disclosed. | 2010-08-26 |
20100214006 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - There is provided a circuit whose output is free from high impedance to improve wrong transmission and waveform overshoot, realizing a semiconductor integrated circuit device in which plural channels is integrated with transmitter circuit as unit channel, in the transmitter circuit used in a medical ultrasound system and drives a transducer by voltage pulses having plural positive and negative electric potentials including ground potential. The transmitter circuit includes a conventional pulse generating circuit supplied with positive and negative voltage largest in absolute value, a P-channel analog switching pulse generating circuit supplied with positive voltage being the second largest therein, an N-channel analog switching pulse generating circuit supplied with negative voltage being the second largest, and an N-channel analog switching ground level damping circuit supplied with ground potential. The circuits are connected to output terminal. Switch control signals drive ultrasound transducers by turning on and off the circuits. | 2010-08-26 |
20100214007 | MICROPROCESSOR PERFORMANCE IMPROVEMENT BY DYNAMIC NBTI COMPENSATION THROUGH TRANSISTOR FORWARD BIASING - A method for compensating negative bias temperature instability (NBTI) effects on a given model of transistors includes monitoring the NBTI effects on the transistors over time, determining a change in a threshold voltage of the transistors over time based on the monitoring, determining a forward bias voltage based on the change in threshold voltage, and applying the forward bias voltage to the transistors over time. The method may further include storing the monitoring results in a lookup table, and adjusting the forward bias voltage based on the lookup table. The monitoring may include emulating the NBTI effects on a system comprising a plurality of semiconductor devices in which the transistors are used. | 2010-08-26 |
20100214008 | SEMICONDUCTOR DEVICE WITH TRANSISTOR-BASED FUSES AND RELATED PROGRAMMING METHOD - A method of programming a transistor-based fuse structure is provided. The fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer. | 2010-08-26 |
20100214009 | METHOD FOR DIGITAL PROGRAMMABLE OPTIMIZATION OF MIXED-SIGNAL CIRCUITS - A method for digital programmable optimization of a mixed-signal circuit is provided. The method comprises dividing up one or more transistor devices of the mixed-signal circuit into one or more transistor segments, with each transistor segment including a body tie bias terminal. Each body tie bias terminal is coupled to at least one voltage bias, either by placing each body tie bias terminal in signal communication with one or more bias nodes in the mixed-signal circuit, or by placing each body tie bias terminal in signal communication with a non-precision bias voltage source. Each body tie terminal is also arranged to be in signal communication with a separate one of one or more digital programmable storage elements. | 2010-08-26 |