34th week of 2011 patent applcation highlights part 20 |
Patent application number | Title | Published |
20110204928 | DISPLAY DEVICE, SEMICONDUCTOR DEVICE, AND DRIVING METHOD THEREOF - An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor. | 2011-08-25 |
20110204929 | DRIVE CIRCUIT OF POWER SEMICONDUCTOR DEVICE - In order to obtain a drive circuit of a power semiconductor device capable of making a fast response to a voltage fluctuation dV/dt and preventing a malfunction of the power semiconductor device while suppressing power consumption with a simple circuit configuration, a control circuit controlling ON and OFF switching of the power semiconductor device, a DC power supply supplying a voltage between control terminals of the power semiconductor device, and a switching element connected between the control terminals of the power semiconductor device are provided. The switching element turns ON in a case where a power supply voltage of the DC power supply drops or in a case where the voltage between the control terminals of the power supply device increases in a state where the power supply voltage of the DC power supply has dropped, and thereby causes a short-circuit between the control terminals of the power semiconductor device. | 2011-08-25 |
20110204930 | SOURCE FOLLOWER INPUT BUFFER - Traditionally, input source follower buffers for analog-to-digital converters (ADCs) lacked sufficiently high linearity. This was due in part to source follower buffers having to drive external capacitive loads by generally providing a signal current to the capacitive load. Here, a buffer is provided that includes a source follower buffer and other biasing circuitry (which provided the signal current). Thus, the overall linearity of the input circuitry (namely, the input buffer) is improved. | 2011-08-25 |
20110204931 | PEAK POWER REDUCTION METHODS IN DISTRIBUTED CHARGE PUMP SYSTEMS - A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage. | 2011-08-25 |
20110204932 | Asynchronous Scheme for Clock Domain Crossing - Apparatus and methods for clock domain crossing between a first clock domain and a second clock domain. The apparatus comprises a first control logic element for processing a handshake signal and producing a first arbiter input signal. Concurrently a second control logic element processes a second handshake signal and produces a second arbiter input signal. Exemplary embodiments include exactly one arbiter element inputting the first arbiter input signal, inputting the second arbiter input signal, outputting a first clocking signal to the first sequential element and outputting a second clocking signal to the second sequential element. For managing metastability by controlling the timing of the clocking inputs of the sequential devices, the apparatus includes a first controllable lock delay element selected to satisfy the setup constraint of the second sequential element, and a second controllable lock delay element selected to satisfy the hold constraint of the second sequential element. | 2011-08-25 |
20110204933 | ELECTRIC CIRCUIT AND SIGNAL PROCESSING METHOD - An electric circuit includes a first circuit, a second circuit, a synchronization detection circuit, a storage circuit, and a correction circuit. The first clock is configured to operate with a first clock, the second circuit is configured to operate with a second clock which is different in frequency from the first clock, and the synchronization detection circuit is configured to detect synchronization of the first and second clocks. The storage circuit is configured to store an output noise pattern of the second circuit, based on the synchronization detected by the synchronization detection circuit, and the correction circuit is configured to correct an output of the second circuit by using the output noise pattern. | 2011-08-25 |
20110204934 | SYSTEM, APPARATUS AND METHOD FOR CALIBRATING A DELAY ALONG A SIGNAL PATH - The present disclosure teaches a calibration system, a calibration apparatus and a method for calibrating a signal path and a method for calibrating a delay. The calibration system comprises an injector, a calibration signal generator, a correlator, a detector unit, a polygon former and a pattern classifier unit. The calibration system is adapted to calculate a fraction of a delay from a set of polygons. The delay is being accumulated along a signal path. The fraction of the delay is indicative of an accuracy of the delay at a fine sampling rate as if the delay was measured at the fine sampling rate being an integer multiple of the coarse sampling rate. The method for calibrating of the signal path uses a calibration signal sampled at a coarse sampling rate. Correlation techniques are used in order to detect a fraction of the delay from a set of polygons. | 2011-08-25 |
20110204935 | PLL circuit - Provided is a PLL circuit improving reliability while suppressing power consumption without degrading noise characteristics. The PLL circuit includes a PLL IC that divides an output frequency Fout from a VCO, compares phase with a reference signal, and feeds back a phase difference as a control voltage to the VCO. A control circuit is capable of finely setting both of a reference frequency Fref and an output frequency Fdds in a DDS circuit, and the DDS circuit generates folding signals of Fdds for Fref and an integral multiple frequency thereof based on the combination of the frequencies. A first AMP amplifies a signal, a variable filter selects a desired Fdds (desired) and a second AMP amplifies the signal and supplies the same to the PLL IC as a reference signal. The control circuit further supplies a division ratio N to the PLL IC. | 2011-08-25 |
20110204936 | APPARATUS AND METHODS FOR REDUCING NOISE IN OSCILLATING SIGNALS - Methods and apparatus are described for reducing noise, such as phase noise, in an oscillating signal. The oscillating signal may be generated by a signal generator having a mechanical resonator, such as a crystal oscillator. A filter may be coupled to the output of the mechanical resonator and may have its center frequency adjusted using a phase-locked loop (PLL). A feedback signal from the filter to the signal generator may also be used. | 2011-08-25 |
20110204937 | PHASE- LOCKED LOOP WITH SWITCHED PHASE DETECTORS - A phase-locked loop includes: a voltage-controlled oscillator (VCO) system receiving one or more control signals and in response thereto generating a PLL output signal; a plurality of phase detectors for comparing a reference signal having a reference frequency to a PLL feedback signal having a PLL feedback frequency derived from the PLL output signal, and in response thereto to output a comparison signal; and a plurality of signal processing paths each connected to an output of a corresponding one of the phase detectors for outputting a phase detection output signal. The signal processing paths have different frequency responses from each other. In operation only one of the phase detectors is activated, and a switching arrangement selectively switches between outputs of the signal processing paths to select the phase detection output signal from the activated phase detector to generate the control signal(s) for the VCO system. | 2011-08-25 |
20110204938 | Charge Pump For a Phase-Locked Loop - A charge pump circuit for connection to another circuit via an output node ( | 2011-08-25 |
20110204939 | Circuit for Clamping Current in a Charge Pump - A circuit for clamping current in a charge pump is disclosed. The charge pump includes switching circuitry having a number of switching circuitry transistors. Each of first and second pairs of transistors in the circuit can provide an additional path for current from its associated one of the switching circuitry transistors during off-switching of that transistor so that a spike in current from the switching circuitry transistor is only partially transmitted through a path extending between the switching circuitry transistor and a capacitor of the charge pump. | 2011-08-25 |
20110204940 | CLOCK GENERATOR, SEMICONDUCTOR DEVICE, AND CLOCK GENERATING METHOD - There is provided a clock generator for generating a modulation waveform which is high in the effect of suppressing a spectrum and making a circuit scale smaller than a modulation system using the Hershey-kiss waveform. More specifically, a modulation waveform generation unit generates a tangent waveform or a tangent+triangular waveform as an SSCG modulation waveform and provides an oscillator with a signal in which the SSCG modulation waveform is combined with the output of a low pass filter of a PLL loop. | 2011-08-25 |
20110204941 | DELAY LOCKED LOOP SEMICONDUCTOR APPARATUS THAT MODELS A DELAY OF AN INTERNAL CLOCK PATH - A delay locked loop semiconductor apparatus that models a delay of an internal clock path is presented. The semiconductor apparatus includes: a DLL and a detection code output block. The DLL includes a delay model unit in which a delay value of an internal clock path is modeled and is configured to output a DLL clock signal of which the phase is controlled by reflecting the delay value of the internal clock path into an applied input clock signal. The detection code output block is configured to output a phase difference detection code having a code value corresponding to a phase difference between a first phase correction clock signal generated by reflecting a model delay value of the delay model unit into the DLL clock signal and a second phase correction clock signal generated by reflecting an actual delay value of the internal clock path into the DLL clock signal. | 2011-08-25 |
20110204942 | CLOCK CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A clock control circuit includes: a phase determination circuit that generates a phase determination signal based on a phase of an external clock signal; a counter circuit having a count value updated based on a logic level of the phase determination signal; a delay line that generates an internal clock signal by delaying the external clock signal based on the count value; and a pitch adjustment circuit that sets an update pitch of the counter circuit to be twice as high as a minimum pitch in a period in which the phase determination signal has no change, and sets the update pitch of the counter circuit to the minimum pitch in response to a change in the phase determination signal. With this configuration, it is possible to realize quick and highly accurate locking of a DLL circuit. | 2011-08-25 |
20110204943 | DELAY CELL AND PHASE LOCKED LOOP USING THE SAME - A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock. | 2011-08-25 |
20110204944 | DIGITAL LOCK DETECTOR AND FREQUENCY SYNTHESIZER USING THE SAME - There is provided a digital lock detector and a frequency synthesizer using the same. The digital lock detector includes a comparator unit receiving a plurality of control bits, and generating a bit signal to notice a lock condition of the plurality of control bits; a delay cell block generating a plurality of delay signals based on the bit signal, and outputting a clock signal by combining the bit signal and the plurality of delay signals; and a detection unit detecting a shift time of the clock signal, and generating a lock indication signal according to the detection result. | 2011-08-25 |
20110204945 | CALIBRATION - A method of calibrating a module whose operation is dependent upon a module clock signal, the method comprising: over each calibration period of a plurality of such periods, obtaining a measure of the frequency of an observed signal, the observed signal being the module clock signal or a clock signal generated based upon the module clock signal; influencing operation of the module in dependence upon the obtained measures so as to calibrate the module; and for each said calibration period, taking account of a position in time of the end of that calibration period relative to a particular feature of the observed signal and delaying the start of the following calibration period relative to a subsequent said particular feature of the observed signal in dependence upon that position. | 2011-08-25 |
20110204946 | SYSTEM AND METHOD FOR SYNCHRONIZING ASYNCHRONOUS SIGNALS WITHOUT EXTERNAL CLOCK - One or more techniques are provided for the synchronization of asynchronous signals without the use of an external system clock. In one embodiment, an asynchronous synchronization device is provided and configured to synchronize one or more asynchronous signals to an internal clock signal provided by an internal clock generator. The internal clock generator may be enabled upon detecting inputs on the one or more asynchronous signals, and disabled once the one or more asynchronous inputs are synchronized with the internal clock signal. Thus, the internal clock signal is provided only for a duration required to synchronize the one or more asynchronous signals. Embodiments of the asynchronous synchronization device, as disclosed herein, may be implemented in a processor-based device and/or a memory device. | 2011-08-25 |
20110204947 | METHOD AND APPARATUS FOR ADAPTIVELY MODIFYING A PULSE WIDTH OF A PULSE WIDTH MODULATED OUTPUT - Systems, methods, and apparatus for improving steady state operation of a pulse width modulator during transient and soft start events are described herein. An apparatus can include a phase component configured to adaptively modify a pulse width of a first pulse width modulated (PWM) output signal based on a pulse width of a PWM input signal. Further, the apparatus can include a power stage component configured to source at least one of a voltage or a current to a load based on the first PWM output signal. In one example, the phase component can be configured to linearly extend the pulse width of the first PWM output signal based on the pulse width of the PWM input signal. In another example, the phase component can be configured to adaptively modify the pulse width of the first PWM output signal based on a predetermined maximum pulse width. | 2011-08-25 |
20110204948 | DUTY CYCLE CORRECTION SYSTEMS AND METHODS - Duty cycle correction systems and methods of adjusting duty cycles are provided. One such duty cycle correction system includes a duty cycle adjustor and a variable delay line coupled to the output of the duty cycle adjustor. First and second phase detectors have first inputs coupled to the output of the duty cycle adjustor through an inverter and second inputs coupled to the output of the variable delay line. The phase detectors cause the delay line to align rising or falling edges of signals at the output of the delay line with rising or falling edges, respectively, of signals at the output of the inverter. The controller simultaneously causes the duty cycle adjustor to adjust the duty cycle of the output clock signal until the rising and falling edges of signals at the output of the delay line are aligned with rising and falling edges, respectively, of signals at the output of the inverter. | 2011-08-25 |
20110204949 | APPARATUS AND METHOD FOR EXTERNAL TO INTERNAL CLOCK GENERATION - A phase recombination circuit includes a first phase input and a first one-shot pulse generator adapted to receive the first phase input and produce a first signal to pull a signal to a first state. The phase recombination circuit also includes a second phase input in phase relationship with the first phase input, and a second one-shot pulse generator adapted to receive the second phase input and produce a second signal to pull a signal to a second state. | 2011-08-25 |
20110204950 | DELAY CIRCUIT AND METHOD FOR DELAYING SIGNAL - A delay circuit includes: a delay unit configured to receive a clock signal, delay an input signal sequentially by a predetermined time interval, and output a plurality of first delayed signals; and an option unit configured to select one of the plurality of first delayed signals based on one or more select signals, and output a second delayed signal. | 2011-08-25 |
20110204951 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison. | 2011-08-25 |
20110204952 | CURRENT DETECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT - The invention provides a current detection circuit for a transistor, that does not influence a current flowing through the transistor, and minimizes a power loss, an increase of the pattern area and so on. A current detection circuit includes a wiring connected to a MOS transistor and forming a current path of a current of the MOS transistor, a current detection MOS transistor of which the gate is connected to the wiring, that flows a current corresponding to the potential of the gate, and a current detector detecting a current flowing through the current detection MOS transistor. The current detection circuit is configured including a load resistor connected to the current detection MOS transistor and a voltage detection circuit detecting a drain voltage of the current detection MOS transistor. | 2011-08-25 |
20110204953 | LEVEL SHIFTER CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A level shifter circuit includes a pull-up unit configured to pull up an output node to a second voltage level being higher than a first voltage level in response to an input signal swinging with an amplitude of the first voltage level, a pull-down unit configured to pull down the output node in response to the input signal, and a protection unit connected between the output node and the pull-down unit to prevent a voltage of the output node from being applied to the pull-down unit. | 2011-08-25 |
20110204954 | Voltage Level Shifter - A voltage level shifter formed by single-typed transistors comprises two input terminals, two power supply terminals, a plurality of thin-film transistors, and an output terminal. Another voltage level shifter formed by single-typed transistors comprises two input terminals, an output terminal, two power supply terminals, two input units, a first thin-film transistor, a disable unit, a feedback unit, and a second thin-film transistor. The voltage level shifters are formed by single-typed TFTs. When integrating the voltage level shifters into a substrate of a TFT display, the manufacturing processes are simplified. Besides, power is saved. | 2011-08-25 |
20110204955 | CONTROL PIN POWERED ANALOG SWITCH - An apparatus comprises at least one input connection, at least one output connection, and at least one control connection, and at least one switch circuit coupled to the input, the output, and the control connections. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by a control signal received at the control connection. Power to the switch circuit is provided via the control connection. | 2011-08-25 |
20110204956 | BOOTSTRAPPED SWITCH CIRCUIT - A bootstrapped switch circuit can include at least one transistor, to receive an input signal and allow the input signal to pass through as an output signal based on a control signal, and a voltage-controlled voltage source, to provide first and second voltages between a gate and a source of the at least one transistor in response to the control signal. The voltage-controlled voltage source can include a differential pair and a current source. A gate of one of the differential pair can receive the control signal and a gate of the other of the differential pair can receive a logical inverse of the control signal. The current source can provide a current to connected sources of the differential pair. The first voltage can turn on the at least one transistor and be produced in response to a first logic state of the control signal resulting in the current of the current source flowing entirely through a first one of the differential pair. The second voltage can turn off the at least one transistor and be produced in response to a second logic state of the control signal resulting in the current of the current source flowing entirely through a second one of the differential pair. | 2011-08-25 |
20110204957 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD FOR THE SAME - The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit. | 2011-08-25 |
20110204958 | METHOD AND SYSTEM FOR OPEN LOOP COMPENSATION OF DELAY VARIATIONS IN A DELAY LINE - The present invention provides a method and system for open loop compensation of delay variations in a delay line. The method includes sensing the Process, Voltage, Temperature (PVT) variations in the delay line using a sensing circuit. A first and second sensitive current are generated based on the PVT variations. The first and second sensitive currents are mirrored currents from the sensing circuit. Then, a first compensation current is generated based on the first sensitive current and a first summing current. The first summing current is a reference current independent of the PVT variations. Further, the first compensation current is mirrored as a second summing current and a second compensation current is generated from the second sensitive current and the second summing current. The second compensation current compensates the delay variations and has a sensitivity based on the sensitivities of the first and second sensitive currents. | 2011-08-25 |
20110204959 | Charge Pump with Reduced Current Variation - Circuits and methods for maintaining a substantially constant input and output current for a charge pump circuit are provided which reduce current variation during switching intervals. The charge pump circuitry of the present invention maintains a current flow path from a current source to the charge pump output which minimizes or eliminates spikes normally associated with the switching intervals. | 2011-08-25 |
20110204960 | Fully Featured Control Pin Powered Analog Switch - An apparatus comprises at least one input connection, at least one output connection, at least one control connection, a voltage converter circuit having an input coupled to the control connection and an output, wherein the voltage converter circuit is configured to provide a voltage at its output that is greater than a voltage present at its input, and at least one switch circuit coupled to the input connection, the output connection, and the output of the voltage converter circuit. The switch circuit passes a signal received at the input to the output when the switch circuit is activated by the voltage converter output. Power to the voltage converter circuit is provided via the control connection, and power to the switch circuit is provided via the output of the voltage converter circuit. | 2011-08-25 |
20110204961 | Power-efficient multi-mode charge pump - Disclosed is a power-efficient multi-mode charge pump. The charge pump comprises a first pumping circuit that provides at least one output voltage produced by a discharge sequence of a shared flyback capacitor. The charge pump also comprises a second pumping circuit that provides a plurality of output voltages produced by a corresponding plurality of discharge sequences of the shared flyback capacitor. The charge pump may include a transition circuit to selectably enable the first pumping circuit or the second pumping circuit. In one embodiment, the first pumping circuit may employ a two-phase discharge sequence. In another embodiment, the second pumping circuit may employ a three-phase plurality of discharge sequences. A related method is also disclosed. | 2011-08-25 |
20110204962 | HIGH EFFICIENCY DC-DC CONVERTER - A charge pump includes an input, an output, and a fixed voltage node; a first capacitor and at least a second capacitor; and a plurality of switches adapted to selectively couple the first capacitor and the at least the second capacitor to the input, the output, and the fixed voltage node. A switch controller is adapted to switch the plurality of switches in response to at least three phase signals to provide fixed gains. A phase generator is adapted to generate the at least three phase signals, wherein at least one of the at least three phase signals has a duty cycle that is different from at least one other of the at least three phase signals. The phase generator is also adapted to adjust the frequency of a clock signal used to generate the at least three phase signals so that a minimum switching frequency is provided. | 2011-08-25 |
20110204963 | SEMICONDUCTOR DEVICE - A semiconductor device is provided, including a charge-pumping unit configured to charge-pump power voltage in every period of a pumping clock to generate pumping voltage, a first voltage level detection unit configured to detect a maximum voltage level of the generated pumping voltage, a second voltage level detection unit configured to detect a minimum voltage level of the generated pumping voltage, and a pumping clock generating unit configured to generate the pumping clock, the pumping clock having a frequency that is adjusted in response to an output signal of the first and the second voltage level detection units. | 2011-08-25 |
20110204964 | LEAKAGE CURRENT CONTROL CIRCUIT - A leakage current control circuit includes a solid state switch that is operable to control a flow of AC to a load. The switch exhibits an AC leakage current in an OFF state. A capacitor is connected in parallel to the load, and is operable to repeatedly charge during a first half cycle of the leakage current and to discharge during a second half cycle of the leakage current. The capacitor charge includes a DC component in response to the leakage current through the solid state switch being greater in a first direction than in a second direction opposite the first direction. A first resistor is connected in parallel to the load. The capacitor and the first resistor prevent a voltage buildup across the load from exceeding a voltage threshold. | 2011-08-25 |
20110204965 | Apparatus and Method Pertaining to Facilitating a Measurement with Respect to Field Effect Transistor - These various embodiments pertain to an FET having a plurality of fingers as correspond to the FET's source and drain. A first conductive lead electrically couples to a given one of this plurality of fingers while a second conductive lead electrically couples as well to this same given finger. A measurement component connects to these first and second conductive leads to measure at least one electrical parameter (such as voltage). By one approach, the first and second conductive leads physically connect to opposing ends of the given finger. These teachings will also accommodate providing a control component that is responsive to the measurement component to facilitate automatically controlling at least one operating state of the FET as a function, at least in part, of the measured electrical parameter. | 2011-08-25 |
20110204966 | Transistor junction diode circuitry systems and methods - Methods and apparatus for capacitive voltage division are provided, an example apparatus having an input and an output and including a first switched capacitor circuit. In some embodiments, the capacitive voltage divider includes first and second MOSFETs. A first capacitor is coupled between the drain of the first MOSFET and the input to the capacitive voltage divider. A first circuit coupled to the drain of the first MOSFET is configured to pull down the drain of the first MOSFET and thus apply a reverse bias to a first junction diode internal to the first MOSFET between the drain and the bulk of the first MOSFET. A second capacitor is coupled between the source of the first MOSFET and the drain of the second MOSFET. A second circuit is configured to reverse bias a second junction diode between the drain and bulk of the second MOSFET. | 2011-08-25 |
20110204967 | False-link protection circuit and method for utilizing same - Disclosed is a false-link protection circuit comprising at least one native switch coupled between a communication terminal of a first differential switch and a communication terminal of a second differential switch. The at least one native switch is configured to provide an attenuation path for a pulse link signal received by either communication terminal when the first and second differential switches are in a powered down state. According to one embodiment, a method to attenuate a pulse link signal comprises activating a native switch of a false-link protection circuit by powering down first and second differential switches, receiving a pulse link signal at a communication terminal of one of the first and second differential switches, and attenuating the pulse link signal by diverting it through the false-link protection circuit when the first and second differential switches are in a powered down state. | 2011-08-25 |
20110204968 | DEMODULATION CIRCUIT AND RFID TAG INCLUDING THE DEMODULATION CIRCUIT - An object is to provide a demodulation circuit having a sufficient demodulation ability. Another object is to provide an RFID tag which uses a demodulation circuit having a sufficient demodulation ability. A material which enables a reverse current to be small enough, for example, an oxide semiconductor material, which is a wide bandgap semiconductor, is used in part of a transistor included in a demodulation circuit. By using the semiconductor material which enables a reverse current of a transistor to be small enough, a sufficient demodulation ability can be secured even when an electromagnetic wave having a high amplitude is received. | 2011-08-25 |
20110204969 | GATED-VARACTORS - Various embodiments of the invention provide a varactor structure that, depends on configurations, can provide a C-V characteristic based on one or a combination of a reverse bias junction capacitor, a channel capacitor, and an oxide capacitor. The junction capacitor is formed by reverse biasing the P+ source region and the N-well. The channel capacitance is formed between the P+ source region and the N+ drain region, and the oxide capacitor is formed in the gate oxide area. Depending on biasing one or a combination of the gate voltage VG, the source voltage VS, and the drain voltage VD, embodiments can utilize one or a combination of the above capacitors. Other embodiments using the varactors in a Voltage-Controlled Oscillator (VCO) are also disclosed. | 2011-08-25 |
20110204970 | Electronic power-saving device - A single-phase electronic power-saving device includes at least one power-saving unit. The power-saving unit includes two ceramic piece capacitors, a safe capacitor, an inductor, a SCR, a first resistor, a second resistor, a live wire and a zero line; the two ceramic piece capacitors connected in series as a whole is connected in parallel with the safe capacitor to two terminals of which are connected the anode and the cathode of SCR, respectively; the anode of SCR is also connected to one terminal of the inductor, the branch composed of the first and the second resistors connected in series is connected in parallel so that one terminal of which is connected to one terminal of the inductor and the other is connected to the cathode of SCR; the gate of SCR is connected between the first and the second resistors. | 2011-08-25 |
20110204971 | DIFFERENTIAL VOLTAGE SENSING SYSTEM AND METHOD FOR USING THE SAME - A differential voltage sensing method for achieving input impedance matching comprises the steps of: providing a first bio-potential signal to a first variable resistor for generating a first signal; providing a second bio-potential signal to a second variable resistor for generating a second signal; differentially amplifying first and second signals for generating a third signal; selecting an operation band of the third signal for generating first and second logic signals; and dynamically adjusting one of the impedances of the first and second variable resistors according to the first and second logic signals, wherein each of the first and second bio-potential signals has a common signal voltage level and a differential signal voltage level. | 2011-08-25 |
20110204972 | AMPLIFYING CIRCUIT - To efficiently obtain two outputs including one at a normal level and the other at an excessive level. An input signal input to the negative input terminal of an operational amplifier ( | 2011-08-25 |
20110204973 | AMPLIFYING DEVICE AND SIGNAL PROCESSING METHOD BASED ON AMPLIFYING DEVICE - An amplifying device and a signal processing method based on an amplifying device are provided, capable of reducing performance requirements of modules and reducing design difficulty of the modules. The amplifying device includes at least one amplifying module, including two receiving paths, in which a first receiving path is configured to attenuate and amplify an input signal after the input signal is pre-amplified, and a second receiving path is configured to amplify the input signal when the input signal is not pre-amplified. The signal processing method based on the amplifying device is further provided. The amplifying device and the signal processing method may be applied in a communication network system. | 2011-08-25 |
20110204974 | APPARATUS FOR IMPROVING PERFORMANCE AT LOW POWER REGION IN A DOHERTY AMPLIFIER - A method and apparatus improve the performance of a carrier amplifier in a Doherty amplifier. The Doherty amplifier includes a power divider, a carrier amplifier, at least one peaking amplifier, offset lines, and a Doherty circuit. The power divider provides a power signal to each of the carrier amplifier and the at least one peaking amplifier. The carrier amplifier amplifies power of a signal inputted from the power divider. The at least one peaking amplifier amplifies power of a signal inputted from the power divider. The offset lines control a load impedance when the at least one peaking amplifier does not operate. When the at least one peaking amplifier does not operate, the Doherty circuit generates the load impedance of the carrier amplifier that is larger than twice a load impedance at the maximum output power of the carrier amplifier. | 2011-08-25 |
20110204975 | CALCULATING APPARATUS, DISTORTION CORRECTING APPARATUS, AMPLIFYING APPARATUS, AND CALCULATING METHOD - A calculating apparatus includes a first state variable calculating unit that calculates first state variables respectively having a memory effect and being of an amplifier that causes signal distortion; an amplifier model unit that based on the calculated first state variables, calculates the signal distortion caused by the amplifier, as a distortion characteristic; and an output unit that outputs the calculated distortion characteristic. | 2011-08-25 |
20110204976 | IMPEDANCE TRANSFORMER, INTEGRATED CIRCUIT DEVICE, AMPLIFIER, AND COMMUNICATOR MODULE - An impedance transformer includes a first transmission line having a first impedance and provided over a first substrate having a first permittivity; a second transmission line and a third transmission line having an impedance lower than the first impedance and provided over a second substrate having a permittivity higher than the first permittivity, the second transmission line and the third transmission line being electrically coupled to the first transmission line; and a resistor coupled between the second transmission line and the third transmission line. | 2011-08-25 |
20110204977 | SOLID-STATE IMAGE PICKUP APPARATUS AND DRIVING METHOD THEREFOR - An apparatus according to an embodiment of the present invention includes a conversion unit configured to generate electric charge, a first amplification unit configured to amplify a signal corresponding to an amount of the electric charge and output a first amplified signal, a second amplification unit configured to amplify the first amplified signal and output a second amplified signal, a current source shared by the first amplification unit and the second amplification unit, and a selection unit configured to bring the first amplification unit and the second amplification unit into an inactive state. The current source is shared by the first amplification unit and the second amplification unit. The number of current sources is therefore reduced. This leads to the reduction in power consumption. | 2011-08-25 |
20110204978 | COMPARATOR CIRCUIT - A comparator circuit ( | 2011-08-25 |
20110204979 | CONSTRUCTIVE FEEDBACK TRAVELING WAVE DEVICE AND METHOD - An apparatus and method include a transmission line carrying a propagating signal between an inlet port and an outlet port. The propagating signal can include a forward traveling wave and optionally a backward traveling wave. A feedback stage samples a the propagating signal at the outlet port, generates a feedback signal the includes a time translation and a gain translation in the feedback energy, and routes the feedback signal to the inlet port such that the gain translation constructively interferes with the forward traveling wave and thereby increases the amplitude of the forward traveling wave. | 2011-08-25 |
20110204980 | INTEGRATED DOHERTY AMPLIFIER - The invention relates to an integrated Doherty amplifier with an input network connecting the input to the main stage and to the peak stage, and with an output network connecting the main stage and the peak stage to the output. The output network has a shunt capacitor to signal-ground in parallel to a parasitic capacitance of the main stage, and has a shunt inductor between the main stage and signal ground. The shunt configuration enables to use the MMIC Doherty amplifier in a wide frequency range. At least some of the inductors of the input network and/or output network are implemented using bond wires. Their orientations and locations provide minimal mutual electromagnetic coupling between the wires and the return RF current paths. | 2011-08-25 |
20110204981 | BIAS CIRCUIT AND AMPLIFIER PROVIDING CONSTANT OUTPUT CURRENT FOR A RANGE OF COMMON MODE INPUTS - Bias circuits, amplifiers and methods are provided, such as those for providing bias signals over a range of common mode inputs for an amplifier to output a constant current. One example of a bias circuit is configured to generate a bias signal having a voltage magnitude according to a reference signal. The reference signal is indicative of a common mode input level of an input signal of the amplifier circuit and the bias circuit is further configured to adjust the bias signal over a range of common mode input levels. An amplifier receiving the bias signal is configured to generate an output signal in response to an input signal and drive an output current based on the voltage magnitude of the bias signal provided by the bias circuit. | 2011-08-25 |
20110204982 | POWER AMPLIFIER AND BRIDGE CIRCUIT IN POWER AMPLIFIER - A power amplifier and a bridge circuit in a power amplifier, thereinto, the power amplifier includes a comparator, a bridge circuit and a low-pass filter. The comparator is adapted to receive a first analog signal, compare the first analog signal with a reference signal and output a square wave signal. The bridge circuit is adapted to amplify the square wave signal and output the amplified square wave signal. The low-pass filter is adapted to convert the amplified square wave signal into a second analog signal. The bridge circuit includes a first MEMS switch and a second MEMS switch. The first MEMS switch and the second MEMS switch turn on alternately when the polarity of the square wave changes, and output a first voltage signal or a second voltage signal respectively. The amplified square wave signal includes the first voltage signal and the second voltage signal output alternately. The present disclosure substitutes the MOS transistors in prior art with surface MEMS switches, so the power consumption, the size of devices and the manufacture costs all can be reduced. | 2011-08-25 |
20110204983 | Fundamental wave/overtone crystal oscillator - Provided is a fundamental wave/overtone crystal oscillator to obtain fundamental wave oscillation and overtone oscillation with one crystal unit and to optimize the excitation current depending on the fundamental wave oscillation and the overtone oscillation. The fundamental wave/overtone crystal oscillator includes a crystal unit that oscillates with fundamental waves or with overtones, and an oscillator circuit that amplifies an excitation current from the crystal unit and outputs an oscillatory frequency. A capacitor Cf and a capacitor Co are connected in parallel with the base of a transistor in the oscillator circuit as well as the emitter. A switch is provided so as to connect or disconnect the capacitor Cf with respect to the circuit in response to a switching signal. The switch turns ON when the crystal oscillator oscillates with fundamental waves, and turns OFF when the crystal oscillator oscillates with overtones. | 2011-08-25 |
20110204984 | SURFACE ACOUSTIC WAVE RESONATOR, SURFACE ACOUSTIC WAVE OSCILLATOR, AND SURFACE ACOUSTIC WAVE MODULE UNIT - It is possible to reduce the size of a surface acoustic wave resonator by enhancing the Q value. In a surface acoustic wave resonator in which an IDT having electrode fingers for exciting surface acoustic waves is formed on a crystal substrate, a line occupying ratio is defined as a value obtained by dividing the width of one electrode finger by the distance between the center lines of the gaps between one electrode finger and the electrode fingers adjacent to both sides thereof, and the IDT includes a region formed by gradually changing the line occupying ratio from the center to both edges so that the frequency gradually becomes lower from the center to both edges than the frequency at the center of the IDT. | 2011-08-25 |
20110204985 | RESONATOR ELEMENT, RESONATOR, OSCILLATOR, AND ELECTRONIC DEVICE - A resonator element capable of improving impact resistance is provided. A quartz crystal resonator element is a resonator element formed by etching a Z plate which is cut at predetermined angles with respect to the crystal axes of a quartz crystal. The quartz crystal resonator element includes a base, a pair of resonating arms extending from the base in the Y-axis direction, and a positive X-axis notch and a negative X-axis notch formed by notching the base in the X-axis direction. The positive X-axis notch is formed by notching the base from the negative side of the X axis towards the positive side so that the width of the positive X-axis notch increases as it approaches the outer circumference. | 2011-08-25 |
20110204986 | METHOD OF MANUFACTURING PACKAGE, PIEZOELECTRIC VIBRATOR, OSCILLATOR, ELECTRONIC DEVICE, AND RADIO-CONTROLLED TIMEPIECE - Provided are a method of manufacturing a package capable of forming a penetration electrode without conduction defects while maintaining the airtightness of a cavity by suppressing the occurrence of voids in a baked glass, a piezoelectric vibrator manufactured by the manufacturing method, and an oscillator, an electronic apparatus, and a radio-controlled timepiece each having the piezoelectric vibrator. The package manufacturing method includes a second glass frit filling step of filling a second glass frit in a penetration hole to be overlapped on a first glass frit and temporarily drying the second glass frit; and a baking step of baking and curing the first and second glass frits filled in the penetration hole. The second particle size of the second glass particles contained in the second glass frit is larger than the first particle size of the first glass particles contained in the first glass frit. | 2011-08-25 |
20110204987 | Phase And Amplitude Modulator - A modulator for an electrical signal comprises a data input port and a clock frequency input port. The modulator also comprises a first phase shifter for subjecting input clock frequency signals to a phase shift and adapted to keep the phase of an input clock frequency signal aligned with the phase of a data stream which is input at the data input port. The modulator also comprises a first XOR gate with an output port, to which first XOR gate said input ports of the modulator are connected, by means of which a BPSK signal is created at the output port when a first data stream is connected to the data input port and a first clock frequency signal is connected to the clock frequency input port. | 2011-08-25 |
20110204988 | GLUE-LOGIC BASED METHOD AND SYSTEM FOR MINIMIZING LOSSES IN OVERSAMPLED DIGITALLY CONTROLLED DC-DC CONVERTERS - A practical method and system for oversampled digitally controlled DC-DC converters is presented. To minimize the switching losses while maintaining all advantages of the oversampling, “glue logic” and application specific oversampling digital pulse-width modulator are introduced. Experimental results demonstrate transient response with 50% smaller deviation than that of conventional controllers, allowing for proportional reduction in the size of the power stage output capacitor. | 2011-08-25 |
20110204989 | NON-RECIPROCAL CIRCUIT ELEMENT - A non-reciprocal circuit element includes first and second isolators of a high-pass type, each of the first and second isolators including a permanent magnet, a ferrite body to which a direct-current magnetic field is applied by the permanent magnet, and first and second center electrodes arranged on the ferrite body so as to cross each other in an insulated state. The first isolator has a passing frequency band that is higher than a passing frequency band of the second isolator. The first and second isolators include input portions that are electrically connected to define a single input port. A low pass filter is provided between the input port and the input portion of the second isolator. | 2011-08-25 |
20110204990 | METHODS AND APPARATUS FOR A SWITCHABLE BALUN FOR COMBINED BLUETOOTH AND WLAN OPERATION - Methods and apparatus for a switchable balun for combined Bluetooth and WLAN operation. A switchable balun is provided that includes an input circuit for receiving an amplified signal, the input circuit comprising first and second coils connected at a center tap, an output circuit comprising a third coil that is inductively coupled to the first and second coils, the output circuit for outputting an adjusted version of the amplified signal for transmission in a selected transmission mode, and a switch coupled to the center tap, wherein the switch is configured to couple a first voltage to the center tap to select operation in a first transmission mode and to couple a second voltage to the center tap to select operation in a second transmission mode. | 2011-08-25 |
20110204991 | FILTERING CIRCUIT TOPOLOGY - The exemplary embodiments described provide a low cost architecture for a quad-mode frontend of a communication device. In particular, the exemplary embodiments use diplexers to reduce the complexity of frontend switches and transceivers. | 2011-08-25 |
20110204992 | RADIO FREQUENCY DIRECTIONAL COUPLER DEVICE AND RELATED METHODS - An electronic device may include a printed circuit board (PCB) including a ground plane and having first and second opposing surfaces. The electronic device may also include a radio frequency (RF) directional coupler carried by the first surface of the PCB and including a housing and circuitry therein defining an input port, an output port, and first and second monitoring ports. A first monitoring circuit may be carried by the first surface of the PCB and connected to the first monitoring port. The electronic device may also include a via conductor connected to the second monitoring port and extending through the PCB to the second surface thereof. A second monitoring circuit may also be carried by the second surface of the PCB and connected to the via conductor. | 2011-08-25 |
20110204993 | TRANSMISSION LINE, IMPEDANCE TRANSFORMER, INTEGRATED CIRCUIT MOUNTED DEVICE, AND COMMUNICATION DEVICE MODULE - A transmission line having a plurality of branch lines that respectively include a first end part and a second end part and have a same line length, in which at least part of the plurality of branch lines includes bent shapes, the first end parts of the plurality of branch lines are connected to a common terminal, and the second end parts of the plurality of branch lines are connected to a common terminal. The plurality of branch lines may include two micro strip lines that are formed on substrates having the same dielectric constant and have bent shapes in symmetry with each other with respect to a straight line. | 2011-08-25 |
20110204994 | BOUNDARY ACOUSTIC WAVE DEVICE AND COMMUNICATION EQUIPMENT - A boundary acoustic waves device includes a piezoelectric substrate ( | 2011-08-25 |
20110204995 | ACOUSTICALLY COUPLED RESONATOR FILTER WITH IMPEDANCE TRANSFORMATION RATIO CONTROLLED BY RESONANT FREQUENCY DIFFERENCE BETWEEN TWO COUPLED RESONATORS - A signal processing device includes a first acoustic resonator, a second acoustic resonator disposed on the first acoustic resonator, and a coupling layer between the first and the second acoustic resonators. The first acoustic resonator has a first electrical impedance and a first resonance frequency and includes a first set of electrodes, and a first piezoelectric layer having a first thickness, disposed between the first set of electrodes. The second acoustic resonator has a second electrical impedance and a second resonance frequency, and includes a second set of electrodes, and a second piezoelectric layer having a second thickness, wherein the second piezoelectric layer is disposed between the second set of electrodes. The first electrical impedance at a passband frequency of the device substantially differs from the second electrical impedance at the passband frequency of the device. The first and second resonance frequencies are substantially different from each other. | 2011-08-25 |
20110204996 | ACOUSTIC COUPLING LAYER FOR COUPLED RESONATOR FILTERS AND METHOD OF FABRICATING ACOUSTIC COUPLING LAYER - In accordance with a representative embodiment, a bulk acoustic wave (BAW) resonator structure, comprises: a first BAW resonator comprising a first lower electrode, a first upper electrode and a first piezoelectric layer disposed between the first lower electrode and the first upper electrode; a second BAW resonator comprising a second lower electrode, a second upper electrode and a second piezoelectric layer disposed between the second lower electrode and the second upper electrode; and a single-material acoustic coupling layer disposed between the first and second BAW resonators, the acoustic coupling layer having an acoustic impedance less than approximately 6.0 MRayls and an acoustic attenuation less than approximately 1000 dB/cm. | 2011-08-25 |
20110204997 | BULK ACOUSTIC RESONATOR STRUCTURES COMPRISING A SINGLE MATERIAL ACOUSTIC COUPLING LAYER COMPRISING INHOMOGENEOUS ACOUSTIC PROPERTY - In accordance with a representative embodiment, a BAW resonator structure comprises: a first BAW resonator comprising a first lower electrode, a first upper electrode and a first piezoelectric layer disposed between the first lower electrode and the first upper electrode; and a second BAW resonator comprising a second lower electrode, a second upper electrode and a second piezoelectric layer disposed between the second lower electrode and the second upper electrode. The BAW resonator structure also comprises a single-material acoustic coupling layer disposed between the first and second BAW resonators. The single-material acoustic coupling layer comprises an inhomogeneous acoustic property across a thickness of the single-material acoustic coupling layer. | 2011-08-25 |
20110204998 | ELASTIC WAVE ELEMENT AND ELECTRONIC DEVICE USING THE SAME - Offers elastic wave device that has convex portion on the top face of first dielectric layer over IDT electrode when elastic wave device has a structure of a boundary wave device in which a film thickness of second dielectric layer is not less than 1.6 times as much as pitch width p of IDT electrode. This convex portion increases an electromechanical coupling coefficient of SH wave that is the major wave. Accordingly, good filter characteristics can be easily achieved. | 2011-08-25 |
20110204999 | FRAME-SHAPED MEMS PIEZORESISTIVE RESONATOR - A novel Si MEMS piezoresistive resonator is described. The resonator has a shape of a frame, such as a ring or a polygon frame, which has two or more anchors. Electrodes located at the outer or inner rim of the resonant structure are used to excite the structure electrostatically into resonance with a desired mode shape. One or plurality of locally doped regions on the structure is used for piezoresistive readout of the signal. In the most preferred embodiments, the structure is a ring, which has four anchors, two electrodes and four piezoresistive regions at different segments of the structure. The piezoresistive regions are alternatively located at the outer rim and inner rim of the structure in such a way that the piezoresistive signals of the same sign from different regions can be collected. Advantages of this device are large readout signal, large electrode area, robustness, suppressed out-of-plane vibration and larger usable linear range. | 2011-08-25 |
20110205000 | DIVIDABLE WAVEGUIDE - A division type waveguide circuit is provided, in which fixing a metal cover to a waveguide body with screws can prevent radiowave leak suitably without any application of the conductive adhesive, solder and braze as a material for the radiowave leak prevention. A radiowave leak preventing plate | 2011-08-25 |
20110205001 | MINIATURIZED DC BREAKER - A DC blocking device of a small size is disclosed. The disclosed DC blocking device may include: an internal conductor where RF signals are inputted; and an external conductor electrically connected to a ground; wherein the internal conductor has an insertion groove, and an insertion conductor is inserted into the insertion groove without touching the internal conductor and at a designated distance, and the diameter of the external conductor in the portion where the insertion conductor is inserted is set to be different from the diameter of another portion. The disclosed DC blocking device has the advantages of minimizing the spatial constraint when the DC blocking device is mounted on a mobile communication device, and of achieving suitable coupling even if the length of the part where coupling is achieved is reduced in the DC blocking device. | 2011-08-25 |
20110205002 | Reduction of multipacting by means of spatially varying magnetization - The present invention discloses an apparatus comprising an enclosure ( | 2011-08-25 |
20110205003 | ELECTROMAGNETIC SWITCHING DEVICE HAVING A PLURALITY OF AREAS GRADUATED RELATIVE TO ONE ANOTHER - An embodiment of the present invention discloses an electromagnetic switching device including a housing including a mounting side and a connector side opposite the mounting side. The connector side includes one first and second main connection area for connecting first and second main lines to first and second fixed main contacts disposed in the interior of the housing. In the interior of the housing, movable main contact bridges are disposed via which one main current path each main current path includes one of the first fixed main contacts, one of the second fixed main contacts, and one of the main contact bridges. The main connection areas are located opposite one another. One first and one second central area are disposed between the main connection areas. The central areas each extend from the first to the second main connection area. The central areas are elevated relative to the main connection areas and disposed next to one another viewed from the first to the second main connection area. The first central area is more elevated relative to the main connection areas than the second central area. | 2011-08-25 |
20110205004 | Hermetic Switch Device Activated Magnetically - A switch device comprising a container of the hermetic type, at least one switch contained inside the hermetic container, actuation devices at least partially contained inside the container and suitable to actively select the switch. Advantageously, the actuation devices comprise at least one internal ferromagnetic element, moving inside the container so as to influence an actuation button of the switch, and comprising in addition a transmission body having a first extremity which interfaces in contact with said internal ferromagnetic element and a second extremity which interfaces in contact with said actuation button. The transmission body is a rigid body which receives and transmits the movement of the internal ferromagnetic element from a rest position in which it does not cause the actuation button ( | 2011-08-25 |
20110205005 | Plastic Cradle - The present invention relates generally to a plastic cradle. More particularly, the invention encompasses a plastic cradle utilized inside a molded circuit breaker (MCB). The present invention is also directed to a novel nonconductive nonmagnetic cradle that engages a contact arm between a first terminal conductor and a second terminal conductor inside a molded circuit breaker (MCB) in an ON state, and disengages same in an OFF or Neutral state. | 2011-08-25 |
20110205006 | R-Fe-B ANISOTROPIC SINTERED MAGNET - An R—Fe—B based anisotropic sintered magnet according to the present invention has, as a main phase, an R | 2011-08-25 |
20110205007 | TRANSFORMER DEVICE - A transformer device includes an iron core, a plurality of stacked coils, wound onto the iron core, a plurality of base members arranged between the plurality of coils adjacent in a stacking direction, a plurality of flow channel member groups provided for each of the coils, each provided at a corresponding base member, and forming a flow channel directed to a flow of an insulating liquid between the corresponding base member and a corresponding coil, and an obstruction member arranged to obstruct the flow of the insulating liquid such that at least one of the flow channels formed by the plurality of flow channel member groups differs in the flow volume of the insulating liquid from another of the flow channels, and to obstruct the flow of the insulating liquid at a region not overlapping with the iron core in the flowing direction of the insulating liquid, among the flow channels. | 2011-08-25 |
20110205008 | HIGH CURRENT INDUCTOR ASSEMBLY - An inductor winding includes first, second, and third arms, a middle portion extending between and connected to at least two of the first, second, and third arms and arranged to support a winding core mounted thereon, and first, second, and third legs extending downwardly from the first, second and third arms, respectively, and arranged to be mounted on a circuit board. The first, second, and third legs are arranged to provide three-point contact with the circuit board, and the inductor winding is arranged to provide a space between a bottom surface of the winding core mounted on the middle portion and an upper surface of electronic components mounted on the circuit board. | 2011-08-25 |
20110205009 | WOVEN WIRE, INDUCTIVE DEVICES, AND METHODS OF MANUFACTURING - Low-cost, high performance woven conductors and associated inductive apparatus, and methods for manufacturing and utilizing the same. In one embodiment, an eight ( | 2011-08-25 |
20110205010 | Inductor For High Frequency Applications - The invention provides an inductor assembly suitable for use in high frequency switched mode power converters, where the rate of change of voltage can exceed 10 | 2011-08-25 |
20110205011 | RAPID DISCONNECT DEVICE - The invention relates to a rapid disconnect device for surge arrestors, in particular plate-type or flat varistors, comprising at least one element that is maintained under a mechanical stress, and a disconnection point for disconnecting the surge arrestor from the respective power grid upon thermal overload, wherein the disconnection point comprises contacts, the positions of which vary relative to one another, wherein one of said contacts is designed to be fixed. According to the invention, the contacts of varying positions relative to one another are electrically connected without the use of solder in such a way that incident current forces act primarily in the contact force direction and such that the moving contacts of the positionally-variable contacts of a lost element located at the surge arrestor and thermally detachable therefrom can be moved from a closed position to the disconnected position. | 2011-08-25 |
20110205012 | System And Method For Determining Characteristics Of A Physical Environment With Simple Motion Patterns - A system and method for determining characteristics of a physical environment with simple motion patterns are provided. A plurality of raw orientation readings are received from a simple motion pattern. A distribution of possible wall orientations upon each raw reading is determined. Wall direction is determined as the mean value of the distribution. | 2011-08-25 |
20110205013 | Method and System of Conditionally Operating a Movable Barrier - A method and system provides conditional allowance of access by operating a movable barrier such that access is not granted unless another condition is met. In one illustrative approach, a first signal is received and, if a second signal is received within a set time frame relative to receipt of the second signal, a movable barrier operator is then activated. By one approach, one of the signals is a long-range transmission, and the other signal is a visual-range transmission. | 2011-08-25 |
20110205014 | Method and Apparatus for Training a Learning Movable Barrier Operator Transceiver - A system and method for training a learning transceiver to a movable barrier system includes a learning transceiver that is configured for being trained to the movable barrier system. To provide ease of use to consumers, a user is able to train the learning transceiver to the movable barrier system without needing to push a button on a movable barrier operator or use a pretrained transmitter. To this end, a movable barrier operator is configured to transmit a transmission signal to the learning transceiver including a rolling access code, which is used to train the learning transceiver. To maintain the security of the movable barrier system and to restrict unauthorized users from accessing the movable barrier system, the movable barrier operator waits to transmit the transmission signal, including the rolling access code, to the learning transceiver until it has received an indication that a predetermined event occurred. | 2011-08-25 |
20110205015 | METHOD FOR CHALLENGE RESPONSE AUTHENTICATION BETWEEN A READING DEVICE AND A TRANSPONDER USING CONTACTLESS DATA TRANSMISSION - A method for challenge-response authentication between a reading device and a transponder based on a contactless data transmission, according to which challenge data (CH) are transferred within an anti-collision loop from the reading device to the transponder by means of one or several commands (AC) of an anti-collision method, with the command or commands (AC) serving to determine transponder identification data. In the command or commands (AC) respective challenge data (CH) are contained in a data field (D | 2011-08-25 |
20110205016 | Method and apparatus for access control using dual biometric authentication - A biometrically authenticated access control in which a wireless authentication signal is provided from a primary instrumentality of access, only after a dual-stage biometric verification of the user's identity is performed. In one embodiment, an accessing device includes memory for storing a device identification code and an authentication code, along with first and second biometric templates corresponding to biometric samples from a user. In another embodiment, an accessing device includes memory for storing a device identification code and more than one authentication code, for separate users, along with first and second biometric templates corresponding to biometric samples from multiple users. In order to gain access to a secured resource, a user undergoes first and second biometric sampling to generate biometric data to be compared with the first and second biometric templates. Upon authentication of the user by positive matches with said first and second biometric samples, the accessing device communicates the accessing device identification code and authentication code to a remote station controlling access to the secured resource. A central server maintains a central database of records each establishing a correlation between an enrolled accessing device's identification code and an authentication code assigned to that accessing device. | 2011-08-25 |
20110205017 | VEHCILE REMOTE STARTER USING AN ELECTRONIC IGNIION MODULE EMULATOR - A remote starter system for a vehicle having an electronic ignition module connected to vehicle controller modules by a serial data interface. The electronic ignition module is capable of receiving at least one keycode from a cryptographic controller vehicle key for verification before changing the state of at least one vehicle controller module. The remote starter system is defined in one embodiment to include a remote starter module having at least a memory for storing at least one keycode and having the ability to send the at least one keycode for verification and the ability to request modification of a state of at least one vehicle controller module. Wherein when the at least one keycode is verified, the state of at least one vehicle controller module is modified as requested by the remote starter module. | 2011-08-25 |
20110205018 | INPUT APPARATUS, REMOTE CONTROLLER AND OPERATING DEVICE FOR VEHICLE - An input apparatus for a vehicle includes: an operation element operable by an occupant of the vehicle; a biological information acquisition element acquiring biological information of the occupant; an unawakened state detection element detecting an unawakened state of the occupant based on the biological information, wherein the unawakened state is defined by a predetermined state different from an awakened state; and an operation disabling element disabling an operation input from the operation element when the unawakened state detection element detects the unawakened state. | 2011-08-25 |
20110205019 | Medical Treatment System and Method for Operation Thereof - A medical device comprises a device adapted to perform a medical procedure; a biometric information sensing device adapted to sense biometric information of a user; a controller adapted to retrieve stored biometric registration information of a user from a storage device in communication with the controller, to determine an identity of the user by comparing the stored biometric registration information and the sensed biometric information, and to prevent performance of the medical procedure if the sensed biometric information does not correspond to the stored biometric registration information. | 2011-08-25 |
20110205020 | Method for improving false acceptance rate discrimination for biometric authentication systems - A method, system and computer program product for improving error discrimination in biometric authentication systems. The error discrimination is set to a predetermined security policy. A plurality of biometric samples are provided and authenticated by a computer system in conjunction with a security token. An alternate embodiment allows inputting of the plurality of biometric samples in a predetermined sequence. The predetermined input sequence is maintained as an authentication secret which may be used to further reduce the authentication transaction error rate. A user may input one or more biometric samples, where a portion of the biometric samples are inputted in a predetermined sequence, selecting from among a plurality of available processing units, a set of processing units which will generate intermediate results from the processing of the biometric samples, processing at least a portion of the biometric samples by the selected set of processing units to provide intermediate results, verifying the predetermined sequence, and arbitrating the intermediate results to generate a final result which at least meets a predetermined security policy. Various embodiments provide for a security token to perform at least a portion of the processing or the arbitration function. | 2011-08-25 |
20110205021 | Global trak - My invention “Global Trak” is comprised of a GPS tracking unit, a lithium ion battery, a microprocessor, and a plastic square protective carrier. This invention is intended to be used for airline passengers whom want to know where their luggage is located at all times. The unit will be linked to a GPS unit, and a computer program which will enable passengers the ability to “track” their luggage. The GPS unit contained in the plastic square protective carrier will enable the unit to communicate with a satellite and then in turn send data to a computer program. The microprocessor contained in the unit may also contain information specific to the passenger. The lithium ion battery will power the GPS unit and microprocessor. The plastic protective carrier can either be used as a “luggage type tag” or can be stored in the luggage itself. | 2011-08-25 |
20110205022 | TRACKING SYSTEM - A system simultaneously tracks multiple objects. All or a subset of the objects includes a wireless receiver and a transmitter for providing an output. The system includes one or more wireless transmitters that send commands to the wireless receivers of the multiple objects instructing different subsets of the multiple objects to output (via their respective transmitter) at different times. The system also includes object sensors that receive output from the transmitters of the multiple objects and a computer system in communication with the object sensors. The computer system calculates locations of the multiple objects based on the sensed output from the multiple objects. In some embodiments, the system can also track an item based on proximity of that item to one or more of the objects. In such embodiments, the multiple objects each includes one or more local sensors. The local sensors detect presence of the item and the items' transmitters communicate presence of the item based on respective one or more local sensors. The computer system identifies a location of the item based on communications from one or more of the objects indicating presence of the item and the calculated locations of the multiple objects detecting the item. | 2011-08-25 |
20110205023 | MOBILE ASSET TRACKING UNIT, SYSTEM AND METHOD - An asset tracking unit, system, and method. The asset tracking unit, system, and method may include at least one transceiver having communicative connections with at least one SATCOM network and at least one GPS network via at least one antenna, wherein tracking information for at least one asset associated with the at least one transceiver is received from the GPS network and is communicated to the SATCOM network, a first link that provides a multi-code one of the communicative connections between the at least one transceiver and the at least one SATCOM network, and a second link that provides a multi-channel one of the communicative connections between the at least one transceiver and he at least one GPS network. The unit system and method may additionally include at least one remote operations center remote from an asset to be tracked, wherein the asset to be tracked is geographically associated with the central processing unit. | 2011-08-25 |
20110205024 | INSPECTION SYSTEM - An inspection system according to the present invention includes a sensor ( | 2011-08-25 |
20110205025 | CONVERTING BETWEEN DIFFERENT RADIO FREQUENCIES - The present disclosure is directed to a system and method for converting between different radio frequencies. In some implementations, a method includes receiving a request from a Radio Frequency Identification Device (RFID) reader configured to communicate with a first type of RFID tag. Independent of digital signal processing, the received request is automatically converted to a request compatible with a second type of RFID tag different from the first type of RFID tag. The converted request is transmitted to an RFID tag of the second type of RFID tag. | 2011-08-25 |
20110205026 | RADIO FREQUENCY IDENTIFICATION READER ANTENNA HAVING A DYNAMICALLY ADJUSTABLE Q-FACTOR - Turning now to the drawings, systems and methods for reading RFID transponders utilizing readers in which the Q-factor of the resonant antenna of the reader shifts over the course of the reader's interrogation cycle in response to the detection of data from FDX and HDX RFID transponders in accordance with embodiments of the invention are illustrated. One embodiment having a dynamically adjustable Q-factor, wherein the reader transmits an activation signal configured to activate half duplex and full duplex transponders includes a signal source configured to drive a resonant antenna and a dynamic switching circuit configured to set the Q-factor of the resonant antenna to a first value during the transmission of the activation signal. In addition, the dynamic switching circuit is configured to set the Q-factor of the resonant antenna to a second value below the first value during and/or in response to detection of a data signal from a full duplex transponder, the dynamic switching circuit is also configured to set the Q-factor of the resonant antenna to a third value below the second value when the RFID reader is not transmitting the activation signal, and the resonant antenna is multi-filar and the dynamic switching circuit is configured to control the Q-factor of the multi-filar resonant antenna by controlling the filars that are incorporated into the resonant antenna circuit. | 2011-08-25 |
20110205027 | Radio frequency tag - The invention relates to a radio frequency tag. The tag comprises a receiver for receiving radio frequency waves having an amplitude spectrum provided with a first frequency component and a second frequency component. The tag also comprises a converter associated with the receiver for generating a signal having a frequency component at the frequency difference between the first frequency and the second frequency. In addition, the tag comprises a signal circuit for processing the generated signal and a coupler for forwarding the generated signal from the receiver towards the signal circuit. The signal circuit comprises a transmitter for transmitting the generated signal as a transmitted radio wave. Further, the transmitter comprises a magnetic loop antenna including a resonant LC loop | 2011-08-25 |