34th week of 2013 patent applcation highlights part 17 |
Patent application number | Title | Published |
20130214365 | MEMS PRESSURE TRANSDUCER ASSEMBLY AND METHOD OF PACKAGING SAME - An assembly ( | 2013-08-22 |
20130214366 | MEMS ELEMENT AND ELECTRICAL DEVICE USING THE SAME - In a MEMS element | 2013-08-22 |
20130214367 | MEMS-BASED DUAL AND SINGLE PROOF-MASS ACCELEROMETER METHODS AND APPARATUS - An integrated MEMS inertial sensor device includes one or more three-axis MEMS inertial sensor devices, such as accelerometers, with dual or single proof mass configurations. These designs can be compact and can decouple the motion of each axis to minimize the measurement errors due to cross-axis sensitivity. Some embodiments include a frame to decouple the motion of two axes and to provide geometric symmetry. Some embodiments also include double-folded springs. In a specific embodiment, the three axes of an integrated MEMS accelerometer device are entirely decoupled. Thus, the actuation of each axis, through a force due to acceleration, has little or substantially no effect on the other axes. | 2013-08-22 |
20130214368 | SEMICONDUCTOR INTEGRATED DEVICE ASSEMBLY PROCESS - A process for assembly of an integrated device, envisages: providing a first body of semiconductor material integrating at least one electronic circuit and having a top surface; providing a second body of semiconductor material integrating at least one microelectromechanical structure and having a bottom surface; and stacking the second body on the first body with the interposition, between the top surface of the first body and the bottom surface of the second body, of an elastic spacer material. Prior to the stacking step, the step is envisaged of providing, in an integrated manner, at the top surface of the first body a confinement and spacing structure that confines inside it the elastic spacer material and supports the second body at a distance from the first body during the stacking step. | 2013-08-22 |
20130214369 | PRESSURE SENSOR - The present disclosure relates to pressure sensor assemblies and methods. The pressure sensor assembly may include a first substrate, a second substrate and a sense die. The first substrate may be connected to the second substrate, such that an aperture in the first substrate is in fluid communication with an aperture in the second substrate. The second substrate may be connected to the sense die, such that the aperture in the second substrate is in fluid communication with a sense diaphragm on the second substrate. The pressure sensor assembly may include a media path that extends through the aperture in the first substrate, through the aperture in the second substrate, and to the sense die. In some cases, the first substrate, the second substrate and the sense die may be connected in a manner that does not include an adhesive. | 2013-08-22 |
20130214370 | SYSTEM AND METHOD FOR MINIMIZING DEFLECTION OF A MEMBRANCE OF AN ABSOLUTE PRESSURE SENSOR - A Micro-Electro-Mechanical System (MEMS) pressure sensor is disclosed, comprising a gauge wafer, comprising a micromachined structure comprising a membrane region and a pedestal region, wherein a first surface of the micromachined structure is configured to be exposed to a pressure medium that exerts a pressure resulting in a deflection of the membrane region. The gauge wafer also comprises a plurality of sensing elements patterned on the electrical insulation layer on a second surface in the membrane region, wherein a thermal expansion coefficient of the material of the sensing elements substantially matches with a thermal expansion coefficient of the material of the gauge wafer. The pressure sensor comprises a cap wafer coupled to the gauge wafer, which includes a recess on an inner surface of the cap wafer facing the gauge wafer that defines a sealed reference cavity that encloses and prevents exposure of the sensing elements to an external environment. | 2013-08-22 |
20130214371 | SOLID-STATE IMAGING DEVICE, IMAGE SENSOR, METHOD OF MANUFACTURING IMAGE SENSOR, AND ELECTRONIC APPARATUS - There is provided a solid-state imaging device including a pixel array unit in which a plurality of unit pixels each having a photoelectric converting unit to generate and store photocharges according to an amount of received light and a charge storage unit to store the photocharges are arranged on a semiconductor substrate. The charge storage unit is formed on a path along which light is incident on the photoelectric converting unit. | 2013-08-22 |
20130214372 | TRIAZINE RING-CONTAINING POLYMER AND MEMBRANE-FORMING COMPOSITION CONTAINING THE SAME - Disclosed is a triazine ring-containing hyperbranched polymer containing a repeating unit structure represented by the expression (1). By this means, it is possible to achieve a triazine ring-containing polymer which, alone, has high heat resistance, high transparency, high refractive index, high light resistance, high solubility, low volume shrinkage without adding metal oxides; and also a membrane-forming composition containing the same. | 2013-08-22 |
20130214373 | SUB-PIXEL NBN DETECTOR - A method of making a two-dimensional detector array (and of such an array) comprising, for each of a plurality of rows and a plurality of columns of individual detectors, forming an n-doped semiconductor photo absorbing layer, forming a barrier layer comprising one or more of AlSb, AlAsSb, AlGaAsSb, AlPSb, AlGaPSb, and HgZnTe, and forming an n-doped semiconductor contact area. | 2013-08-22 |
20130214374 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SOLID-STATE IMAGE SENSOR - A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer. | 2013-08-22 |
20130214375 | PAD AND CIRCUIT LAYOUT FOR SEMICONDUCTOR DEVICES - An apparatus includes an image sensor with a frontside and a backside. The image sensor includes an active circuit region and bonding pads. The active circuit region has a first shape that is substantially rectangular. The substantially rectangular first shape has first chamfered corners. A perimeter of the frontside of the image sensor has a second shape that is substantially rectangular. The second substantially rectangular shape has second chamfered corners. The bonding pads are disposed on the frontside of the image sensor. The bonding pads are disposed between the first chamfered corners and the second chamfered corners. The first shape is disposed inside the second shape. | 2013-08-22 |
20130214376 | APPARATUS COMBINING BYPASS DIODE AND WIRE - The present invention relates to an apparatus combining bypass diode and wire. According to the present invention, the bypass diode can connect with the wire directly. It is not necessary to reserve an extra region on the substrate of the solar cell as the wire soldering area. Thereby, the required area of the ceramic substrate is reduced, and hence lowering the manufacturing cost of the solar cell substantially. | 2013-08-22 |
20130214377 | SOLID-STATE IMAGING DEVICE WITH CHANNEL STOP REGION WITH MULTIPLE IMPURITY REGIONS IN DEPTH DIRECTION AND METHOD FOR MANUFACTURING THE SAME - Channel stop sections formed by multiple times of impurity ion implanting processes. Four-layer impurity regions are formed across the depth of a semiconductor substrate (across the depth of the bulk), so that a P-type impurity region is formed deep in the semiconductor substrate; thus, incorrect movement of electric charges is prevented. Other four-layer impurity regions of another channel stop section are decreased in width step by step across the depth of the substrate, so that the reduction of a charge storage region of a light receiving section due to the dispersion of P-type impurity in the channel stop section is prevented in the depth of the substrate. | 2013-08-22 |
20130214378 | SEMICONDUCTOR DEVICE INCLUDING A MOSFET AND SCHOTTKY JUNCTION - A semiconductor device for use in a power supply circuit has first and second MOSFETS. The source-drain path of one of the MOSFETS are coupled to the source-drain path of the other, and a load element is coupled to a connection node of the source-drain paths. The second MOSFET is formed on a semiconductor substrate with a Schottky barrier diode. First gate electrodes of the second MOSFET are formed in trenches in a first region of the semiconductor substrate, while second gate electrodes of the second MOSFET are formed in trenches in a second region of the semiconductor substrate. The first and second gate electrodes are electrically connected together. Portions of the Schottky barrier diode are formed between adjacent ones of the second gate electrodes. A center-to-center spacing between adjacent first gate electrodes is smaller than a center-to-center spacing between adjacent second gate electrodes. | 2013-08-22 |
20130214379 | PHOTOSENSITIVE RESIN COMPOSITION, PHOTOSENSITIVE RESIN COMPOSITION FILM, AND SEMICONDUCTOR DEVICE USING THE PHOTOSENSITIVE RESIN COMPOSITION OR PHOTOSENSITIVE RESIN COMPOSITION FILM - A photosensitive resin composition contains: (a) an alkali-soluble polyimide; (b) a compound which has two or more epoxy groups and/or oxetanyl groups in each molecule; and (c) a quinonediazide compound. Less than 10 parts by weight of an acrylic resin is contained per 100 parts by weight of the polyimide (a); and the content of the compound (b) is not less than 20 parts by weight per 100 parts by weight of the polyimide (a). | 2013-08-22 |
20130214380 | AREA AND POWER SAVING STANDARD CELL METHODOLOGY - A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools. | 2013-08-22 |
20130214381 | METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES - Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench. | 2013-08-22 |
20130214382 | METHOD OF FORMING SUBSTRATE CONTACT FOR SEMICONDUCTOR ON INSULATOR (SOI) SUBSTRATE - A semiconductor structure is provided that includes a material stack including an epitaxially grown semiconductor layer on a base semiconductor layer, a dielectric layer on the epitaxially grown semiconductor layer, and an upper semiconductor layer present on the dielectric layer. A capacitor is present extending from the upper semiconductor layer through the dielectric layer into contact with the epitaxially grown semiconductor layer. The capacitor includes a node dielectric present on the sidewalls of the trench and an upper electrode filling at least a portion of the trench. A substrate contact is present in a contact trench extending from the upper semiconductor layer through the dielectric layer and the epitaxially semiconductor layer to a doped region of the base semiconductor layer. A substrate contact is also provided that contacts the base semiconductor layer through the sidewall of a trench. Methods for forming the above-described structures are also provided. | 2013-08-22 |
20130214383 | METHOD FOR FORMING ISOLATION STRUCTURE - [Problem] To provide a method for forming an isolation structure having a low shrinkage percentage and a low tensile stress. | 2013-08-22 |
20130214384 | LOW HARMONIC RF SWITCH IN SOI - A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device. | 2013-08-22 |
20130214385 | Package-in-Package Using Through-Hole Via Die on Saw Streets - A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die. | 2013-08-22 |
20130214386 | SIP SYSTEM-INTEGRATION IC CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A system-in-package (SiP) system-integration integrated circuit (IC) chip package and a manufacturing method thereof are provided. The package includes a substrate, a passive device and two IC chips are provided on the substrate, an adhesive film is disposed between each of the two IC chips and the substrate, the IC chips are connected to first pads on the substrate through bonding wires, and the substrate is covered by a mold cap. A third IC chip may be further disposed on one of the IC chips, and the third IC chip is connected to the first pad and the IC chip under the third IC chip respectively through a bonding wire. A substrate adopting a surface mount technology (SMT) PAD window-opening manner is used, chip mounting is performed on the substrate, and the substrate undergoes reflow soldering, cleaning, die bonding, plasma cleaning, bonding, marking, cutting, and packing, so that the SiP system-integration IC chip package is manufactured. The package of the present invention integrates devices of different types, has a complete system function, and can be used as a middle stage of further development of system on chip (SoC). | 2013-08-22 |
20130214387 | CHIP STRUCTURE WITH A PASSIVE DEVICE AND METHOD FOR FORMING THE SAME - The present disclosure provides a method for forming a chip structure with a resistor. A semiconductor substrate is provided and has a surface. A plurality of electronic devices and a resistor is formed on the surface of the semiconductor substrate. A plurality of dielectric layers and a plurality of circuit layers are formed over the semiconductor substrate. The dielectric layers are stacked over the semiconductor substrate and have a plurality of via holes. Each of the circuit layers is disposed on corresponding one of the dielectric layers respectively, wherein the circuit layers are electrically connected with each other through the via holes and are electrically connected to the electronic devices. A passivation layer is formed over the dielectric layers and the circuit layers. A circuit line is formed over the passivation layer, wherein the circuit line passes through the passivation layer and is electrically connected to the resistor. | 2013-08-22 |
20130214388 | Semiconductor Wafer Adapted to Support Transparency in Partial Wafer Processing - A semiconductor wafer is adapted to support partial wafer processing generally transparently to a facility capable of processing a full wafer. The wafer has provided thereon a plurality of semiconductor dice and a plurality of visible reference features. The reference features are positioned among the dice to support a predetermined partitioning of the wafer into partial wafers. The positioning of the reference features may render each partial wafer uniquely visually distinguishable from every other partial wafer. Each partial wafer may contain at least one of the reference features, with the position of each reference feature identified in accordance with a coordinate system of an electronic wafer map. The positioning of the reference features may provide a visual indication of where to cut the wafer to effect the partitioning. | 2013-08-22 |
20130214389 | INTEGRATED CIRCUIT - An integrated circuit includes a first chip having a plurality of through-chip vias, and a second chip stacked on the first chip and having a plurality of through-chip vias which are disposed at positions corresponding to the plurality of through-chip vias of the first chip and each of which is connected with at least one through-chip via of the first chip arranged in an oblique direction, which is not on a straight line extending in a chip stacking direction, among the plurality of through-chip vias of the first chip, wherein the first chip inputs/outputs a signal through a through-chip via which is selected by first repair information among the plurality of through-chip vias of the first chip, and the second chip inputs/outputs a signal through a through-chip via which is selected by second repair information among the plurality of through-chip vias of the second chip. | 2013-08-22 |
20130214390 | TSV SUBSTRATE STRUCTURE AND THE STACKED ASSEMBLY THEREOF - The disclosure provides a TSV substrate structure and the stacked assembly of a plurality of the substrate structures, the TSV substrate structure including: a substrate comprising a first surface, a corresponding second surface, and a TSV communicating the first surface with the second surface through the substrate; and a conductor unit completely filling the TSV, the conductor unit comprising a conductor body which has a first and a second ends corresponding to the first and second surfaces of the substrate, respectively. | 2013-08-22 |
20130214391 | Lateral-Dimension-Reducing Metallic Hard Mask Etch - A combination of gases including at least a fluorocarbon gas, oxygen, and an inert sputter gas is employed to etch at least one opening into an organic photoresist. The amount of oxygen is controlled to a level that limits conversion of a metallic nitride material in an underlying hard mask layer to a metal oxide, and causes organic polymers generated from the organic photoresist to cover peripheral regions of each opening formed in the organic photoresist. The hard mask layer is etched with a taper by the oxygen-limited fluorine-based etch chemistry provided by the combination of gases. The taper angle can be controlled such that a shrink ratio of the lateral dimension by the etch can exceed 2.0. | 2013-08-22 |
20130214392 | METHODS OF FORMING STEPPED ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES USING A SPACER TECHNIQUE - Disclosed herein are various methods of forming stepped isolation structures for semiconductor devices using a spacer technique. In one example, the method includes forming a first trench in a semiconducting substrate, wherein the first trench has a bottom surface, a width and a depth, the depth of the first trench being less than a target final depth for a stepped trench isolation structure, performing an etching process through the first trench on an exposed portion of the bottom surface of the first trench to form a second trench in the substrate, wherein the second trench has a width and a depth, and wherein the width of the second trench is less than the width of the first trench, and forming the stepped isolation structure in the first and second trenches. | 2013-08-22 |
20130214393 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object is to provide a semiconductor device with improved reliability in which a defect stemming from an end portion of a semiconductor layer provided in an island shape is prevented, and a manufacturing method thereof. Over a substrate having an insulating surface, an island-shaped semiconductor layer is formed, a first alteration treatment is performed, a first insulating film is formed on a surface of the island-shaped semiconductor layer, the first insulating film is removed, a second alteration treatment is performed on the island-shaped semiconductor from which the first insulating film is removed, a second insulating film is formed on a surface of the island-shaped semiconductor layer, and a conductive layer is formed over the second insulating film. An upper end portion of the island-shaped semiconductor layer has curvature by the first alteration treatment and the second alteration treatment. | 2013-08-22 |
20130214394 | SEMICONDUCTOR DEVICE - A field plate of a semiconductor device is provided with i) an insulating film that is formed on a surface of the semiconductor substrate, and includes a plurality of first regions, one for each of a plurality of FLR layers, that contact the layers and are arranged at intervals in a radial direction, and a plurality of second regions, one for each of the first regions, that are adjacent to the first regions in the radial direction, and ii) a plurality of first conductive films that are formed, one for each of the layers, inside of the insulating film, are arranged at intervals in the radial direction along the layers when a semiconductor substrate is viewed from above, and that are electrically connected to the layers. A thickness of at least a portion of the second regions is thicker than a thickness of the first regions. | 2013-08-22 |
20130214395 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD - A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone. | 2013-08-22 |
20130214396 | SEMICONDUCTOR PACKAGES - A semiconductor package includes a first package including a first wiring board and at least one first semiconductor chip mounted on the first wiring board, a second package stacked on the first package. The second package includes a second wiring board and at least one second semiconductor chip mounted on the second wiring board. The semiconductor package further includes at least one connection terminal connecting a plurality of signal lines of the first and second wiring boards, respectively, with each other. The semiconductor package further includes at least one ground terminal connecting a plurality of ground lines of the first and second wiring boards, respectively, with each other, and includes a side surface, and a shielding member covering a top surface and a side surface of a structure including the first and second packages and the shielding member is disposed on the at least one ground terminal. | 2013-08-22 |
20130214397 | MULTILAYER WIRING BOARD AND ELECTRONIC DEVICE - A ground layer of a multilayer wiring board includes: a first clearance through which a first differential via is inserted without coming into contact with the ground layer; and a second clearance through which a second differential via is inserted without coming into contact with the ground layer. A distance between an outer edge of the first clearance on the side of the second differential via and the first differential via is set shorter than a distance between an outer edge of the first clearance on the side opposite from the second differential via and the first differential via. A distance between an outer edge of the second clearance on the side of the first differential via and the second differential via is set shorter than a distance between an outer edge of the second clearance on the side opposite from the first differential via and the second differential via. | 2013-08-22 |
20130214398 | Semiconductor Device and Method of Forming Base Leads from Base Substrate as Standoff for Stacking Semiconductor Die - A semiconductor device has a base substrate with first and second opposing surfaces. A first etch-resistant conductive layer is formed over the first surface of the base substrate. A second etch-resistant conductive layer is formed over the second surface of the base substrate. A first semiconductor die has bumps formed over contact pads on an active surface of the first die. The first die is mounted over a first surface of the first conductive layer. An encapsulant is deposited over the first die and base substrate. A portion of the base substrate is removed to form electrically isolated base leads between opposing portions of the first and second conductive layers. A second semiconductor die is mounted over the encapsulant and a second surface of the first conductive layer between the base leads. A height of the base leads is greater than a thickness of the second die. | 2013-08-22 |
20130214399 | DC/DC Converter Power Module Package Incorporating a Stacked Controller and Construction Methodology - Methods and systems are described for enabling the efficient fabrication of small form factor power converters and also the small form factor power converter devices. | 2013-08-22 |
20130214400 | MICRO-ELECTRO MECHANICAL SYSTEMS (MEMS) STRUCTURES AND METHODS OF FORMING THE SAME - A device includes a capping substrate bonded with a substrate structure. The substrate structure includes an integrated circuit structure. The integrated circuit structure includes a top metallic layer disposed on an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the top metallic layer and the outgasing prevention structure. | 2013-08-22 |
20130214401 | System and Method for Fine Pitch PoP Structure - A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection. | 2013-08-22 |
20130214402 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package improves reliability of heat emitting performance by maintaining a heat emitting lid stacked on a top surface of a semiconductor chip at a tightly adhered state. A highly adhesive interface material and a thermal interface material are applied to the top surface of the semiconductor chip. The highly adhesive interface material insures that the heat emitting lid is bonded to the top surface while the thermal interface material insures excellent heat transfer between the top surface and the heat emitting lid. | 2013-08-22 |
20130214403 | FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure. | 2013-08-22 |
20130214404 | SEMICONDUCTOR MODULE - A semiconductor module includes a semiconductor element, a case member, a cylindrical body, a lid member, a bus bar, and an insulating plate. The case member includes a bottom member and an extended portion. Eight protruding portions are formed on an outer peripheral surface of the cylindrical body. Eight recessed portions are formed on an inner surface of a central hole of the bus bar. The cylindrical body is inserted into the central hole of the bus bar. The protruding portions of the cylindrical body are engaged with the recessed portions of the bus bar. A direction in which an extended portion of the bus bar extends is fixed in one direction, from among a plurality of directions in a circumferential direction of the cylindrical body, by engagement of the protruding portions with the recessed portions. | 2013-08-22 |
20130214405 | Component and Method for Producing a Component - A component includes a substrate, a chip and a frame. The frame is bonded to the substrate and the chip rests on the frame. A sealing layer on parts of the frame and the chip is designed to hermetically seal a volume enclosed by the substrate, the chip and the metal frame. | 2013-08-22 |
20130214406 | Flexible Heat Sink With Lateral Compliance - A multi-chip module (MCM) structure comprises more than one semiconductor chip lying in a horizontal plane, the MCM having individual chip contact patches on the chips and a flexible heat sink having lateral compliance and extending in a plane in the MCM and secured in a heat exchange relation to the chips through the contact patches. The MCM has a mismatch between the coefficient of thermal expansion of the heat sink and the MCM and also has chip tilt and chip height mismatches. The flexible heat sink with lateral compliance minimizes or eliminates shear stress and shear strain developed in the horizontal direction at the interface between the heat sink and the chip contact patches by allowing for horizontal expansion and contraction of the heat sink relative to the MCM without moving the individual chip contact patches in a horizontal direction. | 2013-08-22 |
20130214407 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances. | 2013-08-22 |
20130214408 | Interposer Having Conductive Posts - There are disclosed herein various implementations of an interposer for use in semiconductor packaging. One exemplary implementation comprises a conductive post formed from a wire bond. A first end of the conductive post is mechanically joined to a conductive pad on a first surface of the interposer, while a second end of the conductive post is capable of making electrical connection to a contact body on an active surface of a semiconductor die. Such an interposer may include a rigid or flexible interposer dielectric. In one exemplary implementation, the interposer dielectric has a via formed therein, the conductive post being situated in the via and extending through a second surface of the interposer opposite the first surface. | 2013-08-22 |
20130214409 | Semiconductor Device and Method of Forming Bond-on-Lead Interconnection for Mounting Semiconductor Die in FO-WLCSP - A semiconductor die has a conductive layer including a plurality of trace lines formed over a carrier. The conductive layer includes a plurality of contact pads electrically continuous with the trace lines. A semiconductor die has a plurality of contact pads and bumps formed over the contact pads. A plurality of conductive pillars can be formed over the contact pads of the semiconductor die. The bumps are formed over the conductive pillars. The semiconductor die is mounted to the conductive layer with the bumps directly bonded to an end portion of the trace lines to provide a fine pitch interconnect. An encapsulant is deposited over the semiconductor die and conductive layer. The conductive layer contains wettable material to reduce die shifting during encapsulation. The carrier is removed. An interconnect structure is formed over the encapsulant and semiconductor die. An insulating layer can be formed over the conductive layer. | 2013-08-22 |
20130214410 | ORGANIC INTERFACE SUBSTRATE HAVING INTERPOSER WITH THROUGH-SEMICONDUCTOR VIAS - An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided. | 2013-08-22 |
20130214411 | METAL INTERCONNECT OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a metal interconnect of a semiconductor device including: forming a interconnect hole by patterning an interlayer insulating film formed on a substrate; performing a nitriding treatment on a surface of the interlayer insulating film by injecting a gas including nitrogen into a deposition apparatus in which the substrate is disposed; forming a diffusion preventing film by injecting the gas including nitrogen and a metal source gas into the deposition apparatus together; filling the interconnect hole with a metal; and removing the metal formed on a part other than the interconnect hole by a chemical mechanical polishing (CMP) process. Accordingly, the mechanical strength of the interlayer insulating film is increased, thereby preventing scratches or defects that are generated during the chemical mechanical polishing process. | 2013-08-22 |
20130214412 | METHOD OF FORMING THIN FILM INTERCONNECT AND THIN FILM INTERCONNECT - A method of forming a thin film interconnect in which a film is formed by sputtering method using a Cu—Ca alloy target and a thin film interconnect formed by the method, the method comprising: forming a Cu—Ca alloy film by sputtering method using a Cu—Ca alloy target that contains 0.5 atomic % or more and less than 5 atomic % of Ca, and the balance consisting of Cu and unavoidable impurities; and performing heat treatment of the Cu—Ca alloy film at a temperature of 300 to 700° C. in an inert gas atmosphere containing trace amount of oxygen defined by oxygen partial pressure in the range of 10 | 2013-08-22 |
20130214413 | CONDUCTIVE LINE STRUCTURES AND METHODS OF FORMING THE SAME - Conductive line structures, and methods of forming the same, include first and second pattern structures, insulation layer patterns and an insulating interlayer. The first pattern structure includes a conductive line pattern and a hard mask stacked, and extends in a first direction. The second pattern structure includes a second conductive line pattern and another hard mask stacked, and at least a portion of the pattern structure extends in the first direction. The insulation layer patterns contact end portions of the pattern structures. The first pattern structure and an insulation layer pattern form a closed curve shape in plan view, and the second pattern structure and another insulation layer pattern form another closed curve shape in plan view. The insulating interlayer covers upper portions of the pattern structures and the insulation layer patterns, an air gap between the pattern structures, and another air gap between the insulation layer patterns. | 2013-08-22 |
20130214414 | INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES - Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further includes forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further includes completely filling in the structure with additional metal. | 2013-08-22 |
20130214415 | Metal Layer Air Gap Formation - Air gaps are provided to reduce interference and resistance between metal bit lines in non-volatile memory structures. Metal vias can be formed that are electrically coupled with the drain region of an underlying device and extend vertically with respect to the substrate surface to provide contacts for bit lines that are elongated in a column direction above. The metal vias can be separated by a dielectric fill material. Layer stack columns extend in a column direction over the dielectric fill and metal vias. Each layer stack column includes a metal bit line over a nucleation line. Each metal via contacts one of the layer stack columns at its nucleation line. A low temperature dielectric liner extends along sidewalls of the layer stack columns. A non-conformal dielectric overlies the layer stack columns defining a plurality of air gaps between the layer stack columns. | 2013-08-22 |
20130214416 | INTERCONNECT STRUCTURES AND METHODS OF MANUFACTURING OF INTERCONNECT STRUCTURES - Interconnect structures and methods of manufacturing the same are disclosed herein. The method includes forming a barrier layer within a structure and forming an alloy metal on the barrier layer. The method further includes forming a pure metal on the alloy metal, and reflowing the pure metal such that the pure metal migrates to a bottom of the structure, while the alloy metal prevents exposure of the barrier layer. The method further includes completely filling in the structure with additional metal. | 2013-08-22 |
20130214417 | METHODS OF FORMING A METAL SILICIDE REGION ON AT LEAST ONE SILICON STRUCTURE - A method of forming a metal silicide region. The method comprises forming a metal material over and in contact with exposed surfaces of a dielectric material and silicon structures protruding from the dielectric material. A capping material is formed over and in contact with the metal material. The silicon structures are exposed to heat to effectuate a multidirectional diffusion of the metal material into the silicon structures to form a first metal silicide material. The capping material and unreacted portions of the metal material are removed. The silicon structures are exposed to heat to substantially convert the first metal silicide material into a second metal silicide material. A method of semiconductor device fabrication, an array of silicon structures, and a semiconductor device structure are also described. | 2013-08-22 |
20130214418 | Semiconductor Device Package with Slanting Structures - A semiconductor device package structure includes a substrate with a via contact pad on top surface of the substrate, a terminal pad on bottom surface of the substrate and a conductive through hole through the substrate, wherein the conductive through hole electrically couples the via contact pad and the terminal pad on the substrate; a die having bonding pads thereon, wherein the die is formed on the top surface of the substrate; a slanting structure formed adjacent to at least one side of the die for carrying conductive traces; and a conductive trace formed on upper surface of the slanting structure to offer path between the bonding pads and the via contact pad. | 2013-08-22 |
20130214419 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of connection pads; mounting a chip on the substrate, wherein the chip comprises a plurality of copper-containing bumps directly coupled to the connection pads, and each of the copper-containing bumps comprises a ring surface; forming an anti-dissociation gel between the substrate and the chip, wherein the anti-dissociation gel comprises a plurality of anti-dissociation substances, and the ring surfaces of the copper-containing bumps are covered by the anti-dissociation substances. | 2013-08-22 |
20130214420 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device including first and second semiconductor pillars formed on a surface of a semiconductor substrate and aligning in a first direction; a first interconnect extending in a second direction intersecting with the first direction and provided between the first and second semiconductor pillars; and a first contact pad located over the first interconnect, the first contact pad being in contact with and electrically connected to the first semiconductor pillar at a side surface thereof, while being electrically isolated from the second semiconductor pillar. | 2013-08-22 |
20130214421 | DISABLING ELECTRICAL CONNECTIONS USING PASS-THROUGH 3D INTERCONNECTS AND ASSOCIATED SYSTEMS AND METHODS - Pass-through 3D interconnects and microelectronic dies and systems of stacked dies that include such interconnects to disable electrical connections are disclosed herein. In one embodiment, a system of stacked dies includes a first microelectronic die having a backside, an interconnect extending through the first die to the backside, an integrated circuit electrically coupled to the interconnect, and a first electrostatic discharge (ESD) device electrically isolated from the interconnect. A second microelectronic die has a front side coupled to the backside of the first die, a metal contact at the front side electrically coupled to the interconnect, and a second ESD device electrically coupled to the metal contact. In another embodiment, the first die further includes a substrate carrying the integrated circuit and the first ESD device, and the interconnect is positioned in the substrate to disable an electrical connection between the first ESD device and the interconnect. | 2013-08-22 |
20130214422 | CIRCUIT SUBSTRATE STRUCTURE - A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer. | 2013-08-22 |
20130214423 | METHODS FOR FABRICATION OF SEMICONDUCTOR STRUCTURES INCLUDING INTERPOSERS WITH CONDUCTIVE VIAS, AND RELATED STRUCTURES AND DEVICES - Methods of fabricating semiconductor devices that include interposers include the formation of conductive vias through a material layer on a recoverable substrate. A carrier substrate is bonded over the material layer, and the recoverable substrate is then separated from the material layer to recover the recoverable substrate. A detachable interface may be provided between the material layer and the recoverable substrate to facilitate the separation. Electrical contacts that communicate electrically with the conductive vias may be formed over the material layer on a side thereof opposite the carrier substrate. Semiconductor structures and devices are formed using such methods. | 2013-08-22 |
20130214424 | STRUCTURE AND MANUFACTURING METHOD FOR REDUCING STRESS OF CHIP - The invention provides a structure and a manufacturing method thereof for reducing a stress of a chip. The structure comprises a through-silicon via (TSV), a plurality of reinforcing base and a plurality of base bodies. The reinforcing bases are disposed near and around the TSV. The base bodies are disposed near and around the TSV, and the base is disposed on a side of the reinforcing base. The reinforcing base or the base body does not connected with the TSV. | 2013-08-22 |
20130214425 | DUAL SIDE PACKAGE ON PACKAGE - An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material. | 2013-08-22 |
20130214426 | Semiconductor Package Including an Organic Substrate and Interposer Having Through-Semiconductor Vias - The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment. | 2013-08-22 |
20130214427 | SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS STACKED WITH EACH OTHER - A first semiconductor chip includes a first surface and a second surface opposite to the first surface. A second semiconductor chip is stacked over the second surface of the first semiconductor chip. The second semiconductor chip is larger in size than the first semiconductor chip. A first sealing resin covers the first and second semiconductor chips so that the first surface exposes from the first sealing resin. A first width of the first sealing resin that is around the first semiconductor chip is larger than a second width of the first sealing resin that is around the second semiconductor chip. | 2013-08-22 |
20130214428 | SEMICONDUCTOR DEVICE HAVING NON-PLANAR INTERFACE BETWEEN A PLUG LAYER AND A CONTACT LAYER - A semiconductor device is provided, in which it becomes easy to reliably couple a plug conductive layer and a wiring layer located over the plug conductive layer to each other and falling of the wiring can be suppressed. The plug conductive layer contacts a source/drain region formed over a major surface of the semiconductor substrate. A contact conductive layer is formed so as to contact both the upper surface and the side surface of the plug conductive layer. Wiring layers are formed over the contact conductive layer so as to be electrically coupled to the contact conductive layer. | 2013-08-22 |
20130214429 | STRUCTURES WITH THROUGH VIAS PASSING THROUGH A SUBSTRATE COMPRISING A PLANAR INSULATING LAYER BETWEEN SEMICONDUCTOR LAYERS - A through via contains a conductor ( | 2013-08-22 |
20130214430 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH FORMED UNDER-FILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting an integrated circuit above the substrate with an interconnect directly connecting between the substrate and the integrated circuit; and forming an under-fill between the integrated circuit and the substrate having a cast side. | 2013-08-22 |
20130214431 | Fine-Pitch Package-on-Package Structures and Methods for Forming the Same - A method includes laminating a Non-Conductive Film (NCF) over a first package component, and bonding a second package component on the first package component. The NCF and the second package component are on a same side of the first package component. Pillars of a mold tool are then forced into the NCF to form openings in the NCF. The connectors of the first package component are exposed through the openings. | 2013-08-22 |
20130214432 | STACKED DIE ASSEMBLY - Embodiments of stacked die assemblies for an IC are disclosed. One embodiment includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components, avoiding the interconnect restricted area of the first interposer and the second interposer. | 2013-08-22 |
20130214433 | Efficient Non-Integral Multi-Height Standard Cell Placement - An integrated circuit including a first portion of a first cell library including a first plurality of rows, each of the first plurality of rows having a first row height and the first portion having a first portion height, a second portion of a second cell library including a second plurality of rows, each of the second plurality of rows having a second row height and the second portion having a second portion height, wherein the first portion height is equal to the second portion height and the first row height is different from the second row height, and a connector to electrically connect the first portion of the first cell library to the second portion of the second cell library. | 2013-08-22 |
20130214434 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to provide a peeling method that causes no damage to a layer to be peeled and to allow not only a layer to be peeled with a small surface area but also a layer to be peeled with a large surface area to be peeled entirely. Further, it is also an object of the present invention to bond a layer to be peeled to various base materials to provide a lighter semiconductor device and a manufacturing method thereof. Particularly, it is an object to bond various elements typified by a TFT, (a thin film diode, a photoelectric conversion element comprising a PIN junction of silicon, or a silicon resistance element) to a flexible film to provide a lighter semiconductor device and a manufacturing method thereof. | 2013-08-22 |
20130214435 | EPOXY ENCAPSULATING AND LAMINATION ADHESIVE AND METHOD OF MAKING SAME - An adhesive includes an epoxy resin and a hardener. The hardener includes trioxdiamine, diaminodicyclohexylmethane, toluene diamine, and bisphenol-A dianhydride. | 2013-08-22 |
20130214436 | MICRO-BUBBLE GENERATOR - A microbubble generator is described, that generate micro bubbles without adopting the complicated prior art venturi tube structure. One embodiment has a water supply side joint on one end of a main tube which is formed as a cylinder and a water drain side joint on the other. The two joints are connected with a water channel that runs along the axis of the tube, and in the middle of said channel there is a narrower, restricted channel whose internal diameter is 6 millimeters or less. A water supply side channel is constituted between the supply side joint and the restricted channel, and a water drain side channel is constituted between the restricted channel and the drain side joint, and both the supply side channel and the drain side channel have a larger diameter than that of the restricted channel and are formed as non-tapered, straight holes along the axis | 2013-08-22 |
20130214437 | WATER AERATION SYSTEM USING RENEWABLE ENERGY SOURCE - The water aeration system using a renewable energy source is a self-contained unit having a float and a perforated diffuser plate positioned below the float. An electrically powered air pump is installed atop the structure, and a device for collecting renewable energy also extends above the structure. The renewable energy collection device may be one or more solar panels or a wind generator or wind turbine. The pump draws ambient air in through an inlet and pumps the air down through a supply tube to escape from a nozzle below the diffuser plate. The air then bubbles up through the water, the bubbles being broken up by the small perforations of the diffuser plate to provide efficient aeration of the water. An electrical storage battery and auxiliary power receptacle may be provided to power the pump motor during periods when solar or wind power is not available. | 2013-08-22 |
20130214438 | FOAMED WATER SAVING AERATOR - The present invention provides a foamed-water generating aerator which is capable of generating good-quality foamed water containing fine, homogeneously distributed air bubbles. The foamed-water generating aerator ( | 2013-08-22 |
20130214439 | Three-Dimensional Direct-Write Lithography - A method of creating a region of index change in a photopolymer includes providing a photopolymer having a photosensitivity to light of a particular wavelength and creating a region of index change in the photopolymer by applying direct write lithography to expose the photopolymer of the region to light that includes the particular wavelength. | 2013-08-22 |
20130214440 | LENS SHEET MANUFACTURING METHOD AND LENS SHEET MANUFACTURING APPARATUS - A lens sheet manufacturing method according to one aspect of the presently disclosed subject matter includes: conveying an original lens sheet having a plurality of linear lens elements arranged and formed in parallel with each other on a front sheet surface; detecting an edge line of one of the lens elements; determining whether the detected edge line and a trimming direction blade included in a punching blade are parallel with each other; when it is determined that they are not parallel with each other, controlling a conveying direction of the original lens sheet so that the trimming direction blade and the detected edge line are parallel with each other; and temporarily stopping conveying with the edge line of the lens element and the trimming direction blade being parallel with each other and punching the original lens sheet with the punching blade to manufacture a separated lens sheet. | 2013-08-22 |
20130214441 | SECONDARY AQUEOUS DISPERSIONS OF BIODEGRADABLE DIBLOCK COPOLYESTERS, PROCESSES FOR PREPARATION THEREOF AND USE THEREOF - The present invention provides aqueous stable suspensions of biodegradable diblock copolyesters and a method for their production. The diblock copolyesters comprise one block of an aliphatic polyester and one block of a polyethylene oxide. | 2013-08-22 |
20130214442 | METHOD FOR PRODUCTION OF CARBON NANOFIBER MAT OR CARBON PAPER - Method for the preparation of a non-woven mat or paper made of carbon fibers, the method comprising carbonizing a non-woven mat or paper preform (precursor) comprised of a plurality of bonded sulfonated polyolefin fibers to produce said non-woven mat or paper made of carbon fibers. The preforms and resulting non-woven mat or paper made of carbon fiber, as well as articles and devices containing them, and methods for their use, are also described. | 2013-08-22 |
20130214443 | PROCESS FOR THE PRODUCTION OF CARBON FIBERS FROM POLY(ALPHA(1->3) GLUCAN) FIBERS - A process is provided for preparation of carbon fibers based from fibers of poly(α(1→3) glucan). The method comprises three thermal exposures at progressively higher temperatures to drive off volatiles, thermally stabilize the glucan fiber, and carbonize the thermally stabilized fiber. The carbon fibers prepared according to the process hereof are strong, stiff, tough, and easily handled. | 2013-08-22 |
20130214444 | METHOD OF AND APPARATUS FOR BUILDING A SEQUENCE OF TYRES DIFFERENT FROM EACH OTHER - A method of building a sequence of tyres different from each other, includes generating a first deposition surface by a first series of consecutive circumferential sectors. The first deposition surface is selected as a function of the type of a first tyre to be built. Each circumferential sector of the first series is removably coupled to a central body of a forming drum. The method further includes manufacturing at least one component of the at least one first tyre by deposition of the at least one component at a radially external position to the first deposition surface of the forming drum, removing the at least one component from the forming drum and replacing each circumferential sector of the first series with a circumferential sector of a second series for generating a second deposition surface selected as a function of the type of a second tyre to be built which is different from the first tyre. The replacement includes uncoupling each circumferential sector of the first series from the central body and removably coupling each circumferential sector of the second series to the same central body. | 2013-08-22 |
20130214445 | Molding Apparatus and Method - A molding apparatus for making a continuous molded article generally includes a pair of spaced-apart molding assemblies, which cooperatively generate a movable mold having a dynamic mold-cavity therein, each of the molding assemblies including a series of movable mold segments, which are adapted to fit together to form a portion of the dynamic mold-cavity, a drive mechanism for conveying the mold segments along a path, and a dispenser for dispensing a moldable, expandable material into the dynamic mold-cavity. | 2013-08-22 |
20130214446 | METHOD OF FORMING RESIN MOLDED PRODUCT - A method of molding a resin molded product wherein a resin material in a molten state containing a forming agent is injected through a gate into a cavity of molding die thereby forming the form-molded product, wherein the gate communicating with the cavity of the molding die is continuously formed to the rising wall portion of the foam-molded product; the rising wall portion is provided with a rib at a position apart from the gate at a predetermined distance; a foaming of the molten resin material injected from the gate into the cavity is suppressed at a region corresponding to the upstream side portion of the foam-molded product, while the foaming of the molten resin material is promoted at a region corresponding to the downstream side portion of the foam-molded product. | 2013-08-22 |
20130214447 | Apparatuses, Systems, and Associated Methods for Forming Porous Masses for Smoke Filter - A system for producing porous masses may include a mold cavity disposed along the material path, at least one hopper before at least a portion of the mold cavity for feeding a matrix material to the material path, a heat source in thermal communication with at least a first portion of the material path, and a cutter disposed along the material path after the first portion of the material path. | 2013-08-22 |
20130214448 | SURFACE DEACTIVATOR THAT CAN BE REMOVED WHEN DRY - The invention relates to an emulsion consisting of an oily phase dispersed in an aqueous phase, comprising a non-quaternary amine surfactant and an acid with a set-retarding effect as well as to a method for its preparation. | 2013-08-22 |
20130214449 | SHEET FOR DECORATION SIMULTANEOUS WITH INJECTION MOLDING AND DECORATED RESIN MOLDING - The present invention provides a laminate-type decorative sheet for use in simultaneous decoration and injection molding, including a base film and at least a decorative layer provided on the base film, the decorative sheet having an elongation at break as measured at 25° C. of 3 to 10%, and an elongation at break as measured at 120° C. of 200% or more. | 2013-08-22 |
20130214450 | METHOD AND APPARATUS FOR MOLDING PARTS - A method and apparatus for injection molding plastic parts is described. In one embodiment, at least two materials are simultaneously injected into a mold. The resulting molded part can include at least two different regions. Each region can have distinct physical properties. Positions of the regions within the molded part can be at least partially controlled by controlling flow fronts of the at least two materials within the mold. | 2013-08-22 |
20130214451 | Widening Device - The invention relates to a covering device, comprising a feeding device for a tread strip, by means of which the tread strip can be fed to a carcass, wherein a connecting device is provided which allows ends ( | 2013-08-22 |
20130214452 | LARGE AREA IMPRINT LITHOGRAPHY - Methods and systems are provided for patterning polymerizable material dispensed on flexible substrates or flat substrates using imprint lithography techniques. Template replication methods and systems are also presented where patterns from a master are transferred to flexible substrates to form flexible film templates. Such flexible film templates are then used to pattern large area flat substrates. Contact between the imprint template and substrate can be initiated and propagated by relative translation between the template and the substrate. | 2013-08-22 |
20130214453 | PHOTO-CURABLE NANOIMPRINT COMPOSITION, METHOD FOR FORMATING PATTERN USING THE COMPOSITION, AND NANOIMPRINT REPLICA MOLD COMRISING CURED PRODUCT OF THE COMPOSITION - Provided is a photo-curable nanoimprint composition that has excellent properties in terms of etching resistance, dispersibility, and productivity. In addition, the photo-curable nanoimprint composition enables easy transcription of patterns even when a mold is pressed with a relatively low pressure. The photo-curable nanoimprint composition includes: (A) partial hydrolysate obtained by hydrolyzing a mixture of an organic silicon compound and a silicon compound containing (meth)acrylic groups with water in the molar amount of not less than 0.1 times but less than 1.0 times with respect to the number of moles of all alkoxy groups present in the mixture; (B) polymerizable monomer containing (meth)aclyic groups; and (C) pothopolymerization initiator. In addition, the mixture of partial hydrolysate (A) may include further partial hydrolysate of fluorinated silicone compound and/or metal oxide. | 2013-08-22 |
20130214454 | SEAMLESS FUSER MEMBER PROCESS - Described herein is a method forming a belt suitable for use with an image forming system. The method includes coating a composition of a polyimide, a phosphate ester and a solvent onto an outer surface of a rotating metal belt, and subsequently curing and releasing the composition from the metal belt. | 2013-08-22 |
20130214455 | Aliphatic Polyester - A copolymer obtained by condensation of i) 90 to 99.5 mol %, based on components i) to ii), of succinic acid; ii) 0.5 to 10 mol %, based on components i) to ii), of azelaic acid, sebacic acid and/or brassylic acid; iii) 98 to 102 mol %, based on components i) to ii), of 1,3-propanediol or 1,4 butanediol, and iv) 0.01% to 5% by weight, based on the total weight of the components i) to ii), of a chain extender and/or crosslinker selected from the group consisting of an at least trihydric alcohol or an at least tribasic carboxylic acid. | 2013-08-22 |
20130214456 | Apparatus and Method of Manufacturing Objects with Varying Concentration of Particles - An apparatus and method for manufacturing an object with a varying concentration of particles, with a defined concentration profile are disclosed. In an embodiment, the object with varying concentration of particles is manufactured by mixing liquids comprising different particle concentrations, the proportion in which such liquids are mixed being varied over time. The resultant liquid is cast or extruded into the required shape to form the object with a varying concentration of particles. | 2013-08-22 |
20130214457 | METHOD OF ELECTROSPINNING FIBRES - A method of electrospinning fibres is disclosed. The fibres have an inner core surrounded by a porous outer shell. The method comprises co-electrospinning first and second liquids as core and shell respectively, the second liquid surrounding the first liquid in a jet issuing from a Taylor cone, wherein the first and second liquids are miscible or semi-miscible with each other, such that pore generation is driven in the shell of the fibre. The liquids may be solutions or melts. The electrical conductivity, viscosity, miscibility and other parameters of the liquids determine the structure of the produced fibres. As well as producing fibres having a porous shell there are described methods of co-electrospraying porous beads as well as core-shell vesicles having a porous shell. The methods may be used to produce hydrogen storage fibres, vesicles and beads. The methods may also be used for producing controlled drug-delivery fibres, vesicles and beads. | 2013-08-22 |
20130214458 | SAMPLE PREPARATION METHOD AND APPARATUS - Provided is a sample preparation method, including: while displaying a SEM image of a first cross-section of a sample on a display screen, subjecting the first cross-section to etching processing by scanning and irradiation of a focused ion beam, thereby exposing a second cross-section; and while displaying a SEM image of another cross-section on the display screen, changing a scanning direction of the focused ion beam while performing the scanning and irradiation of the focused ion beam and subjecting the second cross-section to etching processing, thereby exposing a desired cross-section of the sample. | 2013-08-22 |
20130214459 | Process For Making An Embossed Web - A process for making an embossed web. A precursor web is provided between a forming structure and a static pressure plenum. The forming structure has a plurality of discrete protruded. elements. Pressure is provided by the static pressure plenum against the precursor web and the forming structure to conform the precursor web to the discrete protruded elements of the forming structure to form the embossed web. The resulting embossed web has a plurality of discrete extended elements having open proximal ends. | 2013-08-22 |
20130214460 | PROCESS FOR PRODUCING INJECTION STRETCH BLOW MOLDED POLYOLEFIN CONTAINERS - Injection stretch blow molding process for preparing polyolefin containers, comprising the following steps: 1) preparing a preform by injection molding a polyolefin composition comprising a polymer (A) selected from ethylene polymers, propylene polymers and mixtures thereof, and a heat absorber (B); 2) supplying heat to reheat the preform prepared in step 1) and stretch blow molding said preform; wherein the heat absorber (B) is selected from phosphates, condensed phosphates, phosphites, and mixed hydroxide/phosphate oxanion compounds of Copper (Cu), Calcium (Ca), Tin (Sn) and/or Iron (Fe). | 2013-08-22 |
20130214461 | Three-Dimensional Wafer-Scale Batch-Micromachined Sensor and Method of Fabrication for the Same - A vibratory sensor is fabricated as a three-dimensional batch-micromachined shell adapted to vibrate and support elastic wave propagation and wave precession in the shell or membrane and at least one driving electrode and preferably a plurality of driving electrodes directly or indirectly coupled to the shell to excite and sustain the elastic waves in the shell. The pattern of elastic waves is determined by the configuration of the driving electrode(s). At least one sensing electrode and preferably a plurality of sensing electrodes are provided to detect the precession of the elastic wave pattern in the shell. The rotation of the shell induces precession of the elastic wave pattern in the shell which is usable to measure the rotation angle or rate of the vibratory sensor. | 2013-08-22 |
20130214462 | PROCESS FOR PRODUCING LITHIUM VANADIUM PHOSPHATE-CARBON COMPOSITE - A process for producing a lithium vanadium phosphate-carbon composite includes a first step that includes mixing a lithium source, a tetravalent or pentavalent vanadium compound, a phosphorus source, and a conductive carbon material source that produces carbon through pyrolysis, in an aqueous solvent to prepare a raw material mixture, a second step that includes heating the raw material mixture to effect a precipitation reaction to obtain a reaction mixture that includes a precipitate, a third step that includes subjecting the reaction mixture that includes the precipitate to wet grinding using a media mill to obtain a slurry that includes ground particles, a fourth step that includes spray-drying the slurry that includes the ground particles to obtain a reaction precursor, and a fifth step that includes calcining the reaction precursor at 600 to 1300° C. in an inert gas atmosphere or a reducing atmosphere. A lithium vanadium phosphate-carbon composite produced by the process may provide a lithium secondary battery with excellent battery performance (e.g., high discharge capacity) when used as a cathode active material. | 2013-08-22 |
20130214463 | ALUMINUM-TITANATE-BASED CERAMIC HONEYCOMB STRUCTURE, ITS PRODUCTION METHOD, AND STARTING MATERIAL POWDER FOR PRODUCING SAME - A ceramic honeycomb structure having a large number of flow paths partitioned by porous cell walls, the cell walls comprising at least main crystals of aluminum titanate, in which MgO and SiO | 2013-08-22 |
20130214464 | Space shuttle damping and isolating device - A device used for providing dynamic isolation and damping of dynamic vibrations, in a passive way, originated in the launch vehicle of a space shuttle and reaching the payload or satellite. The device comprises a plurality of identical elementary unit elements, such that the device is designed in a modular way, allowing the individual modularity of each of the elementary unit elements. Each of the elementary unit elements is tailored and designed individually, and the complete device can be designed for each particular application and payload needed as a function of each of the elementary unit elements allowing an easy design and lower costs, for a wide range of payload applications. Each elementary unit element comprises a spring component and a damping component, such that the functionalities provided for each component are separated and can be individually tailored, thus providing a device having a wider range of adaptation capabilities. | 2013-08-22 |