34th week of 2008 patent applcation highlights part 55 |
Patent application number | Title | Published |
20080201549 | System and Method for Improving Data Caching - According to one embodiment of the present invention, a method for storing data includes partitioning the data into a plurality of sections and storing the sections on one or more server nodes of a plurality of server nodes. The method further includes caching one or more sections of the plurality of sections of data onto one or more caches nodes of a plurality of cache nodes. The method further includes storing, for each section of data, the identity of the particular cache node on which the section of data is cached. | 2008-08-21 |
20080201550 | AUTONOMICALLY SUSPENDING AND RESUMING LOGICAL PARTITIONS WHEN I/O RECONFIGURATION IS REQUIRED - A partition manager includes an I/O reconfiguration mechanism and a logical partition suspend/resume mechanism that work together to perform autonomic I/O reconfiguration in a logically partitioned computer system. When I/O reconfiguration is required, the affected logical partitions are suspended, the I/O is reconfigured, and the affected logical partitions are resumed. Because the logical partitions are suspended during I/O reconfiguration, any ghost packet that may occur when the I/O is reconfigured is ignored. | 2008-08-21 |
20080201551 | Virtual disk router system and virtual disk access system and method therefor - A virtual disk (VD) router system, a VD access system, and a method therefor, applied to a dual-controller system including a first controller and a second controller, are provided. First, a mapping virtual block device (VBD) corresponding to a VD of the second controller and/or the first controller is established in the first controller and/or the second controller, and a mapping relation list and a data transmission channel of the VD and the corresponding VBD thereof are established. When the first controller/the second controller issues an access request to the VD of the second controller/the first controller, the data transmission channel is used to transmit the access request to the VD and transmit the response data to the access request from the VD. Therefore, the overall access to all the VDs in the dual-controller system can be achieved. | 2008-08-21 |
20080201552 | COMPUTER-READABLE MEDIUM STORING PROGRAM FOR CONTROLLING ARCHIVING OF ELECTRONIC DOUCUMENT, DOCUMENT MANAGEMENT SYSTEM, DOCUMENT MANAGEMENT METHOD, AND COMPUTER DATA SIGNAL - There is provided a computer-readable medium storing a program causing a computer to execute a process for controlling archiving of an electronic document, the program causing the computer to function as: a requirement memory that stores a document archive requirement for each rule; and an archive processor that judges, on the basis of the requirement memory, each document archive requirement corresponding to each rule to be applied to an electronic document to be archived, determines an archive mode which satisfies all of the judged document archive requirements, and executes a process to archive the electronic document in an archiving device in the determined archive mode. | 2008-08-21 |
20080201553 | NON-VOLATILE MEMORY SYSTEM - This non-volatile memory system includes: a non-volatile memory; and a memory controller controlling read and write of the non-volatile memory. Access control of the non-volatile memory system is performed in accordance with a logical address, using an address translation table within the memory controller that is updated in association with data write and that indicates a correlation between logical addresses provided by a host and physical addresses of the non-volatile memory. The non-volatile memory system is also configured to be able to set a system configuration and function in relation to the host. | 2008-08-21 |
20080201554 | Optional Function Multi-Function Instruction - A method, system and program product for executing a multi-function instruction in a computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selected function is an installed optional function, wherein the capability query determines which optional functions of the one or more optional functions are installed on the computer system. | 2008-08-21 |
20080201555 | Image processing apparatus, method for controlling image processing apparatus, control program, and recording medium - An image processing apparatus is disclosed that includes an image processing unit section and an information processing unit section. The image processing unit section includes an image scanner that performs an image processing function and a SDK application that expands and controls the function of the image processing apparatus. The information processing unit section includes an operations panel that selectively performs operations between a basic application and the SDK application and a MFP service that transmits an instruction signal to the SDK application so as to control the image scanner in accordance with the operation on the operations panel. The information processing unit section confirms the corresponding relationship between the MFP service and the SDK application when the image processing apparatus performs a starting process and makes the SDK application correspond to the MFP service in accordance with the confirmation results. | 2008-08-21 |
20080201556 | PROGRAM INSTRUCTION REARRANGEMENT METHODS IN COMPUTER - A program instruction rearrangement method calculates the dependency depth of each instruction of a program based on dependency between instructions, based on register access order, and rearranging instructions based on the dependency depth. Additionally, the dependency between instructions can be utilized to locate and remove redundant instructions. | 2008-08-21 |
20080201557 | Security Message Authentication Instruction - A method, system and computer program product for computing a message authentication code for data in storage of a computing environment. An instruction specifies a unit of storage for which an authentication code is to be computed. An computing operation computes an authentication code for the unit of storage. A register is used for providing a cryptographic key for use in the computing to the authentication code. Further, the register may be used in a chaining operation. | 2008-08-21 |
20080201558 | PROCESSOR SYSTEM - A processor system according to an aspect of the present invention has a pipeline. The pipeline includes a cache memory, an instruction fetch buffer which stores commands, an execution module which requests data access to the cache memory, a tag memory which outputs information related to the data access of the execution module, and an arbitration circuit which arbitrates access to the cache memory based on entry information of the instruction fetch buffer and the information related to the data access from the tag memory. | 2008-08-21 |
20080201559 | Switching Device and Corresponding Method for Activating a Load - A cost-effective safety concept for safety-relevant applications in motor vehicles accordingly activates a load not directly from a central unit, but instead indirectly via a switching device. The latter has a first and a second register for the acquisition of the same control data from the central unit, and a third register for outputting data to the load. A transmission device transmits data from the second register to the third register. A first comparison logic compares a content of the second register with that of the third register and sends an interrupt to the central unit, when the two contents are not identical. A second comparison logic compares the content of the first and second registers and enables the transmission device, when the contents of the two registers are identical and otherwise blocks the transmission device. The last held state is thus maintained in the event of an error. | 2008-08-21 |
20080201560 | VERY LONG INSTRUCTION WORD (VLIW) COMPUTER HAVING EFFICIENT INSTRUCTION CODE FORMAT - A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a very long instruction word. Further, the very long instruction word includes a register specifying field which specifies a least one of the registers in the register file and a plurality of instructions. The operand of each instruction includes bits src | 2008-08-21 |
20080201561 | MULTI-THREADED PARALLEL PROCESSOR METHODS AND APPARATUS - A processor system, a processor readable medium and a method for implementing multiple contexts on one or more SPE are disclosed. | 2008-08-21 |
20080201562 | DATA PROCESSING SYSTEM - The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode. | 2008-08-21 |
20080201563 | Apparatus for Improving Single Thread Performance through Speculative Processing - An apparatus is provided for using multiple thread contexts to improve processing performance of a single thread. When an exceptional instruction is encountered, the exceptional instruction and any predicted instructions are reloaded into a buffer of a first thread context. A state of the register file at the time of encountering the exceptional instruction is maintained in a register file of the first thread context. The instructions in the pipeline are executed speculatively using a second register file in a second thread context. During speculative execution, cache misses may cause loading of data to the cache may be performed. Results of the speculative execution are written to the second register file. When a stopping condition is met, contents of the first register file are copied to the second register file and the reloaded instructions are released to the execution pipeline. | 2008-08-21 |
20080201564 | DATA PROCESSOR - An object of the present invention is to achieve fast data processing. A unit (FF) is included for selecting whether a central processing unit (CPU) performs instruction reading in units of 16 bits (a first word length) or in units of 32 bits (a second word length). Depending on whether instruction reading is performed in units of 16 bits or 32 bits, increment values (+2 and +4) by which a program counter (PC) is incremented are switched. Data reading or writing is performed in units of a given data length irrespective of the selecting unit. When the CPU issues a request for instruction reading in units of 16 bits or 32 bits or for data reading or writing, a bus control unit performs reading or writing a predetermined number of times according to a bus width designated for a resource located at an address specified in the request. The bus control unit causes the CPU to wait until an instruction of 16 or 32 bits long (read data) requested by the CPU gets ready. | 2008-08-21 |
20080201565 | CONTEXT SWITCH DATA PREFETCHING IN MULTITHREADED COMPUTER - An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching. | 2008-08-21 |
20080201566 | METHOD AND APPARATUS FOR MEASURING PIPELINE STALLS IN A MICROPROCESSOR - A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares the number of stall cycles to the deterministic execution latency pattern. The process identifies the instruction as a dependent instruction in response to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed. | 2008-08-21 |
20080201567 | METHOD OF DOING PACK UNICODE ZSERIES INSTRUCTIONS - Emulation methods are provided for two PACK instructions, one for Unicode data and the other for ASCII coded data in which processing is carried out in a block-by-block fashion as opposed to a byte-by-byte fashion as a way to provide superior performance in the face of the usual challenges facing the execution of emulated data processing machine instructions as opposed to native instructions. | 2008-08-21 |
20080201568 | VERSION-RESILIENT LOADER FOR CUSTOM CODE RUNTIMES - A method and system for dynamically identifying and loading a version of a runtime for custom code of a host application without modifying the host application is provided. A loading system dynamically identifies the version of the runtime during execution of the host application. The loading system is also dynamically linked into the host application so that its algorithm for identifying the version of the runtime can be modified without modifying the host application. When requested by the host application to load custom code, the loading system identifies a version of the runtime to load, loads the identified version of the runtime, and then requests a load component of the loaded version of the runtime to load the custom code. | 2008-08-21 |
20080201569 | DUAL CPU INVERTER SYSTEM AND METHOD FOR THE SAME - A dual CPU inverter system includes a power module and a control module electrically connected to each other and each having a CPU, a RAM and a ROM. After power on, the two modules can read the respective ROM data to the respective RAM to speed up the ready state. When external IO intends to store command parameters, the dual CPU inverter system can judge which module is the destination for the command parameter and send the command parameter to the ROM respectively. Therefore, the communication load between the two modules can be reduced. | 2008-08-21 |
20080201570 | Apparatus, Method and Product for Selecting an iSCSI Target for Automated Initiator Booting - An apparatus, method and product for selecting an iSCSI target for us in automatically booting a remote initiator is disclosed. A policy engine is created for use in a discovery domain of an iSCSI device. A boot attribute setting within the policy engine is set for selecting an iSCSI target to allow the remote initiator to automatically log onto the selected target for booting. | 2008-08-21 |
20080201571 | SYSTEM AND METHOD FOR MANAGING BOOT IMAGES IN A RETAIL STORE ENVIRONMENT - The present invention is a system for managing boot images in a retail store environment. The system includes a server. The system further includes a plurality of client devices communicatively coupled with the server. A first client device included in the plurality of client devices is configured for downloading a first portion of a boot image from the server via a first connection. The first client device is further configured for downloading a second portion of the boot image from a second client device included in the plurality of client devices via a second connection. | 2008-08-21 |
20080201572 | Method and system for uniformizing product data embedded in a computer platform - A method uniformizes product data embedded in a computer platform equipped with a first-type control unit stored with first product data, and a second-type control unit stored with second product data. The method includes recording a first time value when the first product data are modified; recording a second time value when the second product data are modified; reading the first and second time values when either one of a power-on procedure and a resetting procedure is performed on the computer platform; comparing the first time value with the second time value and determining whether the first time value is identical to the second time value; and updating one of the first product data and the second product data having an earlier one of the first and second time values with the other if the first time value is determined to be not equal to the second time value. | 2008-08-21 |
20080201573 | OPERATING SYSTEM REBOOTING METHOD AND APPARATUS FOR CONTINUING TO EXECUTE A NON-STOP MODULE EVEN DURING REBOOTING - A method of rebooting an operating system including a plurality of load modules in a single computer. One load module which is to be operated during rebooting of the operating system is held in a memory, while establishing a state capable of accepting interrupt to be processed by the one load module. All the other load modules are loaded in a memory of the computer. Processing of the interrupt can be executed by the one load module even during the rebooting of the operating system. | 2008-08-21 |
20080201574 | Data encryption apparatus, data decryption apparatus, data encryption method, data decryption method, and data relay apparatus - A RAID system includes a RAID controller that sends to a disc apparatus data to be encrypted by a data relay apparatus connected to the RAID controller and the disk apparatus. When receiving a data transfer request packet indicating a first receivable size, the data relay apparatus establishes a second receivable size that is equal to or greater than the first receivable size and that is a multiple of an encryption data size. When the RAID controller receives a data transfer request packet containing the established second receivable size, and in response to the data transfer request packet thus received, the data relay apparatus receives data of the second receivable size sent from the RAID controller. The data relay apparatus also encrypts the received data in units of the encryption data size, and then the encrypted data is sent to the disk apparatus in units of the first receivable size. | 2008-08-21 |
20080201575 | Systems and methods for automating certification authority practices - Systems and methods for efficiently verifying identities and for generating and signing digital certificates associated with those identities are disclosed. Generation of a digital certificate of an entity may begin by receiving a certificate signing request from the entity at a certification authority, the certificate signing request including verification information. The certificate signing request may be transmitted to a registration authority and the information of the certificate signing request may be processed. Whether to approve the certificate signing request may be determined, based on a result of the processing, and an approval may be granted when the certificate signing request is approved. A certificate associated with the entity may be generated when the approval is received, and the certificate may be transmitted to the entity. | 2008-08-21 |
20080201576 | Information Processing Server And Information Processing Method - An information-processing server ( | 2008-08-21 |
20080201577 | AUTHENTICATION DEVICE AND METHOD - An apparatus for generating intermediate cryptogram data corresponding to a dynamic password for a first cryptographic scheme, the intermediate cryptogram data being suitable for display using a device designed for a second, different cryptographic scheme, the apparatus including: a communications interface for communicating with a said device; and a processor coupled to a memory, the memory storing processor control code to control the processor, when running, to: generate a dynamic password according to the first cryptographic scheme; and generate intermediate cryptogram data corresponding to said dynamic password, the intermediate cryptogram data being suitable for outputting to the said device so that, when the said device processes said intermediate cryptogram data according to the second cryptographic scheme, the said device generates data suitable for displaying said dynamic password. | 2008-08-21 |
20080201578 | Computer security using visual authentication - A physical token to the user in the form of a unique card having a grid of images thereon. Each column and row of images has a unique text string of text. In addition, each user knows a special image, not necessarily present on the token card, on which one particular point or zone functions as an extra authentication feature. Users may be queried for a username, then shown a random one of the images on their card, and asked for the row text string plus column text string identifying the image. Users are also prompted to select their particular point or zone within their known special image, which is displayed, among a jumble of other images, by the computer system requesting authorization, such display serving to authenticate the computer system to the user. The system may be combined with password protection and methods to identify a user's machine. | 2008-08-21 |
20080201579 | Biometric based repeat visitor recognition system and method - A biometric authorization method, system, and program product Biometric data associated with a subject can be detected and acquired. Thereafter, particular biometric features can be segmented and extracted from the biometric data. These particular biometric features are then compared to biometric data previously stored in a database in order to determine if the particular biometric features match the biometric data previously stored in the database and thereby rapidly and automatically determine if the subject comprises a repeat visitor. | 2008-08-21 |
20080201580 | TRUSTWORTHY TIMESTAMPS AND CERTIFIABLE CLOCKS USING LOGS LINKED BY CRYPTOGRAPHIC HASHES - A method and apparatus for creating and/or using trustworthy timestamps and certifiable clocks using logs linked by cryptographic hashes. In one embodiment, the method comprises maintaining a first, chained-hash log; associating a first clock with the chained-hash log, and entangling the first log; with a second by adding a time-stamped synchronization entry to the chained-hash log, where the synchronization entry has a second time indication associated with the second log and a hash of one or more entries in the first log. | 2008-08-21 |
20080201581 | Method and apparatus for storing data - According to an aspect of an embodiment, a method comprises providing a matrix comprising m rows and n columns, each of the rows and columns comprising elements of zero and one, dividing data into n data blocks, associating each of the data blocks with each of the columns, calculating an exclusive-OR of selected data blocks in reference to one of the rows, the selected data blocks being determined by the element of one in the associated columns in the one of the rows, repeating the calculating in other rows and storing separately the calculated data resulting from the exclusive-OR of data blocks in association with the associated rows, respectively. | 2008-08-21 |
20080201582 | Method for Setting an Electrical Field Device - A method for adjusting an electric field device in order to simplify its operation includes the following steps: an electronic control unit of the field device identifies an external data storage module that is connected to the field device; the electronic control unit reads personal data allocated to a user of the data storage module out of the external data storage module; the electronic control unit makes adjustments on the field device based on the personal data that has been read. | 2008-08-21 |
20080201583 | POWER SUPPLY CONTROL CIRCUIT - A power supply control circuit has an input unit which receives a supply of a power supply from one or a plurality of power supply source apparatuses, and has plural input lines including a first input line and a second input line at least, an output unit which outputs the supplied power supply to a power supply destination apparatus, a current control unit which is arranged between the first input line and the output unit, and includes a first diode D | 2008-08-21 |
20080201584 | SEMICONDUCTOR INTERGRATED CIRCUIT AND METHOD FOR CONTROLLING SEMICONDUCTOR INTERGRATED CIRCUIT - Herein disclosed is a method for controlling a semiconductor integrated circuit having plural domains, the method including controlling plural power supplies which supply power to the plural domains, controlling an asynchronous bridge section being provided between each of the domains, receiving and transmitting data for dynamically changing a power supply voltage of at least one of the domains, wherein, when a power supply voltage of one of the domains is substantially equal to a power supply voltage of the other domains, switching the power supply paths so as to supply the power supply voltage from one power supply to at least two of the domains, and switching the data paths so as to receive and transmit data between the at least two of the domains by bypassing the asynchronous bridge section. | 2008-08-21 |
20080201585 | Multifunctional machine and method of controlling multifunctional machine - A multifunctional machine includes a first component section that starts up taking a first time period, and a second component section that starts up taking a second time period shorter than the first time period. An operation start prediction information obtaining section is provided to obtain operation start prediction information predicting a time when a user starts the multifunctional machine. A start up control section is provided to start up the first component section in advance of the second component section. A power supply control section is provided to supply power from at least one external power source and drive the start up control section in accordance with the operation start prediction information. | 2008-08-21 |
20080201586 | Integrated circult device and electronic instrument - An integrated circuit device includes a digital power supply regulation circuit, an analog power supply regulation circuit, a control logic circuit, an analog circuit, and a power supply wiring region. A digital power supply line which supplies a digital power supply voltage and an analog power supply line which supplies an analog power supply voltage are provided in the power supply wiring region. The digital power supply regulation circuit, the analog circuit, and the analog power supply regulation circuit are disposed in a first direction with respect to the control logic circuit. The power supply wiring region is formed along a second direction in a region between the control logic circuit and the digital power supply regulation circuit, the analog circuit, and the analog power supply regulation circuit. | 2008-08-21 |
20080201587 | ANTICIPATORY POWER MANAGEMENT FOR BATTERY-POWERED ELECTRONIC DEVICE - Methods and apparatus for managing power consumption of a battery-powered electronic device are disclosed. According to one embodiment, power management can take action to reduce power consumption to accommodate estimated power requirements. According to another embodiment, power management can notify a user when a power deficiency is anticipated. According to still another embodiment, power management can advise a user to charge a battery of the battery-powered electronic device. According to still another embodiment, a user can influence power management by user selections. | 2008-08-21 |
20080201588 | SEMICONDUCTOR DEVICE AND METHOD FOR REDUCING POWER CONSUMPTION IN A SYSTEM HAVING INTERCONNECTED DEVICES - A system includes a plurality of memory devices connected in-series that communicate with a memory controller. A memory device designated by an ID number performs operations at a normal power consumption level. The other devices not designated perform signal forwarding operations at a reduced power consumption level. The designated memory device enables its internal clock generator to generate all clocks necessary for operations. The non-designated memory devices generate clocks to perform partial operations for forwarding commands to next memory devices. In another example, memory devices do not forward the input command to the next memory device when there is no ID match. In another example, a memory device transmits the command replacing the content thereof with a static output when there is an ID match. Such partial clock generation, non-forwarding of commands and replacing the command contents will cause the system to operate at the reduced power consumption level. | 2008-08-21 |
20080201589 | Maximum power usage setting for computing device - A maximum power usage setting for a computing device is based on one or more of: a user-specified setting corresponding to how often a frequency of a processor of the computing device is likely to have to be decreased to reduce power usage by the computing device; an average frequency of the processor during a previous period in which the computing device was operated; a minimum frequency of the processor during the previous period; a maximum power that the computing device used during the previous period; and, a nominal frequency of the processor. When the computing device starts to use more power than the maximum power usage setting, the power used by the computing device is reduced so as not to exceed the setting, such as by decreasing the frequency at which the processor operates. | 2008-08-21 |
20080201590 | Method and apparatus to adapt the clock rate of a programmable coprocessor for optimal performance and power dissipation - A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determined by the compiler and enforced at runtime by software-controlled clock circuitry. Power dissipation savings and optimal resource usage are therefore achieved by the adaptation at runtime of the coprocessor clock rate for each of the various kernel loop implementations. | 2008-08-21 |
20080201591 | Method and apparatus for dynamic voltage and frequency scaling - A machine learning technique is used to improve dynamic prediction of processor utilization for multi-threaded user-level applications in a dynamic run-time environment based on processor utilization history. Processor supply voltage and processor clock frequency may be dynamically scaled based on the predicted processor utilization in order to reduce processor power consumption. | 2008-08-21 |
20080201592 | Hibernating a processing apparatus for processing secure data - A data processing apparatus for processing secure data is disclosed. The data processing apparatus comprising: processing circuitry comprising a plurality of state retention cells in the form of scan chains for holding a current state of said processing circuitry, at least some of the state retention cells being arranged in series; encryption circuitry; and a hibernate signal input; said data processing apparatus being responsive to receipt of a hibernate signal at said hibernate signal input to switch from an operational mode in which said data processing apparatus is powered up, to a low power mode in which at least said processing circuitry is powered down, said data processing apparatus being operable prior to powering down said processing circuitry, to output a state of said processing circuitry from said plurality of state retention cells and to encrypt said output state using said encryption circuitry and to save said encrypted state to said storage device. | 2008-08-21 |
20080201593 | Storage control device - The storage control device of the present invention reduces the power consumption amount by stopping the transmission of power to enclosures that are not accessed. A plurality of additional enclosures are switch-connected via backend switches to a base enclosure. Drives that have not been accessed for a predetermined time or more undergo spin-down. When all of the drives in the enclosure enter a spin-down state, the supply of power from the power supply in the enclosure to the respective drives is stopped. The base enclosure that manages the system constitution of the storage control device turns OFF the switch connected to the enclosure when all of the drives in a certain enclosure have spun down. The transmission of power to this enclosure is accordingly stopped. | 2008-08-21 |
20080201594 | ELECTRONIC APPLIANCE, METHOD OF SETTING RETURN INTERFACE, RETURN COMMUNICATION METHOD AND COMPUTER PROGRAM - An electronic appliance designed for low power consumption mode having a plurality of hardware interfaces mounted thereon for communication with an external device is disclosed. The electronic appliance includes a return interface setting part configured to variably set a part of the plurality of the hardware interfaces as a return interface that waits for receiving a return signal. | 2008-08-21 |
20080201595 | INTELLIGENT POWER CONTROL - An intelligent power control system for intelligently controlling startup and shutdown sequences of IT equipment to reduce peak power requirements is provided. The intelligent power control system sends an indication to power up to a power module connected to an electronic device. The system monitors the power consumption of the electronic device during startup, and determines when the electronic device has reached a peak level of power consumption. The system then powers up other devices based on the power consumption characteristics of each preceding device. The system may use similar techniques when shutting down devices or transitioning devices from a low-power state to a normal power state. Thus, the intelligent power control system establishes an order and timing for powering up or down electronic devices that improves the power consumption characteristics of the electronic devices and reduces the power requirements of the electronic devices allowing smaller, lighter, and less expensive power supplies and battery backup systems to be used. | 2008-08-21 |
20080201596 | Clock buffer circuit of semiconductor device - A clock buffer circuit of a semiconductor device is disclosed which receives an external clock signal and generates an internal clock signal with no duty distortion. The clock buffer circuit includes a first clock buffer for receiving and buffering a normal-phase clock signal, a second clock buffer for receiving and buffering a reverse-phase clock signal, and an internal clock generator for generating an internal clock signal in response to output signals from the first and second clock buffers. | 2008-08-21 |
20080201597 | WRITE-LEVELING IMPLEMENTATION IN PROGRAMMABLE LOGIC DEVICES - Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by clocking the DQ/DQS signals with a phase delayed clock signal, where the phase delay has been calibrated. In one example calibration routine, a clock signal is provided to a receiving device. A DQ/DQS signal is also provided and the timing of their reception compared. A delay of the DQ/DQS signal is changed incrementally until the DQ/DQS signal is aligned with the clock signal at the receiving device. This delay is then used during device operation to delay a signal that clocks registers providing the DQ/DQS signals. Each DQ/DQS group can be aligned to the clock, or the DQS and DQ signals in a group may be independently aligned to the clock at the receiving device. | 2008-08-21 |
20080201598 | Device and Method For Preventing Lost Synchronization - A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a synchronization clock from received data. A connection failure processor performs a connection failure process if synchronization based on the synchronization clock between connection nodes is not established when a first predetermined time from when the reception of the received data is started elapses. A correction processor corrects operation of the CDR circuit if synchronization based on the synchronization clock between connection nodes is not established when a second predetermined time, which is shorter than the first predetermined time, from when the reception of the received data is started elapses. | 2008-08-21 |
20080201599 | COMBINED ALIGNMENT SCRAMBLER FUNCTION FOR ELASTIC INTERFACE - An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat. | 2008-08-21 |
20080201600 | DATA PROTECTION METHOD OF STORAGE DEVICE - A data protection method of a storage device is provided. In the method, a system management interrupt program orders a hardware control unit to obtain a type and an address message of an error in a block in a first storage device, and stores the type and address message in a second storage device. An interrupt service routine (ISR) reads the type and address message of the error from the second storage device. The ISR orders an operating system to search for a block that may be accessed normally and not damaged in the first storage device, and sets the block as a reserved block. The ISR transmits the address message of the error to the OS, such that the OS copies the data in the block having the error to the reserved block, thereby increasing the available capacity of the storage device and improving the reliability of the computer. | 2008-08-21 |
20080201601 | Method and Apparatus for Elimination of Faults of a Data Processing System - A method for fault handling of a data processing unit is disclosed. The method includes automatic acquisition of input information and/or output information of a user at at least one user interface of the data processing unit; automatic detection of a fault message that indicates a fault of the data processing unit; transmission of the acquired fault message together with the input information and/or the output information to a fault handling center; and evaluation of the transmitted fault message in the fault handling center. | 2008-08-21 |
20080201602 | Method and apparatus for transactional fault tolerance in a client-server system - Method and apparatus for transactional fault tolerance in a client-server system is described. In one example, output data generated by execution of a service on a primary server during a current epoch between a first checkpoint and a second checkpoint is buffered. A copy of an execution context of the primary server is established on a secondary server in response to the second checkpoint. The output data as buffered is released from the primary server in response to establishment of the copy of the execution context on the secondary server. | 2008-08-21 |
20080201603 | CORRELATING HARDWARE DEVICES BETWEEN LOCAL OPERATING SYSTEM AND GLOBAL MANAGEMENT ENTITY - A method and apparatus for correlating the identities of hardware devices, such as processors and memory controllers, between a local operating system and a global management entity is described. When the operating system detects a faulting device, the operating system generates a fault message and transmits the fault message to the global management entity. The global management entity determines the identity of the faulting device based on information contained in the fault message, selects an appropriate replacement device, changes a routing table to map to the replacement device to the identity of the faulting device, and transmits to the operating system a global identity of the replacement device. The operating system correlates the local identity of the replacement device with the global identity of the replacement device. | 2008-08-21 |
20080201604 | Kernel Error Recovery Disablement and Shared Recovery Routine Footprint Areas - A method, computer program product, and data processing system for providing optional failure recovery features in operating system kernel code are disclosed. In accordance with a preferred embodiment, a segment of mainline code may designate a recovery routine for that segment by calling a kernel service provided for that purpose. The kernel service allocates a “footprint” region on the recovery stack for storing state information arising from the execution of the recovery-enabled code. In the event of an exception, a recovery manager routine uses information from the recovery stack to recover from the exception. Recovery may be disabled altogether for performance purposes by way of boot-time patching to disable the use of the recovery stack and to allow state information to be written to a static “scratchpad” area, which unlike the recovery stack, is allowed to be overwritten, its contents being ignored. | 2008-08-21 |
20080201605 | Dead man timer detecting method, multiprocessor switching method and processor hot plug support method - A Dead man timer detecting method, a multiprocessor switching method, and a processor hot plug support method are provided. A hot spare boot control register communicated with the Dead man timer is used to detect functions of the Dead man timer, such as enabling, timing, disabling, and responding. After an operation system is booted, the Dead man timer is used to achieve automatic switch among multiple processors and the support for the processor hot plug. The method can detect various functions of the Dead man timer, and be switched among multiple processors automatically and periodically, without being limited by the type of operation systems and processors, and realize the support to the processor hot plug, thereby improving the safety for the hot plug operation. | 2008-08-21 |
20080201606 | Recovery Routine Masking and Barriers to Support Phased Recovery Development - A method, computer program product, and data processing system for providing optional exception recovery features in operating system kernel code are disclosed. In a preferred embodiment, a segment of mainline code may designate a recovery routine for that segment by calling a kernel service provided for that purpose. The kernel service pushes the address of the designated recovery routine, context, and re-entry point information corresponding to the segment to a recovery stack. An additional “footprint” region is also allocated on the recovery stack and used to store other state information needed for recovery. A mask value or barrier count value is also stored on the recovery stack to allow recovery to be disabled for non-recoverable routines. | 2008-08-21 |
20080201607 | DISASTER RECOVERY IN A DATA PROCESSING SYSTEM - The present invention relates to a method of disaster recovery in data processing systems and to a recovery system. The invention allows for easy, fast and reliable recovery of a data processing system in a disaster situation. Unmodified backup data is stored to a target data processing system, the hardware of the target data processing system being different from the hardware of the source data processing system, from which the backup data originated. The stored backup data is then adapted to the hardware of the target data processing system by a remote recovery system using previously obtained reference data. | 2008-08-21 |
20080201608 | RECOVERING FROM ABNORMAL INTERRUPTION OF A PARITY UPDATE OPERATION IN A DISK ARRAY SYSTEM - Data associated with the state of a parity update operation in a disk array system such as a RAID-6 system is stored during performance of the operation so that, in the event the operation is interrupted, recovery may be initiated using the stored data. The stored data may include a state indicator that is indicative of the status of the parity update operation, and snapshot data (e.g., a delta value indicative of a difference between new and old data) captured during the parity update operation. | 2008-08-21 |
20080201609 | METHOD AND SYSTEM FOR AUTOMATICALLY DIAGNOSING DISABILITY OF COMPUTER PERIPHERAL DEVICES - A method and a system for automatically diagnosing disability of computer peripheral devices are provided. In the method, a set of interrupt configuration data relevant to a disabled PCI peripheral device, including relevant setting values of a hardware IRQ routing, is input and compared with a PCI IRQ routing table pre-stored in a boot control unit. Then, whether errors exist in the current setting values of the relevant control parameters and flags of all the relevant control units are automatically checked. If an incorrect setting value is found, a corresponding diagnosis result message is displayed for informing the user to make a modification. Therefore, users can know the reasons that cause the computer peripheral device to operate abnormally and make the modification quickly and effectively. | 2008-08-21 |
20080201610 | Integrated test method on multi-operating system platform - An integrated test method on a multi-operation system (OS) platform for performing an integrated test of a file system and disk performance in a computer with an extended firmware interface (EFI) system environment on multiple OS platforms is provided. The method includes the following steps. Scan sectors of an entire physical hard disk and perform a hardware underlying test of a disk device in the EFI environment; select and load an OS, then enter the OS environment to test the file system and the disk performance in the system environment; exit from the OS and return to the EFI environment to summarize a test result; determine whether it is necessary to load other OSes, if necessary, return and load other OSes, and if not, send the summarized test result to a server terminal for analysis and processing. | 2008-08-21 |
20080201611 | Defect Resolution Methodology Target Assessment Process - Embodiments of the invention are generally related to computer systems, and more specifically to the analysis of defects in computer software products. Defects uncovered during software testing may be stored in a data structure as data defects, code defects, or environment defects, along with further data describing a particular nature of the defects. The defects may be analyzed to determine a particular problem area causing the defects. If a particular class of defects is determined to be the dominant class of defects encountered during testing, an analysis path of that class of defects may be followed to determine a cause for the defects in the respective class. Therefore, corrective measures tailored to resolving the defects associated with the determined cause may be taken. | 2008-08-21 |
20080201612 | Defect Resolution Methodology and Data Defects Quality/Risk Metric Model Extension - Methods, systems, and articles of manufacture for analyzing defects associated with a software development project. Descriptions of defects identified during the testing of a software product may be stored in a data structure. One or more of the defects may be identified as data defects. If data defects are determined to be the dominant class of defects in the data structure, the data defects may be analyzed to determine a cause for one or more data defects. For example, the focus areas affected by the defects, the trends over time of the defects, the particular types of the data defects, the stability of the system, etc. may be analyzed to determine a cause for the data defects. Therefore, corrective measures may be taken based on the identified cause of the one or more data defects. | 2008-08-21 |
20080201613 | METHODS AND SYSTEMS FOR FIRST OCCURENCE DEBUGGING - An embodiment relates generally to an apparatus for debugging. The apparatus includes a memory configured to store data and an arithmetic logic unit configured to perform logical and arithmetic operations. The apparatus also includes a control unit configured to interface with the memory and arithmetic logic unit and to decode instructions. The control unit is configured to write a data state designated to be overwritten by a currently executing instruction to a buffer allocated in the memory in response to a trace debug flag being set. | 2008-08-21 |
20080201614 | Peripheral component interconnect bus test system and method therefor - A peripheral component interconnect (PCI) bus test system and method therefor, that is applied in a PCI test card. The PCI test card includes a static random-access-memory (SRAM). In the method, the data transaction of the PCI bus signal is disintegrated into a separate data operation, while eliminating the waveform interfering transaction. Through comparing the waveform of the data operation as separated from a PCI bus signal with the standard PCI bus waveform, the quality of the PCI bus signals can be precisely analyzed, thus realizing the hardware test of PCI bus. | 2008-08-21 |
20080201615 | APPARATUS AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING ATOMIC DATA TRACING - A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU). The auxiliary processor unit (APU) processes a trace instruction. When a trace instruction is identified by the APU, the APU signals the CPU with a pipeline stall signal for stalling the CPU and checks for an enabled trace engine as specified by the trace instruction. When the trace engine for the trace instruction is enabled, then the trace data is written into a trace buffer. The APU signals the CPU with an op done signal for allowing the CPU to continue with instruction processing. | 2008-08-21 |
20080201616 | REDUNDANT STORAGE CONTROLLER SYSTEM WITH ENHANCED FAILURE ANALYSIS CAPABILITY - A redundant storage controller system that robustly provides failure analysis information (FAI) to an operator of the system is disclosed. The system includes first and second storage controllers in communication with one another, such as via a PCI-Express link. When one of the controllers fails, the FAI is transferred from the failed controller to the surviving controller over the link. The operator issues a command to the surviving storage controller, which responsively provides the FAI. In one embodiment, the failed storage controller writes the FAI to the second storage controller. In one embodiment, each storage controller periodically writes the FAI before there is a failure. In one embodiment, the second storage controller reads the FAI from the failed storage controller. The FAI may include boot logs, crash logs, debug logs, and event logs. The FAI may also be written to a disk drive connected to the controllers. | 2008-08-21 |
20080201617 | Network device and network system - A network device and a network system are disclosed. The network device ( | 2008-08-21 |
20080201618 | Method for Running a Computer Program on a Computer System - Errors which may be detected by an error detection unit may occur during execution of a computer program which runs on a computer system and includes at least one run-time object. In order to handle a detected error particularly flexibly and to keep the computer system available as much as possible, an error handling routine is selected from a pre-selectable set of error handling routines as a function of an identifier assigned to the run-time object and the selected error handling routine is executed. | 2008-08-21 |
20080201619 | ERROR CORRECTING DEVICE, ERROR CORRECTING METHOD AND DISK SYSTEM - There is provided an error correcting device, including: a demodulation circuit that reads data from an optical disk and demodulates the data to generate demodulated data; a PI syndrome generation circuit that generates a PI syndrome of the demodulated data and outputs the PI syndrome to an external memory; a PO syndrome generation circuit that generates a PO syndrome of the demodulated data and outputs the PO syndrome to the external memory; and an error correcting circuit that reads the PI syndrome and the PO syndrome from the external memory and performs error correction on the demodulated data stored in the external memory, based on the syndromes. | 2008-08-21 |
20080201620 | METHOD AND SYSTEM FOR UNCORRECTABLE ERROR DETECTION - A system, method and program product for utilizing error correction code (ECC) logic to detect multi-bit errors. In one embodiment, a first test pattern and a second test pattern are applied to a set of hardware bit positions. The first and second patterns are multiple logic level patterns and the second test pattern is the logical complement of the first test pattern. The first and second test patterns are utilized by the ECC logic to detect correctable errors having n or fewer bits. One or more bit positions of a first correctable error occurring responsive to applying the first test pattern are determined and one or more bit positions of a second correctable error occurring responsive to applying the second test pattern are determined. The determined bit positions of the first and second correctable errors are processed to identify a multiple-bit error within the set of hardware bit positions. | 2008-08-21 |
20080201621 | TEST APPARATUS - It is an object of the test apparatus according to the present invention to effectively manage test results. The test apparatus includes a test section that executes testing of each cell of the memory under test; a fail information storage section that stores in a fail memory fail information corresponding to each cell of the memory under test that indicates pass/fail of each cell; a counting section that counts a number of defective cells detected in each block for every block in the memory under test; a reading request receiving section that receives a request to read the fail information of each cell included in each block; a comparing section that compares the number of defective cells in a reading target block to a predetermined reference number; a converting section that, in a case where the number of defective cells in the reading target block exceeds the predetermined reference value, converts into a value indicating defectiveness a plurality of consecutive pieces of fail information in a response data string that includes the fail information of each cell in the reading target block to be returned in response to the reading request; and a compressing section that compresses the response data string and returns the compressed response data string. | 2008-08-21 |
20080201622 | Non-Volatile Memory Device Manufacturing Process Testing Systems and Methods Thereof - Systems and methods of manufacturing and testing non-volatile memory (NVM) devices are described. According to one exemplary embodiment, a function test during manufacturing of the NVM modules is conducted with a system comprises a computer and a NVM tester coupling to the computer via an external bus. The NVM tester comprises a plurality of slots. Each of the slots is configured to accommodate respective one of the NVM modules to be tested. The NVM tester is configured to include an input/output interface, a microcontroller with associated RAM and ROM, a data generator, an address generator, a comparator, a comparison status storage space, a test result indicator and a NVM module detector. The data generator generates a repeatable sequence of data bits as a test vector. The known test vector is written to NVM of the NVM module under test. The known test vector is then compared with the data retrieved from the NVM module. | 2008-08-21 |
20080201623 | EMBEDDED ARCHITECTURE WITH SERIAL INTERFACE FOR TESTING FLASH MEMORIES - A flash memory device includes a flash memory array, a set of non-volatile redundancy registers, a serial interface, and testing logic coupled to the serial interface, the testing logic configured to accept a set of serial commands from an external tester; erase the array; program the array with a test pattern; read the array and compare the results with expected results to identify errors; determine whether the errors can be repaired by substituting a redundant row or column of the array, and if so, generate redundancy information; and program the redundancy information into the non-volatile redundancy registers. | 2008-08-21 |
20080201624 | Sequential semiconductor device tester - A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command. | 2008-08-21 |
20080201625 | ERROR CORRECTION SYSTEM AND METHOD - A method includes receiving payload data from a data source at error correction code (ECC) logic, where the ECC logic is adapted to process a block of data of a particular size via a plurality of stages. The ECC logic is initialized to a selected stage of the plurality of stages. The selected stage includes an initial value and an initial number of cycles. The initial value and the initial number of cycles are related to a number of symbols of padding data corresponding to a difference in size between the payload data and the block of data. The selected stage is related to a state of the ECC logic as if the number of symbols of padding data had already been processed by the ECC logic. The payload data is processed via the ECC logic beginning with the selected stage to produce parity data related to the payload data. | 2008-08-21 |
20080201626 | POWER SAVINGS FOR MEMORY WITH ERROR CORRECTION MODE - The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled. | 2008-08-21 |
20080201627 | Communication Device, Communication Method, and Computer Program - A communication device configured to perform packet reception processing, with the header of a packet including a header sequence and a Reed-Solomon code, includes: a header check sequence inspecting unit configured to detect, based on the header check sequence included in a received packet header, an error of the header; a Reed-Solomon encoding unit configured to encode the header of a received packet other than the Reed-Solomon code to generate a Reed-Solomon code; a Reed-Solomon code inspecting unit configured to detect whether or not the Reed-Solomon code generated by the Reed-Solomon encoding unit is completely identical to the Reed-Solomon code within the received packet header; and a processing control unit configured to control payload processing of a received packet in accordance with the inspection results of the header check sequence inspecting unit and the Reed-Solomon code inspecting unit. | 2008-08-21 |
20080201628 | APPARATUS AND METHOD FOR DETERMINING A DETECTED PUNCTURED POSITION IN PUNCTURED CONVOLUTIONAL CODES - An apparatus for generating a detected punctured position in punctured convolutional codes. A delay line circuit has a plurality of delay elements connected in series, storing a finite sequence of an input bit stream. A logic gate circuit, coupled to outputs of a part of the delay elements of the delay line circuit in accordance with a parity check polynomial, performs a logic operation to output a number stream. The number stream is accumulated for possible punctured positions and the one of the possible punctured positions with a minimal accumulated number is selected and determined as the detected punctured position. | 2008-08-21 |
20080201629 | METHOD AND SYSTEM FOR DETECTING SYNCHRONIZATION ERRORS IN PROGRAMS - A method and system for error detection in programs with collective synchronization and/or procedures are provided. In one aspect, the method and system may use interprocedural analysis for matching synchronizations in a program in order to detect synchronization errors, and, if no such errors exist, may determine the synchronization phases of the program. The method and system in one aspect may use a combination of path expressions and interprocedural program slicing to match the synchronization statements that may execute along each program path. If the synchronization matching succeeds, the method and system in one aspect may determine the sets of synchronization statements that synchronize together. A matching failure may indicate the presence of a synchronization error and the method and system in one aspect may construct a counter example to illustrate the error. | 2008-08-21 |
20080201630 | Storage controlling device and storage controlling method - According to an aspect of an embodiment, a method of storing user data (UD) with parity data (PD) for correcting the UD in a storage apparatus comprising disk units, each of the disk units storing data in data blocks(DBs), each of the DBs storing the UD or associated PD and position information(PI) indicative of the location of the DBs, comprising: obtaining the UD, dividing the UD into UD blocks (UDBs) which are adapted to be stored in the DBs, and determining which UDBs are to be stored into which DBs, respectively; determining PI of the DBs for storing the UDBs; generating PD for a group of UDBs and associated PI by parity operation using a weighting function to the UDBs and the PI; determining PI for the PD for said group by modifying a part of the PD; and storing the group of the UDBs, associated PI, and the PD. | 2008-08-21 |
20080201631 | Method for Error Correction Coding Comprising Local Error Detection Codes, Corresponding Decoding Method, Transmitting, Receiving and Storage Device and Program - The disclosure relates to a coding method for associating redundant and source data and for carrying out a plurality of local codes associating at least one input status word and at least one output status word according to at least one label word and permutations applicable on at least certain of said words. The local codes are embodied in the form of detection codes and not error correction codes on a predetermined coding alphabet. The local codes are interconnected by the status words in such a way that at least one coding matrix is formed, each of which defining a base code. | 2008-08-21 |
20080201632 | SYSTEM AND METHOD FOR ANNOTATING DOCUMENTS - Methods, apparatus and articles of manufacture therefor, are disclosed for annotating documents. An embodiment for annotating documents may be performed by the method of: retrieving a document selected for display by a user; locating sub-document elements in content of the retrieved document; computing a similarity measure for each of the located sub-document elements; identifying similarity measures of annotated sub-document elements and the located sub-document elements that indicate a correspondence there between; augmenting the located sub-document elements of the retrieved document with annotations of those annotated sub-document elements that have comparable similarity measures; displaying the retrieved document augmented with annotations. | 2008-08-21 |
20080201633 | METHOD AND SYSTEM FOR CONVERTING HYPERTEXT MARKUP LANGUAGE WEB PAGE TO PLAIN TEXT - A method for converting an HTML web page to plain text includes extracting from HTML source code of the HTML web page a portion containing a plurality of character strings and tags, calculating length and position of each character string in the extracted portion so as to find a first predetermined percentage of the character strings with the longest lengths, analyzing a number of position intervals between adjacent ones of the character strings belonging to the first predetermined percentage of the character strings with the longest lengths, labeling the corresponding character strings as belonging to a same block if the number of position intervals is not greater than a second predetermined value so as to find a largest character string block, and deleting the tags in the largest character string block so as to obtain main content of the HTML web page in plain text. | 2008-08-21 |
20080201634 | SYSTEM AND METHOD FOR CUSTOMIZING A USER INTERFACE - Described is a system and method for customizing a user interface. A method according to one embodiment of the present invention comprises receiving a given content item and scoring the given content item. When the score exceeds a threshold, at least a portion of the given content is highlighted. The given content item is displayed with at least the portion of the given content item highlighted. | 2008-08-21 |
20080201635 | Document edit device and storage medium - A document edit device includes: an object obtaining unit that obtains objects each being data expressing at least one of a text and an image which are included in a document as an edit target to be edited; an object selection unit that selects at least two target objects from among the objects obtained by the object obtaining unit, the target objects each being an object as a processing target to be processed; a golden rectangle forming unit that forms a golden rectangle having a predetermined positional relationship with at least one target object of the at least two target objects selected by the object selection unit, based on a size or position of the at least one target object; and a position change unit that changes positions of the at least two target objects such that they are inscribed to the golden rectangle formed by the golden rectangle forming unit. | 2008-08-21 |
20080201636 | DOCUMENT MANAGEMENT APPARATUS AND DOCUMENT MANAGEMENT METHOD - A document management apparatus according to the invention is aimed at easily processing, managing and reusing newly taken image data in accordance with user's needs. The apparatus includes: a document area analyzing unit configured to analyze and extract a document area from image data; a text information analyzing unit configured to analyze and extract text information with respect to the document area; a text information semantic analysis unit configured to analyze and extract semantics of the text information from the text information; a managing unit configured to associate the document area, the text information and the semantics of the text information with each other, and manage them as integrated information; an integrated information presenting unit configured to present to a user at least the semantics of the text information, of the integrated information managed by the managing unit; and a user-designated semantic setting unit configured to be capable of allowing the user to change the semantics of the text information presented by the integrated information presenting unit and to set the changed semantics. | 2008-08-21 |
20080201637 | IMAGE PICKUP APPARATUS, METHOD FOR CONTROLLING DISPLAY OF IMAGE PICKUP APPARATUS, AND COMPUTER PROGRAM FOR EXECUTING METHOD FOR CONTROLLING DISPLAY OF IMAGE PICKUP APPARATUS - An image pickup apparatus includes a touch panel used for displaying various screens, each including a plurality of buttons from which a user selects a desired button, a menu screen display controlling unit for controlling the touch panel to sequentially display menu screens through which the user navigates to a setting screen for setting a predetermined function in accordance with the selected buttons, and a guide screen display controlling unit for controlling the touch panel to sequentially display guide screens through which the user navigates to the setting screen in accordance with the selected buttons in a path different from that of the menu screens, each of the guide screens displaying a button or description regarding at least the purpose or effect of the operation. An initial screen of the touch panel includes a menu button for entering the menu screen and a guide button for entering the guide screen. | 2008-08-21 |
20080201638 | Context avatar - Methods and systems for generating information about a physical context of a user are provided. These methods and systems provide the capability to render a context avatar associated with the user as a composite image that can be broadcast in virtual environments to provide information about the physical context of the user. The composite image can be automatically updated without user intervention to include, among other things, a virtual person image of the user and a background image defined by encoded image data associated with the current geographic location of the user. | 2008-08-21 |
20080201639 | Apparatus and method for prompting a sequence of timed activities - The Invention is an apparatus and method for prompting a sequence of timed activities such as a program of exercise. A computer is programmed to allow a user to select an activity or a plurality of activities and the duration of each selected activity. The computer is programmed to select a first prompt and a second prompt. A sequence of activities may be selected by the user and incorporated into a composite audio file, each with its own first and second prompts. The composite audio file may include music selected by the user. The first and second prompts may instruct the user to begin and end the activity while the music provides pacing cues to allow the user to pace him or herself during the period of the activity between the first and second prompts. | 2008-08-21 |
20080201640 | System and Method for Creating and Navigating a Linear Hypermedia Resource Program - A method and system for creating and navigating linear hypermedia resource programs are disclosed. The system includes a distributed hypermedia resource network having a plurality of hypermedia resources residing on one or more remote information nodes. A common remote information node is in communication with a subscriber station and the remote information nodes in the distributed network. The common remote information node contains at least one linear hypermedia resource program consisting of pre-selected media elements from one or more hypermedia resources linked with exclusive linear links, each media element in the linear program having only one forward link to the next media element. The method includes the steps of downloading and displaying a media element in the linear program and responding to user commands to download and display the next media element in the linear program. | 2008-08-21 |
20080201641 | Method And The Associated Mechanism For 3-D Simulation Stored-Image Database-Driven Spectacle Frame Fitting Services Over Public Network - A method of spectacle frame 3-D simulation fitting over public network, such as Internet, based upon database of product information and digitized user images as acquired via devices connected to computer. Particularly, consumers can take advantage of present method to choose spectacle frames from wide variety of selections, expeditiously by the use of public computer network (Internet). Consumers may use digital cameras, network cameras or scanned photos to submit facial image, and by way of calibration steps and additional side-view images of the consumers when test-fitting spectacle frames, simulated 3-D presentation of a consumer wearing the intended spectacle frame can be viewed for purpose of fitting and purchasing over the network. With the accessibility and availability of the Internet, just a few clicks on the mouse enable the consumers to choose spectacle frames of their preference and in a way that affords wide selections at low costs and easy access. | 2008-08-21 |
20080201642 | PROBLEM DETERMINATION IN DISTRIBUTED ENTERPRISE APPLICATIONS - A method, system and computer program are provided for problem determination in an enterprise computer system in a distributed environment. In the method, information is obtained regarding the enterprise applications, and high-level information is presented to a user, with one or more prompts are provided to the user for more detailed information. In response to a request from a user for more detailed information about the application, more detailed information is provided to the user. Several levels of more detailed information about applications, including information as to individual threads, is available. The method also includes the steps of receiving instructions from an administrator to establish an account for a user, associating one or more servers with the account, and providing access to the corresponding user only to the associated servers. In the method, searches may be conducted for strings and requests, and identified strings and requests may be sorted by a variety of criteria. | 2008-08-21 |
20080201643 | System for creating customized web content based on user behavioral portraits - A method is provided for determining a website user behavioral portrait based on navigation on the website and dynamically reconfiguring web pages based on those portraits. In accordance with the method, data relating to the progress of a user through a website is recorded, and an ongoing behavioral portrait of the user is built based on the data. The portrait is then used to dynamically reconfigure web content. | 2008-08-21 |
20080201644 | HARDWARE CURSOR SNOOPING - A feedback subsystem may be used to control the positioning of a local cursor of a display in response to receiving remote cursor movement information from a remote computer system. The feedback subsystem may send the remote cursor movement information to an operating system (OS) which may send local coordinate information to a graphics controller. Local coordinate information from the graphics controller may be used to compare with remote coordinate information received from the remote computer system. The feedback subsystem may repeatedly send the remote cursor movement information to the OS until it is determined that the local coordinate information from the graphics controller is consistent with the remote coordinate information received from the remote computer system. | 2008-08-21 |
20080201645 | Method and Apparatus for Deploying Portlets in Portal Pages Based on Social Networking - A Portal Page Customizer (PPC) provides a tagging component and a portal page generator that enables a user to quickly display portlets most preferred by a community of portlet users. Each tag is associated with one or more portlet. A user can add new descriptive tags to portlets using tools on the portal page. When a user selects a tag from a tag cloud, the PPC displays portlets associated with the selected tag. | 2008-08-21 |
20080201646 | Tab Order Mapping of User Interfaces - An approach is provided to display a common display page on a variety of display devices using the item's tab order property to determine the display order. Controls that are displayed on a display device typically have a tab order. When a window that has controls is displayed, the cursor is typically placed at the control with the lowest (i.e., first) tab order. When the user presses the tab key, the cursor moves to the control corresponding to the next lowest tab order. This allows the designer to design a single window (or panel) that is displayed differently on constrained devices. However, even though the window is displayed differently, using tab order mapping maintains a consistent visible proximity between controls despite the type of display device being used by the user. | 2008-08-21 |
20080201647 | WEATHER INFORMATION IN A CALENDAR - A system receives location information from a user, retrieves weather information based on the received location information, retrieves calendar information associated with the user, and associates the weather information with the calendar information in a calendar application. | 2008-08-21 |
20080201648 | Web page-embedded dialogs - Various embodiments enable creation of dialogs in a manner that binds them to the page from which they were created. In at least some embodiments, dialogs can be created and rendered as part of a page's elements. In this manner, dialogs can be embedded in the web pages themselves or, more accurately, in the markup language that defines the web page. | 2008-08-21 |