34th week of 2008 patent applcation highlights part 18 |
Patent application number | Title | Published |
20080197840 | Non-Invasive Mri Measurement of Tissue Glycogen - In a method for deriving information about a selected monosaccharide or polysaccharide such as glucose or glycogen, a selected modification such as saturation is made of magnetic resonance at a magnetic resonance frequency of protons of hydroxyl groups of the selected monosaccharide or polysaccharide. Probative water proton magnetic resonance data are acquired while the selected modification is substantially in effect. Information is derived about concentration or density of the selected monosaccharide or polysaccharide based at least on the probative water proton magnetic resonance data. | 2008-08-21 |
20080197841 | METHOD AND SYSTEM FOR DETERMINING ACQUISTION PARAMETERS ASSOCIATED WITH MAGNETIC RESONANCE IMAGING FOR A PARTICULAR MEASUREMENT TIME - An exemplary embodiment of system, computer-accessible medium and method for determining exemplary values for acquisition parameters for a given time (e.g., imaging time) can be provided, e.g., with the exemplary values being selectable to increase the signal-to-noise ratio. In accordance with one exemplary embodiment, method, system and computer accessible medium can be provided for generating data (e.g., image data) associated with at least one portion of a target. For example, at least one first excitation pulse can be forwarded toward the target. A first signal from the target resulting from the at least one first excitation pulse may be acquired using a plurality of acquisition parameters having first values. Further, at least one second excitation pulse can be forwarded toward the target. A second signal from the target resulting from the at least one second excitation pulse may be acquired using a plurality of acquisition parameters having second values, with the second values being different from the first values. The data (e.g., image data) may be generated based on the first and second signals. | 2008-08-21 |
20080197842 | K-T SPARSE: HIGH FRAME-RATE DYNAMIC MAGNETIC RESONANCE IMAGING EXPLOITING SPATIO-TEMPORAL SPARSITY - A method of dynamic resonance imaging is provided. A magnetic resonance imaging excitation is applied. Data in 2 or 3 spatial frequency dimensions, and time is acquired, where an acquisition order in at least one spatial frequency dimension and the time dimension are in a pseudo-random order. The pseudo-random order and enforced sparsity constraints are used to reconstruct a time series of dynamic magnetic resonance images. | 2008-08-21 |
20080197843 | Determination Of Relaxation Rate Changes For Mr Molecular Imaging - MR based molecular imaging is strongly supported by the accurate quantification of contrast agents. According to an exemplary embodiment of the present invention, a determination unit of an examination apparatus is adapted for determining an error propagation function, wherein the error propagation function is then used as a weighting function for an accurate determination Of AR | 2008-08-21 |
20080197844 | METHODS AND APPARATUS FOR JOINT IMAGE RECONSTRUCTION AND COIL SENSITIVITY ESTIMATION IN PARALLEL MRI - A method of parallel magnetic resonance imaging (pMRI) comprising acquiring pMRI signals simultaneously through a plurality of receiving coils, wherein each coil has a localized sensitivity with respect to an imaged volume; jointly estimating values for the imaged volume and for a sensitivity function for at least one of the plurality of receiving coils; and transmitting the reconstructed image to a device. | 2008-08-21 |
20080197845 | MAGNETIC STRUCTURE FOR MRI MACHINES AND MRI MACHINE PARTICULARLY FOR ORTHOPEDIC OF RHEUMATOLOGIC APPLICATIONS - Magnetic structure for MRI machines, which machine has a U-shaped or annular, that is O-shaped geometry having two opposite poles between which a magnetic field is generated and are borne at a predetermined distance one with respect to the other by a magnetic yoke having an inverted U shape or an annular one, that is an O shape, which poles generating the magnetic field and/or at least a part of which yoke delimit a cavity housing at least a part of the patient body, while inside the volume of said cavity a partial volume is generated wherein values of the magnetic field are such to guarantee the acquisition of MRI images having quality characteristics sufficient to be used like diagnostic images, so called imaging volume. | 2008-08-21 |
20080197846 | Magnetic Resonance Imaging With Several Types of Contrast - A magnetic resonance imaging system comprises a signal acquisition system to acquire magnetic resonance signals. A reconstructor reconstructs magnetic resonance images from the acquired magnetic resonance signals. The signal acquisition system and/or the reconstructor are controlled to perform overhead activities separately from actual acquisition of the magnetic resonance signals notably for different contrast types. Accordingly, time efficient signal acquisition for multiple contrasts is achieved. | 2008-08-21 |
20080197847 | Detuning of an Rf Shielded Mri Scan Room - The present invention relates to a system and method magnetic resonance (MR) imaging. Furthermore the invention relates to the use of a material and to a computer program. In order to provide a technique which allows to prevent standing waves in an RF cage ( | 2008-08-21 |
20080197848 | Rf Volume Coil With Selectable Field of View - A radio frequency coil for magnetic resonance imaging or spectroscopy includes a plurality of generally parallel conductive members ( | 2008-08-21 |
20080197849 | Magnetic Resonance System Having a Base Body and a Patient Bed and Inductive or Capacitive Signal Transmission - A magnetic resonance system has a base body embodying a magnet system that generates magnetic fields in an excitation region on the base body, a patient bed that is movable in a travel direction through a travel region relative to the base body, the patient bed receiving an examination subject thereon to move the examination subject through the examination region, a local coil that is operable in combination with the magnet system to generate magnetic resonance signals in the examination subject and to detect the magnetic resonance signals resulting therefrom, and an evaluation device that evaluates the magnetic resonance signals detected by the local coil. A base body coupling element, at a predetermined base body location, is connected to the evaluation device. A patient bed coupling element, located at a predetermined patient bed location, is connected to the local coil. The base body and patient bed coupling elements feed the magnetic resonance signals to the evaluation device when, and as long as, the patient bed has moved by a predetermined segment of the travel region. | 2008-08-21 |
20080197850 | MAGNETIC RESONANCE APPARATUS HAVING A SUPERCONDUCTING BASIC FIELD MAGNET WITH A STRUCTURALLY REINFORCED CRYOSHIELD - In an arrangement of a basic field magnet and a gradient coil of a magnetic resonance apparatus, the basic field magnet includes superconducting coils that are arranged in a reservoir with liquid helium for cooling. The helium reservoir is surrounded by a further reservoir, designated as an outer vacuum chamber. A vacuum exists between the outer vacuum chamber and the helium reservoir. A cryoshield is arranged between the outer vacuum chamber and the helium reservoir. The gradient coil is arranged in the inner chamber of the basic field magnet. The cryoshield has additional structure for reinforcement that counteract vibrations of the cryoshield. | 2008-08-21 |
20080197851 | Borehole Conductivity Simulator Verification and Transverse Coil Balancing - Calibration of the arrays of a multicomponent induction logging tool is achieved by positioning the tool horizontally above ground. The upper and lower housings of the tool are connected by a borehole conductivity simulator which as a resistance comparable to that of a borehole. Axial and radial positioning of the transmitter coils is done by monitoring outputs at receiver coils to achieve a minimum. | 2008-08-21 |
20080197852 | System For Monitoring a Group of Electrochemical Cells and Device Therefor - A system for monitoring a group of electrochemical cells (C | 2008-08-21 |
20080197853 | Electric field probe - This is an electronic scanning probe, preferably made up of at least two sensing elements, each sensing element substantially surrounded by reference electrodes. These sensing elements are separated at a distance that causes little or no cross-interference to take place between these sensing elements when positioned in concert with a surface of interest. Ideally, this probe is used in electrostatic marking systems where an electrostatic charge is placed onto a receiving surface. | 2008-08-21 |
20080197854 | Harmonic Derived Arc Detector - An arc detection system includes a radio frequency (RF) signal probe that senses a RF signal at an input of a RF plasma chamber and that generates a signal based on at least one of the voltage, current, and power of the RF signal. A signal analyzer receives the signal, monitors the signal for frequency components that have a frequency greater than or equal to a fundamental frequency of the RF signal, and generates an output signal based on the frequency components. The output signal indicates that an arc is occurring in the RF plasma chamber. | 2008-08-21 |
20080197855 | Insulation Resistance Drop Detector and Failure Self-Diagnosis Method for Insulation Resistance Drop Detector - An insulation resistance drop detector includes a pulse generator that applies a pulse signal to a series circuit in which a detecting resistor, a coupling capacitor, and an insulating resistance are serially connected. In a state where the pulse signal is applied to the series circuit, control circuit detects a pulse-like divided voltage occurring at a node by a voltage detecting circuit via a bandpass filter, to thereby sense a drop of an insulation resistance. Further, the control circuit senses a failure of the insulation resistance drop detector itself when the voltage detected by the voltage detecting circuit is maintained at least at a prescribed voltage exceeding a plurality of cycles of the pulse signal. Thus, the insulation resistance drop detector having a failure self-diagnosis function is realized by a simple configuration. | 2008-08-21 |
20080197856 | Circuit Arrangement to Diagnose a Heating Resistor - A circuit arrangement is proposed to diagnose a heating resistor, which is connected in series with a first switch, which connects the heating resistor to a power source for operation of the heating resistor with a heating current. Provision is made for means to operate the heating resistor with a diagnostic current during a cut-out time of the heating current and for means to acquire a diagnostic voltage as a measurement for the voltages occurring at the heating resistor as well as means to calculate the resistance of the heating resistor, which is taken as a basis for the diagnosis. | 2008-08-21 |
20080197857 | MULTI-MEA TEST STATION AND MULTI-MEA TEST METHOD USING THE SAME - Disclosed is a multi-MEA test station capable of simultaneously testing and activating a plurality of MEAs and a multi-MEA test method using the same. The multi-MEA test station includes a chamber capable of receiving a plurality of MEAs; a first multi cell body including a first channel for supplying an oxidant to a cathode electrode of the MEA, and a second multi cell body including a second channel for supplying fuel to an anode electrode of the MEA; a pressing means closely adhering the first multi cell body, the second multi cell body and the MEA positioned therebetween by applying force in a direction that the first multi cell body and the second multi cell body are opposed to each other; a reactant supply means for supplying the oxidant to the first channel and supplying the fuel to the second channel; and a multi-loader controlling the environment of a test and activation on the plurality of MEAs and performing the test and the activation. | 2008-08-21 |
20080197858 | AUTOMATIC CALIBRATION TECHNIQUES WITH IMPROVED ACCURACY AND LOWER COMPLEXITY FOR HIGH FREQUENCY VECTOR NETWORK ANALYZERS - A calibration module, for use in calibrating a VNA, includes ports connectable to the VNA, calibration standards, and single pole multi throw (SPMT) switches. Each SPMT includes a single pole terminal, multiple throw terminals and a shunt terminal corresponding to each multiple throw terminal. A switching path is between each throw terminal and the single pole terminal, and between each shunt terminal and the single pole terminal. Each switching path includes at least one solid state switching element. The calibration standards are selectively connectable to the ports of the calibration module by selectively controlling the switching elements. Each port of the calibration module is directly connected to a throw terminal of one of the SPMT switches. Also, unique algorithm are provided for calibrating a VNA when using a calibration impedance that is a hybrid of a reflect standard and a transmission standard, which can be achieved using the calibration module. | 2008-08-21 |
20080197859 | Module For Testing Electromagnetic Compatibility of a High-Speed Ethernet Interface Onboard an Aircraft - A module to test electromagnetic compatibility of at least one high speed Ethernet interface onboard an aircraft. The module includes a cable less than 1 meter long, the ends of which are fitted with two aircraft contacts, two standard connectors compatible with standard test equipment, and a mechanism simulating attenuation of a test cable. | 2008-08-21 |
20080197860 | Configurable voltage regulator - A configurable semiconductor has a device characteristic that is controllable as a function of at least one external impedance. A measurement circuit measures an electrical characteristic of the at least one external impedance and determines a select value corresponding to the measured electrical characteristic. A first circuit controls the device characteristic as a function of the select value. | 2008-08-21 |
20080197861 | METHOD OF AUTOMATICALLY TESTING AN ELECTRONIC CIRCUIT WITH A CAPACITIVE SENSOR AND ELECTRONIC CIRCUIT FOR THE IMPLEMENTATION OF THE SAME - A method for automatically testing an electronic circuit with a capacitive sensor having two capacitors is provided, wherein the common electrode of the capacitors moves relative to each fixed electrode. The electronic circuit includes a sensor interface that includes a charge transfer amplifier unit, an integrator unit connected to the amplifier unit to provide measurement output voltage, and an excitation unit. The excitation unit inversely polarizes each fixed electrode at high or low voltage or discharges the capacitors. The method includes several successive measurement cycles each divided into a first phase discharging capacitors by output voltage and a second phase for polarizing the fixed electrode of the first capacitor at high voltage and inversely polarizing the fixed electrode of the second capacitor at low voltage. In the measuring cycles, a test phase replaces a second polarizing phase in at least one cycle in every two successive measurement cycles. | 2008-08-21 |
20080197862 | Proportional Variable Resistor Structures to Electrically Measure Mask Misalignment - A system, method and structures employing proportional variable resistors suitable for electrically measuring unidirectional misalignment of stitched masks in etched interconnect layers. In an example embodiment, there is a structure ( | 2008-08-21 |
20080197863 | LIQUID PROPERTIES SENSOR CIRCUIT - A sensor circuit is coupled to a sensing element for determining a property, such as a dielectric constant, of a fuel suitable where the dielectric constant is used in determining a concentration of ethanol in the gasoline/ethanol blended fuel. The circuit includes an excitation voltage signal generator, a synchronization trigger and a processing circuit configured to generate an output signal indicative of the fuel property (dielectric constant). The excitation voltage signal is applied to the sensing element to produce an induced current signal therethrough. The synchronization trigger is configured to generate a trigger signal when the excitation voltage signal crosses zero volts, at which time the real (resistive) component of the induced current signal is zero. The induced signal is therefore wholly representative of the imaginary component attributable to a capacitance of the sensing element in sensing relation with the fuel, which in turn is dependent on the dielectric constant (and thus ethanol concentration) of the fuel blend itself. The processing circuit is configured to sample the induced signal in response to the trigger signal and produce the output signal. The synchronization scheme provides for a simplified circuit arrangement since there is o need to decompose a signal combining real and imaginary components. | 2008-08-21 |
20080197864 | RESISTANCE MEASURING METHOD - A resistance measuring method for testing a device under test electrically connected to a pair of pads, by use of a measuring apparatus having a resistance measuring function. A voltage arising in the device under test is measured to calculate a resistance of the device under test from the current and voltage. The resistance measuring method includes, forming an electric connection pattern serially connecting the plurality of sets of the devices under test, causing a pair of probes for voltage measurement of the measuring apparatus to come into contact with the pair of pads of the device under test, and causing a pair of probes for current application of the measuring apparatus to come into contact with a pair of pads electrically connected by the electric connection pattern to each of the pair of pads of the device under test. | 2008-08-21 |
20080197865 | PROBE CARD ANALYSIS SYSTEM AND METHOD - A system and method for evaluating wafer test probe cards under real-world wafer test cell condition integrates wafer test cell components into the probe card inspection and analysis process. Disclosed embodiments may utilize existing and/or modified wafer test cell components such as, a head plate, a test head, a signal delivery system, and a manipulator to emulate wafer test cell dynamics during the probe card inspection and analysis process. | 2008-08-21 |
20080197866 | Method of Manufacturing Needle for Probe Card Using Fine Processing Technology, Needle Manufactured by the Method, and Probe Card Comprising the Needle - Disclosed are probe card needles manufactured using microfabrication technology, a method for manufacturing the probe card needles, and a probe card having the probe card needles. The probe needles are manufactured by forming, on a ceramic board, probe needle bases made of conductive metal, and a polymeric elastomer layer, by using photolithography and a photoresist, and continuously depositing conductive metal layers on the probe needle bases in such a manner as to be supported by the polymeric elastomer layer. The probe card comprises: a printed circuit board (PCB) which is connected to a test head for transmitting an electrical signal from a tester; a ceramic board located below the PCB and electrically connected to the PCB by a plurality of interface pins; a jig for mechanically holding the interface pins and the multilayer ceramic board to the PCB; and a plurality of probe needles attached to the lower surface of the multilayer ceramic board and making contact with electrical/electronic devices. | 2008-08-21 |
20080197867 | SOCKET SIGNAL EXTENDER - A socket signal extender (SSE), and a system and method of testing an assembled device under test (DUT) board employing an SSE. In one embodiment, the SSE includes a cover having a portion configured to fit within a test socket. The portion is free of logic and includes electrical conductors configured to provide an electrical connection to contacts of the test socket. | 2008-08-21 |
20080197868 | CIRCUIT BOARD TESTING DEVICE WITH SELF ALIGNING PLATES - A circuit board tester and method that precisely aligns the probe plate and circuit board is disclosed. With a circuit board and probe plate mounting within a housing having a top and bottom, hinged together, at closure there may be slight misalignments of the two. By making one of the two plates floating, or laterally slideable with respect to each other, it is possible to make final alignment at closure. One of the two plates can be provided with a pin and the other with a pin receiving alignment block. With the lateral sideability, the pin and block can insure proper probe alignment. Additional systems for correcting misaligned pins or blocks are also disclosed. | 2008-08-21 |
20080197869 | ELECTRICAL CONNECTING APPARATUS - To restrain misregistration of tips due to change in temperature, an electrical connecting apparatus is used for connection of a tester, and electrical connection terminals of a device under test to undergo electrical test by the tester. The electrical connecting apparatus comprises a probe board having a plurality of probe lands on its underside; and a plurality of contacts having tip portions to be brought into contact with a base end portion fixed at the respective probe lands and the connection terminals of the device under test. The measure from the tip of each contact and the probe land ranges from 1.1 to 1.3 mm, and the coefficient of thermal expansion of the probe board is greater than the coefficient of thermal expansion of the device under test within the range from 1 to 2 ppm/° C. | 2008-08-21 |
20080197870 | Apparatus and Method For Determining Reliability Of An Integrated Circuit - In an embodiment, an integrated circuit or chip is supplied to its intended application and a measurement quantity representing the state of one or a plurality of electrical connections in the chip is determined within the application environment of the chip and, if the measurement quantity determined does not correspond to predefined criteria, a corresponding signal is output. | 2008-08-21 |
20080197871 | Sequential semiconductor device tester - A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test pattern data. | 2008-08-21 |
20080197872 | SEMICONDUCTOR CHIP, MULTI-CHIP SEMICONDUCTOR DEVICE, INSPECTION METHOD OF THE SAME, AND ELECTRIC APPLIANCE INTEGRATING THE SAME - A disclosed semiconductor chip includes a first connection pad adapted to input an input signal; and a second connection pad adapted to selectively output, according to a test mode signal input to the semiconductor chip, one of the input signal and an output signal from the semiconductor chip. | 2008-08-21 |
20080197873 | CLOCK SIGNAL DISTRIBUTING CIRCUIT, INFORMATION PROCESSING DEVICE AND CLOCK SIGNAL DISTRIBUTING METHOD - An integrated circuit includes a test pattern input unit for inputting a test pattern into cells, a clock distributing unit for distributing a clock signal to the cells, a first cell that receives the clock signal distributed by the clock distributing unit, a second cell that receives the clock signal after the clock signal is received by the first cell, a data transfer unit for transferring a data signal from the first cell to the second cell, a clock transfer unit for distributing the clock signal to the first cell and the second cell and transferring the clock signal in the same direction as the transfer direction of the data signal, and a failure detecting unit for inputting the test pattern into the cells and detecting failures of the cells on the basis of the results of the test pattern output from the cells. | 2008-08-21 |
20080197874 | TEST APPARATUS HAVING MULTIPLE TEST SITES AT ONE HANDLER AND ITS TEST METHOD - A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus. | 2008-08-21 |
20080197875 | INTEGRATED CIRCUIT - An integrated circuit is provided having at least one terminal for coupling and/or decoupling of electric signals, particularly of digital signals, and having integrated reference potential means, assigned to the terminal, for providing an electric reference potential to the terminal. It is provided according to an embodiment of the invention that the reference potential means is switchable, particularly by an override process. | 2008-08-21 |
20080197876 | INTEGRATED CIRCUIT, SYSTEM AND METHOD INCLUDING A PERFORMANCE TEST MODE - An integrated circuit includes N configurable cells each including one functional input, one output, one propagation input and one output. The circuit includes a functional mode in which the N configurable cells are coupled by their functional input and their output to logic blocks with which they cooperate to form at least one logic circuit. The disclosed circuit also includes a test mode in which the N configurable cells are coupled by their propagation input and their output to the logic blocks and in which the output of the Nth configurable cell is coupled to a functional input of the first logic block to form an oscillator. | 2008-08-21 |
20080197877 | Per byte lane dynamic on-die termination - Embodiments of the invention are generally directed to systems, methods, and apparatuses for per byte lane dynamic on-die termination. In some embodiments, an integrated circuit includes logic to independently program at least one on-die termination (ODT) value for each of a plurality of integrated circuits coupled together through an interconnect. Other embodiments are described and claimed. | 2008-08-21 |
20080197878 | ENHANCED FIELD PROGRAMMABLE GATE ARRAY - An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O. | 2008-08-21 |
20080197879 | APPARATUS AND METHOD FOR A PROGRAMMABLE LOGIC DEVICE HAVING IMPROVED LOOK UP TABLES - A programmable logic device including a plurality of logic elements organized in an array. Each of the logic elements includes an N-stage Look Up Table structure having 2 | 2008-08-21 |
20080197880 | SOURCE DRIVER AND LEVEL SHIFTING METHOD THEREOF - The present invention provides a source driver comprising a shift register, a line buffer for storing a data signal and outputting a buffered data signal, and a level shifter for generating a level-shifted data signal based on the buffered data signal. The line buffer further comprises a charge pump supplying a pumped voltage based on a voltage source and a buffer powered by the pumped voltage and outputting a buffered data signal based on the data signal. | 2008-08-21 |
20080197881 | RECEIVER CIRCUIT USING NANOTUBE-BASED SWITCHES AND LOGIC - Receiver circuits using nanotube based switches and logic. Preferably, the circuits are dual-rail (differential). A receiver circuit includes a differential input having a first and second input link, and a differential output having a first and second output link. First, second, third and fourth switching elements each have an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The receiver circuit can sense small voltage inputs and convert them to larger voltage swings. | 2008-08-21 |
20080197882 | LOGIC CIRCUITS - A logic circuit includes a logic unit, a driving unit, and a voltage level adjuster. The logic unit includes an output node having a logic state, the logic unit being coupled to a first voltage reference. The driving unit includes an input node, the driving unit being coupled to a second voltage reference, the driving unit and the first logic unit being constructed from a single type of transistor. The voltage level adjuster provides a control signal that causes the driving unit to reduce a current flowing through the driving unit when the output node of the first logic unit has a first logic state, and causes the driving unit to drive an output node of the logic circuit to a voltage level substantially equal to that of the second voltage reference when the output node of the first logic unit has a second logic state. | 2008-08-21 |
20080197883 | Integrated circuit device and electronic instrument - An integrated circuit device includes a first predriver that drives an N-type power MOS transistor of an external driver including the N-type power MOS transistor and a P-type power MOS transistor, a second predriver that drives the P-type power MOS transistor, a low-potential-side power supply pad, a first output pad, a second output pad, and a high-potential-side power supply pad. The low-potential-side power supply pad, the first output pad, the second output pad, and the high-potential-side power supply pad are disposed along a first direction. The first predriver is disposed in a second direction with respect to the low-potential-side power supply pad and the first output pad, the second direction being a direction that is perpendicular to the first direction, and the second predriver is disposed in the second direction with respect to the second output pad and the high-potential-side power supply pad. | 2008-08-21 |
20080197884 | Kick Gate - Feedback is reduced by routing an input signal through a kick gate that opens for a predetermined time period then closes. The gate may be kept closed for a predetermined minimum time period before being allowed to open again. The gate is triggered open based on the input signal and may include a plurality of triggering conditions. | 2008-08-21 |
20080197885 | Circuit for detecting maximal frequency of pulse frequency modulation and method thereof - The circuit for detecting the maximal frequency of the pulse frequency modulation includes an oscillator-controlling unit, a delay circuit and a master-slave register. The oscillator-controlling unit is connected to an oscillator, which generates the pulse frequency modulation signals, and includes a first-half pulse-generating module and a second-half pulse-generating module. The delay circuit is connected to the second-half pulse-generating module. The master-slave register includes a clock, an input end and an output end, wherein the input end is connected to the oscillator-controlling unit, and the clock is connected to the delay circuit. | 2008-08-21 |
20080197886 | CIRCUIT FOR DISCRIMINATING OUTPUT OF SQUELCH CIRCUIT AND CIRCUIT FOR REGULATING SENSIVITY OF THE SAME - A circuit for discriminating a ‘Noisy’ state of an output of a squelch circuit is disclosed. A circuit for resolve the ‘Noisy’ state of the output of the squelch circuit is also disclosed which uses the output identification circuit. The output of the squelch circuit and a clear signal are input into a first AND gate. The output of the first AND gate is input into a first flip-flop. An inversed signal of the output of the first AND gate is input into a second flip-flop. The outputs of the first and second flip-flops are input into a discriminating unit including a second AND gate. The ‘Noisy’ state is identified by the output of the second AND gate. Based on the identification result, sensitivity of the squelch circuit is regulated. | 2008-08-21 |
20080197887 | Comparator Circuit - Provided is a comparator circuit that is capable of operating at high speed and canceling an offset voltage with high precision. The comparator circuit includes a second amplifier circuit for amplifying an output of an amplifier circuit and feeding back the amplified output to an input of the amplifier circuit. When the comparator circuit samples the input voltage, the second amplifier circuit conducts feedback and increases a gain to cancel the offset. Also, when the gain of the amplifier circuit is made lower than the gain of the second amplifier circuit, and the comparator circuit compares the input voltage, the comparing operation can be conducted at high speed by separating the amplifier circuit from the feedback of the second amplifier circuit. | 2008-08-21 |
20080197888 | Low voltage shutdown circuit - A low voltage shutdown circuit comprises an input node for receiving a voltage V | 2008-08-21 |
20080197889 | Semiconductor Integrated Circuit Device and Mobile Device Using Same - An IC includes an internal circuit that switches between on-state and off-state in response to an external signal and also includes an oscillator circuit that is externally synchronized. The IC further includes a state holding circuit that, when pulses for synchronizing the oscillator circuit are inputted to a standby pulse input terminal, applies, to the internal and the oscillator circuits, as an operation signal, a voltage obtained by rectifying pulses outputted from a comparator, and, when a constant voltage for non-operation is applied to the standby pulse input terminal for a given time period, applies, to the internal and oscillator circuits, as a non-operation signal, a constant voltage outputted from the comparator. | 2008-08-21 |
20080197890 | Light receiving circuit - A light receiving circuit according to the present invention includes a current control voltage generation circuit | 2008-08-21 |
20080197891 | Frequency synthesizer using two phase locked loops - The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency. | 2008-08-21 |
20080197892 | BUFFER CIRCUIT AND CONTROL METHOD THEREOF - The present disclosure has been worked out to provide a buffer circuit and a control method thereof capable of controlling the timing at which the output switching element is changed from an OFF state to an ON state, and preventing the output characteristic from becoming unstable. The buffer circuit includes: a driving portion | 2008-08-21 |
20080197893 | VARIABLE OFF-CHIP DRIVE - A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the drivers and at least one additional driver is selected, signal will be driven by the drivers at a level that is greater than the first level by a level of drive provided by the least one additional driver. | 2008-08-21 |
20080197894 | Injection locked frequency divider - An injection locked frequency divider includes a signal injection unit, a Hartley voltage controlled oscillator and a biasing unit. The signal injection unit and the biasing unit output an injection signal to the Hartley voltage controlled oscillator to bias the Hartley voltage controlled oscillator. The Hartley voltage controlled oscillator, which includes a first transistor, a second transistor and a LC tank, receives the injection signal and outputs a differential output signal through a first output terminal and a second output terminal. First terminals of the first and second transistors are respectively coupled to the first and second output terminals, and second terminals of the first and second transistors are coupled to a first node. The LC tank decides a resonant frequency of the Hartley voltage controlled oscillator and serves as a positive feedback circuit for the first and second transistors. | 2008-08-21 |
20080197895 | SYSTEM AND METHOD FOR POWER ON RESET AND UNDER VOLTAGE LOCKOUT SCHEMES - A system and method for power-on reset and under-voltage lockout schemes. The system includes a first transistor, which includes a first gate, a first terminal, and a second terminal, the second terminal being biased to a predetermined voltage. The system includes a second transistor, which include a second gate, a third terminal, and a fourth terminal, the third terminal being configured to receive an input voltage. The system includes a first resistor that is associated with a first resistance. The first resistor includes a fifth terminal and a sixth terminal, the fifth terminal being configured to receive the input voltage. The system includes a second resistor that is associated with a second resistance. The second resistor includes a seventh terminal and an eighth terminal, the seventh terminal being coupled to the sixth terminal. The system includes a first Zener diode that is associated with a first Zener voltage. | 2008-08-21 |
20080197896 | Device and Method for Phase Synchronization with the Aid of a Microcontroller - The phase controller device according to the invention comprises a hardware core that is formed by a signal detector, a voltage-controlled oscillator, a phase comparator, and an integration unit, where the hardware core, by controlling the working clock pulse frequency of the microcontroller, brings an output clock pulse signal that is generated by a microcontroller into phase with the input clock pulse information that is received from the input data stream, and does so in such a manner that the jitter is low. The microcontroller executes a program with this working clock pulse, where with that program the microcontroller generates the output clock pulse signal with an output clock pulse frequency that is in a predetermined division ratio to the control clock pulse frequency that is generated by the voltage-controlled oscillator and is given to the microcontroller as a working clock pulse frequency. In this way the program enables the phase controller device according to the invention to process, with a microcontroller, external periodic signals, data, or events, where the software processes taking place in the microcontroller are always locked in phase with the periodic occurrence of these external signals, data, or events. | 2008-08-21 |
20080197897 | PLL CIRCUIT AND WIRELESS DEVICE - A PLL circuit according to the present invention includes: a voltage controlled oscillator | 2008-08-21 |
20080197898 | Charge pump regulator and method of producing a regulated voltage - A charge pump regulator has a charge pump to establish a charge path and a discharge path alternately, so as to produce a regulated voltage on an output terminal. The charge pump has at least a current control element on the charge path or the discharge path to control the current flowing therethrough according to an output-dependent feedback signal. | 2008-08-21 |
20080197899 | Trimmable Delay Locked Loop Circuitry with Improved Initialization Characteristics - Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay Tref, and the feedback clock as trimmed by a delay Tfb. By using these three phases at the appropriate time, the measurement is aware of the Tac trim for both positive (Tref) and negative (Tfb) trims. Specifically, measurement ‘start’ and ‘stop’ signals each pass through only one of delays Tref and Tfb, such that error in the measurement is a function of both Tref and Tfb. This improves the accuracy of the measurement such that additional shifting of the DLL is not necessary after initialization, and allows a wide trim range even for high clock frequencies. | 2008-08-21 |
20080197900 | DELAY LOCKED LOOP FOR CONTROLLING DELAY TIME USING SHIFTER AND ADDER AND CLOCK DELAYING METHOD - A delay locked loop that controls a delay time period by using a shifter and an adder includes a master delay locked loop and a slave delay locked loop. The master delay locked loop outputs a first digital value corresponding to one clock cycle of a first input clock signal. The slave delay locked loop receives the first digital value and delays a second input clock signal for a time period smaller than the one clock cycle of the first input clock signal. The slave delay locked loop includes a shifter, an operator, and a variable delay circuit. The shifter shifts the first digital value to generate a second digital value. The operator adds or subtracts an offset value to or from the second digital value to generate a third digital value, wherein the offset value varies according to a process, a voltage, and a temperature (PVT). The variable delay circuit delays the second input clock signal for a time period corresponding to the third digital value. | 2008-08-21 |
20080197901 | Multiple Pulse Width Modulation - A method of generating a MPWM signal for a portable device such as a cellular telephone. For a first duty cycle that includes a MPWM frequency having N magnitude levels, the method generates a first waveform comprising a first and a second On pulse during a first MPWM frequency period. The first and second On pulses are separated by an Off period. | 2008-08-21 |
20080197902 | METHOD AND APPARATUS TO REDUCE PWM VOLTAGE DISTORTION IN ELECTRIC DRIVES - Methods and apparatus are provided for reducing voltage distortion effects at low speed operation in electric drives. The method comprises receiving a first signal having a duty cycle with a range between minimum and maximum achievable duty cycles, producing a second duty cycle based on the minimum achievable duty cycle if the duty cycle is within a distortion range and less than a first clipping value, producing a second duty cycle based on the closer of minimum and maximum pulse widths if the duty cycle is within the distortion range and between the first and a second clipping value, producing a second duty cycle based on the maximum achievable duty cycle if the duty cycle is within the distortion range and greater than the second clipping value, and transmitting a second signal to the voltage source inverter having the second duty cycle. | 2008-08-21 |
20080197903 | Clock Pulse Duty Cycle Control Circuit for a Clock Fanout Chip - A clock pulse duty cycle control circuit for receiving an input clock signal and for providing an output clock signal having a desired duty cycle. An error signal generator includes a differential integrator that is connected to receive the output clock signal. The differential integrator integrates the output clock signal to produce a time-varying DC error signal representative of a difference between the output clock signal duty cycle and the desired duty cycle. A duty cycle corrector includes a differential integrator connected to receive the input clock signal and the error signal. The differential integrator integrates the input clock signa to produce a correction stage clock signal. The differential integrator causes the slopes of the input clock signal edges to be adjusted as a function of the error signal. A buffer including a high gain amplifier is connected to receive the correction stage clock signal and squares the edges of the clock signal to produce the output clock signal. | 2008-08-21 |
20080197904 | Circuit Arrangement for Switching a Load - A circuit arrangement for switching a load includes at least one at least partially inductive load, at least one high side switch with a controlled path connected in series with the load and between supply terminals for a supply voltage. At least one freewheeling diode is connected with a first tap between the high side switch and the load. At least one clamp circuit is connected to a control terminal of the high side switch and is used to limit the control potential applied to the control terminal to a first pre-determined voltage value when the high side switch is switched off. | 2008-08-21 |
20080197905 | FIELD-PROGRAMMABLE GATE ARRAY LOW VOLTAGE DIFFERENTIAL SIGNALING DRIVER UTILIZING TWO COMPLIMENTARY OUTPUT BUFFERS - A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer. | 2008-08-21 |
20080197906 | Reference clock receiver compliant with LVPECL, LVDS and PCI-Express supporting both AC coupling and DC coupling - A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal. | 2008-08-21 |
20080197907 | DRIVER AMPLIFIER CIRCUIT - A driver amplifier circuit is provided which includes a voltage level shifting circuit and an Op-Amp. A positive power supply terminal and a negative power supply terminal of the Op-Amp receive a first reference voltage and a second reference voltage outputted from the voltage level shifting circuit, causing a DC voltage level of an output signal to be equal to 0V. Meanwhile, the absolute value of a voltage difference between the first reference voltage and the second reference voltage is equal to V | 2008-08-21 |
20080197908 | Cascode Power Switch for use in a High-Frequency Power MESFET Buck Switching Power Supply - A cascode power switch for use in a MESFET based switching regulator includes a MOSFET in series with a normally-off MESFET. The cascode power switch is typically connected in between a power source and a node Vx. The node Vx is connected to an output node via an inductor and to ground via a Schottky diode or a second MESFET or both. A control circuit drives the MESFET (and the second MESFET) so that the inductor is alternately connected to the battery and to ground. The MOSFET is switched off during sleep or standby modes to minimize leakage current through the MESFET. The MOSFET is therefore switched at a low frequency compared to the MESFET and does not contribute significantly to switching losses in the converter. | 2008-08-21 |
20080197909 | Capacitative Proximity Switch, and Domestic Appliance Equipped With the Same - A capacitive proximity switch has an electrically conductive sensor surface, which is covered by an electrically non-conductive covering plate and which serves as a part of a capacitor with a capacitance that varies with proximity. A household appliance is equipped with a proximity switch of this type. The sensor surface has an active shielding, which is formed by a shielding surface to which a clock signal is applied at the same time as it is applied to the sensor surface. | 2008-08-21 |
20080197910 | Input processing circuit and switch input circuit using the same - An input processing circuit implemented on a semiconductor integrated circuit includes an input terminal for receiving an input signal, a first diode coupled between the input terminal and a power line, a second diode coupled between the input terminal and a ground line, a first MOSFET having a gate and drain coupled together to the input terminal, and a source coupled to the ground line, a second MOSFET coupled to the first MOSFET to construct a current mirror circuit, a current-to-voltage conversion circuit coupled between the power line and the second MOSFET to convert an electric current flowing through the second MOSFET to a voltage, and a determination circuit configured to determine a state of the input signal based on a level of the output voltage of the current-to-voltage conversion circuit. | 2008-08-21 |
20080197911 | CIRCUIT WITH FUSE/ANTI-FUSE TRANSISTOR WITH SELECTIVELY DAMAGED GATE INSULATING LAYER - A semiconductor integrated circuit is disclosed which includes a main transistor and at least one of a fuse transistor or an anti-fuse transistor (“fuse/anti-fuse transistor”). Each transistor type includes an active region formed in a semiconductor substrate, a gate stack comprising a gate insulation layer and a gate electrode sequentially formed on the active region, and source/drain regions separated across the gate stack, but the gate insulation layer of the fuse/anti-fuse transistor is selectively damaged during fabrication. | 2008-08-21 |
20080197912 | Circuit arrangement for generating a temperature-compensated voltage or current reference value - A circuit arrangement for generating a temperature-compensated voltage or current reference value (UREF) from a supply voltage (VCC) based on the bandgap principle comprises a PTAT circuit ( | 2008-08-21 |
20080197913 | ENERGY EFFICIENT VOLTAGE DETECTION CIRCUIT AND METHOD THEREFOR - A voltage detection circuit has a first MOSFET device having a drain, a gate, and a source terminal. A feedback element is coupled to the drain terminal and the gate terminal of the first MOSFET device. An input voltage is coupled to the gate terminal of the first MOSFET device. The voltage detection circuit is actively detecting a voltage from when the input voltage is in an OFF-state voltage region of the first MOSFET device. This detection continues through when the input voltage is at a sub-threshold voltage region of the first MOSFET, to when the input voltage exceeds the threshold voltage of the first MOSFET. This voltage detection circuit dissipates only a pre-selected drain-current at a level exceeding the drain-leakage current of the first MOSFET, as power dissipation. | 2008-08-21 |
20080197914 | Dynamic leakage control using selective back-biasing - Embodiments of a dynamic leakage control circuit for use with graphics processor circuitry are described. The dynamic leakage control circuit selectively enables back biasing of the transistors comprising the graphics processor circuits during particular modes of operation. The back biasing levels are controlled by two separate power rails. A first power rail is coupled to an existing power supply and the second power rail is coupled to a separate adjustable voltage regulator. A separate voltage regulator may also be provided for the first power rail. A hardware-based state machine or software process is programmed to detect the occurrence of one or more modes of operation and adjust the voltage regulators for the first and second power rails to either enable or disable the back biasing state of the circuit, or alter the threshold voltage of the circuit within a specified voltage range. | 2008-08-21 |
20080197915 | SEMICONDUCTOR DEVICE CHIP, SEMICONDUCTOR DEVICE SYSTEM, AND METHOD - A semiconductor device chip, semiconductor device system, and a method. One embodiment provides a semiconductor device chip including a device for determining whether the semiconductor device chip is to be placed in a current saving operating mode. | 2008-08-21 |
20080197916 | Low-Voltage Noise Preventing Circuit Using Abrupt Metal-Insulator Transition Device - Provided are a low-voltage noise preventing circuit using an abrupt metal-insulator transition (MIT) device which can effectively remove a noise signal with a voltage less than a rated signal voltage. The abrupt MIT device is serially connected to the electrical and/or electronic system to be protected from the noise signal, and is subject to abrupt MIT at a predetermined voltage. Accordingly, low-voltage noise can be effectively removed. | 2008-08-21 |
20080197917 | Device For Filtering A Signal And Corresponding Method - A device for filtering a signal delivered as output from a sensor installed in a motor vehicle includes a comparator (A) offering as output a first logic signal (S | 2008-08-21 |
20080197918 | ELECTRONIC APPLIANCE, COMMUNICATION CONDITION SETTING DEVICE, COMMUNICATION CONDITION SETTING METHOD AND COMPUTER PROGRAM - An electronic appliance having a communication function conforming to a wide band wireless communication system is disclosed. The electronic appliance includes: an EMI pattern information storage part configured to store EMI (electromagnetic interference) pattern information unique to the electronic appliance itself or EMI pattern information unique to an electronic appliance of the same type; an EMI standard value information acquiring part configured to acquire EMI standard value information valid in a relevant nation or region based on location information of the electronic appliance itself; and a communication condition setting part configured to set a communication condition relating to a wide band wireless communication based on the result of comparison between the acquired EMI standard value information and the EMI pattern information. | 2008-08-21 |
20080197919 | FULLY DIFFERENTIAL DEMODULATOR WITH VARIABLE GAIN, AND METHOD FOR DEMODULATING A SIGNAL - A demodulator includes input terminals, for receiving an input signal, and an amplifier stage having a gain. The input signal is amplitude-modulated and is defined by a carrier signal at a carrier frequency and by a modulating signal. The demodulator includes, moreover, a gain-control stage, coupled to the amplifier stage for varying the gain of the amplifier stage according to a sinusoid of a frequency equal to the carrier frequency, on the basis of the carrier signal. | 2008-08-21 |
20080197920 | Arrangement For Carrying Out Current-To-Voltage Conversion - An arrangement for carrying out current-to-voltage conversion, preferably for an infrared receiver, in which the static offset, which has an interfering effect with regard to sensitivity or malfunctions, is reduced during the carrying out of current-to-voltage conversion of received input pulses. In this arrangement, outputs of a second stage are fed back to inputs of a first stage of the multistage transimpedance stage. | 2008-08-21 |
20080197921 | System and method for minimizing DC offset in outputs of audio power amplifiers - An amplifier system receives an input signal and generating therefrom an amplified output signal. The amplifier system is recited as comprising an input stage and an amplifier stage. The input stage is configured to receive the input signal and provide a level-shifted signal that has an average signal level that is shifted in regards a level shift value. The amplifier stage is configured to receive the level-shifted input signal from the input stage and generate therefrom the amplified output signal. The level shift value being selected to minimize a DC offset in the amplified output signal at least when the amplifier system is initially powered on. Since the amplified output signal has a minimal or zero DC offset, the amplifier system avoids generation of undesirable noises when it is initially powered on. | 2008-08-21 |
20080197922 | AMPLIFIER DEVICE FOR AN ANTENNA OPERABLE IN AT LEAST ONE MODE - An amplifier device for a mode antenna has a number of amplifiers and a number of outputs. An input signal is fed to each amplifier, which is amplified by the respective amplifier into an amplified input signal. The amplified input signals are fed to an output matrix arranged after the amplifiers. Respective output signals are emitted by the output matrix at the outputs. The output matrix causes each amplified input signal to supply an output signal contribution for each output signal. Each output signal contribution of each output signal has an output-side contribution offset in relation to the corresponding amplified input signal, which depends on the amplified input signal that supplied the output signal contribution, and the output signal to which the output signal contribution contributes. The amplifier device is especially able to be used in a transmit arrangement for radio-frequency signals. | 2008-08-21 |
20080197923 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND HIGH-FREQUENCY POWER AMPLIFIER MODULE - Upon application of an on-state voltage to a control terminal, an antenna switch provided between an antenna terminal and a transmission terminal is turned on, and a transmission signal of a PCS/DCS system passes from the transmission terminal through the antenna terminal. At this time, a booster circuit, to which a part of the transmission signal is supplied, generates at an output terminal a boost voltage higher than a control voltage output from a controller due to the rectification of diodes, and applies the same to the gate of a transistor circuit of the antenna switch. Since in the booster circuit a resistor is coupled to the output terminal, the passage through resistors of an input transmission power in an RF signal path is only the passage through one resistor, thus reducing the attenuation of the transmission signal and providing an excellent insertion loss characteristic. | 2008-08-21 |
20080197924 | Variable gain amplifier circuit and filter circuit - This variable gain amplifier is provided with an operational amplifier. The non-inversion input terminal of the operational amplifier is connected to a reference potential. A feedback resistor is connected between the output terminal and inversion input terminal of the operational amplifier. An input resistor is inserted between the inversion input terminal of the operational amplifier and the input terminal of the variable gain amplifier circuit. An adjustment resistor is connected between the inversion input terminal of the operational amplifier and the reference potential. The resistance value of the adjustment resistor is controlled in such a way as to maintain constant against the resistance value change a combined resistance value in its parallel connection with the input resistor when changing the resistance value of the input resistor. | 2008-08-21 |
20080197925 | Distortion Compensation Amplifying Apparatus - In an amplifying apparatus performing distortion compensation by imparting pre-distortion, a table for distortion compensation is efficiently updated for improving the accuracy of distortion compensation even when the frequency of occurrences of levels near a peak of an input signal is low. Compensation values in a distortion compensation table | 2008-08-21 |
20080197926 | SOURCE FOLLOWER CIRCUIT AND SEMICONDUCTOR APPARATUS - Based on a result of comparing an output common mode direct-current voltage of a pair of source follower transistors when a direct-current voltage is applied to each gate of the pair of source follower transistors with a predetermined reference voltage, the direct-current voltage is controlled such that the output common mode direct-current voltage can match the reference voltage. | 2008-08-21 |
20080197927 | Constant bandwidth DC offset correction in an amplifier - According to one embodiment, a system for constant bandwidth DC offset correction in an amplifier includes a number of amplifier stages having an input and an output coupled together in series. The system for constant bandwidth DC offset correction further includes a number of DC offset correction feedback loops which include a variable gain transconductor coupled to an integration capacitor further coupled to a fixed gain transconductor. Each of the DC offset correction feedback loops are coupled to the input and output of each of the number of amplifier stages. The transconductance of the variable gain transconductor in each of the number of DC correction feedback loops is varied in relation to a gain of the number of amplifier stages, such that the DC offset correction feedback loops provide DC offset correction while maintaining a constant bandwidth. | 2008-08-21 |
20080197928 | THRESHOLD VOLTAGE COMPENSATION FOR A TWO STAGE AMPLIFIER - In an example embodiment, an apparatus, such as a two stage operational amplifier, comprising a first stage amplifier having an input and an output, and a second stage amplifier having an input and an output, the input of the second stage amplifier is coupled to the output of the first stage amplifier. A first bias circuit is operable to set a common mode voltage of the first amplifier. A second bias circuit is operable to set a common mode voltage of the second amplifier. A first feedback circuit is coupled to the first bias circuit and the output of the first stage. The first feedback circuit is operable to control the common mode voltage of the first stage amplifier based on the common mode voltage set by the first bias circuit and the output of the first stage amplifier. | 2008-08-21 |
20080197929 | Resonant Types Of Common-Source/Common-Emitter Struture For High Gain Amplification - Radio frequency/millimeter wave integrated circuits (RF/MMICs) that employ a resonance mechanism between an input stage and a transistor are disclosed. The circuits contain an input stage, a transistor; and a transformer connected between either a gate or a base of the transistor and a voltage supply of the input stage. The methods disclosed maximize either a collector current or a drain current of a transistor by placing a transformer between the transistor and a voltage source. | 2008-08-21 |
20080197930 | Digital Amplifier - Recently, the use of class D audio amplifiers has become more and more widespread. In contrast to the generally employed class A-B linear amplification technology, class D allows for improved efficiency. However, the class D principle is known for its poor distortion characteristics. According to the present invention, a digital amplifier is provided for converting an input signal to a power output. The digital amplifier according to the present invention comprises a supply ripple pre-compensation circuit for compensating voltage ripples on a supply voltage supplied to bridge circuits of the digital amplifier on the basis of the input signal. By this, supply ripples in the supply voltage supplied to the bridge which have been found to cause a major part of the distortions in the output signal of the digital amplifier may be compensated. | 2008-08-21 |
20080197931 | OSCILLATOR - The present invention provides an oscillation circuit including: a plurality of multi-stage inverter rings each having an odd number of inverters connected to each other in cascade to form a ring through the same odd number of nodes on the ring; an inverter group for connecting each one of the nodes on any specific one of the multi-stage inverter rings to a counterpart one of the nodes on another one of the multi-stage inverter rings so as to join the specific and other multi-stage inverter rings to each other in order to shift the phases of generated oscillation signals from each other by a fixed difference: and a current source connected to the inverters of the multi-stage inverter rings and the inverters of the inverter group. | 2008-08-21 |
20080197932 | VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator that is a differential ring oscillator type voltage controlled oscillator that, by connecting in cascade differential delay elements to which differential clock signals of a mutually reverse phase are input and controlling the current that flows to the differential delay elements by a bias voltage, controls a delay amount of this differential clock signal, having a phase detection portion that outputs a detection signal by comparing an output voltage of the differential output of any differential delay element and a reference voltage that is set to a voltage that detects an abnormal operation, and a cross-coupled circuit that is provided at each of the differential delay elements and, when the detection signal is input, amplifies the potential difference between the pair of differential output terminals. | 2008-08-21 |
20080197933 | METHOD OF ELIMINATING TEMPERATURE INDUCED BAND SWITCHING IN ULTRA WIDEBAND VOLTAGE CONTROLLED OSCILLATOR - A method and a voltage-controlled oscillator provide an output signal with a frequency within one of a plurality of frequency bands, while reducing or eliminating temperature-induced band-switching or other drifts in operating frequency. The band-switching is reduced or eliminated by providing a circuit that adjusts a tuning sensitivity according to a calibration performed under test conditions. For example, such a voltage-controlled oscillator may include (a) a digitally controlled variable current source for providing a first control current to select one of the frequency bands for the voltage-controlled oscillator; (b) a variable transconductance circuit providing a second control current to compensate a variation in operating frequency; and (c) a control circuit for varying the frequency of the output signal in accordance with the first and second control signals. The variable transconductance circuit may be programmable by selectively activating elements of an array of varactor circuits, according to a capacitance associated with each varactor circuit. The capacitance associated with each varactor circuit is binary weighted. | 2008-08-21 |
20080197934 | INTEGRATABLE CIRCUIT ARRANGEMENT AND INTEGRATED CIRCUIT - An integratable circuit arrangement is provided having a circuit unit, controllable by means of at least one control voltage, to provide a high-frequency output signal dependent on the at least one control voltage. According to the invention, (a) a clocked DC converter is provided, which is formed to provide at least one control voltage, depending on a control signal applied at its clock input, and (b) the circuit arrangement is formed to supply the clock input with a control signal, dependent on the high-frequency output signal. | 2008-08-21 |
20080197935 | Arrangement for Pulse-Width Modulating an Input Signal - An arrangement for pulse-width modulating an analog or digital input signal is provided. The non-linear distortion generated in the pulse-width modulator is precompensated by applying a signal with reversed error to the pulse-width modulator. The signal with reversed error is generated by a further pulse-width modulator that receives the input signal and whose output signal is subtracted from twice the input signal. The arrangement may e.g. be used to drive class D audio amplifiers. | 2008-08-21 |
20080197936 | Reconfigurable Phase-Shifter - The present invention relates to a phase shifter device arranged for altering the electrical length of a signal path between at least two different values, which device is adapted for guiding a signal through at least one of at least a first signal path, having a first phase and amplitude filter characteristics for varying frequency of the signal, and a second signal path, having a second phase and amplitude filter characteristics for varying frequency of the signal. At least one of said first and second phase and amplitude filter characteristics is realized by means of an all-pass filter. | 2008-08-21 |
20080197937 | High Directivity Ultra-Compact Coupler - A coupler includes a substrate and a stack of first and second dielectric layers extending over a top surface of the substrate. The first dielectric layer comprises different dielectric material than the second dielectric layer. Two conductive lines extend over the stack of first and second dielectric layers, and are formed in the same plane parallel to a surface of the substrate. | 2008-08-21 |
20080197938 | SYSTEM INCLUDING A HIGH DIRECTIVITY ULTRA-COMPACT COUPLER - A system with an RFin terminal and an RFout terminal includes an output matching network. The system further includes a coupler having a thru arm connected between the output matching network and the RFout terminal, and a coupled arm connected to a detector circuit. The coupler further includes a stack of first and second dielectric materials having different dielectric constants. The stack of first and second dielectric materials extends over a top surface of a substrate. The thru arm and the coupled arm extend over the stack of first and second dielectric materials in the same plane parallel to a surface of the substrate. | 2008-08-21 |
20080197939 | PASSIVE MICROWAVE (DE)MULTIPLEXER - The present invention relates to a microwave filter bank intended to be used either as or a multiplexer or de-multiplexer in a UWB-type system, said microwave filter bank including a plurality of filters and an interconnection network both connecting a first port (Pifb) of said microwave filter bank to other ports of said microwave filter bank. Said microwave filter bank is characterised in that said interconnection network includes a plurality of inductors, one of said inductors (Li), said first, has one of its extremities directly connected to said first port (Pifb) and its second extremity connected to the ground through a capacitor (Ci), said first, intended to minimize the effect of the reflection response of the microwave filter bank in its operating sub-bands without degrading its transmission response, said first inductor (Li) and capacitor (Ci) being intended to provide a nearly constant total admittance at said first port of said microwave filter bank for the operating band of each of said filters, each of other inductors, said second, is intended to provide a good in-band matching of the response of one of said filters with a targeted response. | 2008-08-21 |