33rd week of 2013 patent applcation highlights part 48 |
Patent application number | Title | Published |
20130210170 | Apparatus And Method For Repairing An Integrated Circuit - A method for repairing an integrated circuit comprises: fabricating a first circuit, the first circuit including a plurality of regular units and a plurality of redundant units, each of the regular units being identified by an address; performing a first test on the first circuit to determine if a defective regular unit is present; activating, if the defective regular unit is present, at least a first redundant unit to replace the defective regular unit, the first redundant unit being identified by an address of the defective regular unit; performing, if the at least first redundant unit is present, a second test on the first circuit to determine if the first redundant unit is defective; and activating at least a second redundant unit to replace the defective first redundant unit, the second redundant unit being identified by the address of the defective regular unit. | 2013-08-15 |
20130210171 | METHOD FOR MOLECULAR ADHESION BONDING WITH COMPENSATION FOR RADIAL MISALIGNMENT - A method for bonding a first wafer on a second wafer by molecular adhesion, where the wafers have an initial radial misalignment between them. The method includes bringing the two wafers into contact so as to initiate the propagation of a bonding wave between the two wafers while a predefined bonding curvature is imposed on at least one of the two wafers during the contacting step as a function of the initial radial misalignment. | 2013-08-15 |
20130210172 | WAFER THINNING APPARATUS HAVING FEEDBACK CONTROL AND METHOD OF USING - A wafer thinning apparatus includes a first metrology tool configured to measure an initial thickness of the wafer. The wafer thinning apparatus further includes a controller connected to the first metrology tool, and configured to determine a polishing time based on the initial thickness, a predetermined thickness and a material removal rate. The wafer thinning apparatus further includes a polishing tool connected to the controller configured to polish the wafer for a period of time equal to the polishing time. The wafer thinning apparatus includes a second metrology tool connected to the controller and the polishing tool, and configured to measure a polished thickness. The controller is configured to update the material removal rate based on the polished thickness, the predetermined thickness and the polishing time. | 2013-08-15 |
20130210173 | Multiple Zone Temperature Control for CMP - To provide improved planarization, techniques in accordance with this disclosure include a CMP station that includes a plurality of concentric temperature control elements arranged over a number of concentric to-be-polished wafer surfaces. During polishing, a wafer surface planarity sensor monitors relative heights of the concentric to-be-polished wafer surfaces, and adjusts the temperatures of the concentric temperature control elements to provide an extremely well planarized wafer surface. Other systems and methods are also disclosed. | 2013-08-15 |
20130210174 | RESIN COATING DEVICE AND RESIN COATING METHOD - In a resin coating used for manufacturing an LED package including an LED element coated with resin containing phosphor, a light-transmitting member test-coated with resin for an emission characteristic measurement on a light-transmitting member placing section including a light source unit, a deviation between a measurement result of an emission characteristic of light emitted from the resin coated on the light-transmitting member measured by an emission characteristic measurement unit by irradiating the resin with excitation light emitted from the light source unit and a prescribed emission characteristic is obtained, and an appropriate resin coating amount of the resin to be coated on the LED element for an actual production is derived based on the deviation. | 2013-08-15 |
20130210175 | Forming a Device Having a Curved Piezoelectric Membrane - Processes for forming an actuator having a curved piezoelectric membrane are disclosed. The processes utilize a profile-transferring substrate having a curved surface surrounded by a planar surface to form the curved piezoelectric membrane. The piezoelectric material used for the piezoelectric actuator is deposited on at least the curved surface of the profile-transferring substrate before the profile-transferring substrate is removed from the underside of the curved piezoelectric membrane. The resulting curved piezoelectric membrane includes grain structures that are columnar and aligned, and all or substantially all of the columnar grains are locally perpendicular to the curved surface of the piezoelectric membrane. | 2013-08-15 |
20130210176 | METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DEVICE - Provided is a method of manufacturing an organic light emitting device capable of suppressing a patterning defect caused by a residue of a release layer, the method including: a first organic compound layer formation step; a first protective layer formation step; a second protective layer formation step; a second protective layer processing step; a first protective layer processing step; a first organic compound layer processing step; a second organic compound layer formation step; and a lift-off step in which the pattern of the second protective layer obtained in the second protective layer processing step is formed also in a second region. | 2013-08-15 |
20130210177 | METHOD FOR MANUFACTURING AN ORGANIC ELECTRONIC DEVICE - The invention relates to method for manufacturing an electronic device comprising an organic layer ( | 2013-08-15 |
20130210178 | LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A light-emitting device and method for manufacturing the same are described. A method for manufacturing a light-emitting device comprising the steps of: providing a substrate; forming a light-emitting structure on the substrate, wherein the light-emitting structure comprising a plurality of chip areas and a plurality of street areas; forming a conductive structure between the substrate and the light-emitting structure; removing a part of the light-emitting structure in the street areas to expose a sidewall in the chip areas; forming a first passivation layer on the light-emitting structure in the chip areas; and forming a second passivation layer in the street areas, the sidewalls of the light-emitting structure, and the sidewalls of the first passivation layer. | 2013-08-15 |
20130210179 | PRINTING PHOSPHOR ON LED WAFER USING DRY FILM LITHOGRAPHY - A method for depositing a layer of phosphor-containing material on a plurality of LED (light-emitting diode) dies on a wafer includes disposing a layer of dry photoresist film over a plurality of LED dies on a wafer, disposing a mask layer over the dry photoresist film, and patterning the dry photoresist film to form a plurality of openings in the dry photoresist film to expose a top surface of each of the LED dies. The method also includes depositing a phosphor-containing material on the exposed top surface of each the LED dies using a screen printing process, and removing the patterned dry photoresist film. | 2013-08-15 |
20130210180 | LIGHT EMITTING DIODES - A method of producing a light emitting device comprises providing a wafer structure including a light emitting layer of III-nitride semiconductor material; dry etching the wafer at least part way through the light emitting layer so as to leave exposed surfaces of the emitting layer; and treating the exposed surfaces of the emitting layer with a plasma. The treatment may be using hot nitric acid or a hydrogen plasma. | 2013-08-15 |
20130210181 | PROCESS FOR PRODUCING A LAYER COMPOSITE CONSISTING OF A LUMINESCENCE CONVERSION LAYER AND A SCATTERING LAYER - A process of producing a layer composite includes a luminescence conversion layer and a scattering layer, wherein a press having a first pressing tool with a cavity and a second pressing tool is used including introducing a first polymer including a luminescence conversion substance into the cavity, inserting a film between the first and second tools, closing the press and carrying out a first pressing, hardening the first polymer to form a luminescence conversion layer in the press, opening the press, wherein the luminescence conversion layer adhering to the film remains in the press, introducing a second polymer including scattering particles into the cavity, closing the press and carrying out a second pressing, hardening the second polymer to form a scattering layer disposed on the luminescence conversion layer, opening the press, and removing the support film with the layer composite including the luminescence conversion layer and the scattering layer. | 2013-08-15 |
20130210182 | METHODS AND APPARATUS FOR MEASURING ANALYTES - Methods and apparatus relating to FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions. | 2013-08-15 |
20130210183 | ION IMPLANTATION METHOD, CARRIER, AND ION IMPLANTATION DEVICE - An ion implantation method includes: placing, in an atmosphere, a mask, which is used in conjunction with a tray for accommodating a substrate for a solar cell, at a first position covering a partial area on a surface of the substrate while maintaining the mask aligned relative to the substrate or at a second position distanced from the surface of the substrate; implanting, in a vacuum, ions in a first area on the surface of the substrate while the mask is placed at the first position; and implanting, in a vacuum, ions in a second area on the surface of the substrate while the mask is placed at the second position. | 2013-08-15 |
20130210184 | PATTERNING - A method for patterning an article, the article comprising a first layer of a first material, a first major surface of the first layer being in intimate contact with some or all of a first major surface of a second layer of a second different material the method comprising providing a first thread carrying a first species to remove at least a portion of the first layer, and providing a second thread aligned with and adjacent the first thread and contacting the first and second threads with the first layer to remove at least part of the first layer. | 2013-08-15 |
20130210185 | METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A crystalline-based silicon photoelectric conversion device comprises: an intrinsic silicon-based layer and a silicon-based layer of a first conductivity type, on one surface of a single-crystal silicon substrate of the first conductivity type; and an intrinsic silicon-based and a silicon-based layer of an opposite conductivity type, in this order on the other surface of the silicon substrate. At least one of forming the intrinsic silicon-based layer of the first conductivity type layer-side forming the intrinsic silicon-based layer of the opposite conductivity type layer-side includes: forming a first intrinsic silicon-based thin-film layer having a thickness of 1-10 nm on the silicon substrate; plasma-treating the silicon substrate in a gas containing mainly hydrogen; and forming a second intrinsic silicon-based thin-film layer on the first intrinsic silicon-based thin-film. | 2013-08-15 |
20130210186 | METHOD FOR MANUFACTURING FLEXIBLE SOLAR CELL MODULE - An object of the present invention is to provide a method for producing a flexible solar cell module which makes it possible to suitably produce flexible solar cell modules in which a solar cell element and a solar cell encapsulant sheet are well adhered to each other by encapsulating a solar cell by roll-to-roll processing in a continuous manner without the need to perform a crosslinking process and without causing wrinkles and curls. The present invention is a method for producing a flexible solar cell module, including thermocompression bonding of a solar cell encapsulant sheet to at least a light-receiving surface of a solar cell element that includes a flexible substrate and a photoelectric conversion layer on the flexible substrate by pressing the solar cell encapsulant sheet and the solar cell element together between a pair of heating rolls, the solar cell encapsulant sheet including a fluoropolymer sheet and an adhesive layer on the fluoropolymer sheet, the adhesive layer including at least one ethylene copolymer selected from the group consisting of ethylene-unsaturated carboxylic acid copolymers and ionomers of ethylene-unsaturated carboxylic acid copolymers, the ethylene copolymer including 10 to 25% by weight of unsaturated carboxylic acid units. | 2013-08-15 |
20130210187 | METHOD OF MANUFACTURING SOLAR CELL - A solar cell is manufactured, which includes: a solar cell substrate including a semiconductor substrate, a p-type surface and an n-type surface exposed on a first principal surface, and a texture structure in a second principal surface; a p-side electrode disposed on the p-type surface; an n-side electrode disposed on the n-type surface; and an insulation layer formed on the first principal surface and isolating the p-side electrode and the n-side electrode from each other. The manufacturing method of the solar cell includes: forming an insulation film covering the first principal surface; forming the texture structure in the second principal surface; and removing part of the insulation film, thereby forming the insulation layer. | 2013-08-15 |
20130210188 | Method and Apparatus for Reducing Stripe Patterns - A method for reducing stripe patterns comprising receiving scattered light signals from a backside surface of a laser annealed backside illuminated image sensor wafer, generating a backside surface image based upon the scattered light signals, determining a distance between an edge of a sensor array of the laser anneal backside illuminated image sensor wafer and an adjacent boundary of a laser beam and re-calibrating the laser beam if the distance is less than a predetermined value. | 2013-08-15 |
20130210189 | ENHANCED BULK HETEROJUNCTION DEVICES PREPARED BY THERMAL AND SOLVENT VAPOR ANNEALING PROCESSES - A method of preparing a bulk heterojunction organic photovoltaic cell through combinations of thermal and solvent vapor annealing are described. Bulk heterojunction films may prepared by known methods such as spin coating, and then exposed to one or more vaporized solvents and thermally annealed in an effort to enhance the crystalline nature of the photoactive materials. | 2013-08-15 |
20130210190 | APPARATUS AND METHOD FOR PRODUCING SOLAR CELLS - A method and apparatus for forming a solar cell. The apparatus includes a housing defining a vacuum chamber and a rotatable substrate apparatus configured to hold a plurality of substrates on a plurality of surfaces wherein each of the plurality of surfaces are disposed facing an interior surface of the vacuum chamber. A first sputtering source is configured to deposit a plurality of absorber layer atoms of a first type over at least a portion of a surface of each one of the plurality of substrates. An evaporation source is disposed in a first subchamber of the vacuum chamber and configured to deposit a plurality of absorber layer atoms of a second type over at least a portion of the surface of each one of the plurality of substrates. A first isolation source is configured to isolate the evaporation source from the first sputtering source. | 2013-08-15 |
20130210191 | High-Throughput Printing of Semiconductor Precursor Layer by Use of Chalcogen-Rich Chalcogenides - A high-throughput method of forming a semiconductor precursor layer by use of a chalcogen-rich chalcogenides is disclosed. The method comprises forming a precursor material comprising group IB-chalcogenide and/or group IIIA-chalcogenide particles, wherein an overall amount of chalcogen in the particles relative to an overall amount of chalcogen in a group IB-IIIA-chalcogenide film created from the precursor material, is at a ratio that provides an excess amount of chalcogen in the precursor material. The excess amount of chalcogen assumes a liquid form and acts as a flux to improve intermixing of elements to form the group IB-IIIA-chalcogenide film at a desired stoichiometric ratio, wherein the excess amount of chalcogen in the precursor material is an amount greater than or equal to a stoichiometric amount found in the IB-IIIA-chalcogenide film. | 2013-08-15 |
20130210192 | Semiconductor Component - The invention concerns a semiconductor component with a layered arrangement with an electrode, an organic semiconductor layer, an injection layer, and an additive layer, which consists of an additive, which on contact with the molecular doping material modifies its doping affinity with respect to the organic material of the organic semiconductor layer, wherein in the injection layer a layered region is formed with a first doping affinity of the molecular doping material with respect to the organic material and a further layered region is formed with a second, in comparison to the first doping affinity smaller, doping affinity of the molecular doping material with respect to the organic material. Furthermore the invention concerns a method for the manufacture of a semiconductor component and also the application of a semiconductor component. | 2013-08-15 |
20130210193 | ReRAM STACKS PREPARATION BY USING SINGLE ALD OR PVD CHAMBER - Systems and methods for preparing resistive switching memory devices such as resistive random access memory (ReRAM) devices wherein both oxide and nitride layers are deposited in a single chamber are provided. Various oxide and nitride based layers in the ReRAM device such as the switching layer, current-limiting layer, and the top electrode (and optionally the bottom electrode) are deposited in the single chamber. By fabricating the ReRAM device in a single chamber, throughput is increased and cost is decreased. Moreover, processing in a single chamber reduces device exposure to air and to particulates, thereby minimizing device defects. | 2013-08-15 |
20130210194 | METHOD OF TRANSFERRING AND BONDING AN ARRAY OF MICRO DEVICES - Electrostatic transfer head array assemblies and methods of transferring and bonding an array of micro devices to a receiving substrate are described. In an embodiment, a method includes picking up an array of micro devices from a carrier substrate with an electrostatic transfer head assembly supporting an array of electrostatic transfer heads, contacting a receiving substrate with the array of micro devices, transferring energy from the electrostatic transfer head assembly to bond the array of micro devices to the receiving substrate, and releasing the array of micro devices onto the receiving substrate. | 2013-08-15 |
20130210195 | PACKAGING METHOD OF MOLDED WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) - A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove. | 2013-08-15 |
20130210196 | SEMICONDUCTOR PACKAGE WITH INTEGRATED SUBSTRATE THERMAL SLUG - To reduce the thermal stresses that may be caused by a difference in thermal expansion coefficients between a molded casing and an active side of a semiconductor device embedded in the molded casing, and thus reduce the number of corresponding failures caused by the thermal stresses, the active side of the semiconductor device is arranged face-down, towards a substrate supporting the semiconductor device. The semiconductor device includes a through via that electrically connects the active side of the semiconductor device to a passive side of the semiconductor device. A wire bond electrically connects the passive side of the semiconductor device to the substrate. To increase the dissipation of heat generated in the semiconductor device, a thermally conductive slug may be disposed in the substrate, and the active side of the semiconductor device may be attached to the thermally conductive slug. | 2013-08-15 |
20130210197 | LEADFRAME BASED MULTI TERMINAL IC PACKAGE - A semiconductor package comprises a die attach pad and a support member at least partially circumscribing it. Several sets of contact pads are attached to the support member. The support member is able to be etched away thereby electrically isolating the contact pads. A method for making a leadframe and subsequently a semiconductor package comprises partially etching desired features into a copper substrate, and then through etching the substrate to form the support member and several sets of contact pads. Die attach, wirebonding and molding follow. The support member is etched away, electrically isolating the contact pads and leaving a groove in the bottom of the package. The groove is able to be filled with epoxy or mold compound. | 2013-08-15 |
20130210198 | PROCESS FOR FORMING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure. A semiconductor substrate including a plurality of dies mounted thereon is provided. The substrate includes a first portion proximate to the dies and a second portion distal to the dies. In some embodiments, the first portion may include front side metallization. The second portion of the substrate is thinned and a plurality of conductive through substrate vias (TSVs) is formed in the second portion of the substrate after the thinning operation. Prior to thinning, the second portion may not contain metallization. In one embodiment, the substrate may be a silicon interposer. Further back side metallization may be formed to electrically connect the TSVs to other packaging substrates or printed circuit boards. | 2013-08-15 |
20130210199 | METHOD FOR DEPOSITING AN ENCAPSULATING FILM - A method and apparatus for depositing a material layer, such as encapsulating film, onto a substrate is described. In one embodiment, an encapsulating film formation method includes delivering a gas mixture into a processing chamber, the gas mixture comprising a silicone-containing gas, a first nitrogen-containing gas, a second nitrogen-containing gas and hydrogen gas; energizing the gas mixture within the processing chamber by applying between about 0.350 watts/cm | 2013-08-15 |
20130210200 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention prevents a conductive fuse blown out by laser trimming from reconnecting by a plating electrode in a plating process and prevents a plating solution etc from entering a fuse blowout portion. On a semiconductor substrate of a multilayered wiring structure including a fuse blowout groove formed by blowing out a conductive fuse by laser trimming in a trimming element forming region, a second protection layer is formed so as to cover the trimming element forming region and then a plating electrode is formed on an draw-out pad electrode made of a topmost metal wiring. A third protection layer is then formed so as to cover the semiconductor substrate including the second protection layer and have an opening on the plating electrode. | 2013-08-15 |
20130210201 | METHOD FOR MANUFACTURING ACTIVE ARRAY SUBSTRATE - A method for manufacturing an active array substrate is provided herein. The active array substrate can be manufactured by using only two photolithography process steps. The photolithography process step using a first photomask may be provided for forming a drain electrode, a source electrode, a data line and/or a data line connecting pad and a patterned transparent conductive layer, etc. The photolithography process step using a second photomask may be utilized for forming a gate electrode, a gate line, a gate insulating layer, a channel layer and/or a gate line connecting pad, and so forth. | 2013-08-15 |
20130210202 | METHOD OF PLANARIZING SUBSTRATE AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR USING THE SAME - A method of planarizing a substrate includes forming a conductive pattern on a first surface of a base substrate, forming a positive photoresist layer on the base substrate and the conductive pattern, exposing the positive photoresist layer to light by irradiating a second surface of the base substrate opposite to the first surface with light, developing the positive photoresist layer to form a protruded portion on the conductive pattern, forming a planarizing layer on the base substrate and the protruded portion and eliminating the protruded portion. | 2013-08-15 |
20130210203 | METHOD OF MANUFACTURING COMPOUND SEMICONDUCTOR DEVICE - A compound semiconductor device has a buffer layer formed on a conductive SiC substrate, an AlxGa1-xN layer formed on the buffer layer in which an impurity for reducing carrier concentration from an unintentionally doped donor impurity is added and in which the Al composition x is 02013-08-15 | |
20130210204 | METHOD FOR ETCHING POLYCRYSTALLINE SILICON, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ETCHING PROGRAM - According to an embodiment, a method for etching polycrystalline silicon includes a step of holding the polycrystalline silicon at a temperature higher than or equal to T | 2013-08-15 |
20130210205 | MANUFACTURING METHOD OF POWER TRANSISTOR DEVICE WITH SUPER JUNCTION - The present invention provides a manufacturing method of a power transistor device. First, a semiconductor substrate of a first conductivity type is provided, and at least one trench is formed in the semiconductor substrate. Next, the trench is filled with a dopant source layer, and a first thermal drive-in process is performed to form two doped diffusion regions of a second conductivity type in the semiconductor substrate, wherein the doping concentration of each doped diffusion region close to the trench is different from the one of each doped diffusion region far from the trench. Then, the dopant source layer is removed and a tilt-angle ion implantation process and a second thermal drive-in process are performed to adjust the doping concentration of each doped diffusion region close to the trench. | 2013-08-15 |
20130210206 | BULK FIN-FIELD EFFECT TRANSISTORS WITH WELL DEFINED ISOLATION - A fin field-effect-transistor fabricated by forming a dummy fin structure on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. The dielectric layer surrounds the dummy fin structure. The dummy fin structure is removed to form a cavity within the dielectric layer. The cavity exposes a portion of the semiconductor substrate thereby forming an exposed portion of the semiconductor substrate within the cavity. A dopant is implanted into the exposed portion of the semiconductor substrate within the cavity thereby creating a dopant implanted exposed portion of the semiconductor substrate within the cavity. A semiconductor layer is epitaxially grown within the cavity atop the dopant implanted exposed portion of the semiconductor substrate. | 2013-08-15 |
20130210207 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF DYNAMIC THRESHOLD TRANSISTOR - A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion. | 2013-08-15 |
20130210208 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A first layer constituting a first surface of a silicon carbide layer and of a first conductivity type is prepared. An internal trench is formed at a face opposite to the first surface of the first layer. Impurities are implanted such that the conductivity type of the first layer is inverted on the sidewall of the internal trench. By the implantation of impurities, there are formed from the first layer an implantation region located on the sidewall of the internal trench and of a second conductivity type, and a non-implantation region of the first conductivity type. A second layer of the first conductivity type is formed, filling the internal trench, and constituting the first region together with the non-implantation region. | 2013-08-15 |
20130210209 | METHOD OF INTEGRATING A CHARGE-TRAPPING GATE STACK INTO A CMOS FLOW - Embodiments of a method of integration of a non-volatile memory device into a MOS flow are described. Generally, the method includes: forming a dielectric stack on a surface of a substrate, the dielectric stack including a tunneling dielectric overlying the surface of the substrate and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack; patterning the cap layer and the dielectric stack to form a gate stack of a memory device in a first region of the substrate and to remove the cap layer and the charge-trapping layer from a second region of the substrate; and performing an oxidation process to form a gate oxide of a MOS device overlying the surface of the substrate in the second region while simultaneously oxidizing the cap layer to form a blocking oxide overlying the charge-trapping layer. Other embodiments are also disclosed. | 2013-08-15 |
20130210210 | SILICON GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR STRUCTURE AND METHOD - Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology. | 2013-08-15 |
20130210211 | Vertical Cross-Point Memory Arrays - A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F | 2013-08-15 |
20130210212 | Semiconductor Device Manufacturing Methods - Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece. | 2013-08-15 |
20130210213 | METHOD FOR FORMING SELF-ALIGNED OVERLAY MARK - A method for forming a self-aligned overlay mark is disclosed. First, a first region, a second region and a main feature which is disposed between the first region and the second region all disposed on the substrate are provided. The first region defines a first edge and the second region defines a second edge. Second, a cut mask layer is formed to respectively cover the first region and the second region to expose the main feature. Next, the cut mask layer is determined if it is self-aligned with the second edge or the first edge, and creates a self-aligned overlay mark. Later, a main feature etching step is carried out to transfer the main feature into the substrate when the cut mask layer is determined to be self-aligned with the second edge or the first edge. | 2013-08-15 |
20130210214 | VERTICAL INTEGRATION OF CMOS ELECTRONICS WITH PHOTONIC DEVICES - A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure. | 2013-08-15 |
20130210215 | PACKAGING METHOD WITH BACKSIDE WAFER DICING - A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a centre area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside. | 2013-08-15 |
20130210216 | EPITAXIAL CHANNEL FORMATION METHODS AND STRUCTURES - A method for forming field effect transistors (FETs) in a multiple wafers per batch epi-reactor includes, providing substrates having therein at least one semiconductor (SC) region with a substantially flat outer surface, modifying such substantially flat outer surface to form a convex-outward curved surface, forming an epitaxial semiconductor layer on the curved surface, and incorporating the epitaxial layer in a field effect transistor formed on the substrate. Where the SC region is of silicon, the epitaxial layer can include silicon-germanium. In a preferred embodiment, the epi-layer forms part of the FET channel. Because of the convex-outward curved surface, the epi-layer grown thereon has much more uniform thickness even when formed in a high volume reactor holding as many as 100 or more substrates per batch. FETs with much more uniform properties are obtained, thereby greatly increasing the manufacturing yield and reducing the cost. | 2013-08-15 |
20130210217 | Precursors for GST Films in ALD/CVD Processes - The present invention is a process of making a germanium-antimony-tellurium alloy (GST) or germanium-bismuth-tellurium (GBT) film using a process selected from the group consisting of atomic layer deposition and chemical vapor deposition, wherein a silylantimony precursor is used as a source of antimony for the alloy film. The invention is also related to making antimony alloy with other elements using a process selected from the group consisting of atomic layer deposition and chemical vapor deposition, wherein a silylantimony or silylbismuth precursor is used as a source of antimony or bismuth. | 2013-08-15 |
20130210218 | METHOD FOR TRANSFERRING A GRAPHENE LAYER - A method transfers a graphene layer from a donor substrate onto a final substrate. The method includes: providing a metal layer on the donor substrate; and growing a graphene layer on the metal layer. The method also includes: laminating a dry film photo-resist on the graphene layer; laminating a tape on the dry film photo-resist; chemically. etching the metal layer, obtaining an initial structure that includes the tape, the dry film photo-resist and the graphene layer; laminating the initial structure on the final substrate; thermally realizing the tape, so as to obtain an intermediate structure that includes the dry film photo-resist, the graphene layer and the final substrate; removing the dry film photo-resist; and obtaining a final structure that includes the final substrate with a transferred graphene layer. | 2013-08-15 |
20130210219 | ANTIMONIDE-BASED COMPOUND SEMICONDUCTOR WITH TITANIUM TUNGSTEN STACK - An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer. | 2013-08-15 |
20130210220 | METHODS OF FORMING REVERSE SIDE ENGINEERED III-NITRIDE DEVICES - Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed. | 2013-08-15 |
20130210221 | SELECTIVE EPITAXIAL GERMANIUM GROWTH ON SILICON-TRENCH FILL AND IN SITU DOPING - Methods and apparatus for forming a germanium containing film on a patterned substrate are described. The patterned substrate is a silicon, or silicon containing material, and may have a mask material formed on a surface thereof. The germanium containing material is formed selectively on exposed silicon in the recesses of the substrate, and an overburden of at least 50% is formed on the substrate. The germanium containing layer is thermally treated using pulsed laser radiation, which melts a portion of the overburden, but does not melt the germanium containing material in the recesses. The germanium containing material in the recesses is typically annealed, at least in part, by the thermal treatment. The overburden is then removed. | 2013-08-15 |
20130210222 | SEMICONDUCTOR DEVICES HAVING CONDUCTIVE VIA STRUCTURES AND METHODS FOR FABRICATING THE SAME - In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer. | 2013-08-15 |
20130210223 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES USING MODIFIED RECTANGULAR MASK PATTERNS TO INCREASE RELIABILITY OF CONTACTS TO ELECTRICALLY CONDUCTIVE LINES - Methods of forming integrated circuit devices include forming first and second electrically conductive lines at side-by-side locations on an integrated circuit substrate. Steps are performed to selectively etch each of the first and second electrically conductive lines into a respective pair of interconnects having facing ends that are separated from each other. This selective etching step is performed using a photolithography mask having a modified-rectangular mask pattern thereon, which is configured to define a shape of the facing ends of each of the pair of interconnects. | 2013-08-15 |
20130210224 | METHOD AND APPARATUS FOR DIVIDING THIN FILM DEVICE INTO SEPARATE CELLS - A method and apparatus for dividing a thin film device having a first layer which is a lower electrode layer, a second layer which is an active layer and a third layer which is an upper electrode layer, the layers each being continuous over the device, into separate cells each having a width W, which are electrically interconnected in series by interconnect structures. The dividing of the cells and the formation of the interconnect structures between adjacent cells are carried out by a process head which is arranged to operate on more than one interconnect structure at a time in a sequence of passes to and fro over the device, the process head performing the following steps: a) making a first cut through the first, second and third layers; b) making a second cut through the second and third layers, the second cut being adjacent to the first cut; c) making a third cut through the third layer the third cut being adjacent to the second cut and on the opposite side of the second cut to the first cut; d) using a first ink jet print head to deposit a non-conducting material into the first cut; and e) using a second ink jet print head to apply conducting material to bridge the non-conducting material in the first cut and either fully or partially fill the second cut such to form an electrical connection between the first layer and the third layer, wherein step (a) precedes step (d), step (d) precedes step (e) and step (b) precedes step (e), (otherwise the steps may be carried out in any order in the single pass of the process head across the device). The thin film device may be a solar panel, a lighting panel or a battery. | 2013-08-15 |
20130210225 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes etching a substrate to form a pillar isolated by a trench, forming a buffer layer along the entire structure including the pillar, forming a diffusion barrier layer that exposes a portion of the buffer layer at a first sidewall of the pillar, forming a liner layer along the entire structure including the diffusion barrier layer, selectively ion-implanting dopants into the liner layer, and forming a junction in the first sidewall of the pillar by diffusing the dopants through a thermal process. | 2013-08-15 |
20130210226 | PATTERN FORMATION METHOD - According to one embodiment, a pattern formation method comprises forming a hard mask material on a processed film on a wiring, forming a guide layer on the hard mask material, forming a tetragonal opening in the guide layer, coating the opening with a block polymer, heating the block polymer to form a micro phase separation structure film in which first polymer parts and second polymer parts parallel to the wiring are alternately arranged, removing the second polymer part while leaving the first polymer part, processing the hard mask material with the guide layer and the first polymer part as a mask to form a first hole pattern in the hard mask material, and processing the processed film with the hard mask material as a mask to form a second hole pattern corresponding to the first hole pattern in the processed film. | 2013-08-15 |
20130210227 | USE OF CONTACTS TO CREATE DIFFERENTIAL STRESSES ON DEVICES - Disclosed herein are various methods and structures using contacts to create differential stresses on devices in an integrated circuit (IC) chip. An IC chip is disclosed having a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), a PFET contact to a source/drain region of the PFET and an NFET contact to a source/drain region of the NFET. In a first embodiment, a silicon germanium (SiGe) layer is included only under the PFET contact, between the PFET contact and the source/drain region of the PFET. In a second embodiment, either the PFET contact extends into the source/drain region of the PFET or the NFET contact extends into the source/drain region of the NFET. | 2013-08-15 |
20130210228 | METHOD OF FORMING PITCH MULTIPLIED CONTACTS - Methods of forming electrically conductive and/or semiconductive features for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. The features can have a reduced pitch in one direction and a wider pitch in another direction. Conventional photo-lithography steps can be used in combination with pitch-reduction techniques to form elongate, pitch-reduced features such as bit-line contacts, for example. | 2013-08-15 |
20130210229 | SILICON-CONTAINING SURFACE MODIFIER, RESIST LOWER LAYER FILM-FORMING COMPOSITION CONTAINING THE SAME, AND PATTERNING PROCESS - The present invention provides a silicon-containing surface modifier containing one or more repeating units each represented by the following general formula (A), or one or more partial structures each represented by the following general formula (C): | 2013-08-15 |
20130210230 | METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES - An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face. | 2013-08-15 |
20130210231 | METHOD OF FORMING CONTACT HOLE PATTERN - A method of forming a contact hole pattern, including: a block copolymer layer forming step in which a layer containing a block copolymer having a plurality of blocks bonded is formed on a substrate having on a surface thereof a thin film with a hole pattern formed, so as to cover the thin film; a phase separation step in which the layer containing the block copolymer is subjected to phase separation; a selective removing step in which phase of at least one block of the plurality of blocks constituting the block copolymer is removed, wherein hole diameter of the hole pattern formed on the thin film is 0.8 to 3.1 times period of the block copolymer, and in the layer forming step, thickness between upper face of the thin film and surface of the layer containing the block copolymer is 70% or less of thickness of the thin film. | 2013-08-15 |
20130210232 | CUT-MASK PATTERNING PROCESS FOR FIN-LIKE FIELD EFFECT TRANSISTOR (FINFET) DEVICE - A method for patterning a plurality of features in a non-rectangular pattern, such as on an integrated circuit device, includes providing a substrate including a surface with a plurality of elongated protrusions, the elongated protrusions extending in a first direction. A first layer is formed above the surface and above the plurality of elongated protrusions, and patterned with an end cutting mask. The end cutting mask includes two nearly-adjacent patterns with a sub-resolution feature positioned and configured such that when the resulting pattern on the first layer includes the two nearly adjacent patterns and a connection there between. The method further includes cutting ends of the elongated protrusions using the pattern on the first layer. | 2013-08-15 |
20130210233 | Methods for Particle Reduction in Semiconductor Processing - Methods for removing particles from a wafer for photolithography. A method is provided including providing a semiconductor wafer; attaching a polyimide layer to a backside of the semiconductor wafer; and performing an etch on an active surface of the semiconductor wafer; wherein particles that impinge on the backside during the etch are captured by the polyimide layer. In another method, includes attaching a layer of polyimide film to a backside of a semiconductor wafer; dry etching a material on an active surface of the semiconductor wafer; depositing of an additional layer of material on the active surface of the semiconductor wafer; removing the layer of polyimide film from the backside of the semiconductor wafer; patterning the layer of material using an immersion photolithography process to expose a photoresist on the active surface of the wafer; and repeating the attaching, dry etching, depositing, removing and patterning steps. | 2013-08-15 |
20130210234 | LITHOGRAPHY PROCESSES UTILIZING EXTREME ULTRAVIOLET RAYS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - Lithography processes are provided. The lithography process includes installing a reticle masking (REMA) part having a REMA open region in a lithography apparatus, loading a reticle including at least one reticle chip region in which circuit patterns are disposed into the lithography apparatus, and sequentially exposing a first wafer field, which includes a first chip region corresponding to the reticle chip region, and a second wafer field, which includes a second chip region corresponding to the reticle chip region, of a wafer to rays using the reticle and the REMA part to transfer images of the circuit patterns onto the wafer. An edge boundary of the REMA open region transferred on the first wafer field is located on a scribe lane region between the first and second chip regions while the first wafer field is exposed. Methods of manufacturing a semiconductor device using the lithography process are also provided. | 2013-08-15 |
20130210235 | APPARATUS AND METHOD FOR THE RAPID THERMAL CONTROL OF A WORK PIECE IN LIQUID OR SUPERCRITICAL FLUID - A surface cleaning apparatus comprising a chamber, and a thermal transfer device. The chamber is capable of holding a semiconductor structure therein. The thermal transfer device is connected to the chamber. The thermal transfer device has a surface disposed inside the chamber for contacting the semiconducting structure and controlling a temperature of the semiconductor structure in contact with the surface. The thermal transfer device has a thermal control module connected to the surface for heating and cooling the surface to thermally cycle the surface. The thermal control module effects a substantially immediate thermal response of the surface when thermally recycling the surface. | 2013-08-15 |
20130210236 | SILICON-CONTAINING SURFACE MODIFIER, RESIST UNDERLAYER FILM COMPOSITION CONTAINING THIS, AND PATTERNING PROCESS - The present invention provides a silicon-containing surface modifier wherein the modifier contains one or more of a repeating unit shown by the following general formula (A) and a partial structure shown by the following general formula (C).The present invention has an object to provide a resist underlayer film applicable not only to a negatively developed resist pattern formed by a hydrophilic organic compound but also to a conventional positively developed resist pattern formed by a hydrophobic compound. | 2013-08-15 |
20130210237 | PHOTORESIST REMOVAL METHOD AND PATTERNING PROCESS UTILIZING THE SAME - A photoresist removal method is described. A substrate having thereon a positive photoresist layer to be removed is provided. The positive photoresist layer is UV-exposed without using a photomask. A development liquid is used to remove the UV-exposed positive photoresist layer. The substrate as provided may further have thereon a sacrificial masking layer under the positive photoresist layer. The sacrificial masking layer is removed after the UV-exposed positive photoresist layer is removed. | 2013-08-15 |
20130210238 | Multi-Injector Spatial ALD Carousel and Methods of Use - A substrate processing chamber and methods for processing multiple substrates is provided and generally includes a plurality of spaced gas distribution assemblies and a substrate support apparatus to rotate substrates along a path adjacent each of the plurality of gas distribution assemblies. Each of the gas distribution assemblies comprises a plurality of elongate gas ports extending in a direction substantially perpendicularly to the path traversed by the substrate. | 2013-08-15 |
20130210239 | PRE-CUT WAFER APPLIED UNDERFILL FILM - A method for preparing a semiconductor with preapplied underfill comprises providing a semiconductor wafer with a plurality of metallic bumps on its top side and, optionally, through-silica-vias vertically through the silicon wafer; laminating a back grinding tape to the top of the wafer covering the metallic bumps and through silicon vias; thinning the back side of the wafer; mounting a dicing tape to the back side of the thinned wafer and mounting the silicon wafer and dicing tape to a dicing frame; removing the back grinding tape; providing an underfill material precut into the shape of the wafer; aligning the underfill on with the wafer and laminating the underfill to the wafer. | 2013-08-15 |
20130210240 | METHODS AND APPARATUS FOR SELECTIVE OXIDATION OF A SUBSTRATE - Methods and apparatus for improving selective oxidation against metals in a process chamber are provided herein. In some embodiments, a method of oxidizing a first surface of a substrate disposed in a process chamber having a processing volume defined by one or more chamber walls may include exposing the substrate to an oxidizing gas to oxidize the first surface; and actively heating at least one of the one or more chamber walls to increase a temperature of the one or more chamber walls to a first temperature of at least the dew point of water while exposing the substrate to the oxidizing gas. | 2013-08-15 |
20130210241 | Precursors for Plasma Activated Conformal Film Deposition - A method of depositing a film on a substrate surface includes providing a substrate in a reaction chamber; selecting a silicon-containing reactant from a precursor group consisting of di-tert-butyl diazidosilane, bis(ethylmethylamido)silane, bis(diisopropylamino)silane, bis(tert-butylhydrazido)diethylsilane, tris(dimethylamido) silylazide, tris(dimethylamido)silylamide, ethylsilicon triazide, diisopropylaminosilane, and hexakis(dimethylamido)disilazane; introducing the silicon-containing reactant in vapor phase into the reaction chamber under conditions allowing the silicon-containing reactant to adsorb onto the substrate surface; introducing a second reactant in vapor phase into the reaction chamber while the silicon-containing reactant is adsorbed on the substrate surface, and wherein the second reactant is introduced without first sweeping the silicon-containing reactant out of the reaction chamber; and exposing the substrate surface to plasma to drive a reaction between the silicon-containing reactant and the second reactant on the substrate surface to form the film. | 2013-08-15 |
20130210242 | LASER ANNEALING TREATMENT APPARATUS AND LASER ANNEALING TREATMENT METHOD - Provided is a laser annealing treatment including a laser light source that outputs pulse laser light, an optical system that shapes the pulse laser light, and leads the shaped pulse laser light to a semiconductor film subject to treatment, and a stage that carries the semiconductor film to be irradiated by the pulse laser light, wherein the pulse laser light irradiating the semiconductor film presents a rising time equal to or less than 35 nanoseconds from 10% of the maximum height to the maximum height in the pulse energy density, and a falling time equal to or more than 80 nanoseconds from the maximum height to 10% of the maximum height, thereby increasing, while an energy density suitable for crystallization and the like is not particularly increased, a margin quantity thereof, and carrying out high quality annealing treatment without decreasing a throughput. | 2013-08-15 |
20130210243 | LONG-LIFE METAL SLIDING CONTACTS - In one embodiment, a sliding contact system includes a first metal contact, a second metal contact in sliding engagement with the first contact, and a lubricant in which the first metal contact and the second metal contact are immersed to inhibit oxidation and cold welding of the contacts. | 2013-08-15 |
20130210244 | MAGNETIC ARRANGEMENTS AND LABELS FOR CONNECTORS - Magnetic connectors that may be readily manufactured and provide a high landed force and labels for magnetic connectors that may protect magnets or magnetic elements in the connectors, provide an aesthetically pleasing appearance, and improve the magnetic performance of the connectors. In various examples, power and signal paths may be formed using contacts that are separate from magnets or magnetic elements, paths may be formed using magnets or magnetic elements, or paths may be formed using a combination of contacts and magnets and magnetic elements. The magnets may have various arrangements. One or more magnets may be used in conjunction with magnetic elements. The interface surface of these magnets and magnetic elements may have various contours, such as flat, spline, or involute. | 2013-08-15 |
20130210245 | INTERPOSER AND METHOD FOR PRODUCING HOLES IN AN INTERPOSER - An interposer for electrical connection between a CPU chip and a circuit board is provided. The interposer includes a board-shaped base substrate made of glass having a coefficient of thermal expansion ranging from 3.1×10 | 2013-08-15 |
20130210246 | Midplane Orthogonal Connector System - A receptacle assembly for a midplane connector system has a receptacle housing having openings receiving signal contacts and ground shields of a header assembly. The receptacle assembly includes contact modules coupled to the receptacle housing that each have a leadframe, a dielectric frame and a ground shield. The leadframe has signal contacts arranged in pairs carrying differential signals that are generally arranged along a leadframe plane with mating portions at ends thereof that have at least two points of contact electrically connected to a corresponding signal contact of the header assembly. The dielectric frame holds the signal contacts. The ground shield is coupled to a side of the dielectric frame and has ground tabs extending into the dielectric frame to provide electrical shielding between the pairs of signal contacts and grounding beams electrically connected to ground shields of the header assembly. | 2013-08-15 |
20130210247 | CONTACT ELEMENT FOR PLUG-IN CONNECTOR SOCKET - To compensate the lateral offset of an opposing plug, a contact element for a plug-in connector socket has particularly large tolerances. For this purpose, the contact element is embodied in two pieces, a contact spring element for making electrical contact with the opposing plug and a securing element in which the contact spring element is mounted so as to be rotatable about a rotational axis. In contrast to a case in which tolerances depend on deformation of a spring element, by virtue of rotation of the contact spring element no forces act on the soldering points with which the securing element is soldered to a printed circuit board. The contact element is particularly suitable for soldering according to SMT. | 2013-08-15 |
20130210248 | EARTH CONNECTION FOR ELECTRICALLY AND MECHANICALLY CONNECTING EARTH WIRES - An earth connection for electrically and mechanically connecting a plurality of earth wires to a structure, in particular to an aircraft structure, comprising an angled element which element is formed in one piece and is made of electrically conductive material, which comprises a first and a second fastening portion. The first fastening portion is fastened to the structure and the second fastening portion comprises a plurality of electrical connections for connecting the earth wires. The electrical connections comprise socket contact elements which are formed so as to receive pin contact elements of the earth wires. | 2013-08-15 |
20130210249 | CONVERTER AND PROGRAM - There is provided a converter including a connecting terminal connectable to a connecting device, a communicating unit capable of carrying out communication, and a communication restricting unit configured to restrict the communication carried out by the communicating unit if the connecting device is removed from the connecting terminal. | 2013-08-15 |
20130210250 | CONVERTER AND PROGRAM - There is provided a converter including a converting unit converting a communication mode of a connecting device having a connecting terminal. | 2013-08-15 |
20130210251 | ELECTRICAL CONNECTOR WITH MULTIPLE DETECT MECHANISM THEREOF - A receptacle connector includes an insulative housing defining a base with a mating tongue. A plurality of contacts are disposed in the housing with contacting sections exposed on the mating tongue. A metallic shell is assembled to the housing and defines a mating cavity into which the mating tongue extends. A plurality of spring tangs are formed on the shell and extend into the mating cavity for retainable abutment against the inserted plug. A dome switch is located outside of the shell and intimately confronts the corresponding spring tang so as to be activated when the corresponding spring tang is outwardly deflected by the inserted plug. An addition detect pin is electrically connected to the dome switch when the dome switch is activated to verify whether the plug is inserted in the mating cavity or to identify whether a high power is required. | 2013-08-15 |
20130210252 | CONTROLLER DEVICE - An electrical device includes a housing and an electrically insulating base secured to the housing. A communication terminal protrudes from the base. Electrically conductive main terminals protrude from the base and are spaced apart from each other and from the communication terminal. The main terminals are arcuate shaped and form arcs of a reference ring the center of which is a rotational axis of the electrical device. The communication terminal is disposed within the reference ring. Also featured is a controller device. | 2013-08-15 |
20130210253 | TERMINAL FITTING AND BULB SOCKET - A bulb socket includes a socket body in which a bulb is mounted, an earth terminal, a pair of terminal fittings for making elastic contact with a contact point of the bulb, and packing | 2013-08-15 |
20130210254 | RECEPTACLE CONNECTOR - A receptacle connector includes an insulating housing with a plurality of openings apart opened in a front face thereof. A terminal group includes a ground terminal embedded in the insulating housing. The terminal group has a plurality of contact slices molded in the insulating housing and exposed through the openings respectively, and a plurality of touching arms elastically stretching outside the insulating housing. At least one connecting member is molded in the insulating housing to electrically connect with the ground terminal, and has a connecting slice exposed outside and abreast with the front face of the insulating housing. A metal shell is mounted to the front face of the insulating housing and point welded with the connecting slice. A window is opened in the metal shell and located to face the openings for further exposing the contact slices therethrough. A waterproof washer is sealed around the metal shell. | 2013-08-15 |
20130210255 | TERMINAL FITTING - An object of the present invention is to provide a terminal fitting with improved waterproof property. A terminal fitting ( | 2013-08-15 |
20130210256 | ELECTRIC CONNECTION BOX - An electric connection box includes a circuit board, a box member having a main body part and a cover part, a film-shaped electric wire connected to the circuit board and disposed between the main body part and the cover part, a covering member, and an annular waterproof packing. The box member accommodates the circuit board in an internal space defined by the main body part and the cover part. The covering member covers an outer peripheral surface of a region of the wire between the main body part and the cover part along its whole circumference. The box member includes a fitting part fitted to the covering member. The packing is disposed around the circuit board and compressed between the main body part and the cover part. The packing includes an annular part pressing an outer peripheral surface of the covering member along the box member over its entire circumference. | 2013-08-15 |
20130210257 | HAND-HELD POWER TOOL - A hand-held power tool is disclosed. The tool has a tool receptacle, an electric motor which drives the tool receptacle, and a machine housing. A two-part supply cable has a first section, which is mechanically fastened inside the machine housing, and a second section, which is coupled to the first section outside of the machine housing by a detachable plug connection. The detachable plug connection locks by rotating around an axis and unlocks along the axis in the case of a tensile load above a limit value. | 2013-08-15 |
20130210258 | Lockable Connector - A connection assembly is provided. The connection assembly includes a socket with connection pins, a plug with matching connection pins and a locker for locking the plug relative to the socket while the matching pins are engaged. The lock includes a bolt having a barrel provided with balls movable between a locking position projecting in relation to the barrel and a position retracted inside the barrel, and a rod for retaining the balls in the locking position. The locker also includes a shaft arranged in the plug or the socket for at least partially receiving the bolt and having a groove for receiving the balls in the locked and projecting position. The bolt further includes a spring for returning the rod toward the ball-retaining position, and the rod has a cam surface pushing the balls back into the locked position when the spring urges the rod towards the retaining position. | 2013-08-15 |
20130210259 | ELECTRICAL CLIP CONNECTOR, ELECTRICAL CLIP CONNECTION AND ALSO READY-TO-USE ELECTRICAL CABLE - The invention relates to an electrical clip connector for an electrical connection of a cable ( | 2013-08-15 |
20130210260 | Electrical Plug Element with Contact Lock Member and Test Stop - The present invention relates to a plug element ( | 2013-08-15 |
20130210261 | RETENTION MECHANISM DEVICE - An improved retention mechanism having corresponding retention features is provided herein. The mechanism may include a pair of spring arm retention features in a connector receptacle engageable with a corresponding pair of recessed retention features in a connector tab and backup spring members for reducing stress within the spring arms during insertion of the tab and/or lubricating members for lubricating the retention mechanism. The backup spring is positioned adjacent an outer-facing surface or extends laterally outward from the spring arms so that deflection of the spring arms displaces the backup spring reducing stresses within each arm and/or increasing the retention force on the. The backup spring may include any or all of a bent portion of an bracket or arm, a wire, a loop, a complementary spring arm, dual backup springs, elastomeric members, compression springs and lubricating members. Methods of use and assembly such retention mechanisms are also provided. | 2013-08-15 |
20130210262 | CONNECTOR, IN PARTICULAR FOR UNDERWATER GEOPHYSICAL OPERATIONS - A connector is provided, which is configured for being connected to a similar connector. The connector has a global cylindrical shape around a longitudinal axis and includes a connection zone having comprising at least one electrical contact. A housing extends at least partly around the connection zone and has at least two projecting members. A cylindrical locking nut surrounds the housing and is at least partly movable relative to the housing. The housing and the locking nut are configured for respectively cooperating with corresponding locking nut and housing of the similar connector. | 2013-08-15 |
20130210263 | ELECTRICAL CONNECTOR - An electrical connector for electrically connecting a mating element to a motherboard includes an insulating body having two side surfaces disposed symmetrically, at least one rotating shaft protruding from the side surface, a casing including at least one side portion corresponding to the side surface, and at least one protruding block. The side portion of the casing extends backward to form a rotating portion. The rotating portion is disposed with an elongated hole. A distance between an edge of the elongated hole and an edge of the rotating portion is substantially a fixed value. A distance between the protruding block and the rotating shaft is equal to or slightly larger than the fixed value. The rotating shaft urges against the edge of the elongated hole of the casing, and the protruding block urges against the edge of the rotating portion of the casing. | 2013-08-15 |
20130210264 | Cable Assemblies, Methods and Systems - Exemplary embodiments are directed to cable assemblies, methods and systems that generally include a first cable and a second cable. The first cable includes a first elongated cord and a first connector mounted with respect to one end of the first elongated cord. The second cable generally includes a second elongated cord and a second connector mounted with respect to one end of the second elongated cord. The first connector can be disposed in an opposing direction relative to the second connector. The first connector can be positioned adjacent of the second elongated cord and the second connector can be positioned adjacent to the first elongated cord. The cable assemblies generally include at least one coupler element for maintaining the first connector positioned adjacent to the second elongated cord and the second connector positioned adjacent to the first elongated cord. | 2013-08-15 |
20130210265 | CONNECTOR ASSEMBLY HAVING ALIGNMENT FEATURES - A connector assembly includes a housing having a mating end being configured for mating with a mating connector assembly. The housing holds a plurality of contacts configured for mating with corresponding contacts of the mating connector assembly. The housing has horizontal alignment features at the mating end for horizontally aligning the housing with the mating connector assembly. The housing has vertical alignment features at the mating end for vertically aligning the housing with the mating connector assembly. The vertical alignment features are separate from the horizontal alignment features. | 2013-08-15 |
20130210266 | INCOMPLETE FITTING PREVENTION CONNECTOR - An incomplete fitting prevention connector includes a first connector, a second connector that is fitted to the first connector, and a connector position assurance lock that is slidably mounted to an outer side of the second connector. The first connector includes a male beak, a short spring and a terminal The second connector includes a female lock passing over the male beak and a short-circuit removal plate part inserted between the short spring and the terminal A draw-in slanted surface is formed at a leading end of the male beak, a restoring force for returning the female lock to its original position serves as a driving force for fitting the connector when the female lock reaches the draw-in slanted surface, and the insertion force of the short-circuit removal plate part applied between the short spring and the terminal is reduced. | 2013-08-15 |
20130210267 | CONNECTOR - A connector includes a block, a connector body formed on a bottom surface of the block, and a number of cables connected to the connector body and extending through a top surface of the block. A binding member includes a plate extending out from the block and a binding portion extending from the plate. A distal end of the binding portion is detachably engaged with the plate, thereby binding the cables between the plate and the binding portion. | 2013-08-15 |
20130210268 | Conductive Gripping Element for Retaining and Conductively Connecting Electric Wires - Conductive gripping element for retaining and conductively connecting electric wires ( | 2013-08-15 |
20130210269 | CAGE, RECEPTACLE AND SYSTEM FOR USE THEREWITH - A cage can include a thermal plate positioned so as to be aligned with a bottom of a channel. An adjustable biasing system is provided to urge a module toward the thermal plate. The adjustable biasing system may be a riding heat sink. The thermal plate may include a fin to help increase its surface area. A housing with a card slot aligned with the channel can be provided in the cage to provide a receptacle that has a card slot aligned with the channel. A receptacle so configured allows for greater thermal energy to be removed from a module. | 2013-08-15 |