32nd week of 2010 patent applcation highlights part 16 |
Patent application number | Title | Published |
20100200902 | NAND Flash Memory Device - A method of manufacturing a NAND flash memory device. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices. | 2010-08-12 |
20100200903 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench. | 2010-08-12 |
20100200904 | GATE FRINGING EFFECT BASED CHANNEL FORMATION FOR SEMICONDUCTOR DEVICE - Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors. | 2010-08-12 |
20100200905 | NAND MEMORY CELLS AND MANUFACTURING METHOD THEREOF - A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; sequentially forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI defining a plurality of recesses in the substrate through the patterned hard mask; sequentially forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures. | 2010-08-12 |
20100200906 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - A nonvolatile semiconductor memory device includes: a semiconductor substrate; a multilayer structure; a semiconductor pillar; a third insulating film; and a fourth insulating film layer. The a multilayer structure is provided on the semiconductor substrate and including a plurality of constituent multilayer bodies stacked in a first direction perpendicular to a major surface of the semiconductor substrate. Each of the plurality of constituent multilayer bodies includes an electrode film provided parallel to the major surface, a first insulating film, a charge storage layer provided between the electrode film and the first insulating film, and a second insulating film provided between the charge storage layer and the electrode film. The semiconductor pillar penetrates through the multilayer structure in the first direction. The third insulating film is provided between the semiconductor pillar and the electrode film. The fourth insulating film is provided between the semiconductor pillar and the charge storage layer. | 2010-08-12 |
20100200907 | Semiconductor Integrated Circuit Device and Method of Fabricating the Same - A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer. | 2010-08-12 |
20100200908 | Nonvolatile memory device and method of fabricating the same - Provided are a nonvolatile memory device having a vertical folding structure and a method of manufacturing the nonvolatile memory device. A semiconductor structure includes first and second portions that are substantially vertical. A plurality of memory cells are arranged along the first and second portions of the semiconductor structure and are serially connected. | 2010-08-12 |
20100200909 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a technique capable of improving reliability of a semiconductor device having a nonvolatile memory cell by suppressing the reduction of the drive force. | 2010-08-12 |
20100200910 | Semiconductor Devices with Stable and Controlled Avalanche Characteristics and Methods of Fabricating the Same - Disclosed are semiconductor devices with breakdown voltages that are more controlled and stable after repeated exposure to breakdown conditions than prior art devices. The disclosed devices can be used to provide secondary circuit functions not previously contemplated by the prior art. | 2010-08-12 |
20100200911 | ELECTROSTATIC DISCHARGE FAILURE PROTECTIVE ELEMENT, ELECTROSTATIC DISCHARGE FAILURE PROTECTIVE CIRCUIT, SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An electrostatic discharge failure protective element ( | 2010-08-12 |
20100200912 | Mosfets with terrace irench gate and improved source-body contact - A trench MOSFET with terrace gates and improved source-body contact structure is disclosed. When refilling the gate trenches, the deposited polysilicon layer is higher than the sidewalls of the trenches to be used as terrace gates of the MOSFET, and the improved source-body contact structure can enlarge the P+ area below to wrap the sidewalls and bottom of source-body contact within P body region to further enhance the avalanche capability. | 2010-08-12 |
20100200913 | SEMICONDUCTOR STORAGE DEVICE - It is intended to achieve a sufficiently-small SRAM cell area and a stable operation margin in an E/R type 4T-SRAM comprising a vertical transistor SGT. In a static type memory cell made up using four MOS transistors and two load resistor elements, each of the MOS transistor constituting the memory cell is formed on a planar silicon layer formed on a buried oxide film, to have a structure where a drain, a gate and a source are arranged in a vertical direction, wherein the gate is formed to surround a pillar-shaped semiconductor layer, and each of the load resistor elements is made of polysilicon and formed on the planar silicon layer. | 2010-08-12 |
20100200914 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A source layer | 2010-08-12 |
20100200915 | LATERAL TRENCH MOSFET HAVING A FIELD PLATE - One embodiment relates to an integrated circuit that includes a lateral trench MOSFET disposed in a semiconductor body. The lateral trench MOSFET includes source and drain regions having a body region therebetween. A gate electrode region is disposed in a trench that extends beneath the surface of the semiconductor body at least partially between the source and drain. A gate dielectric separates the gate electrode region from the semiconductor body. In addition, a field plate region in the trench is coupled to the gate electrode region, and a field plate dielectric separates the field plate region from the semiconductor body. Other integrated circuits and methods are also disclosed. | 2010-08-12 |
20100200916 | SEMICONDUCTOR DEVICES - In an embodiment, a semiconductor device is provided. The semiconductor device may include a substrate having a main processing surface, a first source/drain region comprising a first material of a first conductivity type, a second source/drain region comprising a second material of a second conductivity type, wherein the second conductivity type is different from the first conductivity type, a body region electrically coupled between the first source/drain region and the second source/drain region, wherein the body region extends deeper into the substrate than the first source/drain region in a first direction that is perpendicular to the main processing surface of the substrate, a gate dielectric disposed over the body region, and a gate region disposed over the gate dielectric, wherein the gate region overlaps with at least a part of the first source/drain region and with a part of the body region in the first direction. | 2010-08-12 |
20100200917 | NONPLANAR DEVICE WITH STRESS INCORPORATION LAYER AND METHOD OF FABRICATION - A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body. | 2010-08-12 |
20100200918 | Heavy Ion Upset Hardened Floating Body SRAM Cells - A CMOS memory element comprising silicon-on-insulator MOSFET transistors is disclosed wherein at least one of the MOSFET transistors is configured such that the body of the transistor is not connected to a voltage source and is instead permitted to electrically float. Implementations of the disclosed memory element with increased immunity to errors caused by heavy ion radiation are also disclosed. | 2010-08-12 |
20100200919 | Semiconductor device - The invention provides a semiconductor device capable of suppressing a short channel effect and fluctuation in a threshold. The semiconductor device includes: a plurality of first transistors formed in a first region in a semiconductor layer in a multilayer substrate having, on a semiconductor substrate, an insulating layer and the semiconductor layer in order from the semiconductor substrate; a plurality of second transistors formed in a second region in the semiconductor layer; a first impurity layer formed in a region opposed to the first region in the semiconductor substrate; a second impurity layer formed in a region opposed to the second region in the semiconductor substrate; and a first isolation part that isolates the first and second regions from each other and electrically isolates the first and second impurity layers from each other to a degree that at least current flowing between the first and second impurity layers is interrupted. | 2010-08-12 |
20100200920 | Configuration of gate to drain (GD) clamp and ESD protection circuit for power device breakdown protection - A semiconductor power device supported on a semiconductor substrate comprising a plurality of transistor cells each having a source and a drain with a gate to control an electric current transmitted between the source and the drain. The semiconductor further includes a gate-to-drain (GD) clamp termination connected in series between the gate and the drain further includes a plurality of back-to-back polysilicon diodes connected in series to a silicon diode includes parallel doped columns in the semiconductor substrate wherein the parallel doped columns having a predefined gap. The doped columns further include a U-shaped bend column connect together the ends of parallel doped columns with a deep doped well disposed below and engulfing the U-shaped bend. | 2010-08-12 |
20100200921 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: a field effect transistor that is provided with a gate region, a drain region and a source region and that is formed on a substrate; a circuit region that is formed on the substrate so as to be electrically isolated from the field effect transistor; a first guard ring that is formed in a ring shape encircling the field effect transistor and that includes an internal resistance; and a second guard ring that is formed in a ring shape encircling the circuit region, that forms a capacitance between the second guard ring and the gate region by capacitive coupling with the gate region, and that includes an internal resistance. | 2010-08-12 |
20100200922 | Electrostatic Discharge Protection Device and Method - Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well. | 2010-08-12 |
20100200923 | MULTIPLE-GATE TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING - A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized. | 2010-08-12 |
20100200924 | SEMICONDUCTOR DEVICE - A semiconductor device has a plurality of divided elements which are formed over a substrate, each of which containing a film having a predetermined pattern with the long-axis direction and the short-axis direction definable therein, and are arranged in a distributed manner in the same layer in the in-plane direction of the substrate, wherein the plurality of divided elements are arranged so that every adjacent divided element in a first direction has the long-axis direction thereof aligned differently from those of the neighbors, or, so that every adjacent divided element in the first direction is shifted in a second direction, which is orthogonal to the first direction, by an amount smaller than the length of the divided element in the second direction. | 2010-08-12 |
20100200925 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a pair of impurity regions in a semiconductor substrate. A silicon layer is formed on the impurity region. A gate insulating film is formed between the impurity regions. A gate electrode is formed on the gate insulating film. A first silicon nitride film is formed on the gate electrode. A silicon oxide film is formed on a side surface of the gate electrode. A second silicon nitride film is partially formed on the silicon layer and on a side surface of the silicon oxide film. A conductive layer is formed on the silicon layer. | 2010-08-12 |
20100200926 | Memory Cells Having Contact Structures and Related Intermediate Structures - Intermediate structures are provided that are formed during the manufacture of a memory device. These structures include first and second spaced apart gate patterns on a semiconductor substrate. A source/drain region is provided in the semiconductor substrate between the first and second gate patterns. An etch stop layer is provided on first and second sidewalls of the first gate pattern. The first and second sidewalls face each other to define a gap region between the etch stop layer on the first sidewall and the etch stop layer on the second sidewall. A dielectric layer is provided in the gap region. Finally, a preliminary contact hole is provided in the dielectric layer. | 2010-08-12 |
20100200927 | SEMICONDUCTOR-ON-INSULATOR SUBSTRATE AND STRUCTURE INCLUDING MULTIPLE ORDER RADIO FERQUENCY HARMONIC SUPRESSING REGION - A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure. | 2010-08-12 |
20100200928 | SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti(titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to form a barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film. | 2010-08-12 |
20100200929 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit memory device includes a gate line that extends in a first direction, an active region adjacent to a first end of the gate line and that extends in a second direction, a silicide layer formed on a top surface of the active region, on a top surface of the gate line, on both sidewalls of the first end of the gate line, and on a transverse endwall of the first end of the gate line. A spacer may be formed on sidewalls of the gate line, excluding the first end of the gate line, and a contact shared by the active region may be formed on the first end of the gate line. | 2010-08-12 |
20100200930 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed as the gate insulating film of a high-breakdown-voltage MIS transistor, while the middle-breakdown-voltage insulating film is formed as the gate insulating film of a middle-breakdown-voltage MIS transistor. | 2010-08-12 |
20100200931 | MOSFET DEVICES AND METHODS OF MAKING - A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence. | 2010-08-12 |
20100200932 | Electronic-Component-Housing Package and Electronic Device - An electronic-component-housing package comprises a container including a rectangular mount on which an electronic component is to be mounted and a sidewall surrounding the mount. The electronic-component-housing package comprises a lead terminal extending from an inside of a space enclosed by the sidewall to an outside of the space. A tip part of the lead terminal is extending along one side of the mount. | 2010-08-12 |
20100200933 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET. | 2010-08-12 |
20100200934 | FIELD EFFECT DEVICE INCLUDNG RECESSED AND ALIGNED GERMANIUM CONTAINING CHANNEL - A field effect structure and a method for fabricating the field effect structure include a germanium containing channel interposed between a plurality of source and drain regions. The germanium containing channel is coplanar with the plurality of source and drain regions, and the germanium containing channel includes a germanium containing material having a germanium content greater than the germanium content of the plurality of source and drain regions. | 2010-08-12 |
20100200935 | SEMICONDUCTOR DEVICE COMPRISING GATE ELECTRODE HAVING ARSENIC AND PHOSPHORUS - A semiconductor device is disclosed, which comprises a gate electrode having a laminated structure of a polycrystalline silicon film or a polycrystalline germanium film containing arsenic and a first nickel silicide layer formed in sequence on an element forming region of a semiconductor substrate through a gate insulating film, a sidewall insulating film formed on a side surface of the gate electrode, source/drain layers containing arsenic formed in the element forming region at both side portions of the gate electrode, and second nickel silicide layers formed on the source/drain layers, wherein a peak concentration of arsenic contained in the gate electrode is at least 1/10 of a peak concentration of arsenic contained in the source/drain layers. | 2010-08-12 |
20100200936 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor layer of a first conductivity type; a first semiconductor pillar region of the first conductivity type provided on a major surface of the semiconductor layer; a second semiconductor pillar region of a second conductivity type provided adjacent to the first semiconductor pillar region on the major surface of the semiconductor layer, the second semiconductor pillar region forming a periodic arrangement structure substantially parallel to the major surface of the semiconductor layer together with the first semiconductor pillar region; a first main electrode; a first semiconductor region of the second conductivity type; a second semiconductor region of the first conductivity type; a second main electrode; a control electrode; and a high-resistance semiconductor layer provided on the semiconductor layer in an edge termination section surrounding the first semiconductor pillar region and the second semiconductor pillar region. The high-resistance semiconductor layer has a lower dopant concentration than the first semiconductor pillar region. A boundary region is provided between a device central region and the edge termination section. The first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer in the boundary region have a depth decreasing stepwise toward the edge termination section. | 2010-08-12 |
20100200937 | METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING - Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided. | 2010-08-12 |
20100200938 | METHODS FOR FORMING LAYERS WITHIN A MEMS DEVICE USING LIFTOFF PROCESSES - Certain MEMS devices include layers patterned to have tapered edges. One method for forming layers having tapered edges includes the use of an etch leading layer. Another method for forming layers having tapered edges includes the deposition of a layer in which the upper portion is etchable at a faster rate than the lower portion. Another method for forming layers having tapered edges includes the use of multiple iterative etches. Another method for forming layers having tapered edges includes the use of a liftoff mask layer having an aperture including a negative angle, such that a layer can be deposited over the liftoff mask layer and the mask layer removed, leaving a structure having tapered edges. | 2010-08-12 |
20100200939 | STORAGE ELEMENT AND MEMORY - A memory is provided that is capable of improving the thermal stability without increasing the write current. The memory is configured to include: a storage element which has a storage layer that holds information according to a magnetization state of a magnetic substance and in which a magnetization fixed layer is provided on the storage layer with an intermediate layer | 2010-08-12 |
20100200940 | Photodetector for Imaging System - There is disclosed a substrate including at least one photodetector, the photodetector having a first active area on a first surface of the substrate and a second active area on a second surface of the substrate, wherein the photodetector is provided with a conductive via electrically isolated from the substrate, said conductive via extending through the photodetector from the first surface of the substrate to the second surface of the substrate for connecting the first active area to the second surface of the substrate, the second surface providing electrical connections for the first and second active areas of the photodetector. | 2010-08-12 |
20100200941 | PHOTODIODE, OPTICAL COMMUNICATION DEVICE, AND OPTICAL INTERCONNECTION MODULE - Intended is to provide a device structure, which makes the light receiving sensitivity and the high speediness of a photodiode compatible. Also provided is a Schottky barrier type photodiode having a conductive layer formed on the surface of a semiconductor layer. The photodiode is so constituted that a light can be incident on the back side of the semiconductor layer, and that a periodic structure, in which a light incident from the back side of the semiconductor layer causes a surface plasmon resonance, is made around the Schottky junction of the photodiode. | 2010-08-12 |
20100200942 | SOLID STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND IMAGING APPARATUS - A solid state imaging device having a light sensing section that performs photoelectric conversion of incident light includes: an insulating layer formed on a light receiving surface of the light sensing section; a layer having negative electric charges formed on the insulating layer; and a hole accumulation layer formed on the light receiving surface of the light sensing section. | 2010-08-12 |
20100200943 | Photosensitive cell with light guide - An integrated circuit having a photosensitive cell with an entry face, a photosensitive element and at least two elements forming a light guide and placed between the entry face and the photosensitive element. The second element is located between the first element and the entry face such that the two elements guide the light coming from the entry face onto the photosensitive element and each element forms a light guide. The inner volume has a first surface located on the same side as the photosensitive element, a second surface located on the same side as the entry face, and a lateral surface joining said first surface to said second surface and separating the inner volume from the outer volume. The first surface of the inner volume of the second element has a smaller area than that of the second surface of the inner volume of the first element. | 2010-08-12 |
20100200944 | DARK CURRENT REDUCTION IN BACK-ILLUMINATED IMAGING SENSORS - A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The device includes an insulator layer; a semiconductor substrate, having an interface with the insulator layer; an epitaxial layer grown on the semiconductor substrate by epitaxial growth; and one or more imaging components in the epitaxial layer in proximity to a face of the epitaxial layer, the face being opposite the interface of the semiconductor substrate and the insulator layer, the imaging components comprising junctions within the epitaxial layer; wherein the semiconductor substrate and the epitaxial layer exhibit a net doping concentration having a maximum value at a predetermined distance from the interface of the insulating layer and the semiconductor substrate and which decreases monotonically on both sides of the profile from the maximum value within a portion of the semiconductor substrate and the epitaxial layer. The doping profile between the interface with the insulation layer and the peak of the doping profile functions as a “dead band” to prevent dark current carriers from penetrating to the front side of the device. | 2010-08-12 |
20100200945 | Schottky diode and method of fabricating the same - A schottky diode may include a schottky junction including a well formed in a semiconductor substrate and a first electrode contacting the first well. The well may have a first conductivity type. A first ohmic junction may include a first junction region formed in the well and a second electrode contacting the first junction region. The first junction region may have a higher concentration of the first conductivity type than the well. A first device isolation region may be formed in the semiconductor substrate separating the schottky junction and the first ohmic junction. A well guard having a second conductivity type opposite to the first conductivity type may be formed in the well. At least a portion of the well guard may be formed under a portion of the schottky junction. | 2010-08-12 |
20100200946 | Method for forming trench isolation using a gas cluster ion beam growth process - A method of forming shallow trench isolation on a substrate using a gas cluster ion beam (GCIB) is described. The method comprises generating a GCIB, and irradiating the substrate with the GCIB to form a shallow trench isolation structure by growing a dielectric layer in at least one region on the substrate. | 2010-08-12 |
20100200947 | DIE SEAL RING - A die seal ring disposed outside of a die region of a semiconductor substrate is disclosed. The die seal ring includes a first isolation structure, a second isolation structure, and at least one third isolation structure disposed between the first isolation structure and the second isolation structure; a plurality of first regions between the first isolation structure, the second isolation structure and the third isolation structure; a second region under the first region and the third isolation structure; and a third region under the first isolation structure. | 2010-08-12 |
20100200948 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - Disclosed herein is a fabrication method of a semiconductor device to order to increase an operation liability of the semiconductor device. A method for fabricating a semiconductor device comprises forming a recess in a semiconductor substrate, forming a word line in a lower part of the recess, oxidizing a top portion of the word line, and depositing an insulating material in a remained part of the recess. | 2010-08-12 |
20100200949 | METHOD FOR TUNING THE THRESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE - A method of forming a deep trench capacitor includes providing a wafer. Devices are formed on a front side of the wafer. A through-silicon-via is formed on a substrate of the wafer. Deep trenches are formed on a back side of the wafer. A deep trench capacitor is formed in the deep trench. The through-silicon-via connects the deep trench capacitor to the devices. | 2010-08-12 |
20100200950 | Semiconductor device having dielectric layer with improved electrical characteristics and associated methods - A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film. | 2010-08-12 |
20100200951 | Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) - A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer. | 2010-08-12 |
20100200952 | SEMICONDUCTOR DEVICE - Provided is a method which is capable of producing polycrystalline silicon resistors with a high ratio accuracy so that a precision resistor circuit may be designed. A semiconductor device has a structure in which an occupation area of a metal portion covering a low concentration impurity region constituting each of the polycrystalline silicon resistors is adjusted so that ratio accuracy may be further corrected after a resistance is corrected. | 2010-08-12 |
20100200953 | ON-CHIP HEATER AND METHODS FOR FABRICATION THEREOF AND USE THEREOF - An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure. | 2010-08-12 |
20100200954 | ION IMPLANTED SUBSTRATE HAVING CAPPING LAYER AND METHOD - In an ion implantation method, a substrate is placed in a process zone and ions are implanted into a region of the substrate to form an ion implanted region. A porous capping layer is deposited on the ion implanted region. The substrate is annealed to volatize at least 80% of the porous capping layer overlying the ion implanted region during the annealing process. An intermediate product comprises a substrate, a plurality of ion implantation regions on the substrate, and a porous capping layer covering the ion implantation regions. | 2010-08-12 |
20100200955 | Group III-V nitride based semiconductor substrate and method of making same - A group III-V nitride-based semiconductor substrate includes a group III-V nitride-based semiconductor crystal. A surface area of the substrate is greater than or equal to 45 cm | 2010-08-12 |
20100200956 | COMPOUND SEMICONDUCTOR SUBSTRATE, PROCESS FOR PRODUCING COMPOUND SEMICONDUCTOR SUBSTRATE, AND SEMICONDUCTOR DEVICE - A method for manufacturing the compound semiconductor substrate having a reduced dislocation density at an interface between a Si substrate. Contaminants, such as organic matter and metal, on a surface of a Si substrate are removed whereby a flat oxide film is formed. The oxide film on the surface is removed by using an aqueous hydrogen fluoride solution, whereby hydrogen termination treatment is performed. Immediately after being subjected to the hydrogen termination treatment the temperature of the Si substrate is raised in a vacuum apparatus. If the substrate temperature is raised without any operation, the termination hydrogen is released. Before the hydrogen is released, pre-irradiation with As is performed. Thus, an interface between the Si substrate and the compound semiconductor layer is prepared. Several minutes later, irradiation with Ga and As is performed. Thereby, the compound semiconductor is formed. | 2010-08-12 |
20100200957 | Scribe-Line Through Silicon Vias - A semiconductor wafer includes dies to be scored from the semiconductor wafer. The semiconductor wafer also includes scribe-lines between the dies. Each scribe-line includes multiple through silicon vias. | 2010-08-12 |
20100200958 | PEDESTAL GUARD RING HAVING CONTINUOUS M1 METAL BARRIER CONNECTED TO CRACK STOP - A microelectronic element, e.g., a semiconductor chip having a silicon-on-insulator layer (“SOI layer”) separated from a bulk monocrystalline silicon layer by a buried oxide (BOX) layer in which a crack stop extends in first lateral directions at least generally parallel to the edges of the chip to define a ring-like barrier separating an active portion of the chip inside the barrier with a peripheral portion of the chip. The crack stop can include a first crack stop ring contacting a silicon portion of the chip above the BOX layer; the first crack stop ring may extend continuously in the first lateral directions to surround the active portion of the chip. A guard ring (“GR”) including a GR contact ring can extend downwardly through the SOI layer and the BOX layer to conductively contact the bulk monocrystalline silicon region, the GR contact ring extending at least generally parallel to the first crack stop ring to surround the active portion of the chip. A continuous metal ring extending continuously in the first lateral directions can surround the active portion of the chip, such metal ring connecting the GR contact ring with the first crack stop ring such that the metal line and the GR contact ring form a continuous seal preventing mobile ions from moving between the peripheral and active portions of the chip. | 2010-08-12 |
20100200959 | SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE, SEMICONDUCTOR PLATE AND METHOD OF MANUFACTURING THE SAME - A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: insulating layers formed in the plurality of groove portions; a rectangular unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode including an extended terminal portion extended from the unit region to the inside of the groove portion. The semiconductor substrate is manufactured by forming a plurality of groove portions along scribe lines; embedding an insulating material in the plurality of groove portions and planarizing a surface to form insulating layers; and forming a wiring electrode including an extended terminal portion extended from a rectangular unit region in contact with at least any one of the plurality of groove portions to the inside of the groove portion. | 2010-08-12 |
20100200960 | DEEP TRENCH CRACKSTOPS UNDER CONTACTS - Deep trenches formed beneath contact level in a semiconductor substrate function as crackstops, in a die area or in a scribe area of the wafer, and may be disposed in rows of increasing distance from a device which they are intended to protect, and may be located under a lattice work crackstop structure in an interconnect stack layer. The deep trenches may remain unfilled, or may be filled with a dielectric material or conductor. The deep trenches may have a depth into the substrate of approximately 1 micron to 100 microns, and a width of approximately 10 nm to 10 microns. | 2010-08-12 |
20100200961 | THRU SILICON ENABLED DIE STACKING SCHEME - A die to die bonding system and method includes an upper die having a front side, a back side, and a fully filled thru silicon via, a portion of the fully filled thru silicon via protruding from the back side of the upper die. A lower die includes a front side, a back side, and a partially filled thru silicon via formed to define a via opening exposed to the front side of the die, a portion of the partially filled thru silicon via protruding from the back side of the lower die. An interconnect bonds an outer surface of the protruding portion of the upper die thru silicon via with an inner surface of via opening in the lower die. | 2010-08-12 |
20100200962 | SILOCON WAFER SUPPORTING METHOD, HEAT TREATMENT JIG AND HEAT-TREATED WAFER - Provided is a method applicable to the production of silicon wafers having crystal orientation <100> or <110> and consisting in specifying wafer-supporting positions on the occasion of heat treatment in a vertical heat treatment furnace as well as a heat treatment jig for use in carrying out that method. It becomes possible to suppress the shear stress which contributes to the extension of the slip generated at each wafer-supporting element contact point as an initiation, suppress slip growth and thus markedly improve the yield of heat-treated silicon wafers. The heat-treated wafer obtained by using the supporting method and the heat treatment jig has few slip, in particular has no long and large slip, and is high in quality. | 2010-08-12 |
20100200963 | PROTEIN REPELLING SILICON AND GERMANIUM SURFACES - The present invention relates to a process for preparing a functionalized Si/Ge-surface, wherein an unfunctionalised Si/Ge-surface is contacted in the presence of ultraviolet radiation with a C | 2010-08-12 |
20100200964 | METHOD OF PRODUCING A POROUS DIELECTRIC ELEMENT AND CORRESPONDING DIELECTRIC ELEMENT - A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed from the second dielectric by using a chemical dissolution. The removal of the second dielectric from the first dielectric leaves pores in the first dielectric. The pores, which are filled with air, improve the overall dielectric constant of the resulting dielectric element. | 2010-08-12 |
20100200965 | PACKAGE STRUCTURE FOR WIRELESS COMMUNICATION MODULE - A package structure for a wireless communication module is disclosed and includes: a substrate having an upper surface defining a supporting region, an annular ground pad surrounding the supporting region, and at least one auxiliary ground pad formed in the supporting region; at least one chip mounted on the supporting region and electrically connected to the substrate; and a shielding lid having a receiving space for receiving the chip, a ground end surface electrically connected to the annular ground pad of the substrate, and at least one auxiliary ground portion electrically connected to the auxiliary ground pad for forming at least one auxiliary ground pathway to adjust the characteristic of the enhanced peak generated by the cavity-resonance effect of the shielding lid. Thus, the enhanced peak can be shifted out of a regulated frequency range of the EMI shielding test, so that the yield thereof can be increased. | 2010-08-12 |
20100200966 | SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING PACKAGE STACKED OVER DIE-UP FLIP CHIP BALL GRID ARRAY PACKAGE AND HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES - A semiconductor multi-package module having stacked second and first packages, each package including a die attached to a substrate, in which the first and second package substrates are interconnected by wire bonding, and in which the first package is a flip chip ball grid array package in a die-up configuration. Also, a method for making a semiconductor multi-package module, by providing a first package including a first package substrate and having a die-up flip chip configuration, affixing a second package including a second package substrate an upper surface of the first package, and forming z-interconnects between the first and second package substrates. | 2010-08-12 |
20100200967 | INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING SHIELD - An integrated circuit package system includes: a substrate; a first device attached to the substrate; a shield attached to the substrate and surrounding the first device; apertures formed within the shield; the shield configured to block electromagnetic energy that passes through the apertures; and an encapsulation material deposited through the apertures. | 2010-08-12 |
20100200968 | MICROWAVE CIRCUIT ASSEMBLY - A microwave circuit assembly including a flip-chip attachable integrated circuit die attached to a substrate by an interconnect device. The integrated circuit die and the substrate have microstrip transmission lines that are electrically coupled through the interconnect device. The interconnect device forms a transmission line configured to electrically couple the microstrip transmission line on the substrate to the microstrip transmission line on the integrated circuit die The interconnect device includes stubs to enhance the ground elements of the interconnect device transmission line and provide a microwave short for the integrated circuit die. | 2010-08-12 |
20100200969 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor package including a wire binding process, a first end of the bonding wire is bonded to a first pad so as to form a first bond portion. A second end of the bonding wire is bonded to a second pad, wherein an interface surface between the bonding wire and the second pad has a first connecting area. The bonded second end of the bonding wire is scrubbed so as to form a second bond portion, wherein a new interface surface between the bonding wire and the second pad has a second connecting area larger than the first connecting area. A remainder of the bonding wire is separated from the second bond portion. | 2010-08-12 |
20100200970 | Semiconductor Assembly With One Metal Layer After Base Metal Removal - A method for packaging an integrated circuit. A barrier metal pattern is disposed on a baseplate. A conductive layer is disposed on the barrier metal pattern. A photoresist having a pattern is applied to the conductive layer. A via is then disposed on the conductive layer. An integrated circuit is coupled to the via and encapsulated. Then, at least a part of the baseplate is removed. An integrated circuit package is produced by the method. | 2010-08-12 |
20100200971 | High current capacity inner leads for semiconductor device - The invention can be used for improving performance of laser diodes, solar cells, microprocessors and other devices. The invention enables to create semiconductor devices having a great area of die, a great number of leads, a high operating current and a high heat dissipation. This is achieved by the following manner: offered leads are made of copper foil; the rigidity of the foil is decreased by means of disposing of alternating parallel narrow trenches on both sides of the foil; the offered leads are microspring; additional decreasing of rigidity can be achieved by the bending of foil along wide trenches that are created for this aim. Offered leads can be directly connected to the die. | 2010-08-12 |
20100200972 | BGA package with leads on chip - A BGA package primarily includes a leadless leadframe with a plurality of leads, a chip disposed on the leads, a die-attaching layer adhering to an active surface of the chip and the top surfaces of the leads, a plurality of bonding wires electrically connecting the chip to the leads, an encapsulant, and a plurality of solder balls. Each lead has a bottom surface including a wire-bonding area and a ball-placement area, moreover, a plurality of lips project from the bottom surfaces of the leads around the ball-placement areas. The encapsulant encapsulates the chip, the bonding wires, the die-attaching layer, and the top surfaces, the bottom surfaces except the ball-placement areas, and the laterals of the leads between the top surfaces and the bottom surfaces. A plurality of cavities are formed in the bottom of the encapsulant to expose the corresponding and embedded ball-placement areas. The lips have a plurality of internal sides exposed inside the cavities. The solder balls are disposed on the ball-placement areas and on the internal sides of the cavities to make the solder balls partially embedded in the corresponding cavities to offer non-planar ball pads. It is effective to resolve the solderability of the solder balls and to enhance the reliability of wire bonding and the stability of solder ball placement. | 2010-08-12 |
20100200973 | LEADFRAME STRUCTURE FOR ELECTRONIC PACKAGES - A leadframe structure ( | 2010-08-12 |
20100200974 | SEMICONDUCTOR PACKAGE STRUCTURE USING THE SAME - A semiconductor package structure using the same is provided. The semiconductor package structure includes a first semiconductor element, a second semiconductor element, a binding wire and a molding compound. The first semiconductor element includes a semiconductor die and a pad. The pad is disposed above the semiconductor die and includes a metal base, a hard metal layer disposed above the metal base and an anti-oxidant metal layer disposed above the hard metal layer. The hardness of the hard metal layer is larger than that of the metal base. The activity of the anti-oxidant metal layer is lower than that of the hard metal layer. The first semiconductor element is disposed above the second semiconductor element. The bonding wire is connected to the pad and the second semiconductor element. The molding compound seals the first semiconductor element and the bonding wire and covers the second semiconductor element. | 2010-08-12 |
20100200975 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A first multilayer wiring structure has a first surface and a second surface positioned on an opposite side to the first surface, a first wiring pattern formed on the second surface side and a housing portion penetrating through the first multilayer wiring structure from the first surface to the second surface. An electronic component has an electrode pad. The electronic component is accommodated in the housing portion in a state that an electrode pad formation surface at the side where the electrode pad is formed is positioned on the second surface side of the first multilayer wiring structure. A second multilayer wiring structure has an insulating layer and a second wiring pattern which are stacked on the second surface of the first multilayer wiring structure and the electrode pad formation surface of the electronic component. The second wiring pattern is electrically connected to the first wiring pattern and the electrode pad. | 2010-08-12 |
20100200976 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A plurality of semiconductor elements configuring a first element group are stacked in a step-like shape on a wiring board. A plurality of semiconductor elements configuring a second element group are stacked in a step-like shape on the first element group toward a direction opposite to the stepped direction of the first element group. The semiconductor elements are electrically connected to connection pads of the wiring board through metallic wires. Among the plurality of semiconductor elements configuring the second element group, the lowermost semiconductor element has a thickness larger than those of the other semiconductor elements. | 2010-08-12 |
20100200977 | Layered chip package and method of manufacturing same - A layered chip package has a main body including a plurality of pairs of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip. The plurality of pairs of layer portions include at least one specific pair of layer portions consisting of a first-type layer portion and a second-type layer portion. The first-type layer portion includes a plurality of electrodes each connected to the semiconductor chip and each having an end face located at the side surface of the main body on which the wiring is disposed, whereas the second-type layer portion does not include such electrodes. A layered substructure formed of a stack of two substructures each of which includes a plurality of preliminary layer portions aligned is used to fabricate a stack of a predetermined two or greater number of pairs of layer portions, and the main body is fabricated by stacking an additional first-type layer portion together with the stack, the number of the additional first-type layer portion being equal to the number of the specific pair(s) of layer portions included in the stack. | 2010-08-12 |
20100200978 | SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes placing a chip on a carrier, and applying an electrically conducting layer to the chip and the carrier. The method additionally includes converting the electrically conducting layer into an electrically insulating layer. | 2010-08-12 |
20100200979 | Power Transistor Package with Integrated Bus Bar - According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections. | 2010-08-12 |
20100200980 | SEMICONDUCTOR DEVICE - This semiconductor device has a frame including a bed portion on which a semiconductor chip is mounted, lead groups arranged in an outer peripheral portion, first bus bars, second bus bars and a rectifying bus bar. The first bus bars and the second bus bars are arranged between the bed portion and the lead groups. The rectifying bus bar is arranged in a region where the second bus bar is not arranged. Wire bonding is not performed on the rectifying bus bar. The rectifying bus bar includes a third bus bar having at least one end joined to a lead or a hanging pin and/or a fourth bus bar formed by extending the first bus bar in an outer peripheral direction in which the leads are arranged. The semiconductor device is provided in which deformation and damage of bonding wires when molding a resin sealed body are prevented. | 2010-08-12 |
20100200981 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a method of manufacturing a semiconductor package, a chip is disposed on a carrier. An inert gas is run around one end of a line portion of a copper bonding wire while the end is being formed into a spherical portion. The spherical portion is bonded to a pad of the chip. The chip and the copper bonding wire are sealed and the carrier is covered by a molding compound. | 2010-08-12 |
20100200982 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a resin sealed semiconductor device including: a semiconductor element; a plurality of micro-balls including an internal terminal surface and an external connection electrode in two sides of the micro-balls; metal wires for electrically connecting the semiconductor element and an internal terminal surface; and a sealing body for sealing the semiconductor element, a part of each the plurality of the terminals, and metal wires with a sealing resin, in which a back surface of the semiconductor element is exposed from the sealing body, and a part of each the plurality of micro-balls are exposed as the external connection electrodes from a bottom surface of the sealing body in a projection manner. | 2010-08-12 |
20100200983 | ELECTRONIC COMPONENT - An electronic component has a board, a semiconductor element mounted on an upper surface of the board, a ground electrode formed in a region surrounding the semiconductor element on the upper surface of the board, a conductive cap that overlaps the board such that the semiconductor element is covered therewith, and a conductive joining member that joins a whole periphery of a lower surface of the conductive cap to the ground electrode. The conductive cap includes a pressing portion on the lower surface thereof The lower surface of the conductive cap and the ground electrode are joined by the conductive joining member on an outer peripheral side of the pressing portion. | 2010-08-12 |
20100200984 | ADJUSTABLE THREADED CORES FOR LED THERMAL MANAGEMENT - Adjustable threaded cores for LED thermal management. The cores provide a direct thermal path between a LED and a heat sink while minimizing gaps and stresses between materials. The system includes a heat generating object, a first substrate housing containing a threaded hole beginning adjacent to the heat generating object, a second substrate having compatible threading with the threaded hole, and a third substrate including a heat sink. The second substrate has a higher thermal conductivity in comparison to the first substrate. The threaded hole and threaded core may terminate adjactent to the heat sink or may extent into the heat sink. | 2010-08-12 |
20100200985 | Semiconductor Device and Method of Protecting Passivation Layer in a Solder Bump Process - A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate in electrical contact with the plurality of active devices. A passivation layer is formed over the substrate and intermediate conduction layer. An adhesive layer is formed over the passivation layer. A barrier layer is formed over the adhesive layer. A wetting layer is formed over the barrier layer. The barrier layer and wetting layer in a first region are removed, while the barrier layer, wetting layer, and adhesive layer in a second region are maintained. The adhesive layer over the passivation layer in the first region are maintained until the solder bumps are formed. By keeping the adhesive layer over the passivation layer until after formation of the solder bumps, less cracking occurs in the passivation layer. | 2010-08-12 |
20100200986 | Grooving Bumped Wafer Pre-Underfill System - A method of forming a semiconductor device includes providing a bumped wafer. A plurality of grooves is formed in an active surface of the bumped wafer. A pre-underfill layer is disposed over the active surface, filling the plurality of grooves. A first adhesive layer is mounted to the pre-underfill layer, and a back surface of the bumped wafer is ground. A second adhesive layer is mounted to the back surface of the bumped wafer. The first adhesive layer is peeled from the active surface of the bumped wafer, or the second adhesive layer is mounted to the first adhesive layer. The bumped wafer is singulated into a plurality of segments by cutting the bumped wafer along the plurality of grooves. | 2010-08-12 |
20100200987 | Semiconductor Device and a Method of Manufacturing the Same - A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad | 2010-08-12 |
20100200988 | GRAIN REFINEMENT BY PRECIPITATE FORMATION IN Pb-FREE ALLOYS OF TIN - Micro-addition of a metal to a Sn-based lead-free C4 ball is employed to enhance reliability. Specifically, a metal having a low solubility in Sn is added in a small quantity corresponding to less than 1% in atomic concentration. Due to the low solubility of the added metal, fine precipitates are formed during solidification of the C4 ball, which act as nucleation sites for formation multiple grains in the solidified C4 ball. The fine precipitates also inhibit rapid grain growth by plugging grain boundaries and act as agents for pinning dislocations in the C4 ball. The grain boundaries enable grain boundary sliding for mitigation of stress during thermal cycling of the semiconductor chip and the package on the C4 ball. Further, the fine precipitates prevent electromigration along the grain boundaries due to their pinned nature. | 2010-08-12 |
20100200989 | LINER MATERIALS AND RELATED PROCESSES FOR 3-D INTEGRATION - In some embodiments, a low-k dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of through-silicon vias used in three-dimensional (3-D) integration of integrated circuits. A semiconductor workpiece having a via is provided. A dielectric film liner, preferably comprising benzocyclobutene, is deposited on the sidewalls of the via by chemical vapor deposition. Following the deposition of the dielectric film liner, conductive material is deposited into the via. The conductive material on the bottom of the via can be exposed by thinning the back of the semiconductor workpiece, thereby forming a through-silicon via. The semiconductor workpiece can form a stack with one or more additional semiconductor workpieces having vias filled with conductive material to form a 3-D integrated circuit. The conductive material electrically interconnects the integrated circuits at different levels of the stack. | 2010-08-12 |
20100200990 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE PRODUCED THEREWITH - A semiconductor device (having an interlayer insulating film) which is sufficiently low in the dielectric constant and high in the mechanical strength is provided. | 2010-08-12 |
20100200991 | Dopant Enhanced Interconnect - Techniques are disclosed that enable an interconnect structure that is resistance to electromigration. A liner is deployed underneath a seed layer of the structure. The liner can be a thin continuous and conformal layer, and may also limit oxidation of an underlying barrier (or other underlying surface). A dopant that is compatible (non-alloying, non-reactive) with the liner is provided to alloy the seed layer, and allows for dopant segregation at the interface at the top of the seed layer. Thus, electromigration performance is improved. | 2010-08-12 |
20100200992 | Lock and Key Through-Via Method for Wafer Level 3D Integration and Structures Produced - A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art. | 2010-08-12 |
20100200993 | DIELECTRIC BARRIER LAYER FOR INCREASING ELECTROMIGRATION LIFETIMES IN COPPER INTERCONNECT STRUCTURES - Embodiments of the invention include a copper interconnect structure having increased electromigration lifetime. Such structures can include a semiconductor substrate having a copper layer formed thereon. A dielectric barrier stack is formed on the copper layer. The dielectric barrier stack includes a first portion formed adjacent to the copper layer and a second portion formed on the first portion, the first portion having improved adhesion to copper relative to the second portion and both portions are formed having resistance to copper diffusion. The invention also includes several embodiments for constructing such structures. Adhesion of the dielectric barrier stack to copper can be increased by plasma treating or ion implanting selected portions of the dielectric barrier stack with adhesion enhancing materials to increase the concentration of such materials in the stack. | 2010-08-12 |
20100200994 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device comprises insulating layer including damascene patterns and formed over a semiconductor substrate, conductive line formed higher than the insulating layer within the respective damascene patterns, and interference-prevention grooves formed within the damascene patterns between sidewalls of the conductive line and the insulating layer. | 2010-08-12 |
20100200995 | COUPLING LAYER COMPOSITION FOR A SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, METHOD OF FORMING THE COUPLING LAYER, AND APPARATUS FOR THE MANUFACTURE OF A SEMICONDUCTOR DEVICE - Molecules of a coupling layer composition in a semiconductor device are bidimensionally polymerized in order to provide enhanced moisture blocking effect, particularly when the coupling layer is formed on a porous layer, such as a porous dielectric layer. The deposition of the coupling layer on the underlying structure and/or the cross-polymerization of the coupling layer composition and/or a final metallization can be photo-activated, especially, but not only, using an ultraviolet light. | 2010-08-12 |
20100200996 | Structural feature formation within an integrated circuit - An integrated circuit is formed using an lithographic process including a stage of forming a lithographic layer from a plurality of separately printed pattern layers. Within the integrated circuit there is formed a circuit including at least two devices that are matched devices such that the performance of the circuit is degraded if the match devices deviate from having matched performance characteristics. Dummy contacts | 2010-08-12 |
20100200997 | SEMICONDUCTOR DEVICE HAVING DECREASED CONTACT RESISTANCE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a first plug formed on a semiconductor substrate and exposed on side and upper surfaces of an upper part thereof and a second plug formed on the first plug to contact the exposed side and upper surfaces of the upper part of the first plug. | 2010-08-12 |
20100200998 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted. | 2010-08-12 |
20100200999 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. This makes it easy to make contacts even if the circuit pattern is complex. | 2010-08-12 |
20100201000 | BOND PAD SUPPORT STRUCTURE FOR SEMICONDUCTOR DEVICE - According to certain embodiments, integrated circuits are fabricated using brittle low-k dielectric material to reduce undesired capacitances between conductive structures. To avoid permanent damage to such dielectric material, bond pads are fabricated with support structures that shield the dielectric material from destructive forces during wire bonding. In one implementation, the support structure includes a passivation structure between the bond pad and the topmost metallization layer. In another implementation, the support structure includes metal features between the topmost metallization layer and the next-topmost metallization layer. In both cases, the region of the next-topmost metallization layer under the bond pad can have multiple metal lines corresponding to different signal routing paths. As such, restrictions on the use of the next-topmost metallization layer for routing purposes are reduced compared to prior-art bond-pad support structures that require the region of the next-topmost metallization layer under the bond pad to be a single metal structure. | 2010-08-12 |
20100201001 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: a) preparing a structure including a semiconductor substrate, an electrode provided on a first surface of the semiconductor substrate, and an insulation film provided on the first surface and having an opening positioned on a first part of the electrode; b) forming a first metal layer from an upper surface of the first part of the electrode to an upper surface of the insulation film; c) forming a resin layer on a first part of the first metal layer, which is positioned on the first part of the electrode, and on the insulation film after the step b); d) removing at least a second part of the resin layer, which is positioned on the first part of the first metal layer, in a manner to leave a first part of the resin layer so as to form a resin protrusion; and e) forming a second metal layer, which is electrically connected with the electrode, from an upper surface of the first metal layer to an upper surface of the resin protrusion. | 2010-08-12 |