32nd week of 2011 patent applcation highlights part 37 |
Patent application number | Title | Published |
20110195530 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A method including forming an intermediate product, the intermediate product being configured to include a wiring substrate including a plurality of first electrodes, a plurality of second electrodes and a plurality of test electrodes, a first semiconductor chip mounted over the wiring substrate and including a plurality of first pads electrically connected respectively to the first electrodes, and a second semiconductor chip stacked over the first semiconductor chip and including a plurality of second pads electrically connected respectively to the second electrodes; encapsulating the first and second semiconductor chips; and performing electrical tests on the first and second semiconductor chips by use of the test electrodes, after the encapsulating of the first and second semiconductor chips. | 2011-08-11 |
20110195531 | APPARATUS AND METHOD FOR EVALUATING OPTICAL PROPERTIES OF LED AND METHOD FOR MANUFACTURING LED DEVICE - An optical property evaluation apparatus includes: a light conversion filter converting light emitted from an LED chip or a bare LED package, which is to be evaluated, into a different wavelength of light, and emitting a specific color of light; and an optical property measurement unit receiving the specific color of light emitted from the light conversion filter and measuring the optical properties of the received light. | 2011-08-11 |
20110195532 | Solid State Light Sheet for General Illumination - A solid state light sheet and method of fabricating the sheet are disclosed. In one embodiment, bare blue-light LED chips have top and bottom electrodes, where the bottom electrode is a large reflective electrode. The bottom electrodes of an array of LEDs (e.g., 500 LEDs) are bonded to an array of electrodes formed on a flexible bottom substrate. Conductive traces are formed on the bottom substrate connected to the electrodes. In one embodiment, an intermediate sheet having holes is then affixed to the bottom substrate, with the LEDs passing through the holes. A transparent top substrate having conductors is then laminated over the intermediate sheet. In another embodiment, no intermediate sheet is used. Various ways to connect the LEDs in series are described along with many embodiments. The light sheet provides a practical substitute for a standard 2×4 foot fluorescent ceiling fixture. A phosphor is used to generate white light. | 2011-08-11 |
20110195533 | METHOD OF MANUFACTURING ORGANIC LIGHTING DEVICE - A method of manufacturing an organic lighting device, having a form factor substantially equal to or less than 900 square centimeters, without involving a cutting process is provided. The method includes providing one or more first substrates with a size substantially equal to the form factor. Thereafter, the method includes a high throughput first processing of the one or more first substrates and active layer deposition processing on the one or more first substrates. Further, one or more second substrates having a size substantially equal or less than the form factor are provided. Thereafter, a high throughput second processing is performed on the one or more second substrates. Finally, the method includes encapsulating at least one of the one or more first substrates with at least one of the one or more second substrates to form the organic lighting device having the form factor. | 2011-08-11 |
20110195534 | Liquid Crystal Display Device and a Manufacturing Method of the Same - A four-mask process and a three-mask process proposal are constructed for a TN-type liquid crystal display device and an IPS-type liquid crystal device in which the formation of a passivation insulating layer is not required by streamlining the formation of a scan line and a pseudo-pixel element, both comprising a laminate made of a transparent conductive layer and a metal layer, at the same time and the formation of the transparent conductive pixel electrode by removing the metal layer on the pseudo-pixel electrode at the time of the formation of the opening in the gate insulating layer, by streamlining the treatment of the formation process of the contact and the formation process of the protective insulating layer using one photomask due to the introduction of half-tone exposure technology, and the formation of source-drain wires for etch-stop type insulating gate-type transistor using a photosensitive organic insulating layer and leaving the photosensitive organic insulating layer unchanged on source-drain wires or on the source wire (signal line), or by forming an anodized layer, which is an insulating layer, on source-drain wires. | 2011-08-11 |
20110195535 | OPTICAL DEVICE WAFER PROCESSING METHOD - An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer. The optical device wafer processing method includes a division start point forming step of applying a laser beam having a transmission wavelength to the substrate to the intersections of the crossing division lines in the condition where the focal point of the laser beam is set inside the substrate in an area corresponding to the intersections of the crossing division lines, thereby forming a plurality of modified dots as division start points inside the substrate at the intersections of the crossing division lines; and a crack growing step of applying a CO | 2011-08-11 |
20110195536 | OPTICAL DEVICE WAFER PROCESSING METHOD - An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of crossing division lines formed on the semiconductor layer. The optical device wafer processing method includes a division start point forming step of applying a laser beam having a transmission wavelength to the substrate to the intersections of the crossing division lines in the condition where the focal point of the laser beam is set inside the substrate in an area corresponding to the intersections of the crossing division lines, thereby forming a plurality of crossing modified layers as division start points inside the substrate at the intersections of the crossing division lines; and a crack growing step of applying a CO | 2011-08-11 |
20110195537 | OPTICAL DEVICE WAFER PROCESSING METHOD - An optical device wafer processing method for dividing an optical device wafer into a plurality of individual optical devices. The optical device wafer is composed of a substrate and a semiconductor layer formed on the front side of the substrate. The optical devices are partitioned by a plurality of division lines formed on the semiconductor layer. The optical device wafer processing method includes a division start point forming step of applying a laser beam having a transmission wavelength to the substrate along the division lines in the condition where the focal point of the laser beam is set inside the substrate in an area corresponding to the division lines, thereby forming a plurality of modified layers as division start points inside the substrate along the division lines; and a crack growing step of applying a CO | 2011-08-11 |
20110195538 | METHOD OF FABRICATING LIGHT EMITING DIODE CHIP - The present invention provides a method of fabricating a light emitting diode chip having an active layer between an N type semiconductor layer and a P type semiconductor layer. The method comprises the steps of preparing a substrate; laminating the semiconductor layers on the substrate, the semiconductor layers having the active layer between the N type semiconductor layer and the P type semiconductor layer; and forming grooves on the semiconductor layers laminated on the substrate until the substrate is exposed, whereby inclined sidewalls are formed by the grooves in the semiconductor layers divided into a plurality of chips. According to embodiments of the present invention, a sidewall of a semiconductor layer formed on a substrate of a light emitting diode chip is inclined with respect to the substrate, whereby its directional angle is widened as compared with a light emitting diode chip without such inclination. As the directional angle of the light emitting diode chip is wider, when a white light emitting device is fabricated using the light emitting diode chip and a phosphor, light uniformity can be adjusted even though the phosphor is not concentrated at the center of the device. Thus, the overall light emitting efficiency can be enhanced by reducing a light blocking phenomenon caused by the increased amount of the phosphor distributed at the center portion. | 2011-08-11 |
20110195539 | METHOD FOR FORMING SEMICONDUCTOR LAYER AND METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE - A method for manufacturing a light emitting device according to an embodiment of the present invention includes preparing a growth substrate; selectively forming a projection pattern on the growth substrate; forming a first conductive type semiconductor layer on the growth substrate and the projection pattern; forming an active layer on the first conductive type semiconductor layer; forming a second conductive type semiconductor layer on the active layer; and executing an isolation etching for selectively removing the first conductive type semiconductor layer, the active layer, and the second conductive type semiconductor layer including the projection pattern. | 2011-08-11 |
20110195540 | COMPOSITION FOR FORMING P-TYPE DIFFUSION LAYER, METHOD FOR FORMING P-TYPE DIFFUSION LAYER, AND METHOD FOR PRODUCING PHOTOVOLTAIC CELL - The composition for forming a p-type diffusion layer in accordance with the present invention contains an acceptor element-containing glass powder and a dispersion medium. A p-type diffusion layer and a photovoltaic cell having a p-type diffusion layer are prepared by applying the composition for forming a p-type diffusion layer, followed by a thermal diffusion treatment. | 2011-08-11 |
20110195541 | COMPOSITION FOR FORMING N-TYPE DIFFUSION LAYER, METHOD FOR FORMING N-TYPE DIFFUSION LAYER, AND METHOD FOR PRODUCING PHOTOVOLTAIC CELL - The composition for forming an n-type diffusion layer in accordance with the present invention contains a donor element-containing glass powder and a dispersion medium. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment. | 2011-08-11 |
20110195542 | METHOD OF PROVIDING SOLAR CELL ELECTRODE BY ELECTROLESS PLATING AND AN ACTIVATOR USED THEREIN - A method of providing solar cell electrode by electroless plating and an activator used therein are disclosed. The method of the present invention can be performed without silver paste, and comprises steps: (A) providing a silicon substrate; (B) contacting the silicon substrate with an activator, wherein the activator comprises: a noble metal or a noble metal compound, a thickening agent, and water; (C) washing the silicon substrate by a cleaning agent; (D) dipping the silicon substrate in an electroless nickel plating solution to perform electroless plating. The method of providing solar cell electrode by electroless plating of the present invention has high selectivity between silicon nitride and silicon, large working window, and is steady, easily to be controlled, therefore is suitable for being used in the fabrication of the electrodes of the solar cell substrate. | 2011-08-11 |
20110195543 | FLIP-CHIP ASSEMBLY WITH ORGANIC CHIP CARRIER HAVING MUSHROOM-PLATED SOLDER RESIST OPENING - Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility. | 2011-08-11 |
20110195544 | SOLDER BUMP STRUCTURE FOR FLIP CHIP SEMICONDUCTOR DEVICES AND METHOD OF MANUFACTURE THEREFOR - The invention provides, in one aspect, a semiconductor device that comprises an interconnect layer located over a semiconductor substrate. A passivation layer is located over the interconnect layer and having a solder bump support opening formed therein. Support pillars that comprise a conductive material are located within the solder bump support opening. | 2011-08-11 |
20110195545 | PACKAGE PROCESS - A package process is provided. The package process includes: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has plural contacts at a side facing the carrier; thinning the semiconductor substrate from a back side of the semiconductor substrate and then forming plural through silicon vias in the thinned semiconductor substrate; forming plural first pads on the semiconductor substrate, wherein the first pads respectively connected to the through silicon vias; bonding plural chips to the semiconductor substrate, wherein the chips are electrically connected to the corresponding pads; forming a molding compound on the semiconductor substrate to cover the chips and the first pads; separating the semiconductor substrate and the carrier and then forming plural solder balls on the semiconductor substrate; and sawing the molding compound and the semiconductor substrate. | 2011-08-11 |
20110195546 | STACKING PACKAGE STRUCTURE WITH CHIP EMBEDDED INSIDE AND DIE HAVING THROUGH SILICON VIA AND METHOD OF THE SAME - The semiconductor device package structure includes a first die with a through silicon via (TSV) open from back side of the first die to expose bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via (TSV); a substrate with a second die embedded inside and top circuit wiring and bottom circuit wiring on top and bottom side of the substrate respectively; and a conductive through hole structure coupled between the terminal metal pads to the top circuit wiring and the bottom circuit wiring. | 2011-08-11 |
20110195547 | METHODS FOR FORMING INTERCONNECT STRUCTURES FOR INTEGRATION OF MULTI LAYERED INTEGRATED CIRCUIT DEVICES - Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed. | 2011-08-11 |
20110195548 | METHOD OF FABRICATING GATE ELECTRODE USING A TREATED HARD MASK - A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure. | 2011-08-11 |
20110195549 | GATE STACK FOR HIGH-K/METAL GATE LAST PROCESS - A method for fabricating an integrated circuit device is disclosed. An exemplary method includes providing a substrate; forming a high-k dielectric layer over the substrate; forming a first capping layer over the high-k dielectric layer; forming a second capping layer over the first capping layer; forming a dummy gate layer over the second capping layer; performing a patterning process to form a gate stack including the high-k dielectric layer, first and second capping layers, and dummy gate layer; removing the dummy gate layer from the gate stack, thereby forming an opening that exposes the second capping layer; and filling the opening with a first metal layer over the exposed second capping layer and a second metal layer over the first metal layer, wherein the first metal layer is different from the second metal layer and has a work function suitable to the semiconductor device. | 2011-08-11 |
20110195550 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, the method including providing a semiconductor substrate; forming a gate pattern on the semiconductor substrate such that the gate pattern includes a gate dielectric layer and a sacrificial gate electrode; forming an etch stop layer and a dielectric layer on the semiconductor substrate and the gate pattern; removing portions of the dielectric layer to expose the etch stop layer; performing an etch-back process on the etch stop layer to expose the sacrificial gate electrode; removing the sacrificial gate electrode to form a trench; forming a metal layer on the semiconductor substrate including the trench; removing portions of the metal layer to expose the dielectric layer; and performing an etch-back process on the metal layer to a predetermined target. | 2011-08-11 |
20110195551 | SEMICONDUCTOR DEVICES HAVING BIT LINE INTERCONNECTIONS WITH INCREASED WIDTH AND REDUCED DISTANCE FROM CORRESPONDING BIT LINE CONTACTS AND METHODS OF FABRICATING SUCH DEVICES - A semiconductor device has a bit line interconnection with a greater width and a reduced level on a bit line contact is provided, as are methods of fabricating such devices. These method includes forming a buried gate electrode to intersect an active region of a substrate. Source and drain regions are formed in the active region. A first conductive pattern is formed on the substrate. The first conductive pattern has a first conductive layer hole configured to expose the drain region. A second conductive pattern is formed in the first conductive layer hole to contact the drain region. A top surface of the second conductive pattern is at a lower level than a top surface of the first conductive pattern. A third conductive layer and a bit line capping layer are formed on the first conductive pattern and the second conductive pattern and patterned to form a third conductive pattern and a bit line capping pattern. The second conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the drain region, constitute first bit line structures, and the first conductive pattern, the third conductive pattern, and the bit line capping pattern, which are sequentially stacked on the isolation region, constitute second bit line structures. | 2011-08-11 |
20110195552 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a transistor. A gate insulating film of the transistor contains oxygen and nitrogen atoms. The gate insulating film does not contain the nitrogen atoms in a first face thereof being in a contact with the semiconductor layer, and in a second face thereof being in a contact with the gate electrode. A concentration peak of the nitrogen atoms appears between the first and second faces in the gate insulating film. | 2011-08-11 |
20110195553 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. The method comprises: forming a first layer; forming a P-well on the first layer; forming an isolation region in the P-well; performing an extra implantation on a surface between the P-well and the first layer; and forming a source/drain region. The method of the present invention can solve the punch through problem of the conventional iso-NMOS transistor without increasing cost. | 2011-08-11 |
20110195554 | Strain Bars in Stressed Layers of MOS Devices - A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region. | 2011-08-11 |
20110195555 | Techniques for FinFET Doping - A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer. | 2011-08-11 |
20110195556 | POWER MOSFET WITH A GATE STRUCTURE OF DIFFERENT MATERIAL - A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage. | 2011-08-11 |
20110195557 | METHOD FOR FORMING LOW RESISTANCE AND UNIFORM METAL GATE - The present disclosure provides a method that includes forming a high k dielectric layer on a semiconductor substrate; forming a polysilicon layer on the high k dielectric layer; patterning the high k dielectric layer and polysilicon layer to form first and second dummy gates in first and second field effect transistor (FET) regions, respectively; forming an inter-level dielectric (ILD); applying a first CMP process to the semiconductor substrate, exposing the first and second dummy gates; removing the polysilicon from the first dummy gate, resulting in a first gate trench; forming a first metal electrode in the first gate trench; applying a second CMP process; forming a mask covering the first FET region and exposing the second dummy gate; thereafter removing the polysilicon from the second dummy gate, resulting in a second gate trench; forming a second metal electrode in the second gate trench; and applying a third CMP process. | 2011-08-11 |
20110195558 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a non-volatile semiconductor memory device including previously forming a recess in a first peripheral region on a semiconductor substrate, forming a first gate insulator having a first thickness in the recess, forming a second gate insulator having a second thickness less than the first thickness in an array region and a second peripheral region on the semiconductor substrate, successively depositing first and second gate electrode films and first and second mask insulators on each of the first and second gate insulators, forming an isolation trench on a surface of the semiconductor substrate to correspond to each position between the array region and the first and second regions of the peripheral region, depositing a buried insulator on the entire surface, and polishing an upper surface of the buried insulator so that the upper surface can be planarized. | 2011-08-11 |
20110195559 | METHOD OF FORMING SHALLOW TRENCH ISOLATION STRUCTURE - An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed extending from the top surface into the substrate. The trench has sidewalls and a bottom surface. A liner oxide layer is formed on the sidewalls and the bottom surface. The liner oxide layer is treated in a plasma environment comprises at least one of NF | 2011-08-11 |
20110195560 | METHOD OF PRODUCING A SILICON-ON-SAPPHIRE TYPE HETEROSTRUCTURE - The invention provides a method of producing a heterostructure of the silicon-on-sapphire type, comprising bonding an SOI substrate onto a sapphire substrate and thinning the SOI substrate, thinning being carried out by grinding followed by etching of the SOI substrate. In accordance with the method, grinding is carried out using a wheel with a grinding surface that comprises abrasive particles having a mean dimension of more than 6.7 μm; further, after grinding and before etching, the method comprises a step of post-grinding annealing of the heterostructure carried out at a temperature in the range of 150° C. to 170° C. | 2011-08-11 |
20110195561 | ADHESIVE SHEET - An adhesive sheet includes a substrate and an energy-ray curable adhesive layer formed on the substrate. The energy-ray curable adhesive layer includes an energy-ray curable acrylic copolymer and a urethane acrylate. The energy-ray curable acrylic copolymer is formed by copolymerizing at least one of either a dialkyl(meth)acrylamide that has an alkyl group with carbon number of not more than 4, a phenol EO modified (meth)acrylate that has an ethylene glycol chain with a phenyl group bonded to the ethylene glycol chain, a (meth)acryloyl morpholine, or a (meth)acrylate that has an aceto-acetoxyl group, in total of 1 to 30 weight percent of all monomers to form the energy-ray curable acrylic copolymer. The energy-ray curable acrylic copolymer further includes a side chain with an unsaturated group. | 2011-08-11 |
20110195562 | Sputtering Apparatus, Thin-Film Forming Method, and Manufacturing Method for a Field Effect Transistor - [Object] To provide a sputtering apparatus, a thin-film forming method, and a manufacturing method for a field effect transistor, which are capable of reducing damage of a base layer. | 2011-08-11 |
20110195563 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device according to the present invention includes the steps of (a) forming an implantation mask made up of a plurality of unit masks on a silicon carbide semiconductor layer, and (b) implanting predetermined ion in the silicon carbide semiconductor layer at a predetermined implantation energy by using the implantation mask. In the step (a), the implantation mask is formed such that a length from any point in the unit mask to an end of the unit mask can be equal to or less than a scattering length obtained when the predetermined ion is implanted in silicon carbide at the predetermined implantation energy and the implantation mask can have a plurality of regions different from each other in terms of a size and an arrangement interval of the unit masks. | 2011-08-11 |
20110195564 | Memory Cell Layout - A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved. | 2011-08-11 |
20110195565 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece having a buried layer disposed beneath a top portion thereof. A trench is disposed in the workpiece extending at least through the buried layer. At least one sinker contact is disposed in the top portion of the workpiece. The at least one sinker contact is proximate sidewalls of at least a portion of the trench and is adjacent the buried layer. An insulating material is disposed on the sidewalls of the trench. A conductive material is disposed within the trench and is coupled to a lower portion of the workpiece. | 2011-08-11 |
20110195566 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - There is provided an SOI-MISFET including: an SOI layer; a gate electrode provided on the SOI layer interposing a gate insulator; and a first elevated layer provided higher in height from the SOI layer than the gate electrode at both sidewall sides of the gate electrode on the SOI layer so as to constitute a source and drain. Further, there is also provided a bulk-MISFET including: a gate electrode provided on a silicon substrate interposing a gate insulator thicker than the gate insulator of the SOI MISFET; and a second elevated layer configuring a source and drain provided on a semiconductor substrate at both sidewalls of the gate electrode. A the first elevated layer is thicker than the elevated layer, and the whole of the gate electrodes, part of the source and drain of the SOI-MISFET, and part of the source and drain of the bulk-MISFET are silicided. | 2011-08-11 |
20110195567 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises: immersing a semiconductor substrates in a Pd activating solution containing Pd ions and adhering a Pd catalyst to a surface of the semiconductor substrate; and immersing the semiconductor substrate, to which the Pd catalyst is adhered, in a Pd electroless plating solution and forming an electroless-plated Pd film on the semiconductor substrate. | 2011-08-11 |
20110195568 | SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PACKAGE - A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of the silicon substrate is removed to form a ring hole and a silicon pillar surrounded by the silicon pillar. Then, a photosensitive material is disposed in the ring hole, wherein the photosensitive material is insulating. After that, the silicon pillar is removed, such that the ring hole forms a through hole and the photosensitive material covers a lateral wall of the through hole. Lastly, the conductive material is disposed in the through hole, wherein the outer surface of the conductive material is surrounded by the photosensitive material. | 2011-08-11 |
20110195569 | Semiconductor Device and Method for Forming the Same - Methods of forming field effect transistors include forming a metal alloy gate electrode (e.g., aluminum alloy) containing about 0.5 to about 1.0 atomic percent silicon, on a substrate, and electroless plating an electrically conductive gate protection layer directly on at least a portion of an upper surface of the metal alloy gate electrode. A gate dielectric layer may be formed on the substrate. This gate dielectric layer may have a dielectric constant greater than a dielectric constant of silicon dioxide. The forming of the metal alloy gate electrode may include forming a metal alloy gate electrode directly on an upper surface of the gate dielectric layer. | 2011-08-11 |
20110195570 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios. | 2011-08-11 |
20110195571 | SEMICONDUCTOR PROCESS - A semiconductor process is described. A substrate with at least one conductive region is provided, on which a dielectric layer is formed. An opening is formed in the dielectric layer, such that the conductive region is exposed. A first conductive layer is conformally formed on the surface of the opening. A first cleaning step is conducted using a first cleaning solution. A baking step is conducted after the first cleaning step. Afterwards, the opening is filled with a second conductive layer. | 2011-08-11 |
20110195572 | Chip-stacked semiconductor device and manufacturing method thereof - A method of manufacturing a semiconductor device, includes forming a trench surrounding a first area of a semiconductor substrate, the trench having a bottom surface and two side surfaces being opposite to each other, forming a silicon film on the bottom surface and side surfaces of the trench, forming an insulation film on the silicon film in the trench, grinding a bottom surface of the semiconductor substrate to expose the insulation film formed over the bottom surface of the trench, and forming a through electrode in the first area after grinding the bottom surface of the semiconductor substrate, the through electrode penetrating the semiconductor substrate. | 2011-08-11 |
20110195573 | CLEANING LIQUID FOR LITHOGRAPHY AND METHOD FOR FORMING WIRING - Provided are a cleaning liquid for lithography that exhibits excellent corrosion suppression performance in relation to ILD materials, and excellent removal performance in relation to a resist film and a bottom antireflective coating film, and a method for forming a wiring using the cleaning liquid for lithography. The cleaning liquid for lithography according to the present invention includes a quaternary ammonium hydroxide, a water soluble organic solvent, water, and an inorganic base. The water soluble organic solvent contains a highly polar solvent having a dipole moment of no less than 3.0 D, a glycol ether solvent and a polyhydric alcohol, and the total content of the highly polar solvent and the glycol ether solvent is no less than 30% by mass relative to the total mass of the liquid for lithography. | 2011-08-11 |
20110195574 | NIOBIUM AND VANADIUM ORGANOMETALLIC PRECURSORS FOR THIN FILM DEPOSITION - Compound of the formula Cp(R | 2011-08-11 |
20110195575 | NOVEL HARD MASK REMOVAL METHOD - The embodiments of methods described in this disclosure for removing a hard mask layer(s) over a polysilicon layer of a gate stack after the gate stack is etched allows the complete removal of the hard mask layer without the assistance of photolithography. A dielectric material is deposited over the substrate with the gate stacks. The topography of the substrate is removed by chemical mechanical polishing first. Afterwards, an etching gas (or vapor) is used to etch a portion of the remaining dielectric layer and the hard mask layer. The etching gas forms an etch byproduct that deposits on the substrate surface and can be subsequently removed by heating. The etching and heating to remove etch byproduct are repeated until the hard mask layer is completed removed. Afterwards, the remaining dielectric layer is removed by wet etch. The methods described are simpler and cheaper to use than conventional methods for hard mask removal. | 2011-08-11 |
20110195576 | DOUBLE PATTERNING STRATEGY FOR CONTACT HOLE AND TRENCH IN PHOTOLITHOGRAPHY - A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer. | 2011-08-11 |
20110195577 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND PLASMA ETCHING APPARATUS - A semiconductor device manufacturing method includes a plasma etching step for etching an etching target film formed on a substrate accommodated in a processing chamber. In the plasma etching step, a processing gas including a gaseous mixture containing predetermined gases is supplied into the processing chamber, and a cycle including a first step in which a flow rate of at least one of the predetermined gases is set to a first value during a first time period and a second step in which the flow rate thereof is set to a second value that is different from the first value during a second time period is repeated consecutively at least three times without removing a plasma. The first time period and the second time period are set to about 1 to 15 seconds. | 2011-08-11 |
20110195578 | PLANAR CELL ON CUT USING IN-SITU POLYMER DEPOSITION AND ETCH - A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed. | 2011-08-11 |
20110195579 | SCRIBE-LINE DRAINING DURING WET-BENCH ETCH AND CLEAN PROCESSES - Controlling scribe line orientation during wet-bench processes has been found to improve yield and reduce particles from inadequate draining when the scribe lines are oriented about 45 degrees from horizontal. A wafer is provided to the wet bench apparatus and immersed in a solution. When removed from the solution, the wafer should be oriented vertically with scribe lines oriented about 45 degrees, plus or minus 15 degrees from horizontal. Wafer scribe line orientation are checked and changed before the wet bench process or during the wet bench processing. | 2011-08-11 |
20110195580 | METHOD FOR FORMING LAMINATED STRUCTURE INCLUDING AMORPHOUS CARBON FILM - A method for forming a laminated structure including an amorphous carbon film on an underlying layer includes forming an initial layer containing Si—C bonds on a surface of the underlying layer, by supplying an organic silicon gas onto the underlying layer; and forming the amorphous carbon film by thermal film formation on the underlying layer with the initial layer formed on the surface thereof, by supplying a film formation gas containing a hydrocarbon compound gas onto the underlying layer. | 2011-08-11 |
20110195581 | STRUCTURE AND METHOD TO ENHANCE BOTH NFET AND PFET PERFORMANCE USING DIFFERENT KINDS OF STRESSED LAYERS - In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits. | 2011-08-11 |
20110195582 | CVD Precursors - A method of producing silicon containing thin films by the thermal polymerization of a reactive gas mixture bisaminosilacyclobutane and source gas selected from a nitrogen providing gas, an oxygen providing gas and mixtures thereof. The films deposited may be silicon nitride, silicon carbonitride, silicon dioxide or carbon doped silicon dioxide. These films are useful as dielectrics, passivation coatings, barrier coatings, spacers, liners and/or stressors in semiconductor devices. | 2011-08-11 |
20110195583 | WAVELENGTH CONVERTING LAYER FOR A LIGHT EMITTING DEVICE - A layer of wavelength converting material is formed by supplying energy to a particle of wavelength converting material and causing the particle to contact a surface such that the energy causes the particle to adhere to the surface. In some embodiments, the wavelength converting material is a phosphor and the surface is a surface of a semiconductor light emitting device. | 2011-08-11 |
20110195584 | PRINTED CIRCUIT BOARD PLUG-TYPE CONNECTOR AND CONNECTION MODULE WITH PRINTED CIRCUIT BOARD PLUG-TYPE CONNECTOR - The invention relates to a printed circuit board plug-type connector ( | 2011-08-11 |
20110195585 | Connecting Device For Connecting An Electrical Conductor To A Solar Module And Method For The Production Thereof, Together With A Solar Module With Such A Connecting Device - A connecting device that connects to at least one external electrical conductor of a photovoltaic solar module. The connecting device includes a plurality of busbars, a support element, a housing, a diode and a contact. The plurality of busbars are arranged next to one another, while the support element is attached to the plurality of busbars and includes a bottom face to be positioned on the solar module. The housing is positioned over the support element and the plurality of busbars and includes an edge surrounding the support element and the plurality of busbars when the overhousing is positioned on the solar module. The diode fits onto the plurality of busbars and includes diode leads that fit onto one of the plurality of busbars, such that the plurality of busbars are connected together through the diode. | 2011-08-11 |
20110195586 | CABLE CONNECTOR ASSEMBLY - A cable connector assembly includes a housing including a first base and a second base coupled with the first base, at least a circuit board received in the housing and defining two rows of conductive pads located at two opposite sides thereof, at least a cable including a plurality of conductors electrically connecting with one row of the conductive pads of the circuit board, a pulling mechanism movably fixed to an outside face of the housing and separating the cable connector assembly from a complementary cable connector, and a metal shell partially shielding the pulling mechanism. The second base defines through grooves. The first base includes locking pieces inserted into the through grooves with free ends extending out of the through grooves from the outside face and bended to abut against the outside face of the housing. | 2011-08-11 |
20110195587 | CONNECTOR ASSEMBLY FOR AN INTERLOCK CIRCUIT - A connector assembly includes a housing, a current carrying conductor, and an interlock conductor. The housing has a cavity that receives conductive members and a shunt of a first connector. The cavity is bifurcated into a conductor channel and an interlock channel that receives a conductive member of a second connector. The current carrying conductor is in the housing and extends through the cavity and the conductor channel. The interlock conductor is in the housing and extends through the cavity and the interlock channel. The interlock conductor closes an interlock circuit when the interlock conductor mates the shunt of the first connector with the conductive member of the second connector. The current carrying conductors mate to the conductive members of the first connector to begin transferring electric current through the current carrying conductor when the interlock circuit is closed. | 2011-08-11 |
20110195588 | SOCKET CONNECTOR HAVING STIFFENER PROVIDED WITH LATCH-ENABLED STANDOFF - A socket connector comprises a housing having a plurality of contacts revived therein, a stiffener coupled with the housing and defining a plurality of mounting holes, and a plurality of standoffs each inserted into a mounting holes of the stiffener. Each standoff defines at least one post positioning the standoff in the mounting hole and at least one latch member grasping edge of the mounting hole. | 2011-08-11 |
20110195589 | Socket connector having a recess provided with a spring member on a side thereof - A socket connector includes a socket body having a recess adapted to receive therein a connection object such as a semiconductor module, contact members disposed at a bottom surface portion of the recess, and a spring member disposed on one side of the recess. The spring member has an engaging portion adapted to engage the connection object in a detaching direction for provisionally holding it in a first stage of an attaching operation of the connection object and a pressing portion adapted to press the connection object parallel to the bottom surface portion and inward of the recess for positioning the connection object at a predetermined position of the recess. | 2011-08-11 |
20110195590 | CABEL CONNECTOR ASSEMBLY WITH IMPROVED CONDUCTIVE SHELL - A cable connector assembly includes a conductive housing, a pair of PCBs, two cables and a metal shell assembled to the housing. The housing defines a receiving cavity. The PCBs are received in the receiving cavity at different levels. The two cables are located at a rear wall of the housing and electrically connect to the PCBs. The metal shell is assembled to the housing and includes a frame portion, and an extension portion extending forwardly from an upper wall of the frame portion. The frame portion encloses a rear portion of the housing and the extension portion has a pair of first position holes. The housing has a pair of second position holes are aligned with first position holes respectively. Two bolts penetrate through the first position holes and are locked in the second position holes respectively. | 2011-08-11 |
20110195591 | CHECKABLE PLUG-IN CONNECTION AND METHOD FOR CHECKING THE CONNECTION STATE OF A PLUG-IN CONNECTION - The method according to the invention comprises the following steps: a) securely attaching the verification element ( | 2011-08-11 |
20110195592 | Electrical Connector - The cable assembly may include a plug connector, a cable, and a connector. The plug connector may include a housing and a board assembly. The board assembly may include a printed circuit board. The edge of the printed circuit board may be enclosed with a material. The material may be an overmolded plastic or a coating of a material. In order to reduce the crosstalk in the areas where the cable shield is removed, a shielding assembly may be used. The shielding assembly may provide 360 degrees of shielding for the wire pair at the location where the cable shield is removed. The printed circuit board may have a trace layer, a core layer, and a ground plane layer. The ground plane layer may have a portion which is a solid layer and another portion which is a non-solid layer. | 2011-08-11 |
20110195593 | Electrical Connector - The cable assembly may include a plug connector, a cable, and a connector. The plug connector may include a housing and a board assembly. The board assembly may include a printed circuit board. The edge of the printed circuit board may be enclosed with a material. The material may be an overmolded plastic or a coating of a material. In order to reduce the crosstalk in the areas where the cable shield is removed, a shielding assembly may be used. The shielding assembly may provide 360 degrees of shielding for the wire pair at the location where the cable shield is removed. The printed circuit board may have a trace layer, a core layer, and a ground plane layer. The ground plane layer may have a portion which is a solid layer and another portion which is a non-solid layer. | 2011-08-11 |
20110195594 | RJ-45 CONNECTOR AND ELECTRONIC DEVICE HAVING THE SAME - A Registered Jack-45 (RJ-45) connector includes a main body, and a cable electrically connected to a rear end of the main body. The main body includes a resilient latching piece formed on a top of the main body. Two opposite sides of the main body each define a slot adjacent to the rear end of the main body, with opposite ends of the slot extending through the top and a bottom of the main body, respectively. | 2011-08-11 |
20110195595 | ELECTRICAL CONNECTOR ASSEMBLY WITH LATCH SYSTEM EASY TO OPERATING - An electrical connector assembly includes an insulative housing defining at least two mating cavities arranged side by side in a widthwise direction and extending in a front and rear direction; two PCB (printed circuit board) modules received in each mating cavity in a stacked manner; a platform fitly attached to a top surface of the insulative housing, the platform includes a pair of supporting sections disposed at a front edge thereof and a pair of connecting portion at a rear edge thereof; a pair of latches associated to the top surface of the insulative housing and comprising a locking portion for retaining a complementary connector and a pressed portion extending rearwards and disposed above the supporting portion; and a driver rotatably retained on the pair of connecting portions of the platform and comprising a pair of contacting portions pressing against the pressed portions of the latches to urge the pressing portion downwards movement. | 2011-08-11 |
20110195596 | CONNECTOR - A connector is provided for improving connection reliability between terminal fittings by preventing wires from shaking to prevent sliding movements of the terminal fittings. The connector includes a metallic shield shell ( | 2011-08-11 |
20110195597 | CONNECTION STRUCTURE OF HOISTWAY CABLE AND DOOR INTERLOCK SWITCH - Disclosed herein is a connection structure of a hoistway cable and a door interlock switch. The connection structure includes a hoistway cable, a connection wire, a terminal block, and a support block. The hoistway cable includes core wires in a sheath having a shape of a flat band. The core wires include a positive wire having a positive polarity, a negative wire having a negative polarity, and a ground wire for grounding. The connection wire connects any one of the core wires having polarities to both ends of the door interlock switch. The terminal block covers one surface of the hoistway cable, and includes two terminal members each having input and output terminal parts which are integrated with each other, and a cutting member cutting and insulating the core wire. The support block covers the other surface of the hoistway cable and is coupled to the terminal block. | 2011-08-11 |
20110195598 | Termination Cap For Use In Wired Network Management System - A termination unit ( | 2011-08-11 |
20110195599 | FLAT RESTORABLE CABLE - A flat restorable cable has a cable body and two connectors. The cable body is wound to have a spirally wound form. The cable body is extended by pulling two ends of the cable, and restores back to the original spirally wound form once either end of the cable is released. The two connectors are securely mounted to respective ends of the cable body and used to respectively connect with two external compatible interfaces. As a result of less part required, compact size and thin thickness, the flat restorable cable addresses an inexpensive and portable solution to connect two electronic devices over a short distance. | 2011-08-11 |
20110195600 | DISTRIBUTION STRIP AND EQUIPMENT CABINET - The invention relates to a distribution strip for distributing electric energy for equipment and/or server cabinets ( | 2011-08-11 |
20110195601 | EXTENSION TO VERSION 2.0 UNIVERSAL SERIAL BUS CONNECTOR WITH ADDITIONAL CONTACTS - An extension to USB includes an insulative tongue portion and a number of contacts held in the insulative tongue portion. The contacts have four conductive contacts and a plurality of differential contacts for transferring differential signals located behind/forward the four standard USB contacts along a front-to-rear direction. The four conductive contacts are adapted for USB 2.0 protocol and the plurality of differential contacts are adapted for non-USB 2.0 protocol. The extension to USB is capable of mating with a complementary standard USB 2.0 connector and a non-USB 2.0 connector, alternatively. | 2011-08-11 |
20110195602 | CARD CONNECTOR WITH ADJUSTMENT SECTIONS - A card connector includes an insulative housing having an elongated base and a pair of arms located at opposite sides of the base thereby defining a receiving cavity therebetween. Each arm defines a guiding slot extending along a rear-to-front direction and in communication with the receiving cavity. A plurality of contacts are retained in the base, each having a pin shaped contacting portion projecting into the receiving cavity and a solder portion extending out of the base. A shell device is attached to the insulative housing. Opposite sides of each guiding slot extend inwardly so as to form an adjustment section interconnecting with the base, which can ensure a card to be inserted accurately. | 2011-08-11 |
20110195603 | SHIELD CONNECTOR - A shield connector ( | 2011-08-11 |
20110195604 | ELECTRICAL CONNECTOR FOR TEST PURPOSE - An electrical connector ( | 2011-08-11 |
20110195605 | COMPLEX ELECTRICAL CONNECTOR - An electrical connector includes a first connector interface and a second connector interface arranged side by side and spaced from each other along a longitudinal direction of the electrical connector. The first connector interface is of tongue portion with a plurality of contacts arranged on the tongue portion; the second connector interface is of frame shape. Two end walls are disposed at two opposite ends of the connector along the longitudinal direction and aligned with two connector interfaces and a connecting wall connects with the end walls at one side of the connector interfaces. The second connector interface has at least one mating cavity, which has no wall at one side so that the mating cavity directly faces to one guiding slot on the end wall. | 2011-08-11 |
20110195606 | ELECTRICAL CONNECTOR - An electrical connector includes an insulation pedestal, an outer cover, an enhanced shell and a plurality of terminals partially embedded in the insulation pedestal. The insulation pedestal includes a main body and a tongue section. The enhanced shell includes a fixed side and a support side. The fixed side is embedded in the main body; and the tongue section is partially covered by the support side such that the support side can support the tongue section. The insulation pedestal is integratedly formed together with the terminals and the enhanced shell to strengthen the structure of the tongue section. | 2011-08-11 |
20110195607 | LEAD FRAME ASSEMBLY FOR AN ELECTRICAL CONNECTOR - A lead frame assembly for an electrical connector is provided. The lead frame assembly includes a first lead, a second lead adjacent the first lead and a dielectric material. The leads have a first end, a second end and an intermediate portion between the first end and the second end. The leads are received within the dielectric material with the intermediate portions being substantially surrounded by the dielectric material. The dielectric material includes at least a first channel in the dielectric material arranged in-between the first and second leads. The first channel is defined by at least three sides and has a length extending in a direction substantially parallel to the intermediate portions of the first and second leads. | 2011-08-11 |
20110195608 | ELECTRICAL CONNECTOR WITH IMPROVED RECEIVING CHANNELS LATCHED WITH CONTACTS - An electrical connector ( | 2011-08-11 |
20110195609 | CABLE CONNECTOR ASSEMBLY HAVING A FIRM CONNECTION BETWEEN CONTACTS AND CABLE THEREIN - A cable connector assembly comprising: an insulative housing ( | 2011-08-11 |
20110195610 | SOCKET AND CONNECTOR - A socket includes a substantially rectangular columnar socket body made of an insulating material and the socket body including a connection recess portion defined on one surface thereof. Side walls opposed to each other in a transverse direction and lead-out pathways formed in the side walls. The socket further includes a plurality of socket contact members arranged side by side within the connection recess portion along a longitudinal direction. One-end portions of the socket contact members extend through the lead-out pathways and protruding outwards beyond an outer surface of at least one of the side walls of the socket body. The socket body includes a depression portion formed on the side wall through which the socket contact members protrude and the depression portion being formed at least around the socket contact members. | 2011-08-11 |
20110195611 | WATERPROOF AUDIO JACK CONNECTOR - An audio jack connector ( | 2011-08-11 |
20110195612 | LOW PROFILE PLUGS - Apparatus, systems, and methods for assembling a plug with a low profile for use with an electronic device are provided. In some embodiments, a 4-pin plug may include a diameter similar to the diameter of a 3-pin plug. In some embodiments, the fourth pin may be coupled to the plug such that a portion of the fourth pin may be coupled to any suitable device on an internal surface of the plug. In some embodiments, the fourth pin may dive into the plug at the same depth as one of the other three pins of the plug. The pins within the plug may be coupled (e.g., soldered) at the ends that may emerge underneath an overmold to any other suitable device to form electrical connections. The plug may be used to transmit audio or transfer data to a user of the electronic device. | 2011-08-11 |
20110195613 | NETWORK LINE PLUG ASSEMBLY - A network line plug and network line, and more particularly to a network line plug, network line plug assembly and network line; the network line plug of the present invention comprises of a short-head main body, rubber core and eight welded terminals; the rubber core is fixed into the short-head main body; said welded terminals are inserted into the rubber core; the first and second ends of said welded terminal are an electrical contact portion and welding portion, respectively; the welding portions of the welded terminal penetrate selectively the through-holes of the rubber core; the welding portions of two welded terminals corresponding to the same core pair are arranged adjacent to one another. | 2011-08-11 |
20110195614 | CABEL CONNECTOR ASSEMBLY WITH ALIGNED CABLE ARRANGEMENT - A cable connector assembly includes a conductive housing including a base in cooperation with a cover to define a receiving cavity, a pair of first and second PCBs received in the receiving cavity at different levels, and at least two cables located at a same level at a rear wall of the housing. The receiving cavity includes a hollow portion and a mating port located in front of the hollow portion. Both PCBs have mating interfaces extending into the mating port and mounting portions located within the hollow portion. The at least two cables electrically connect to the mounting portions of the first and second PCBs, respectively. | 2011-08-11 |
20110195615 | CLAMP FOR MALE TERMINAL - A clamp for male terminal comprising a clamping ring capable of inserting on a male terminal, two jaws connected to the clamping ring and mutually approachable to tighten the clamping ring on the male terminal, clamping means acting on the jaws to move them between a distant position and a close position along a clamping direction. The clamping means comprise a clamping member rotating around a clamping axis inclined with respect to a plane perpendicular to the axis of the clamping ring. The clamp further comprises guiding means cooperating with a movable jaw to guide the movement of such movable jaw along the clamping direction on said plane, between the distant position and the close position. | 2011-08-11 |
20110195616 | SPRING CONNECTOR - A spring connector includes a barrel, a plunger and a spring. The barrel includes a longitudinal space formed therein, an opening formed at a top thereof, a bottom plate formed at a bottom thereof and a narrow portion formed from a middle portion and to the bottom thereof. The plunger includes a contact portion protruding from the opening, a sliding portion received in the longitudinal space, and a limit recess formed in the lower sliding portion. A top end of the spring is received in and limited by the limit recess, and a bottom end and a middle portion is limited by the narrower portion to restrict the spring being compressed along a longitudinal direction thereof. The spring is also prevented from deviating from the longitudinal direction thereof. | 2011-08-11 |
20110195617 | Contact Arrangement For Connection With A Polygonal Socket - The invention relates to an electrical contact arrangement for high pulsed currents and for connection with a polygonal socket. The electrical contact arrangement includes first contact, arm, a second contact arm, an intermediate space provided between the first and second contact arms, and a third contact arm. The second contact arm positioned apart from the first contact arm in a deflection direction extending perpendicularly to the plug-in direction. The first contact arm and second contact arm extend substantially in a plug-in direction, and one of the first contact arm or second contact arm resiliently deflectable relative to the other contact arm in the deflection direction. The third contact arm extends in the plug-in direction and is positioned apart from the first contact arm and the second contact arm in a transverse direction extending perpendicularly to the plug-in and deflection directions. The third contact arm movable in the deflection direction and into the intermediate space. | 2011-08-11 |
20110195618 | Systems and Methods for Controlling Battery Performance in Hybrid Marine Propulsion Systems - A hybrid propulsion system has an internal combustion engine and an electric motor that each selectively powers a marine propulsor to propel a marine vessel. A plurality of batteries discharges current to power the motor. A controller is programmed to aggregate the recharge and/or discharge limits of plurality of batteries and then operate the system according to a method that preferably prevents internal fault and disconnection of batteries in the plurality. | 2011-08-11 |
20110195619 | TRIMMABLE POD DRIVE - Disclosed herein is a trimmable pod drive assembly that includes a pod drive unit having a transmission assembly secured to a steering unit, a gear case assembly coupled to and rotatable by the steering unit about a steering axis, and a propeller rotatable about a propeller driveshaft axis extending through the gear case assembly so as to generate thrust along a thrust vector. The trimmable pod drive assembly further includes a trim assembly secured to the pod drive unit in a manner allowing for rotation of the pod drive unit about a trim axis that is substantially perpendicular to the steering axis, wherein actuation of at least one component of the trim assembly causes movement of the pod drive unit and the thrust vector about the trim axis. | 2011-08-11 |
20110195620 | LARGE OUTBOARD MOTOR FOR MARINE VESSEL APPLICATION AND RELATED METHODS OF MAKING AND OPERATING SAME - An outboard motor for a marine vessel application, and related methods of making and operating same, are disclosed herein. In at least one embodiment, the outboard motor includes a horizontal-crankshaft engine in an upper portion of the outboard motor, positioned substantially positioned above a trimming axis of the outboard motor. In at least another embodiment, first, second and third transmission devices are employed to transmit rotational power from the engine to one or more propellers at a lower portion of the outboard motor. In at least a further embodiment, the outboard motor is made to include a rigid interior assembly formed by the engine, multiple transmission devices, and a further structural component. In further embodiments, the outboard motor includes numerous cooling, exhaust, and/or oil system components, as well as other transmission features. | 2011-08-11 |
20110195621 | PROPELLER DRIVE ARRANGEMENT FOR CONTROLLING AND DRIVING A SHIP - A propeller drive configuration, for the control and drive of a ship ( | 2011-08-11 |
20110195622 | Oar Apparatus and Method of Use - An apparatus and method for allowing a fisherman to utilize an oar or paddle while maintaining possession and control of a fishing pole rod and fishing reel. The oar or paddle is designed to be an integral member with or affixed to the fishing pole rod and fishing reel without altering the full movement and operation of the fishing pole rod and fishing reel. | 2011-08-11 |
20110195623 | Cooling Systems and Methods for Hybrid Marine Propulsion Systems - Cooling systems and methods for hybrid marine propulsion systems are disclosed. A first cooling circuit is arranged to convey raw cooling water through an internal combustion engine and to at least one drive component of a drive unit for the marine propulsion system. A second control circuit is arranged to convey raw cooling water through an electric motor. The system is arranged such that raw cooling water in the second cooling circuit is conveyed to the first cooling circuit to cool the drive component without cooling the component of the internal combustion engine. | 2011-08-11 |
20110195624 | FLASH SPUN WEB CONTAINING SUB-MICRON FILAMENTS AND PROCESS FOR FORMING SAME - A nonwoven fibrous structure and process for forming it, which is an interconnecting web of polyolefin filaments having filament widths greater than about 1 micrometer which are further interconnected with webs of smaller polyolefin filaments having filament widths less than about 1 micrometer, wherein the smaller polyolefin filaments comprise a majority of all filaments. | 2011-08-11 |
20110195625 | Adhesive Tape - A tape having a woven fabric and an adhesive on at least one side of the fabric. The woven fabric comprises polyester warp yarns and acetate weft yarns. | 2011-08-11 |
20110195626 | Reprocessing Of Alkyd Resins - Disclosed herein are methods of reforming or recycling infusible, insoluble alkyd resins into new shapes and forms. The insoluble alkyd resins that are reformed or recycled can include pellets, powders, chips, chunks, scraps, pulverized articles, and mixtures thereof. Also disclosed herein are alkyd resins that have been reformed into shaped articles that have traditionally been made with thermoplastics. The shapes of the reformed alkyd resins can include pellets, films, sheets, fibers, nonwovens, and molded articles. | 2011-08-11 |
20110195627 | NATURAL RENEWABLE FIBER TRIM LAMINATE - A deformable structure for automotive interior components includes a substrate and a cushion element. The cushion element is disposed over the substrate. The cushion element includes a fiber section which has cellulosic fibers. The deformable structure also includes a cover disposed over the cushion element. A vehicle seat and trim laminate incorporating the deformable structure is also provided. | 2011-08-11 |
20110195628 | LAYOUT OF LIQUID CRYSTAL DISPLAY PANELS AND SIZE OF MOTHER SUBSTRATE - A layout of LCD panels and a size of the mother substrate are disclosed, to improve the efficiency in arrangement of the LCD panels, and to maximize the substrate efficiency, the layout comprising a mother substrate; a dummy region of 15 mm or less in a periphery of the mother substrate; and six LCD panels of the 26-inch model in a matrix of 2×3 on the mother substrate excluding the dummy region with a margin corresponding to 2˜4% of a length of the LCD panel. | 2011-08-11 |
20110195629 | ELECTRO-OPTIC MEDIA PRODUCED USING INK JET PRINTING - Ink jet printing can be used in the production of electro-optic displays for (a) forming a layer of a polymer-dispersed electrophoretic medium on a substrate; (b) forming a color electro-optic layer; (c) forming a color filter; and (d) printing electrodes and/or associated conductors on a layer of electro-optic material. | 2011-08-11 |