31st week of 2009 patent applcation highlights part 37 |
Patent application number | Title | Published |
20090191619 | METHOD AND DEVICE FOR SELECTIVELY TARGETING CELLS WITHIN A THREE-DIMENSIONAL SPECIMEN - The invention provides an apparatus for electromagnetically affecting a particle of interest in a specimen. The apparatus includes (a) a stage capable of supporting the specimen; (b) a detector including at least one camera, wherein the detector is capable of resolving a particle of interest within the specimen; (c) a means for locating the particle of interest in three dimensions; (d) a means for focusing electromagnetic radiation to a focal volume within the specimen; and (e) a means for adjusting the relative positions of the stage and electromagnetic radiation focusing means, thereby positioning the particle of interest within the focal volume. | 2009-07-30 |
20090191620 | LIMITED ACCESS MULTI-LAYER CELL CULTURE SYSTEM - The present invention provides a multi-layer cell culture device having a rectangular footprint and having multiple cell culture chambers separated by tracheal air spaces, each cell culture chamber having a port and a port cover or an external manifold structured and arranged to allow for transfer of fluid into and out of the cell culture device with reduced risk of contamination, and methods of using the device. | 2009-07-30 |
20090191621 | Cover Device for a Sample Carrier - The present invention relates to a cover device for a sample carrier, comprising a sticky surface area for connection to the sample carrier, wherein the sticky surface area is configured such that the sample carrier is covered in liquid-tight fashion after connection of the cover device to the sample carrier in the sticky surface area. | 2009-07-30 |
20090191622 | SYNTHETIC NUCLEIC ACIDS FROM AQUATIC SPECIES - A synthetic nucleic acid molecule is provided that includes nucleotides of a coding region for a fluorescent polypeptide having a codon composition differing at more than 25% of the codons from a parent nucleic acid sequence encoding a fluorescent polypeptide. The synthetic nucleic acid molecule has at least 3-fold fewer transcription regulatory sequences relative to the average number of such sequences in the parent nucleic acid sequence. The polypeptide encoded by the synthetic nucleic acid molecule preferably has at least 85% sequence identity to the polypeptide encoded by the parent nucleic acid sequence. | 2009-07-30 |
20090191623 | COMPOSITIONS AND METHODS FOR TREATING HIV INFECTION WITH CUPREDOXIN AND CYTOCHROME C - The present invention relates to cupredoxin, specifically | 2009-07-30 |
20090191624 | Use of transthyretin peptide/protein fussions to increase the serum half-life of pharmacologically active peptides/proteins - The present invention provides a means for increasing the serum half-life of a selected biologically active agent by utilizing transthyretin (TTR) as a fusion partner with a biologically active agent. Specifically, the present invention provides substantially homogenous preparations of TTR (or a TTR variant)-biologically active agent fusions and PEG-TTR (PEG-TTR variant)-biologically active agent fusions. As compared to the biologically active agent alone, the TTR-biologically active agent fusion and/or PEG-TTR-biologically active agent fusion has substantially increased serum half-life. | 2009-07-30 |
20090191625 | siRNA targeting connective tissue growth factor (CTGF) - Efficient sequence specific gene silencing is possible through the use of siRNA technology. By selecting particular siRNAs by rational design, one can maximize the generation of an effective gene silencing reagent, as well as methods for silencing genes. Methods, compositions, and kits generated through rational design of siRNAs are disclosed including those directed to CTGF. | 2009-07-30 |
20090191626 | Synthetic Surfaces for Culturing Stem Cell Derived Oligodendrocyte Progenitor Cells - Synthetic surfaces suitable for culturing stem cell derived oligodendrocyte progenitor cells contain acrylate polymers formed from one or more acrylate monomers. The acrylate surfaces, in many cases, are suitable for culturing stem cell derived oligodendrocyte progenitor cells in chemically defined media. | 2009-07-30 |
20090191627 | SYNTHETIC SURFACES FOR CULTURING CELLS IN CHEMICALLY DEFINED MEDIA - Synthetic surfaces capable of supporting culture of eukaryotic cells including stem cells and undifferentiated human embryonic stem cells in a chemically defined medium include a swellable (meth)acrylate layer and a polypeptide conjugated to the swellable (meth)acrylate layer. The swellable (meth)acrylate layer may be formed by polymerizing monomers in a composition that includes a carboxyl group-containing (meth)acrylate monomer, a cross-linking (di- or higher-functional) (meth)acrylate monomer, and a hydrophilic monomer capable of polymerizing with the carboxyl group-containing (meth)acrylate monomer and the cross-linking (meth)acrylate monomer. The swellable (meth)acrylate layer has an equilibrium water content in water of between about 5% and about 70%. The conjugated peptide may include an RGD amino acid sequence. | 2009-07-30 |
20090191628 | Methods for co-culturing cord blood derived cells with menstrual stem cells - Methods are provided for obtaining expanded human cord blood cells expressing CD34. The methods involve seeding a sufficient amount of cord blood cells with a sufficient amount of menstrual cells under co-culture conditions suitable to promote expansion of the cord blood cells, and co-culturing the cord blood cells with the menstrual cells under culture conditions that support at least two or more population doublings of the cord blood cells. Methods are also provided for growing expanded human cord blood cells to give rise to any one of colony forming units, colony forming unit granulocyte macrophages (CFU-GM), burst forming unit erythroids (BFU-E), and colony forming unit granulocyte erythrocyte macrophage megakaryocyte (CFU-GEMM) blood lineage precursor cells. The expanded cells may express CD34, SSEA-4, and HLA-II. Compositions of the expanded cells are also provided. | 2009-07-30 |
20090191629 | MAMMALIAN CHEMOKINE REAGENTS - Novel chemokines from mammals, reagents related thereto including purified proteins, specific antibodies, and nucleic acids encoding said chemokines. Chemokine receptors are also provided. Methods of using said reagents and diagnostic kits are also provided. | 2009-07-30 |
20090191630 | Dual Inhibitors of HIV-1 GP-120 Interactions - Compounds, which inhibit the binding of gp120 to CD4 as well as 17b and methods for their use in inhibiting the HIV fusion process, are provided. | 2009-07-30 |
20090191631 | 3-D petri-dish for the culture and studies of cells - A three-dimensional (3-D) culture “Petri-dish” for research in regenerative medicine, biotechnology and clinical translation is described. This 3-D perfusion culture dish is to advance in vitro culture tools from static 2-D to dynamic 3-D perfusion culture. Interwoven hollow fiber capillary membranes divide the “Petri-dish” culture space into a controllable 3-D pattern of different compartments, serving the functions of the organ's larger vasculature. These physically active scaffolds, which can be suitable for cell adhesion or cell aggregate immobilization, offer a supply of cells with high-performance mass exchange including gas supply and under perfusion conditions. In contrast to static and discontinuous medium supply, a dynamic culture can be achieved with continuous or alternating medium supply and integral oxygenation. They provide a more physiologic supply in the cell macro environment, including homeostasis of oxygen, pH, nutrition, soluble factors, and gradients of metabolites for the cells. Also, medium perfusion can be achieved. Consequently the invention was made for cultures at tissue density, especially stem cells and support cells, which strive to create their own stem cell niche. | 2009-07-30 |
20090191632 | SWELLABLE (METH)ACRYLATE SURFACES FOR CULTURING CELLS IN CHEMICALLY DEFINED MEDIA - Synthetic surfaces capable of supporting culture of undifferentiated human embryonic stem cells in a chemically defined medium include a swellable (meth)acrylate layer and a peptide conjugated to the swellable (meth)acrylate layer. The swellable (meth)acrylate layer may be formed by polymerizing monomers in a composition that includes hydroxyethyl methacrylate, 2-carboxyehylacrylate, and tetra(ethylene glycol) dimethacrylate. The conjugated peptide may include an amino acid sequence of Xaa | 2009-07-30 |
20090191633 | Synthetic Surfaces for Culturing Stem Cell Derived Cardiomyocytes - Synthetic surfaces suitable for culturing stem cell derived cardiomyocytes contain acrylate polymers formed from one or more acrylate monomers. The acrylate surfaces, in many cases, are suitable for culturing stem cell derived cardiomyocytes in chemically defined media. | 2009-07-30 |
20090191634 | (METH)ACRYLATE SURFACES FOR CELL CULTURE, METHODS OF MAKING AND USING THE SURFACES - A synthetic cell culture surface, prepared from a polymerized blend of at least two (meth)acrylate monomers is provided, which supports the growth of undifferentiated human embryonic stem cells in defined media augmented with fetal bovine serum. The cell culture surface forms a uniform layer over the growth area of a typical cell culture vessel. | 2009-07-30 |
20090191635 | PLANT EGG CELL TRANSCRIPTIONAL CONTROL SEQUENCES - The present invention relates generally to transcriptional control sequences. Generally, the present invention relates to transcriptional control sequences that specifically or preferentially direct expression of a nucleotide sequence of interest in a plant egg cell. The present invention is predicated, in part, on the identification of transcriptional control sequences derived from EC1 genes which, in preferred embodiments, direct preferential expression in an egg cell of at least one plant taxon. | 2009-07-30 |
20090191636 | Method of Producing Transgenic Graminaceous Cells and Plants - The present invention provides a method for producing a transgenic graminaceous plant cell, said method comprising: (i) obtaining embryonic cells from a mature graminaceous grain; and (ii) contacting said embryonic cells with a bacterium capable of transforming a plant cell, said bacterium comprising transfer-nucleic acid to be introduced into the embryonic cells, said contacting being for a time and under conditions sufficient for said bacterium to introduce said transfer-nucleic acid into one or more of the embryonic cells, thereby producing a transgenic graminaceous plant cell. The present invention also provides a method for producing a transgenic graminaceous plant. The present invention also provides a transgenic graminaceous plant cell and/or a transgenic graminaceous plant produced by said method. The present invention also provides a method for expressing a nucleic acid in a transgenic graminaceous plant cell or a transgenic graminaceous plant. | 2009-07-30 |
20090191637 | Method and apparatus for determining anticoagulant therapy factors - Methods and apparatus are disclosed for determining a new anticoagulant therapy factors for monitoring oral anticoagulant therapy to help prevent excessive bleeding or deleterious blood clots that might otherwise occur before, during or after surgery. New anticoagulant therapy factors maybe based upon the time to maximum acceleration from the time of reagent injection (TX) into a plasma sample, Embodiments include methods and apparatus for determining an anticoagulant therapy factor without requiring use of a mean normal prothrombin time determination or ISI, and may be carried out with the patient sample and a coagulation reagent. | 2009-07-30 |
20090191638 | Assay Preparation Plates, Fluid Assay Preparation and Analysis Systems, and Methods for Preparing and Analyzing Assays - Assay preparation plates are provided which include an array of wells, a magnet, and an actuator configured to move the magnet proximate and remote relative to the array. A fluid assay preparation and analysis system is provided which includes a pipette disposed above an assay plate receiving area, a magnet disposed below the assay plate receiving area in approximate alignment with the pipette, and an actuator configured to move the magnet proximate the assay plate receiving area. A method for preparing and analyzing an assay includes injecting a sample into a sample well of an assay preparation plate and inserting the assay preparation plate into a fluid assay analysis system. The method further includes mixing the sample with one or more reagents in an assay plate receiving area of the system and subsequently aspirating the prepared assay into an examination chamber of the system. | 2009-07-30 |
20090191639 | Non-Invasive Rapid Diagnostic Test For M.Tuberculosis Infection - This invention relates to a test for detecting a | 2009-07-30 |
20090191640 | Methods of Screening for Atherosclerosis - Methods for screening for altered focal proliferation states in non-pregnant patients, which include detecting levels of pregnancy-associated plasma protein-A (PAPP-A), are described. Methods for identifying agents that alter the protease activity of PAPP-A, and pharmaceutical compositions and medical devices that include such agents also are described. | 2009-07-30 |
20090191641 | IMMUNODIAGNOSTIC TEST CARDS HAVING INDICATING INDICIA - An immunodiagnostic test card includes a plurality of transparent chambers wherein each chamber includes a quantity of testing material that combines with a patient sample, when mixed, to produce an agglutination reaction. A plurality of indicia are disposed to aid in the manufacture and determining the usability of the cards prior to test and also in objectively grading the agglutination reactions that are formed or lack of agglutination. | 2009-07-30 |
20090191642 | Compositions, Systems, and Methods for Continuous Glucose Monitoring - A polymeric sensing fluid for detecting the presence of glucose and systems and methods of its use are generally disclosed. The polymeric sensing fluid includes a polymer in a solvent (e.g., an aqueous solvent). The polymer has a plurality of boronic acid moieties extending from its polymeric backbone. As such, the polymeric sensing fluid is configured to increase in viscosity upon addition of glucose due to crosslinking between the boronic acid moieties of the polymer and glucose. | 2009-07-30 |
20090191643 | Rotatable Test Element - A test element and method for detecting an analyte with the aid thereof is provided. The test element is essentially disk-shaped and flat, and can be rotated about a preferably central axis which is perpendicular to the plane of the disk-shaped test element. The test element has a sample application opening for applying a liquid sample, a capillary-active zone, in particular a porous, absorbent matrix, having a first end that is remote from the axis and a second end that is near to the axis, and a sample channel which extends from an area near to the axis to the first end of the capillary-active zone that is remote from the axis. | 2009-07-30 |
20090191644 | Imprinted polymer for binding of organic molecules or metal ions - The invention relates to an imprinted polymer imprinted with an organic molecule or a metal ion wherein the matrix of the polymer has been prepared from one or more monomers including bilirubin or an analogue thereof. The imprinted polymers may be prepared by polymerising one or more monomers including bilirubin or an analogue or derivative thereof in the presence of the molecule or metal ion to be imprinted or an analogue or derivative thereof, and subsequently at least partly removing the molecule or ion to be imprinted or its analogue or derivative. The polymers may be used in a method for detection and/or assay of the imprinting molecule or metal ion. | 2009-07-30 |
20090191645 | COMPOUNDS AND METHODS FOR MODULATING INTEGRIN ACTIVITY - The present invention provides methods and compositions for modulating integrin activity. In particular, the present invention encompasses methods and compositions for altering the interaction between the α and β chain extracellular clasp regions. | 2009-07-30 |
20090191646 | MOLYBDENUM COMPLEX & TEST KIT TO ENHANCE ACCURACY OF ANALYSIS OF ENDOGENOUS ANALYTES IN BIOLOGICAL FLUIDS - Methods for enhancement in accuracy of immunochemical analysis of heterogeneous biological fluids containing exogenous substances that can interfere in immunochemical analysis for endogenous analytes of interest. According to this method a heterogeneous biological fluid sample is pretreated with an interferant suppression effective amount of a molybdenum coordination complex, so as to reduce manifestation of the presence of said exogenous material under immunoassay conditions. This invention is suitable for the suppression of manifestation of exogenous substances, specifically metabolites of drugs of abuse, during the immunoassay of biological fluids of infants for detection of endogenous substances indicative of a wellness or disease state. This invention also has application for similar suppression exogenous substances in the biological fluid of adults that have been inadvertently exposed to such substances (e.g. secondhand smoke). | 2009-07-30 |
20090191647 | Antibody Pair Screening Methods - The invention provides methods for identifying antibody preparations that can form a pair of antibodies that optimally detect a target antigen, for example, in a sandwich immunoassay. These methods provide high affinity and epitope-specific antibodies. | 2009-07-30 |
20090191648 | Method and device to detect the presence of analytes in a sample - Disclosed are methods and apparatus useful for determining the presence or absence of one or more analytes in a liquid sample, such as a biological or environmental sample. In some embodiments, the method can use an indirect competitive immunochromatographic test strip. | 2009-07-30 |
20090191649 | BIOSENSOR AND METHOD OF ASSAYING OBJECT - A biosensor capable of analyzing an object, such as antigen, antibody, DNA or RNA, through detection of magnetic field to thereby allow washout of unbound label molecules to be unnecessary, which biosensor is compact and available at low price, excelling in detection precision. Coils are arranged at an upper part and a lower part of a magnetic sensor using a hall element as a magnetic field detection element. An object and magnetic particles having an antibody capable of specific bonding with the object bound to the surface thereof are introduced in the magnetic sensor having a molecular receptor capable of specific bonding with the object attached to the surface thereof. Therefore, a change in magnetic field by magnetic particles bonded through the molecular receptor to the surface of the magnetic sensor is detected by means of the hall element. At that time, one applied magnetic field is set so that the magnetization intensity of magnetic particles falls within the range from initial magnetic permeability to maximum magnetic permeability while another applied magnetic field is set so that the magnetization intensity of some or all of the magnetic particles becomes saturated, and output signals are compared with each other. Thus, the amount of bonded magnetic particles can be identified. | 2009-07-30 |
20090191650 | ANTIBODY SPECIFIC FOR MUTANT PRESENILIN 1 AND METHOD OF USE THEREOF - The present invention describes the identification, isolation, cloning, and determination of the Alzheimer Related Membrane Protein (ARMP) gene on chromosome 14 and a related gene, E5-1, on chromosome 1. Normal and mutant copies of both genes are presented. Transcripts and products of these genes are useful in detecting and diagnosing Alzheimer's disease, developing therapeutics for treatment of Alzheimer's disease, as well as the isolation and manufacture of the protein and the construction of transgenic animals expressing the mutant genes. | 2009-07-30 |
20090191651 | POSITIONING APPARATUS, EXPOSURE APPARATUS, AND METHOD OF MANUFACTURING DEVICE - A positioning apparatus comprises a detector which detects the mark and outputs a mark signal and a controller. The controller includes a calculating unit which calculates position data of the mark based on the mark signal, a processing unit which calculates a parameter representing a displacement of the object, based on the mark signal and the position data of the mark, and a positioning controller which controls the positioning of the object, based on the position information of the object corrected by using the parameter calculated by said processing unit. The processing unit calculates a feature value, calculates a degree of influence that the feature value exerts on a displacement of the mark, corrects the calculated position data of the mark based on the calculated degree of influence, and statistically calculates the corrected position data of the mark, thereby calculating a parameter representing a displacement of the object. | 2009-07-30 |
20090191652 | Pixel structure and method for manufacturing the same - A pixel structure includes a scan line, a data line, an active element, a first passivation layer, a second passivation layer and a pixel electrode. The data line includes a first data metal segment and a second data metal layer. The active element includes a gate electrode, an insulating layer, a channel layer, a source and a drain. The channel layer is positioned on the insulating layer above the gate electrode. The source and the drain are positioned on the channel layer. The source is coupled to the data line. The first passivation layer and the second passivation layer cover the active element and form a first contact hole to expose a part of the drain. The second passivation layer covers a part edge of the drain. The pixel electrode is disposed across the second passivation layer and coupled to the drain via the first contact hole. | 2009-07-30 |
20090191653 | Transflective liquid crystal display device and method of fabricating the same - An array substrate for a transflective liquid crystal display device includes: a substrate; a gate line and a data line on the substrate, the gate line and the data line crossing each other to define a pixel region including a transmissive area and a reflective area surrounding the transmissive area; a thin film transistor having a gate insulating layer, the thin film transistor connected to the gate line and the data line; a first passivation layer on the thin film transistor, the first passivation layer having a drain contact hole exposing a drain electrode of the thin film transistor and a through hole exposing the substrate in the transmissive area; a reflective plate on the first passivation layer; a second passivation layer on the reflective plate; and a pixel electrode on the second passivation layer, the pixel electrode contacting the substrate in the transmissive area through the through hole and contacting the drain electrode through the drain contact hole. | 2009-07-30 |
20090191654 | METHOD OF MANUFACTURING COLOR FILTER SUBSTRATE AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE - A method of manufacturing a color filter substrate includes forming a plurality of trenches having a predetermined depth by etching a surface of a transparent substrate, disposing a color filter material in the plurality of trenches to form a color filter layer, and forming a transparent electrode on the transparent substrate including the color filter layer therein. | 2009-07-30 |
20090191655 | METHOD OF ETCHING AMORPHOUS SILICON LAYER AND METHOD OF MANUFACTURING LIQUID CRYSTAL DISPLAY USING THE SAME - A method of etching an amorphous silicon layer includes providing a substrate with an amorphous silicon layer formed thereon into an atmospheric pressure plasma etching device, providing a plasma generation gas and etching gas to a plasma generator of the atmospheric pressure plasma etching device and generating an atmospheric pressure plasma gas between two electrodes provided in the plasma generator in which the two electrodes face each other. The method further includes repeatedly passing the substrate through the plasma generator at a predetermined speed, thereby etching the amorphous silicon layer on the substrate by using the atmospheric pressure plasma gas generated from the plasma generator. | 2009-07-30 |
20090191656 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - An in-plane switching liquid crystal display device is designed in such a way that an angle defined by the lengthwise direction of a common electrode and a pixel electrode and a rubbing direction of an alignment layer is set to 10 to 20°, a cell gap d is set to 2.7 μm or smaller, the dielectric anisotropy Δ∈ of a liquid crystal constituting a liquid crystal layer is set to 8 to 20, a white voltage V | 2009-07-30 |
20090191657 | ALL-SILICON RAMAN AMPLIFIERS AND LASERS BASED ON MICRO RING RESONATORS - Methods of manufacturing a lasing device are provided by some embodiments, the methods including: creating a silicon micro ring with a predetermined radius and a predetermined first cross-sectional dimension; creating a silicon waveguide with a predetermined second cross-sectional dimension, the silicon waveguide spaced from the silicon micro ring by a predetermined distance; and wherein the predetermined distance, the predetermined radius, the predetermined first cross-sectional dimension, and the predetermined second cross-sectional dimension are determined so that at least one first whispering gallery mode resonant frequency of the silicon micro ring and at least one second whispering gallery mode resonant frequency of the silicon micro ring are separated by an optical phonon frequency of silicon. | 2009-07-30 |
20090191658 | SEMICONDUCTOR LIGHT EMITTING DEVICE WITH LATERAL CURRENT INJECTION IN THE LIGHT EMITTING REGION - A semiconductor light emitting device includes an active region, an n-type region, and a p-type region comprising a portion that extends into the active region. The active region may include multiple quantum wells separated by barrier layers, and the p-type extension penetrates at least one of the quantum well layers. The extensions of the p-type region into the active region may provide uniform filling of carriers in the individual quantum wells of the active region by providing direct current paths into individual quantum wells. Such uniform filling may improve the operating efficiency at high current density by reducing the carrier density in the quantum wells closest to the bulk p-type region, thereby reducing the number of carriers lost to nonradiative recombination. | 2009-07-30 |
20090191659 | SINGLE-CRYSTAL NITRIDE-BASED SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURING HIGH-QUALITY NITRIDE-BASED LIGHT EMITTING DEVICE BY USING THE SAME - A nitride-based light emitting device is manufactured by using a single-crystal nitride-based semiconductor substrate. A seed material layer is deposited on a first substrate where organic residues including a natural oxide layer are removed from an upper surface of the first substrate. A multifunctional substrate is grown from the seed material layer. The single-crystal nitride-based semiconductor layer including a nitride-based buffer layer is formed on the multifunctional substrate. The seed material layer primarily assists the growth of the multifunctional substrate, which is essentially required for the growth of the single-crystal nitride-based semiconductor substrate. The multifunctional substrate is prepared in the form of a single-crystal layer or a poly-crystal layer having a hexagonal crystalline structure. The light emitting device employing the single-crystal nitride-based semiconductor substrate is used as a next-generation white light source having high capacity, large area, high brightness and high performance. | 2009-07-30 |
20090191660 | Method for manufacturing a sensor device - A motion sensor in the form of an angular rate sensor and a method of making a sensor are provided and includes a support substrate and a silicon sensing ring supported by the substrate and having a flexive resonance. Drive electrodes apply electrostatic force on the ring to cause the ring to resonate. Sensing electrodes sense a change in capacitance indicative of vibration modes of resonance of the ring so as to sense motion. A plurality of silicon support rings connect the substrate to the ring. The support rings are located at an angle to substantially match a modulus of elasticity of the silicon, such as about 22.5 degrees and 67.5 degrees, with respect to the crystalline orientation of the silicon. | 2009-07-30 |
20090191661 | PLACING A MEMS PART ON AN APPLICATION PLATFORM USING A GUIDE MASK - A method for fabricating a micro-electro-mechanical system (MEMS) device. The method comprises placing a guiding mask on an application platform, the guiding mask including an opening that defines the position of a MEMS part to be placed on the application platform. The method further comprises placing the MEMS part into the opening of the guiding mask on the application platform, and removing the guiding mask from the application platform after the MEMS part is bonded to the application platform. | 2009-07-30 |
20090191662 | IMAGE SENSOR APPLIED WITH DEVICE ISOLATION TECHNIQUE FOR REDUCING DARK SIGNALS AND FABRICATION METHOD THEREOF - The present invention relates to an image sensor applied with a device isolation technique for reducing dark signals and a fabrication method thereof. The image sensor includes: a logic unit; and a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each other by a field ion-implantation region formed under a surface of a substrate and an insulation layer formed on the surface of the substrate. | 2009-07-30 |
20090191663 | Method for producing a photovoltaic module - For producing a photovoltaic module ( | 2009-07-30 |
20090191664 | Apparatus for Improved Power Distribution in Wirebond Semiconductor Packages - A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting plate. | 2009-07-30 |
20090191665 | Electronic Device and Method of Manufacturing Same - This application relates to a method of manufacturing an electronic device comprising placing a first chip on a carrier; applying an insulating layer over the first chip and the carrier; applying a metal ions containing solution to the insulating layer for producing a first metal layer of a first thickness; and producing a second metal layer of a second thickness on the insulating layer wherein at least one of the first metal layer and the second metal layer comprises at least a portion that is laterally spaced apart from the respective other metal layer. | 2009-07-30 |
20090191666 | METHOD OF MANUFACTURING STACKED-TYPE SEMICONDUCTOR DEVICE - A method of manufacturing a stacked-type semiconductor device, including the steps of: forming dividing grooves, having a depth corresponding to a finished thickness for a plurality of first chips formed on the face side of a wafer, on the face side of the wafer along planned dividing lines; stacking existing second chips on the first chips; covering the face-side surfaces of the second chips with a protective member; and grinding the back side of the wafer until the dividing grooves are exposed and the first chips are thinned to the finished thickness, to obtain semiconductor devices of a two-layer structure. | 2009-07-30 |
20090191667 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured. | 2009-07-30 |
20090191668 | METHOD FOR MANUFACTURING IC TAG INLET - An IC tag inlet ( | 2009-07-30 |
20090191669 | METHOD OF ENCAPSULATING AN ELECTRONIC COMPONENT - A procedure of packaging an electronic component is provided, comprising the following steps: step A for mount at which a conductor and a chip are temporarily mounted on a carrier removable, and next step B for encapsulation at which the conductor and the chip are encapsulated with colloid and mounted and then removed from the carrier so that the chipset after modeled without any substrate may be mounted for decreasing the costs of substrate use and design and the probability of damage of the substrate an chip due to the thermal expansion and increasing the yield factor of a finished product. | 2009-07-30 |
20090191670 | SILICON THIN FILM TRANSISTORS, SYSTEMS, AND METHODS OF MAKING SAME - Systems and methods of fabricating silicon-based thin film transistors (TFTs) on flexible substrates. The systems and methods incorporate and combine deposition processes such as chemical vapor deposition and plasma-enhance vapor deposition, printing, coating, and other deposition processes, with laser annealing, etching techniques, and laser doping, all performed at low temperatures such that the precision, resolution, and registration is achieved to produce a high performing transistor. Such TFTs can be used in applications such as displays, packaging, labeling, and the like. | 2009-07-30 |
20090191671 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHODS FOR THEM - The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film. On this account, on fabricating the semiconductor device having a high-performance integration system by forming the non-singlecrystalline Si semiconductor element and the singlecrystalline Si semiconductor element on the large insulating substrate, the process for making the singlecrystalline Si is simplified. Further, the foregoing arrangement provides a semiconductor substrate and a fabrication method thereof, which ensures device isolation of the minute singlecrystalline Si semiconductor element without highly-accurate photolithography, when the singlecrystalline Si semiconductor element is transferred onto the large insulating substrate. | 2009-07-30 |
20090191672 | Method for production of thin-film semiconductor device - Disclosed herein is a method for production of a thin-film semiconductor device which includes, a first step to form a gate electrode on a substrate, a second step to form a gate insulating film of silicon oxynitride on the substrate in such a way as to cover the gate electrode, a third step to form a semiconductor thin film on the gate insulating film, and a fourth step to perform heat treatment in an oxygen-containing oxidizing atmosphere for modification through oxygen binding with oxygen-deficient parts in the silicon oxynitride film constituting the gate insulating film. | 2009-07-30 |
20090191673 | Method of manufacturing thin film transistor - A thin film transistor (TFT) and a method of manufacturing the same are provided. The TFT includes a transparent substrate, an insulating layer on a region of the transparent substrate, a monocrystalline silicon layer, which includes source, drain, and channel regions, on the insulating layer and a gate insulating film and a gate electrode on the channel region of the monocrystalline silicon layer. | 2009-07-30 |
20090191674 | AIGaN/GaN HIGH ELECTRON MOBILITY TRANSISTOR DEVICES - The present invention recites a new method for manufacturing Group III-N field-effect devices, such as HEMT, MOSHFET, MISHFET devices or MESFET devices, grown by Metal-Organic Vapor Phase Expitaxy, with higher performance (power), by covering the surface with a thin SiN layer on the top AlGaN layer, in the reactor where the growth takes place at high temperature, prior cooling down the structure and loading the sample out of the reactor, as well as a method to produce some HEMT transistors on those heterostructures, by depositing the contact on the surface without any removal of the SiN layer by MOCVD. The present invention recites also a device. | 2009-07-30 |
20090191675 | Method for Forming CMOS Transistors Having FUSI Gate Electrodes and Targeted Work Functions - A method for making CMOS transistors that includes forming a NMOS transistor and a PMOS transistor having an undoped polysilicon gate electrode and a hardmask. The method also includes forming a layer of insulating material and then removing the hardmasks and a portion of the layer of insulating material. A layer of silicidation metal is formed and a first silicide anneal changes the undoped polysilicon gate electrodes into partially silicided gate electrodes. Dopants of a first type and a second type are implanted into the partially silicided gate electrode of the PMOS and NMOS transistors and a second silicide anneal is performed to change the doped partially silicided gate electrodes into fully silicided gate electrodes. | 2009-07-30 |
20090191676 | FLASH MEMORY HAVING A HIGH-PERMITTIVITY TUNNEL DIELECTRIC - A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages. The flash memory cell has a substrate with source/drain regions. The high-k tunneling dielectric is formed above the substrate. The high-k tunneling dielectric can be deposited using evaporation techniques or atomic layer deposition techniques. The floating gate is formed on top of the high-k dielectric layer with an oxide gate insulator on top of that. A polysilicon control gate is formed on the top gate insulator. | 2009-07-30 |
20090191677 | MEMORY ARRAY WITH SURROUNDING GATE ACCESS TRANSISTORS AND CAPACITORS WITH GLOBAL AND STAGGERED LOCAL BIT LINES - A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration. | 2009-07-30 |
20090191678 | Method of Forming a Shielded Gate Field Effect Transistor - A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion. A two-pass angled implant of dopants of the first conductivity type is carried out to form a silicon region of first conductivity type along sidewalls of the lower trench portion, while the protective material blocks the implant dopants from entering the sidewalls of the upper trench portion and the mesa region adjacent the upper trench portion. | 2009-07-30 |
20090191679 | LOCAL STRESS ENGINEERING FOR CMOS DEVICES - A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A second dielectric layer is formed over the PFET gate and the NFET gate, and lithographically patterned to expose the NFET area, while covering the PFET area. Exposed NFET active area is etched and refilled with a silicon-carbon alloy, which applies a uniaxial tensile stress to an NFET channel. Dopants may be introduced into the SiGe and silicon-carbon regions by in-situ doping or by ion implantation. | 2009-07-30 |
20090191680 | DUAL-GATE MEMORY DEVICE WITH CHANNEL CRYSTALLIZATION FOR MULTIPLE LEVELS PER CELL (MLC) - A method and a dual-gate memory device having a memory transistor and an access transistor are provided to allow multiple bits to be stored in the dual-gate memory device. The memory transistor and the access transistor each have a channel region formed in a mobility enhanced material crystallized from an amorphous semiconductor material. The amorphous semiconductor material may include, for example, silicon. Mobility enhancement may be achieved by: (a) Excimer laser annealing; (b) lateral crystallization; (c) metal-induced lateral crystallization; (d) a combination of laser annealing and metal-induced laterally crystallization steps; or (e) solid-phase, epitaxially growth. | 2009-07-30 |
20090191681 | NOR-TYPE FLASH MEMORY DEVICE WITH TWIN BIT CELL STRUCTURE AND METHOD OF FABRICATING THE SAME - A NOR-type flash memory device comprises a plurality twin-bit memory cells arranged so that pairs of adjacent memory cells share a source/drain region and groups of four adjacent memory cells are electrically connected to each other by a single bitline contact. | 2009-07-30 |
20090191682 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions. | 2009-07-30 |
20090191683 | METHOD OF FORMING TRANSISTOR HAVING CHANNEL REGION AT SIDEWALL OF CHANNEL PORTION HOLE - According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of the semiconductor substrate. Two channel portion holes are formed to extend downward from a main surface of the semiconductor substrate to be in contact with the channel region. Gate patterns fill the channel portion holes and cross the active region. The resulting transistor is capable of ensuring a constant threshold voltage without being affected by an alignment state of the channel portion hole and the gate pattern. | 2009-07-30 |
20090191684 | Novel Approach to Reduce the Contact Resistance - A method for fabricating a semiconductor device is disclosed. First, a semiconductor substrate having a doped region(s) is provided. Thereafter, a pre-amorphous implantation process and neutral (or non-neutral) species implantation process is performed over the doped region(s) of the semiconductor substrate. Subsequently, a silicide is formed in the doped region(s). By conducting a pre-amorphous implantation combined with a neutral species implantation, the present invention reduces the contact resistance, such as at the contact area silicide and source/drain substrate interface. | 2009-07-30 |
20090191685 | METHOD FOR FORMING CAPACITOR IN DYNAMIC RANDOM ACCESS MEMORY - A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor; depositing an etching stop layer on the first plug and the interlayer dielectric layer; depositing a first insulating layer on the etching stop layer; forming at least a second plug on the first insulating layer and the etching stop layer so that the second plug is connected to the first plug; depositing a second insulating layer on the first insulating layer and the second plug; forming at least a mold cavity in the second insulating layer so that the aperture of the mold cavity is larger than the diameter of the second plug and there is a deviation between the mold cavity and the second plug; removing the first insulating layer in the mold cavity until the etching stop layer; depositing a first electrode layer to cover the second insulating layer, a sidewall portion of the mold cavity, the second plug and the etching stop layer; removing the second insulating layer so that the first electrode layer forms a single open-ended cavity; and depositing a dielectric layer and a second electrode layer. | 2009-07-30 |
20090191686 | Method for Preparing Doped Polysilicon Conductor and Method for Preparing Trench Capacitor Structure Using the Same - A method for preparing a doped polysilicon conductor according to this aspect of the present invention comprises the steps of (a) placing a substrate in a reaction chamber, (b) performing a deposition process to form a polysilicon layer on the substrate, (c) performing a grain growth process to form a plurality of polysilicon grains on the polysilicon layer, and (d) performing a dopant diffusion process to diffuse conductive dopants into the polysilicon layer via the polysilicon grains to form the doped polysilicon conductor. | 2009-07-30 |
20090191687 | METHOD OF FILLING A TRENCH AND METHOD OF FORMING AN ISOLATING LAYER STRUCTURE USING THE SAME - A method of filling a trench in a substrate ensures that a void or seam is not left in the material occupying the trench. First, a preliminary insulating layer is formed so as to extend contiguously along the bottom and sides of the trench and along an upper surface of the substrate. Impurities are then implanted into a portion of the preliminary insulating layer adjacent the top of the first trench to form a first insulating layer having a doped region and an undoped region. The doped region is removed to form a first insulating layer pattern at the bottom and sides of the first trench, and which first insulating layer pattern defines a second trench. The second trench is then filled with insulating material. | 2009-07-30 |
20090191688 | Shallow Trench Isolation Process Using Two Liners - A method for making STI structure includes etching a STI trench through a nitride layer, through an oxide layer, and into a silicon layer. The method also includes forming a sacrificial liner, pulling-back the nitride layer, and removing a remaining portion of the sacrificial liner. Furthermore, the method includes forming a STI liner and forming a STI fill coupled to the STI liner. | 2009-07-30 |
20090191689 | Method of Arranging Dies in a Wafer for Easy Inkless Partial Wafer Process - In a method and system for fabricating a full wafer ( | 2009-07-30 |
20090191690 | Increasing Die Strength by Etching During or After Dicing - A semiconductor wafer having an active layer is mounted on a carrier with the active layer away from the carrier and at least partially diced on the carrier from a major surface of the semiconductor wafer. The at least partially diced semiconductor wafer is etched on the carrier from the said major surface with a spontaneous etchant to remove sufficient semiconductor material from a die produced from the at least partially diced semiconductor wafer to improve flexural bend strength of the die by removing at least some defects caused by dicing. | 2009-07-30 |
20090191691 | Method for singulating semiconductor devices - Disclosed is a method for singulating semiconductor devices. The substrate has a plurality of scribe lines between the substrate units. A protecting film is provided having a patterned adhesive layer formed thereon corresponding to the scribe lines. The protecting film is attached and aligned to the substrate in a manner that the patterned adhesive layer adheres to the scribe lines without covering the substrate units. The substrate is cut by a laser beam aimed at the protecting film firstly and cut through the substrate along the peripheries of the scribe lines to singulate the substrate units. Therefore, the residue films of the protecting film on the substrate units can easily be removed. The contaminations of the substrate units by the sputtered particles and the melted protecting film during laser cutting can be eliminated. The shapes of the substrate units can be diverse. | 2009-07-30 |
20090191692 | Wafer processing method - A method of processing a wafer having a plurality of devices which are composed of a laminate consisting of an insulating film and a functional film on the front surface of a substrate, along streets for sectioning the plurality of devices, the method comprising a first blocking groove forming step for forming a first blocking groove for dividing the laminate in a one-side portion in the width direction of a street of the wafer held on a chuck table by moving the chuck table in a first direction in the processing-feed direction while activating a first laser beam application means; and a second blocking groove and dividing groove forming step for forming a second blocking groove which divides the laminate in the other-side portion in the width direction of the street of the wafer which has undergone the first blocking groove forming step by moving the chuck table in a second direction in the processing-feed direction while activating the first laser beam application means and at the same time, forming a dividing groove in the laminate and the substrate along an intermediate portion between the first blocking groove and the second blocking groove formed in the street of the wafer by activating second laser beam application means. | 2009-07-30 |
20090191693 | Wafer processing method - A method of processing a wafer having a plurality of devices which are composed of a laminate consisting of an insulating film and a functional film laminated on the front surface of a substrate, along streets for sectioning the plurality of devices, comprising a first trip blocking groove forming step for activating a first laser beam application means to form a blocking groove for dividing the laminate along a street of the wafer while moving the chuck table in a first direction in the processing-feed direction; a second trip blocking groove and dividing groove forming step for activating the first laser beam application means to form a blocking groove for dividing the laminate along a street next to the street which has undergone the first trip blocking groove forming step and also to form a dividing groove along the blocking groove formed by the first trip blocking groove forming step while moving the chuck table in a second direction in the processing-feed direction; and a first trip blocking groove and dividing groove forming step for activating the first laser beam application means to form a blocking groove for dividing the laminate along a street next to the street which has undergone the second trip blocking groove and dividing groove forming step and also, to form a dividing groove along the blocking groove formed by the second trip blocking groove and dividing groove forming step while moving the chuck table in a first direction in the processing-feed direction. | 2009-07-30 |
20090191694 | MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE - A surface of a single crystal semiconductor substrate is irradiated with ions to form a damaged region, an insulating layer is formed over the surface of the single crystal semiconductor substrate, and a surface of a substrate having an insulating surface is made to be in contact with a surface of the insulating layer to bond the substrate having an insulating surface to the single crystal semiconductor substrate. Then, the single crystal semiconductor substrate is separated at the damaged region by performing heat treatment to form a single crystal semiconductor layer over the substrate having an insulating surface, and the single crystal semiconductor layer is patterned to form a plurality of island-shaped semiconductor layers. One of the island-shaped semiconductor layers is irradiated with a laser beam which is shaped to entirely cover the island-shaped semiconductor layer. | 2009-07-30 |
20090191695 | Method of manufacturing nitride semiconductor substrate - A method of manufacturing a nitride semiconductor substrate according to example embodiments may include forming a buffer layer on a (100) plane of a silicon (Si) substrate. The buffer layer may have a hexagonal crystal system and a (1010) plane. A nitride semiconductor layer may be epitaxially grown on the buffer layer. The nitride semiconductor layer may have a (1010) plane. Accordingly, because example embodiments enable the use of a relatively inexpensive Si substrate, a more economical nitride semiconductor substrate having a relatively large diameter may be achieved. | 2009-07-30 |
20090191696 | METHOD FOR INCREASING THE PENETRATION DEPTH OF MATERIAL INFUSION IN A SUBSTRATE USING A GAS CLUSTER ION BEAM - A method for infusing material below the surface of a substrate is described. The method comprises modifying a surface condition of a surface on a substrate to produce a modified surface layer, and thereafter, infusing material into the modified surface in the substrate by exposing the substrate to a gas cluster ion beam (GCIB) comprising the material. | 2009-07-30 |
20090191697 | METHOD FOR MANUFACTURING A NONVOLATILE MEMORY DEVICE - In a method for manufacturing a nonvolatile memory device, an etch mask layer formed on a dielectric layer to define contact holes in the dielectric layer is slope-etched to form an etch mask pattern having an opening wider at the upper end thereof than the lower end thereof. Thus, the contact holes are defined in the dielectric layer to have a finer size than the upper end of the opening of the etch mask pattern. The method for manufacturing a nonvolatile memory device includes forming an etch mask pattern on a dielectric layer such that a width of a lower end of each opening defined in the etch mask pattern is less than a width of an upper end thereof; and defining contact holes by removing portions of the dielectric layer using the etch mask pattern. | 2009-07-30 |
20090191698 | TFT ARRAY PANEL AND FABRICATING METHOD THEREOF - Disclosed is display part such as a TFT array panel comprising an aluminum layer, and a molybdenum layer formed on the aluminum layer. The thickness of the molybdenum layer may be about 10% to about 40% the thickness of the aluminum layer. As a result, a top surface of the aluminum layer may have a width about equal to a bottom surface of the molybdenum layer. | 2009-07-30 |
20090191699 | METHODS FOR FORMING SILICIDE CONDUCTORS USING SUBSTRATE MASKING - A plurality of spaced-apart conductor structures is formed on a semiconductor substrate, each of the conductor structures including a conductive layer. Insulating spacers are formed on sidewalls of the conductor structures. An interlayer-insulating film that fills gaps between adjacent ones of the insulating spacers is formed. Portions of the interlayer-insulating layer are removed to expose upper surfaces of the conductive layers. Respective epilayers are grown on the respective exposed upper surfaces of the conductive layers and respective metal silicide layers are formed from the respective epilayers. | 2009-07-30 |
20090191700 | Semiconductor device with integrated flash memory and peripheral circuit and its manufacture method - A non-volatile semiconductor memory device includes: a nonvolatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of the gate electrode; a peripheral circuit area including single-layer gate electrodes made of the same layer as the control gate; and a first border area including: a first isolation region formed in the semiconductor substrate for isolating the non-volatile memory area and peripheral circuit area; a first conductive pattern including a portion made of the same layer as the control gate and formed above the isolation region; and a first redundant insulating side wall made of the same layer as the first insulating side wall and formed on the side wall of the first conductive pattern on the side of the non-volatile memory area. | 2009-07-30 |
20090191701 | MICROELECTRONIC DEVICES AND METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC DEVICES - Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material. | 2009-07-30 |
20090191702 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad. | 2009-07-30 |
20090191703 | PROCESS WITH SATURATION AT LOW ETCH AMOUNT FOR HIGH CONTACT BOTTOM CLEANING EFFICIENCY FOR CHEMICAL DRY CLEAN PROCESS - A method for removing oxides from the bottom surface of a contact hole is provided. The method provides efficient cleaning of the bottom surface without distortion of the contact hole upper and sidewall surfaces. | 2009-07-30 |
20090191704 | Formation of Through-Wafer Electrical Interconnections and Other Structures Using a Thin Dielectric Membrane - Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes. | 2009-07-30 |
20090191705 | Semiconductor Contact Barrier - System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer. | 2009-07-30 |
20090191706 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, including forming a dielectric film above a substrate; forming a metal containing film above the dielectric film; forming at least one carbon containing film of a silicon carbon containing film containing silicon and carbon and a nitrogen carbon containing film containing nitrogen and carbon above the metal containing film; etching the carbon containing film selectively; etching the metal containing film selectively to transfer an opening of the carbon containing film formed by etching; and etching the dielectric film using the carbon containing film and the metal containing film as masks in a state in which a surface of the carbon containing film other than the opening is exposed. | 2009-07-30 |
20090191707 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - To provide a technique capable of improving the reliability of a semiconductor element and its product yield by reducing the variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate | 2009-07-30 |
20090191708 | METHOD FOR FORMING A THROUGH SILICON VIA LAYOUT - A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields. | 2009-07-30 |
20090191709 | Method for Manufacturing a Semiconductor Device - A polymer for immersion lithography comprising a repeating unit represented by Formula 1 and a photoresist composition containing the same. A photoresist film formed by the photoresist composition of the invention is highly resistant to dissolution, a photoacid generator in an aqueous solution for immersion lithography, thereby preventing contamination of an exposure lens and deformation of the photoresist pattern by exposure. | 2009-07-30 |
20090191710 | CMP method for improved oxide removal rate - The invention provides a method for the chemical-mechanical polishing of a substrate with a chemical-mechanical polishing composition that comprises an abrasive, a halide salt, water and a polishing pad. | 2009-07-30 |
20090191711 | HARDMASK OPEN PROCESS WITH ENHANCED CD SPACE SHRINK AND REDUCTION - Methods for forming an ultra thin structure. The method includes a polymer deposition and etching process. In one embodiment, the methods may be utilized to form fabricate submicron structure having a critical dimension less than 30 nm and beyond. The method further includes a multiple etching processes. The processes may be varied to meet different process requirements. In one embodiment, the process gently etches the substrate while shrinking critical dimension of the structures formed within the substrate. The dimension of the structures may be shank by coating a photoresist like polymer to sidewalls of the formed structure, but substantially no polymer accumulation on the bottom surface of the formed structure on the substrate. The embodiments described herein also provide high selectivity in between each layers formed on the substrate during the fabricating process and preserving a good control of profile formed within the structure. | 2009-07-30 |
20090191712 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In one aspect of the present invention, a method of manufacturing a semiconductor device may include forming a first film on an amorphous silicon layer to be patterned, the first film and the amorphous film having a line-and-space ratio of approximately 3:1, sliming down, after processing the first film, a line portion of the pattern from both longitudinal sides of the line portion until the width of the line portion is reduced to approximately one third, reforming a part of the amorphous silicon layer where the first film is not provided such that reformed part has different etching ratio, and removing the first film and the amorphous silicon layer other than reformed part. | 2009-07-30 |
20090191713 | METHOD OF FORMING FINE PATTERN USING BLOCK COPOLYMER - Provided is a method of forming a fine pattern using a block copolymer. The method comprises forming a coating layer including a block copolymer having a plurality of repeating units on a substrate. A mold is provided having a first pattern comprising a plurality of ridges and valleys. The first pattern is transferred from the mold into the coating layer. Then, a self-assembly structure is formed comprising a plurality of polymer blocks aligned in a direction guided by the ridges and valleys of the mold thereby rearranging the repeating units of the block copolymer within the coating layer by phase separation while the coating layer is located within the valleys of the mold. A portion of the polymer blocks are removed from among the plurality of polymer blocks and a self-assembly fine pattern of remaining polymer blocks is formed. | 2009-07-30 |
20090191714 | Method of removing oxides - The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching process is performed. A first thermal treatment process is then carried out. Finally, a second thermal treatment process is carried out, and a reaction temperature of the second thermal treatment process is higher than a reaction temperature of the first thermal treatment process. | 2009-07-30 |
20090191715 | Method for etching interlayer dielectric film - In the fine processing of holes and/or trenches by dry-etching an interlayer dielectric film covered with a resist mask formed by ArF-photolithography within a plasma atmosphere, the etching gas used comprises a halogen atom-containing gas (the halogen atom being selected from F, I and/or Br) or a fluorinated carbon atom-containing compound gas in which the ratio of at least one of I and Br is not more than 26% of the total amount of the halogen atoms as expressed in terms of the atomic compositional ratio and the balance of the gas consists of fluorine atoms. Occurrence of striation can be suppressed and a high processing accuracy through etching can be accomplished. | 2009-07-30 |
20090191716 | POLYSILICON LAYER REMOVING METHOD AND STORAGE MEDIUM - A polysilicon layer removing method capable of substantially removing etching residue, while improving the shape of an etching boundary is disclosed. The method for removing the polysilicon layer from a beveled portion of a wafer W through wet etching includes hydrophilizing the polysilicon layer, without removing the polysilicon layer from the beveled portion, and supplying an etchant having the mixture of hydrofluoric acid and nitric acid onto the hydrophilized polysilicon layer of the beveled portion, while the wafer is rotated at revolutions enough for flattening an etching boundary. | 2009-07-30 |
20090191717 | ATOMIC LAYER DEPOSITION APPARATUS - An atomic layer deposition apparatus and an atomic layer deposition method increase productivity. The atomic layer deposition apparatus includes a reaction chamber, a heater for supporting a plurality of semiconductor substrates with a given interval within the reaction chamber and to heat the plurality of semiconductor substrates and a plurality of injectors respectively positioned within the reaction chamber and corresponding to the plurality of semiconductor substrates supported by the heater. The plurality of injectors are individually swept above the plurality of semiconductor substrates to spray reaction gas. | 2009-07-30 |
20090191718 | Substrate processing apparatus, method of manufacturing semiconductor device, and reaction vessel - A method of manufacturing a semiconductor device includes the steps of: conveying a plurality of substrates disposed in a direction perpendicular to a substrate processing surface into a processing chamber provided inside of a reaction tube, with an outer periphery surrounded by a heating device; and processing the substrates by introducing gas to a gas inlet tube provided on a side face of the reaction tube in a region for processing the substrates inside the reaction tube, so as to reach at least an outside of the heating device, and spouting the gas into the processing chamber from a slit-shaped gas spouting port disposed in a form so as to straddle at least a plurality of the substrates in a direction perpendicular to the substrate processing surface. | 2009-07-30 |