31st week of 2009 patent applcation highlights part 17 |
Patent application number | Title | Published |
20090189617 | CONTINUOUS SUBSURFACE HEATER TEMPERATURE MEASUREMENT - A method for assessing one or more temperatures of an electrically powered subsurface heater includes accessing an impedance profile of the electrically powered subsurface heater while the heater is being operated in the subsurface. The impedance profile is analyzed with a frequency domain algorithm to assess one or more temperatures of the heater. | 2009-07-30 |
20090189618 | METHOD, SYSTEM, AND APPARATUS FOR LIQUID MONITORING, ANALYSIS, AND IDENTIFICATION - Embodiments of liquid monitoring, analysis, and identification are described generally herein. Other embodiments may be described and claimed. | 2009-07-30 |
20090189619 | SYSTEMS AND METHODS FOR DETECTING CAPACITOR PROCESS VARIATION - A method for detecting capacitor variation in a device comprises operating an oscillator in the device, the oscillator being an Inductive-Capacitive (LC) oscillator and including an inductor of known value and a capacitor under test, comparing an output of the oscillator to a reference output, and evaluating variation for a plurality of capacitors in the device based on the comparing. | 2009-07-30 |
20090189620 | COMPLIANT MEMBRANE PROBE - A probe test head for a high density pin count integrated circuit, includes: a flexible membrane; an array of conductive structures, each one of the structures including a mechanically compliant probe tip affixed to the membrane, such that an attachment point enables mechanical actuation of the probe tip through a conductive member parallel to the membrane. A method for fabrication and measurement apparatus are provided. | 2009-07-30 |
20090189621 | PROBE DEVICE - A probe device for testing a semiconductor chip includes a substrate and a balun formed on the substrate. The balun includes first and second differential ports and a single-ended port. The probe device includes first and second probe tips respectively coupled to the first and second differential ports. | 2009-07-30 |
20090189622 | Probe For Testing Integrated Circuit Devices - A device for providing electrical contact comprises a first reciprocating conductive body having a first abutting body at one end, a second reciprocating conductive body having a second abutting body at one end and a resilient means biasing the first reciprocating conductive body and the second reciprocating conductive body in opposing directions axially away from each other. The first abutting body is slidably abutting the second abutting body, thereby providing electrical conductivity between the first reciprocating conductive body and the second reciprocating body. In another embodiment, the first reciprocating conductive body, the second reciprocating body and at least one securing means are disposed within one of plurality of through holes of an elastic non-conductive housing body. The elastic non-conductive housing body biases the first reciprocating conductive body and the second reciprocating conductive body in opposing directions axially from each other. | 2009-07-30 |
20090189623 | Differential waveguide probe - A wafer probe comprises a contact conductively interconnected with the wall of a waveguide channel and supported by a substrate that projects from an end of a waveguide channel. | 2009-07-30 |
20090189624 | Interposer and a probe card assembly for electrical die sorting and methods of operating and manufacturing the same - An interposer and a probe card assembly for electrical die sorting is provided. The assembly may include probes electrically contacting pads of dies on a substrate, a first wiring unit including a first wire on and electrically contacting the probes, an interposer unit including interposers on the first wiring unit and electrically contacting the first wire, and a second wiring unit including a second wire on the interposer unit and electrically contacting the interposers. At least one interposer includes a conductive member, a first connection member adjacent to a first end of the conductive member so as to electrically connect the conductive member to the first wire, a second connection member adjacent to a second end of the conductive member so as to electrically connect the conductive member to the second wire, and at least one protrusion member on an external surface of the conductive member between the first and second connection members. | 2009-07-30 |
20090189625 | Method and System for Continuity Testing of Conductive Interconnects - In accordance with one embodiment of the present disclosure, a method for testing electronics includes forming at least a portion of an electrical circuit by electrically coupling a plurality of indicators in series with respect to each other such that each indicator is operable to substantially simultaneously indicate an electrical characteristic of a respective one or more of a plurality of conductive interconnects. Respective ones of the plurality of conductive interconnects are coupled to a respective pair of a plurality of reception nodes of the electrical circuit such that each conductive interconnect is coupled to the electrical circuit in parallel with a respective one of a plurality of indicators. The method also includes determining, based at least in part on the electrical characteristics indicated by at least three of the plurality of indicators, whether two of the plurality of conductive interconnects are electrically shorted together. | 2009-07-30 |
20090189626 | APPARATUS AND METHOD FOR DETECTING ELECTRONIC DEVICE TESTING SOCKET - An apparatus for detecting an electronic device testing socket including a testing base, a detecting circuit board, a depth gauge, and a conductive pressing block is provided. The detecting circuit board disposed on the testing base has a carrying surface for carrying an electronic device testing socket. The electronic device testing socket includes a plurality of pin units, and each of the pin units includes an S-shaped pin and a pair of elastic rods accommodated within recesses thereof. The depth gauge disposed on the testing base presses against a top surface of the conductive pressing block, and presses with a bottom surface thereof against the electronic device testing socket. The depth gauge is adapted to adjust a distance between the top surface of the conductive pressing block and the carrying surface. The detecting circuit board is electrically connected to the pin units for detecting the status of the pin units. | 2009-07-30 |
20090189627 | Methods And Apparatus For Planar Extension Of Electrical Conductors Beyond The Edges Of A Substrate - Concurrent electrical access to the pads of integrated circuits on a wafer is provided by an edge-extended wafer translator that carries signals from one or more pads on one or more integrated circuits to contact terminals on the inquiry-side of the edge-extended wafer translator, including portions of the inquiry-side that are superjacent the wafer when the wafer and the edge-extended wafer translator are in a removably attached state, and portions of the inquiry side that reside outside a region defined by the intersection of the wafer and the edge-extended wafer translator. In a further aspect of the present invention, access to the pads of integrated circuits on a wafer is additionally provided by contact terminals in a second inquiry area located on the wafer-side of the edge-extended wafer translator in a region thereof bounded by its outer circumference and the circumference of the attached wafer. | 2009-07-30 |
20090189628 | Reworkable bonding pad layout and debug method thereof - The reworkable bonding pad layout includes a first point, a second point, a reworkable bonding pad, a first leading wire, and a second leading wire. There is a debug position defined between the first point and the second point. The reworkable bonding pad is formed at the debug position. The first leading wire may connect the reworkable bonding pad and the first point. The second leading wire may connect the reworkable bonding pad and the second point. The reworkable bonding pad is cut into a first debug area connecting with the first leading wire, and a second debug area connecting with the second leading wire. | 2009-07-30 |
20090189629 | SEMICONDUCTOR WAFER HAVING A MULTITUDE OF SENSOR ELEMENTS AND METHOD FOR MEASURING SENSOR ELEMENTS ON A SEMICONDUCTOR WAFER - In the measurement of sensor elements in a wafer composite, whereby non-electric stimuli are to be applied to the sensor elements, a semiconductor wafer having a multitude of sensor elements, each sensor element having a voltage supply connection, a grounded connection, and at least one sensor signal output, is configured such that a bus system is integrated in the semiconductor wafer, to which bus system at least the grounded connections of the sensor elements are connected and via which a supply voltage may be applied to the sensor elements, and that each sensor element is equipped with at least one controllable switching element for selecting the sensor element, so that only a selected sensor element supplies a sensor signal to a diagnosis device. | 2009-07-30 |
20090189630 | ANGULAR SPECTRUM TAILORING IN SOLID IMMERSION MICROSCOPY FOR CIRCUIT ANALYSIS - A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively. | 2009-07-30 |
20090189631 | MOVEMENT APPARATUS AND ELECTRONIC DEVICE TEST APPARATUS - An air cylinder raising and lowering a pickup head for holding an IC device in an electronic device test apparatus, the air cylinder includes a cylinder tube; a piston; a first hollow chamber formed below the piston; a second hollow chamber formed above the piston and being larger than the first hollow chamber in terms of a pressure receiving area of the piston; and a rod with one end coupled with the piston and the other end coupled with the pickup head. The first hollow chamber is connected to the air feed device via a first feed system in which the air feed is secured even if the electric power supply of the electronic device test apparatus is cut off, and the second hollow chamber is connected to the air feed device via a second feed system having a shutoff valve. | 2009-07-30 |
20090189632 | Test board used for a reliability test and reliability test method - To conduct a reliability test for a tape automated bonding (TAB) package under a state being close to a mounting state to a product, the TAB package ( | 2009-07-30 |
20090189633 | SUPERCONDUCTIVE CROSSBAR SWITCH - A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less. | 2009-07-30 |
20090189634 | SINGLE EVENT TRANSIENT MITIGATION AND MEASUREMENT IN INTEGRATED CIRCUITS - A method for single event transient filtering in an integrated circuit device is described. The device comprises three sequential elements, each having a data input and a data output with each of the three data outputs coupled to one of three inputs of a voting gate. The method comprises generating first and second nominally equivalent logic signals in first and second SET domains, converting the first and second nominally equivalent logic signals into first, second and third nominally equivalent data channels, and transmitting the first, second and third nominally equivalent data channels to the data inputs of the first, second and third sequential elements. | 2009-07-30 |
20090189635 | METHOD AND APPARATUS FOR IMPLEMENTING REDUCED COUPLING EFFECTS ON SINGLE ENDED CLOCKS - A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2). | 2009-07-30 |
20090189636 | CIRCUIT HAVING LOGIC STATE RETENTION DURING POWER-DOWN AND METHOD THEREFOR - A storage circuit has an input for receiving and storing data, a first power terminal coupled to a first conductor for receiving a first power supply voltage, and a second power terminal coupled to a second conductor. A power gate device has a first terminal coupled to the second conductor, a control terminal for receiving a bias voltage in response to a control signal, and a second terminal coupled to a terminal for receiving a second power supply voltage. A shorting device selectively electrically short circuits the first terminal of the power gate device to the control terminal of the power gate device in response to the control signal, thereby converting the power gate device from a transistor into a diode-connected device. The shorting device is smaller in size than the power gate device. | 2009-07-30 |
20090189637 | Machine for programming on-board chipsets - The present invention discloses a machine for programming on-board chipsets, wherein the on-board chipsets means that some chipsets are mounted on a circuit board, and the circuit board has a plurality of input pads electrically connected to each chipset individually. The machine comprises a platform, a number of programming modules and an IC programming burner in which the platform faces a surface of the circuit board having the input pads, the programming modules disposed movably on the platform separately extends a number of output pins outwardly so that for connecting electrically an input pad as contacting the input pad, and the IC programming burner electrically connected to each of the programming modules separately distributes a set of programming codes into each programming module when the output pins electrically connect to the input pads. | 2009-07-30 |
20090189638 | LEVEL SHIFTER CIRCUIT - A level shifter comprises a voltage converting circuit, a voltage pull-up circuit, and a control signal generating circuit. The voltage converting circuit is configured to receive an input signal of a first voltage level and to output an output signal of a second voltage level. The voltage pull-up circuit is coupled to the voltage converting circuit and configured to expeditiously pull up a voltage of an output node of the level shifter to the second voltage level in response to a control signal. The control signal generating circuit is configured to receive the input signal and to provide the control signal to the voltage pull-up circuit. The control signal generating circuit includes three transistors. | 2009-07-30 |
20090189639 | CIRCUITS AND METHODS FOR COMMUNICATING DATA BETWEEN DOMAINS DURING VOLTAGE AND FREQUENCY SHIFTING - When communicating data between different voltage and frequency domains, for example chiplets, in an integrated circuit, the data signals can be formatted to compensate for propagation delays and different operating frequencies between the domains, and the signaling voltage level of the formatted data signals can then be changed from the operating voltage of the transmitting domain to the operating voltage of the receiving domain so that the formatted and changed data signals can be transmitted. As such, voltage crossings are combined with frequency crossings, which can have the effect of hiding the voltage shifting within the propagation delays. | 2009-07-30 |
20090189640 | Semiconductor Device - According to an aspect of the present invention, there is provided a semiconductor device including: a first circuit portion including: a first circuit that is connected between a first high-side power line and a low-side power line and that outputs a second signal based on a first signal input thereto; and a second circuit portion including: a first transistor that is connected between a second high-side power line and a node and that has a normally-on characteristic; a second circuit that is connected between the node and the low-side power line and that outputs a third signal based on the second signal input thereto. | 2009-07-30 |
20090189641 | INTEGRATED CIRCUIT DEVICE AND LAYOUT DESIGN METHOD THEREFOR - An integrated circuit device has multiple first circuit elements arranged in a first area. A signal distribution circuit that has multiple drive circuits is connected in the form of a tree structure and that distributes a common signal that is input to the starting point of said tree structure to each of the multiple first circuit elements through the same number of levels of drive circuits. At least some of the drive circuits of the tree structure are arranged one each in each of multiple second areas into which the first area is divided to include approximately the same number of the first circuit elements, and the common signal is supplied to the first circuit elements included in the second area where they are arranged. | 2009-07-30 |
20090189642 | Nanowire Crossbar Implementations of logic Gates using configurable, tunneling resistor junctions - Various embodiments of the present invention are directed to nanowire crossbars that use configurable, tunneling resistor junctions to electronically implement logic gates. In one embodiment of the present invention, a method for implementing a logic gate comprises: providing a first layer of approximately parallel nanowires; interconnecting the first layer of approximately parallel nanowires with a second layer of approximately parallel nanowires through configurable, tunneling resistor junctions; selecting nanowires from among the first and second layer of nanowires to carry input and output electrical signals representing logical values; applying electrical signals representing input logical values to the input nanowires; and detecting an electrical signal representing an output logical value on the output nanowires. | 2009-07-30 |
20090189643 | CONSTANT VOLTAGE GENERATING DEVICE - A constant voltage generator device provides a first and a second transistor having their main current path coupled serially via a common terminal for providing a constant output voltage at the common terminal of said transistors. The device provides one or more potential dividers having a plurality of serially connected resistive elements. A first voltage is obtained from a first combination of resistive elements of the potential divider and a second voltage obtained from a second combination of resistive elements of the potential divider. The first and the second voltages are supplied to the first and the second voltage at the control terminals of the first and the second transistors, respectively. | 2009-07-30 |
20090189644 | Short pulse rejection circuit and method thereof - A short pulse rejection circuit may include an edge detector, a filter circuit, a comparison circuit, and a gating circuit. The edge detector may delay an input signal to generate a delayed input signal, and detect an edge of the input signal to generate an edge detection signal. The filter circuit may perform a low pass filtering on the edge detection signal to generate a first signal. The comparison circuit may compare the first signal with a reference voltage. The gating circuit may gate the delayed input signal based on an output signal of the comparison circuit. Therefore, the short pulse rejection circuit may have a sufficient setup/hold time margin of a flip-flop, and may sample an input signal even when a state of the input signal does not change during an initial operation. | 2009-07-30 |
20090189645 | FILTER AND FILTERING METHOD - A filter and a filtering method are provided. The filter includes a first compare voltage generation unit, a second compare voltage generation unit, a comparator and a first inverter. The first compare voltage generation unit generates a first compare voltage according to an input signal. The second compare voltage generation unit generates a second compare voltage. When the first compare voltage is not over the first reference voltage, the second compare voltage equals the first reference voltage. When the first compare voltage is over the first reference voltage, the second compare voltage equals the second reference voltage. The first reference voltage and the second reference voltage depend on a minimum pulse width. The comparator outputs a filtered signal according to the first compare voltage and the second compare voltage. The first inverter inverts a filtered signal to an output signal. | 2009-07-30 |
20090189646 | Method and Apparatus for Detection and Accommodation of Hot-Plug Conditions - An apparatus, method, and discriminator circuit are provided for filtering false signals. A discriminator circuit receives a low-state signal via an input and, responsive to receiving the low-state signal, the discriminator circuit compares the low-state signal to a static signal. Responsive to the low-state signal being greater than the static signal, the discriminator circuit outputs a high-voltage signal. The high-voltage signal output by the discriminator circuit indicates that the low-state signal is a false low signal. Responsive to the low-state signal being less than or equal to the static signal, the discriminator circuit outputs a low-voltage signal. The low-voltage signal output by the discriminator circuit indicates that the low-state signal is a valid low signal. | 2009-07-30 |
20090189647 | BIAS CURRENT GENERATOR FOR MULTIPLIE SUPPLY VOLTAGE CIRCUIT - An electronic device supplied by multiple supply voltages includes a bias current generating stage and maximum current selection stage. The bias current generating stage comprises a crude bias current generator for generating an crude bias current during a power up phase in which at least one of the multiple supply voltages has not yet reached its target supply voltage level, a reference current stage for providing a reference current having a target current value greater than the target value of the crude bias current when the multiple supply voltages have reached their target supply voltage levels. The maximum current selection stage is adapted to continuously output a bias current which is the maximum current of the crude bias current and the reference current. | 2009-07-30 |
20090189648 | Clock Signal Recovery Device and Method for Recovering Clock Signals - A clock signal recovery device has a digital data signal input for the input of a digital data signal and a clock signal output for the output of a recovered clock signal. The digital data signal has a given nominal clock signal frequency. The clock signal recovery device is a digital circuit. | 2009-07-30 |
20090189649 | ELECTRONIC CIRCUIT AND METHOD THEREFOR - The electronic circuit comprises a functional module ( | 2009-07-30 |
20090189650 | PLL circuit including voltage controlled oscillator having voltage-current conversion circuit - A Phase-Locked Loop (PLL) circuit includes a voltage-controlled oscillator. The voltage-controlled oscillator includes a voltage-current conversion circuit and a current-controlled oscillation circuit. The voltage-current conversion circuit includes an input transistor having a gate terminal connecting a control voltage, a first transistor connected in series to the input transistor, a second transistor connected as a current-mirror to the first transistor, to generate a control current, and a current source connected in parallel to the first transistor. The current-controlled oscillation circuit oscillates at a frequency according to the control current. | 2009-07-30 |
20090189651 | High Speed Arbitrary Waveform Generator - A high-speed arbitrary waveform generator (AWG) that utilizes multiple digital-to-analog converters (D/A converters) and overcomes bandwidth limitations of individual D/A converters to produce high-speed waveforms. | 2009-07-30 |
20090189652 | Frequency Multiplier - A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted. | 2009-07-30 |
20090189653 | Phase Lock Loop Clock Distribution Method and System - A method and apparatus and program use the quiet, regulated power supply inherent to the PLL to drive a CMOS buffer. In this manner, the CMOS buffer may distribute the reference clock in a manner that minimizes the power and space consumption associated with clock distribution processes. | 2009-07-30 |
20090189654 | Common-Mode Feedback Method Using a Current Starved Replica Biasing - A method, system, and circuit design product for setting the common-mode voltage level of a charge pump to yield low duty cycle distortion from a voltage controlled oscillator (VCO). Differential charge pumps utilize common-mode feedback (CMF) networks to control the common-mode voltage level. A replica circuit of a current starved delay cell from a VCO replaces the unity gain buffering circuit within a common-mode feedback circuit. Inserting the current starved delay cell replica circuit permits adequate negative feedback compensation, while allowing a phase locked loop (PLL) to operate with a wide bandwidth. As a result of utilizing the replica circuit of a current starved delay cell from a VCO, the common-mode voltage level is optimally centered to interface with the VCO, thereby minimizing duty cycle distortion. | 2009-07-30 |
20090189655 | PHASE-LOCKED LOOP CIRCUIT AND DELAY-LOCKED LOOP CIRCUIT - A phase-locked loop circuit includes a phase comparator that compares phases between a reference signal and a feedback signal and outputs a phase difference signal indicating a phase difference therebetween; a charge pump that outputs a charge pump current according to the phase difference signal; a low-pass filter that includes a resistor and a capacitor and that smoothes the charge pump current and converts the smoothed current into a control voltage; a voltage-controlled oscillator that generates an oscillation signal with a frequency according to the control voltage; and a frequency divider that generates a frequency-divided signal by frequency-dividing the oscillation signal and outputs the frequency-divided signal to the phase comparator as the feedback signal, wherein the resistor in the low-pass filter is a variable resistor that is changed according to the control voltage. | 2009-07-30 |
20090189656 | Delay-locked loop and a stabilizing method thereof - A delay-locked loop includes a phase detector, a shift register, a digital low pass filter, a digital to analog converter, a bias circuit, and a delay circuit. The phase detector generates a lagging signal and a leading signal corresponding to a phase difference between an input clock signal and a feedback clock signal. The shift register outputs a digital data according to the lagging signal and the leading signal. The digital low pass filter generates a selecting signal according to the digital data. The bias circuit generates a first control voltage and a second control voltage in response to the bias voltage converted from the selecting signal. The delay circuit generates the feedback clock signal corresponding to the first control voltage and the second control voltage. | 2009-07-30 |
20090189657 | Delay locked loop circuit and method for eliminating jitter and offset therein - A delay locked loop circuit includes a phase-frequency detector, a sampler, a charge pump, a bias generator and a voltage-controlled element. The phase-frequency detector outputs at least one difference signal by detecting a phase difference between an input clock signal and a feedback clock signal. The sampler outputs at least one sampled signal by delaying the difference signal in accordance with the input clock signal. The charge pump generates a control voltage in accordance with the sampled signal. The bias generator generates at least one bias voltage in accordance with the control voltage. The voltage-controlled element is controlled with the bias voltage to output the feedback clock signal to the phase-frequency detector in accordance with the input clock signal. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed. | 2009-07-30 |
20090189658 | DLL circuit, semiconductor device using the same, and method for controlling DLL circuit - There is provided a DLL circuit that uses a small amount of area on a chip, and is compatible with a wide range of clock frequencies. The DLL circuit has a delay line | 2009-07-30 |
20090189659 | SWITCHING CIRCUIT IN A PHASE LOCKED LOOP (PLL) TO MINIMIZE CURRENT LEAKAGE IN INTEGRATED CIRCUITS - In an apparatus and method for reducing current leakage in a phase locked loop (PLL), a pair of resistive divider circuit is coupled to receive a pair of differential input signals and provide a pair of differential output signals. A timing control circuit controls a pair of switches, the pair of switches being operable to conduct the pair of differential output signals in response to at least one signal of the pair of differential input signals being present. An operational amplifier (OA) includes a pair of OA input terminals and an OA output terminal. The pair of OA input terminals is coupled to receive the pair of differential output signals conducted by the pair of switches. A feedback circuit is coupled between the OA output terminal and a first one of the pair of OA input terminals. The pair of switches is disabled by the timing control circuit to block a current leakage from the feedback circuit. | 2009-07-30 |
20090189660 | SEMICONDUCTOR DEVICE - A semiconductor device includes an input circuit, an output circuit, and a test circuit that is adapted to evaluate delaying of a signal which is input to the input circuit to be output from the output circuit. The test circuit includes a first delay circuit for delaying a signal output from the input circuit, a second delay circuit which is configured of a plurality of serially connected gate circuits and is adapted to further delay a signal output from the first delay circuit, a through-path which is configured of a wiring pattern and is adapted to transmit the signal output from the first delay circuit, a selector that selects one of a signal output from the second delay circuit and a signal transmitted through the through-path according to a control signal to supply the selected signal to the output circuit, and a control signal generating circuit that generates the control signal according to the signal output from the input circuit so as to allow the selector to alternately select the signal output from the second delay circuit and the signal transmitted through the through-path. | 2009-07-30 |
20090189661 | PULSE WIDTH MODULATION CONTROLLER AND THE CONTROLLING METHOD THEREOF - A pulse width modulation controller comprises a disabling unit, a level sensor and an over current protector. These three devices are all coupled to a multi-function node for accomplishing a disable function, input level sensing, and over-current protection, respectively. | 2009-07-30 |
20090189662 | Apparatus and circuit including latch circuit, and method of controlling latch circuit - An apparatus includes a first selector which selects a test data during a first operation mode, and selects a first input data during a second operation mode, a first latch circuit which latches an output signal of the first selector according to a first clock signal, a second selector which selects one from a second input data and an output signal of the first latch circuit, and a second latch circuit which latches the second input data sent from the second selector according to a second clock signal during the second operation mode, and passes through the output signal of the first latch circuit sent from the second selector during the first operation mode. | 2009-07-30 |
20090189663 | STANDARD CELL AND SEMICONDUCTOR DEVICE - The present invention provides a standard cell and a scan flip flop circuit capable of introducing a scan test also to a system LSI having an ACS circuit. One standard cell is configured by: a 3-input selection circuit for selecting one signal from three input signals; and a flip flop circuit. The 3-input selection circuit receives a control signal and a test signal at its control input part and its first input part, respectively. First and second signals are supplied to second and third input parts, and a selection signal is supplied to a selector input part. On the basis of the control signal and the selection signal, any of the signals input to the first to third input parts is output from the output part. | 2009-07-30 |
20090189664 | STATE RETAINING POWER GATED LATCH AND METHOD THEREFOR - A circuit has first latch, a second latch, a coupling circuit, and a power down circuit. The first latch has an input/output coupled to a data node. The second latch has an input/output. The coupling circuit is coupled between the input/output of the second latch and the data node. The coupling circuit is enabled during a normal operation of the circuit and disabled during a power down mode of the circuit. The power down control circuit is for disabling the first latch during the power down mode and for a time period after a transition from the power down mode to the normal operation. This allows the second latch to set the state of the first latch when transitioning from the power down mode to the normal mode. Thus normal operation can be fast, and the power down mode can have low leakage current. | 2009-07-30 |
20090189665 | SCHMITT-TRIGGER-BASED LEVEL DETECTION CIRCUIT - A Schmitt trigger includes A first PMOS transistors having the drains and sources thereof serially connected and coupled between a voltage source and an output end, and having gates thereof coupled to an input end; B first NMOS transistors having the drains and sources thereof serially connected and coupled between the output end and ground, and having gates thereof coupled to the input end; C second PMOS transistors, each being coupled between ground and a node between the drain and the source of the first PMOS transistors and having the gate thereof coupled to the output end; and D second NMOS transistors, each being coupled between the voltage source and a node between the drain and the source of the first NMOS transistors and having the gate thereof coupled to the output end. A is greater than 2 and C, and B is greater than 2 and D. | 2009-07-30 |
20090189666 | JITTER INJECTION CIRCUIT, PATTERN GENERATOR, TEST APPARATUS, AND ELECTRONIC DEVICE - Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal. | 2009-07-30 |
20090189667 | JITTER INJECTION CIRCUIT, PATTERN GENERATOR, TEST APPARATUS, AND ELECTRONIC DEVICE - Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that are connected in a cascading manner and that each sequentially delay a supplied reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal. | 2009-07-30 |
20090189668 | VOLTAGE DETECTING CIRCUIT - A voltage detecting circuit for comparing a voltage to be detected with a reference voltage and outputting an output signal having a level depending on the comparison is disclosed. The voltage detecting circuit includes an inverting amplifier circuit configured to receive an intermediate signal having a level depending on the comparison and output the output signal. The inverting amplifier circuit includes an active element having a control terminal. A threshold voltage of the control terminal is as low as or lower than the reference voltage. The voltage to be detected is applied to the control terminal of the active element. | 2009-07-30 |
20090189669 | METHODS AND APPARATUS TO REDUCE PROPAGATION DELAY OF CIRCUITS - Methods and apparatus to reduce propagation delay of circuits are disclosed. A disclosed apparatus to reduce propagation delay of a circuit comprises a level shifter to selectively turn a first circuit on and off; a first switch to couple the first circuit to a second circuit when the first circuit is on, wherein the second circuit is to selectively receive a first current from the first circuit based on a signal the second circuit receives from the level shifter; and a second switch to couple the first circuit to a reference signal based on the first current, the second switch causing the first circuit to start to turn off. | 2009-07-30 |
20090189670 | LEVEL SHIFTER WITH REDUCED POWER CONSUMPTION AND LOW PROPAGATION DELAY - A level shifter includes a Not gate coupled to a signal input and operable between a first high level and a low level; a first PMOS transistor coupled to a second voltage source and a control end; a first NMOS transistor coupled to the first PMOS transistor, a Not-gate output end and a reference voltage; and a control circuit coupled to the signal input, the Not-gate output end and the second voltage source. When the signal input and the Not-gate output end are at the first high level and the low level, respectively, the first PMOS transistor is turned on so that the signal output is at a second high level; and when the signal input and the Not-gate output end are switched contrarily, the first PMOS transistor is turned off and the signal output is at the low level. | 2009-07-30 |
20090189671 | Method and Apparatus for Improvement of Matching FET Currents Using a Digital to Analog Converter - A method and apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs. | 2009-07-30 |
20090189672 | Pseudo-differential active RC integrator - A pseudo-differential active RC integrator is described. The pseudo-differential active RC integrator includes a common-mode feedback sub-circuit to control the common-mode output signal of the integrator. The common-mode feedback subcircuit may be coupled to one or more virtual ground nodes of the pseudo-differential active RC integrator, and may include one or more transconductors. | 2009-07-30 |
20090189673 | MIXER WITH BALANCED LOCAL OSCILLATOR SIGNAL - A mixer includes a first field effect transistor (FET) having a gate that receives a first signal of a balanced local oscillator (LO) signal, a first source/drain coupled to a ground voltage, and a second source/drain; and a second FET having a gate that receives a second signal of the balanced LO signal, a first source/drain that floats, and a second source/drain connected to the second source/drain of the first FET to form a mixing node, the second signal being out of phase with the first signal. A diplexer is connected between the mixing node and each of a radio frequency (RF) port and an intermediate frequency (IF) port. A first LO leakage caused by the first FET is substantially canceled by a second LO leakage caused by the second FET at the mixing node. | 2009-07-30 |
20090189674 | Circuit that facilitates proximity communication - One embodiment of the present invention provides a system that facilitates proximity communication. This system includes a circuit containing a bootstrap transistor and a pass-gate transistor, where the drain of the bootstrap transistor is coupled to the gate of the pass-gate transistor. Note that a first coupling capacitance exists between the source of the pass-gate transistor and the drain of the bootstrap transistor and a second coupling capacitance exists between the drain of the pass-gate transistor and the drain of the bootstrap transistor. During operation, the gate and the source of the bootstrap transistor are coupled to a high voltage, thereby causing an intermediate voltage at the drain of the bootstrap transistor. When the source of the pass-gate transistor transitions to a high voltage, the first coupling capacitance and the second coupling capacitance boost the voltage at the gate of the pass-gate transistor higher than the high voltage, thereby enabling the high voltage at the source of the pass-gate transistor to pass to the drain of the pass-gate transistor. | 2009-07-30 |
20090189675 | HIGH PERFORMANCE PSEUDO DYNAMIC PULSE CONTROLLABLE MULTIPLEXER - A high performance, set associative, cache memory tag multiplexer provides wide output pulse width without impacting hold time by separating the evaluation and restore paths and using a wider clock in the restore path than in the evaluation path. A clock controls the evaluation of the input signals. Its leading edge (i.e., rising edge) turns on NR to allow evaluation, its trailing edge (falling edge) turns off NR to stop evaluation. At this point, when NR is shut off, the inputs can start changing to set up for the next cycle. Hence the hold time of the input is determined by the clock trailing edge. | 2009-07-30 |
20090189676 | Semiconductor device - A semiconductor device includes a first conductive type first transistor, a first conductive type second transistor, a first power supply pad arranged between the first transistor and the second transistor and supplying a first potential, a second conductive type third transistor, a second conductive type fourth transistor, a second power supply pad arranged between the third transistor and the fourth transistor and supplying a second potential, a first output pad arranged between the first transistor and the third transistor, and a second output pad arranged between the second transistor and the fourth transistor, in which a direction in which a line connecting the first power supply pad with the second power supply pad extends is perpendicular to a direction in which a line connecting the first output pad with the second output pad extends. | 2009-07-30 |
20090189677 | GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME - A gate driving circuit includes stages, the stages being cascaded and each including: a pull-up part which pulls up a gate voltage to a clock signal during a horizontal scanning period (1H); a carry part which pulls up a carry voltage to the clock signal during the horizontal scanning period (1H); a pull-up driving part connected to a control terminal (Q-node) common to the carry part and the pull-up part and which receives a previous carry voltage from a first previous stage to turn on the pull-up part and the carry part; and a ripple preventing part which prevents a ripple generated at a previous Q-node of a second previous stage based on a ripple generated at the Q-node of the carry part and the pull-up part. | 2009-07-30 |
20090189678 | HIGH TEMPERATURE OPERATING PACKAGE AND CIRCUIT DESIGN - The invention provides a semiconductor device that is thermally isolated from the printed circuit board such that the device operates at a higher temperature and radiates heat away from the printed circuit board. In another embodiment, the semiconductor is stacked onto a second device and optionally thermally isolated from the second device. | 2009-07-30 |
20090189679 | GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME - A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval. | 2009-07-30 |
20090189680 | VOLTAGE-CONTROLLED SEMICONDUCTOR INDUCTOR AND METHOD - A voltage-controlled semiconductor inductor and method is provided. According to various embodiments, the voltage-controlled inductor includes a conductor configured with a number of inductive coils. The inductor also includes a semiconductor material having a contact with at least a portion of at least one of the coils. The semiconductor material is doped to form a diode with a first doped region of first conductivity type, a second doped region of second conductivity type, and a depletion region. A voltage across the diode changes lengths of the first doped region, the second doped region and the depletion region, and adjacent coils in contact with at least one of the doped regions are electrically shorted, thereby varying the inductance of the inductor. In various embodiments, the inductor is electrically connected to a resistor and a capacitor to provide a tunable RLC circuit. Other aspects and embodiments are provided herein. | 2009-07-30 |
20090189681 | SELF-OSCILLATING REGULATED LOW-RIPPLE CHARGE PUMP AND METHOD - Charge pump circuitry ( | 2009-07-30 |
20090189682 | METHOD AND APPARATUS FOR MODE SELECTION FOR HIGH VOLTAGE INTEGRATED CIRCUITS - A method is disclosed to add functionality to a terminal of a high voltage integrated circuit without the penalty of additional high voltage circuitry. The benefit is that alternative modes of operation can be selected for testing, trimming parameters of the integrated circuit, or any other purpose without the cost of an additional terminal. In one embodiment, ordinary low voltage circuitry monitors the voltage on the terminal that normally is exposed to high voltage. The configuration of a simple voltage detector and an ordinary latch allows easy entry into the test and trimming mode when the integrated circuit is not in the intended application, but prohibits entry into the test and trimming mode when the integrated circuit operates in the intended application. | 2009-07-30 |
20090189683 | CIRCUIT FOR GENERATING A REFERENCE VOLTAGE AND METHOD THEREOF - A circuit for generating a reference voltage at an output node comprises a first branch, a second branch, and a main current source. The first branch is electrically connected between a first terminal and a second terminal of the circuit, and comprises at least one first semiconductor device. Each first semiconductor device comprises a first node and a second node. The second branch is electrically connected between the first terminal and the second terminal of the circuit, and comprises at least one second semiconductor device and a branch current source. Each second semiconductor device comprises a first node and a second node. The branch current source is serially connected to the second transistor. The main current source is electrically connected to one of the first terminal and the second terminal of the circuit. The output node is in the first branch or the second branch. | 2009-07-30 |
20090189684 | Apparatus and Method for Waking up a Circuit - A method for waking up a circuit, comprising charging a voltage line of the circuit with a constant wake-up current until the voltage line reaches a predetermined voltage. Also, an apparatus, comprising a circuit portion, a switch configured to selectively couple an input of the circuit portion to a supply voltage, a current source configured to generate a first current, and a control circuit configured to control a state of the switch depending on the first current. | 2009-07-30 |
20090189685 | Leakage Control - In one embodiment, a leakage reduction circuit is provided that includes: a virtual power supply node; a first PMOS transistor coupled between the virtual power supply node and a power supply node; a second PMOS transistor having a source coupled to the power supply node; and a native NMOS transistor coupled between a drain of the second PMOS transistor and the virtual power supply node, the native NMOS transistor having a gate driven by the power supply node. | 2009-07-30 |
20090189686 | SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER CONTROL METHOD - Each of computing units on a semiconductor integrated circuit includes a first signal output unit that outputs a first status signal indicating a state of a input/output control unit with regard to an access to a storage unit, a second signal output unit that outputs a second status signal indicating a state of a process control unit with regard to an access to a processing unit, and a power control unit that control ON and OFF of power of the storage unit and the processing unit based on states of the first status signal and the second status signal. | 2009-07-30 |
20090189687 | MULTI-MODE RECONSTRUCTION FILTER - A circuit (e.g., a reconstruction filtering circuit) may include a single operational amplifier (op-amp) that is arranged to receive a voltage input and that is arranged to have a biasing of constant g | 2009-07-30 |
20090189688 | HIGH DYNAMIC RANGE ASK DEMODULATOR FOR USE IN AN RFID TRANSPONDER - An ASK demodulator for use in an RFID transponder having a limiter circuit associated with the antenna circuit and converting the ASK antenna fieldstrength modulation into an ASK limiter current modulation by limiting the antenna voltage to a fixed value and thereby causing the limiter current to be substantially proportional to the ASK antenna field strength, and a current discriminator circuit that discriminates the ASK limiter current modulation. By converting the fieldstrength modulation into a proportional limiter current and discriminating that limiter current, a linear relationship and a stable demodulator sensitivity are achieved. The current discrimination can be made accurately under low-voltage conditions. | 2009-07-30 |
20090189689 | Power supply processing for power amplifiers - The present invention, generally speaking, uses multiple selectable power supply paths, a saturation detector, or combinations of the same to achieve efficient power supply processing. In one aspect of the invention, a power supply processing circuit includes a first switched converter stage and a second linear stage. Depending on the power supply desired, the first stage may be bypassed to avoid conversion losses. In another aspect of the invention, a saturation detector is used to control the first stage such that the second stage operates efficiently just short of saturation, thereby avoiding distortion. | 2009-07-30 |
20090189690 | FEED-FORWARD AUTOMATIC-GAIN CONTROL AMPLIFIER (FFAGCA) FOR BIOMEDICAL APPLICATIONS AND AN ASSOCIATED METHOD - The present invention is a feed-forward automatic-gain control amplifier (FFAGCA) for biomedical applications and associated method, the FFAGCA comprises a detector, a controller, a variable gain amplifier (VGA), an input and an output. The associated method to process various kinds of biomedical signals with the FFAGCA comprises acts of adjusting gain setting with control path and simultaneously a signal amplification with signal path. | 2009-07-30 |
20090189691 | METHOD AND APPARATUS FOR REDUCING INTERMODULATION DISTORTION IN AN ELECTRONIC DEVICE HAVING AN AMPLIFIER CIRCUIT - An electronic device includes an amplifier circuit coupled to a linearizer. The amplifier circuit may receive a first input signal including first and second frequencies and generate a first output signal including a delta frequency signal at a delta frequency, which is the difference between the first frequency and the second frequency. The linearizer includes a signal detector circuit, a current-mirror circuit, a low pass filter, a phase shifter, and a bias circuit. The signal detector circuit may generate a second output signal. The current-mirror circuit may adjust an amplitude of a signal. The low pass filter may eliminate a portion of the second output signal having frequencies greater than the delta frequency. The phase shifter may generate a feedback signal corresponding to the delta frequency signal. An amplitude and/or a phase of the feedback signal is different from an amplitude and/or a phase of the delta frequency signal. | 2009-07-30 |
20090189692 | PREDISTORTER - A predistorter for correcting distortion caused by a memory effect in amplifying a signal by an amplifier is provided. In the memory PD | 2009-07-30 |
20090189693 | OPERATIONAL AMPLIFIER - An operational amplifier includes a differential amplifier circuit provided at an input stage and an amplifier circuit at a post stage. In the differential amplifier circuit, first and third bipolar transistors are PNP-type bipolar transistors and Darlington-connected. An inverting input terminal is connected to the base terminal of the first bipolar transistor. The first and third bipolar transistors and second and fourth bipolar transistors construct an input differential pair. First and second protection diodes are connected between the base terminals of the first and second bipolar transistors constructing the input differential pair and the ground potential, respectively. Each of the protection diodes is connected so that the cathode terminal is positioned on the base terminal side of the bipolar transistor, and the cathode terminal is positioned on the ground potential side. | 2009-07-30 |
20090189694 | DIFFERENTIAL AMPLIFIER WITH ACCURATE INPUT OFFSET VOLTAGE - An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage. | 2009-07-30 |
20090189695 | AMPLIFIER CIRCUIT HAVING STACKED MAIN AMPLIFIER AND PARALLEL SUB-AMPLIFIER - An amplifier circuit for amplifying an input signal to generate an output signal is provided. The amplifier circuit has a stacked main amplifier, a parallel sub-amplifier, and a signal combiner. The stacked main amplifier includes a first amplifier unit for outputting a first amplified signal generated from processing the input signal; and a second amplifier unit for outputting a second amplified signal generated from processing the first amplified signal. The first amplifier unit and the second amplifier unit share bias current. The parallel sub-amplifier is coupled to the stacked main amplifier according to a parallel connection fashion, and outputs a third amplified signal generated from processing the input signal. The signal combiner combines the second amplified signal and the third amplified signal to generate the output signal. | 2009-07-30 |
20090189696 | LOW-NOISE AMPLIFIER - A low-noise amplifier is provided according to the present invention. The low-noise amplifier includes a first amplifier stage, a second amplifier stage, a third amplifier stage, an input matching network, inter-stage matching networks, and an output matching network. The impedance of the input matching network and the input impedance of the first amplifier stage are conjugate matched, thereby decreasing system power consumption and noise factor. The system gain is enhanced by cascading three stages of amplifiers. | 2009-07-30 |
20090189697 | AUTO-TUNING AMPLIFIER - This document discloses, among other things, a front end circuit having a selectable center frequency. The center frequency is selected based on a control signal proportional to a phase difference between a reference frequency and an amplifier output. A resonant frequency of a tank circuit coupled to the amplifier is tuned using the control signal. | 2009-07-30 |
20090189698 | Pll circuit - The present invention relates to a phase locked loop arrangement having an oscillator circuit ( | 2009-07-30 |
20090189699 | FIXED BANDWIDTH LO-GEN - A local oscillation generator (LO-GEN) maintains a fixed bandwidth using a gain calibration module that compensates for variations in the voltage controlled oscillation (VCO) gain based on the oscillation frequency. During an open loop calibration of the LO-GEN, the gain calibration module adjusts the charge pump current to compensate for the VCO gain changes. | 2009-07-30 |
20090189700 | Frequency synthesizer - A frequency synthesizer includes first and second frequency dividers for receiving and frequency-dividing a signal generated by a voltage-controlled oscillator, a frequency mixer for mixing output signals of the first and second frequency dividers, and a third frequency divider for receiving and frequency-dividing a signal having one frequency of two frequencies that are output by the frequency mixer. The first, second third and frequency dividers and the frequency mixer are provided in a feedback loop within a PLL circuit between the voltage-controlled oscillator and the phase comparator. The phase comparator has a first input terminal to which a signal to which a signal that is output by the third frequency divider is input and a second input terminal to which a reference clock signal that is output by a reference signal generator is input. A loop filter supplies the voltage-controlled oscillator with a voltage that is based upon result of the phase comparison by a phase comparator. The voltage-controlled oscillator supplies the first and second frequency dividers with a signal that oscillates at a frequency corresponding to the voltage input to the oscillator. | 2009-07-30 |
20090189701 | Single-Ended to Differential Translator to Control Current Starved Delay Cell Bias - A method, system, and circuit device for interfacing single-ended charge pump output to differential voltage controlled oscillator (VCO) inputs to yield low duty cycle distortion from a VCO. A single-ended charge pump output is utilized to create a compliment differential voltage leg, while optimally centering the common-mode voltage level to interface to a current starved ring VCO. A replica of the VCO's current starved delay cell is implemented along with negative feedback to generate the compliment differential voltage leg. The single-ended charge pump output is coupled to a first transistor, while a second transistor is coupled to the output of an error amplifier. The error amplifier utilizes negative feedback to bias the second transistor, forcing the output of the replica circuit to equal a reference voltage. | 2009-07-30 |
20090189702 | CIRCUIT AND METHOD FOR DETECTING A VOLTAGE CHANGE - A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison. | 2009-07-30 |
20090189703 | CIRCUITS AND DESIGN STRUCTURES FOR MONITORING NBTI (NEGATIVE BIAS TEMPERATURE INSTABILITY) EFFECT AND/OR PBTI (POSITIVE BIAS TEMPERATURE INSTABILITY) EFFECT - A ring oscillator has an odd number of NOR-gates greater than or equal to three, each with first and second input terminals, a voltage supply terminal, and an output terminal. The first input terminals of all the NOR-gates are interconnected, and each of the NOR-gates has its output terminal connected to the second input terminal of an immediately adjacent one of the NOR-gates. During a stress mode, a voltage supply and control block applies a stress enable signal to the interconnected first input terminals, and an increased supply voltage to the voltage supply terminals. During a measurement mode, this block grounds the interconnected first input terminals, and applies a normal supply voltage to the voltage supply terminals. Also included are an analogous NAND-gate based circuit, a circuit combining the NAND- and NOR-aspects, a circuit with a ring oscillator where the inverters may be coupled directly or through inverting paths, and circuits for measuring the bias temperature instability effect in pass gates. | 2009-07-30 |
20090189704 | Voltage controlled oscillator with multi-tap inductor - According to one exemplary embodiment, a voltage controlled oscillator configured to operate in low and high band modes includes a low band section and a high band section. The voltage controlled oscillator further includes a multi-tap inductor having a high inductance portion coupled to the low band section and a low inductance portion coupled to the high band section. The low band section is configured to provide a low frequency band oscillator output in the low band mode and the high band section is configure to provide a high frequency band oscillator output in the high band mode. The low band section is disabled in the high band mode and the high band section is disabled in the low band mode. A center tap of the multi-tap inductor is coupled to a supply voltage. | 2009-07-30 |
20090189705 | Crystal oscillator for surface mounting - A crystal oscillator includes an oscillator circuit, a main body, a first switching circuit, a second switching circuit, and a voltage detecting circuit. The oscillator circuit includes an IC chip including an output circuit and a function circuit. The crystal element includes a first excitation electrode and a second excitation electrode. The main body houses the oscillator circuit and the crystal element and includes a power supply terminal, a ground terminal, an output terminal, and a function terminal. The output terminal is electrically connected to the output circuit and the first excitation electrode via the first switching circuit. The function terminal is electrically connected to the function circuit and the second excitation electrode via the second switching circuit. The first switching circuit and the second switching circuit are operated on the basis of a switching signal from the voltage detecting circuit connected to the power supply terminal. | 2009-07-30 |
20090189706 | INDUCTANCE-SWITCHABLE DUAL-BAND VOLTAGE CONTROLLED OSCILLATION CIRCUIT - An inductance-switchable dual-band voltage-controlled oscillation circuit is proposed, which is designed for integration to a high-frequency signal processing system, such as an ultra-wideband (UWB) circuit system, for providing a dual-band voltage-controlled oscillating signal generating function. The proposed voltage-controlled oscillation circuit is characterized by the use of a switchable inductance circuit architecture in lieu of a switchable capacitive circuit architecture for integration to a fixed-inductance circuit architecture to constitute a variable-inductance LC tuning circuit architecture that allows the provision of a dual-band oscillating signal generating function. Further, a current mirror circuit module is used to maintain the quality factor of the LC tuning circuit in both operating modes; a buffer-stage circuit architecture is used to achieve low power consumption, low phase noise, and broad tuning range. | 2009-07-30 |
20090189707 | Wideband quadrature imbalance compensation system and method - Compensating for wideband quadrature imbalance error by introducing inverse complex inputs to phase quadrature estimator filters to generate estimated quadrature distortion; summing estimator quadrature distortion with a delayed version of the actual complex input to obtain estimated quadrature output; comparing the output with the true output to obtain residual quadrature imbalance error; applying a least mean square to the inverse input and imbalance residual error to obtain an updated estimate of filter coefficients; updating the filter coefficients of the phase quadrature estimator; and updating the filter coefficients of a phase quadrature compensator with the filter coefficients of the phase quadrature estimator to obtain a quadrature output pre-compensated for quadrature imbalance error. | 2009-07-30 |
20090189708 | COUPLING CANCELLATION SCHEME - Methods and apparatus are disclosed, such as those involving an interconnection layout for an integrated circuit (IC). One such layout includes a plurality of differential pairs of lines. Each differential pair has two lines including one or more parallel portions extending substantially parallel to each other. Each pair also includes a shield line. Each of the shield lines includes one or more parallel portions interposed between the parallel portions of one of the pairs of differential lines. One or more of the shield lines are electrically connected to a voltage reference, such as ground. This layout is believed to reduce or eliminate intra-pair coupling as well as inter-pair coupling. | 2009-07-30 |
20090189709 | Signal splitter with improved transmisson line transformer - A splitter circuit for use in a CATV network. A signal input communicates with a first balun to supply two signal outputs, wherein the first balun is impedance matched to the impedance of the input using two or more additional baluns in parallel with each other. The additional baluns are transmission line baluns in parallel or series with resistive and/or capacitive and/or inductive components. | 2009-07-30 |
20090189710 | DUAL-FREQUENCY MATCHING CIRCUIT - The connection topology of input terminals ( | 2009-07-30 |
20090189711 | RF SYSTEM HAVING A ONE-DIMENSIONAL NANOSTRUCTURE MULTI-PORT COUPLER - A one-dimensional nanostructure multi-port coupler ( | 2009-07-30 |
20090189712 | Spiral Coupler - An improved spiral coupler including a plurality of parallel, coextensive conductive strips disposed in a planar spiral path, including a first strip having an input port and a direct or through port, a second strip having a coupler port and an isolated port and a first cross-over connection for bridging the strips from the inside to the outside of the spiral path to provide all four the ports external access to the spiral path. | 2009-07-30 |
20090189713 | Voltage Controlled On-Chip Decoupling Capacitance to Mitigate Power Supply Noise - A method and system for reducing the noise level of a power supply system with the implementation of a voltage controlled decoupling capacitor in an electrical circuit. Voltage variations of the power supply caused by switching currents are detected by a voltage sensor control circuit. The voltage sensor circuit compares a stable reference voltage with the varying voltage level of the power supply in order to generate a sensor control voltage. When applied to the decoupling capacitor, the control voltage adjusts the capacitance of the voltage controlled capacitor. The adjusted capacitance allows the voltage controlled decoupling capacitor to compensate for the effects of the voltage variations by supplying an increased quantity of charge to various circuit components. Thus, the voltage controlled capacitor is able to efficiently reduce noise within the power supply system. | 2009-07-30 |
20090189714 | Layered low-pass filter - A layered low-pass filter includes: a first inductor and a second inductor that are connected in series and are located between an input terminal and an output terminal; a first capacitor connected in parallel to the first inductor; a second capacitor connected in parallel to the second inductor; and third to fifth capacitors and third to fifth inductors. The output of the first inductor and the input of the second inductor are connected to the ground via the third capacitor and the third inductor connected in series. The input of the first inductor is connected to the ground via the fourth capacitor and the fourth inductor connected in series. The output of the second inductor is connected to the ground via the fifth capacitor and the fifth inductor | 2009-07-30 |
20090189715 | Layered low-pass filter - A layered low-pass filter includes: a layered substrate; an input terminal, an output terminal and a grounding terminal each disposed on a periphery of the layered substrate; first and second inductors connected in series and provided between the input terminal and the output terminal; first to fifth capacitors formed within the layered substrate; a grounding conductor layer provided within the layered substrate; and a conducting portion formed within the layered substrate. The conducting portion includes a conductor layer connected to the grounding terminal, and a conducting path formed of a plurality of through holes. The conducting portion connects the grounding conductor layer to the grounding terminal via a path longer than the shortest distance between the grounding conductor layer and the grounding terminal. | 2009-07-30 |
20090189716 | FILTER DEVICE WITH FINITE TRANSMISSION ZEROS - A filter device with transmission zeros is provided according to the present invention, which has an odd mode resonant frequency and an even mode resonant frequency. The filter device includes: a substrate, a metallic rectangular ring, a signal couple-in/couple-out module, and a metallic ground plane, wherein the surface of said metallic ground plane is parallel to the plane enclosed by said metallic rectangular ring, and said metallic rectangular ring applied to the filter device of the present invention has a perimeter shorter than or equal to the wavelength corresponding to the mean of said odd mode resonant frequency and said even mode resonant frequency, thereby allowing said filter device of the present invention, in a situation of specific bandpass frequency, to reduce its perimeter to about half of the perimeter of conventional annular rectangular dual mode filters. In addition, the locations of the transmission zeros can be changed by adjusting the length/width ratio of said metallic rectangular ring, and the frequency response of the filter signal can also be reduced by disposing a ground capacitor module. Accordingly, the area of the dual mode filter can be greatly reduced. Furthermore, the frequency response of the filter signal can be increased by disposing a ground inductor module, accordingly, decreasing the size of dual mode filter and providing a means of easy fabrication thereof. | 2009-07-30 |